[mirror_ubuntu-focal-kernel.git] / drivers / gpu / drm / amd / powerplay / hwmgr / hwmgr.c

/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include "pp_debug.h"
#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <drm/amdgpu_drm.h>
#include "power_state.h"
#include "hwmgr.h"
#include "ppsmc.h"
#include "amd_acpi.h"
#include "pp_psm.h"

extern const struct pp_smumgr_func ci_smu_funcs;
extern const struct pp_smumgr_func smu8_smu_funcs;
extern const struct pp_smumgr_func iceland_smu_funcs;
extern const struct pp_smumgr_func tonga_smu_funcs;
extern const struct pp_smumgr_func fiji_smu_funcs;
extern const struct pp_smumgr_func polaris10_smu_funcs;
extern const struct pp_smumgr_func vegam_smu_funcs;
extern const struct pp_smumgr_func vega10_smu_funcs;
extern const struct pp_smumgr_func vega12_smu_funcs;
extern const struct pp_smumgr_func smu10_smu_funcs;
extern const struct pp_smumgr_func vega20_smu_funcs;

extern int smu7_init_function_pointers(struct pp_hwmgr *hwmgr);
extern int smu8_init_function_pointers(struct pp_hwmgr *hwmgr);
extern int vega10_hwmgr_init(struct pp_hwmgr *hwmgr);
extern int vega12_hwmgr_init(struct pp_hwmgr *hwmgr);
extern int vega20_hwmgr_init(struct pp_hwmgr *hwmgr);
extern int smu10_init_function_pointers(struct pp_hwmgr *hwmgr);

static int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr);
static void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr);
static int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr);
static int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr);
static int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr);
static int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr);
static int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr);


static void hwmgr_init_workload_prority(struct pp_hwmgr *hwmgr)
{
	hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
	hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
	hwmgr->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
	hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
	hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
	hwmgr->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;

	hwmgr->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
	hwmgr->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
	hwmgr->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
	hwmgr->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
	hwmgr->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
	hwmgr->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
}

int hwmgr_early_init(struct pp_hwmgr *hwmgr)
{
	if (!hwmgr)
		return -EINVAL;

	hwmgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
	hwmgr->pp_table_version = PP_TABLE_V1;
	hwmgr->dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
	hwmgr->request_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
	hwmgr_init_default_caps(hwmgr);
	hwmgr_set_user_specify_caps(hwmgr);
	hwmgr->fan_ctrl_is_in_default_mode = true;
	hwmgr_init_workload_prority(hwmgr);

	switch (hwmgr->chip_family) {
	case AMDGPU_FAMILY_CI:
		hwmgr->smumgr_funcs = &ci_smu_funcs;
		ci_set_asic_special_caps(hwmgr);
		hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK |
					 PP_ENABLE_GFX_CG_THRU_SMU |
					 PP_GFXOFF_MASK);
		hwmgr->pp_table_version = PP_TABLE_V0;
		hwmgr->od_enabled = false;
		smu7_init_function_pointers(hwmgr);
		break;
	case AMDGPU_FAMILY_CZ:
		hwmgr->od_enabled = false;
		hwmgr->smumgr_funcs = &smu8_smu_funcs;
		hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
		smu8_init_function_pointers(hwmgr);
		break;
	case AMDGPU_FAMILY_VI:
		hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
		switch (hwmgr->chip_id) {
		case CHIP_TOPAZ:
			hwmgr->smumgr_funcs = &iceland_smu_funcs;
			topaz_set_asic_special_caps(hwmgr);
			hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |
						PP_ENABLE_GFX_CG_THRU_SMU);
			hwmgr->pp_table_version = PP_TABLE_V0;
			hwmgr->od_enabled = false;
			break;
		case CHIP_TONGA:
			hwmgr->smumgr_funcs = &tonga_smu_funcs;
			tonga_set_asic_special_caps(hwmgr);
			hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK;
			break;
		case CHIP_FIJI:
			hwmgr->smumgr_funcs = &fiji_smu_funcs;
			fiji_set_asic_special_caps(hwmgr);
			hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |
						PP_ENABLE_GFX_CG_THRU_SMU);
			break;
		case CHIP_POLARIS11:
		case CHIP_POLARIS10:
		case CHIP_POLARIS12:
			hwmgr->smumgr_funcs = &polaris10_smu_funcs;
			polaris_set_asic_special_caps(hwmgr);
			hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);
			break;
		case CHIP_VEGAM:
			hwmgr->smumgr_funcs = &vegam_smu_funcs;
			polaris_set_asic_special_caps(hwmgr);
			hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);
			break;
		default:
			return -EINVAL;
		}
		smu7_init_function_pointers(hwmgr);
		break;
	case AMDGPU_FAMILY_AI:
		switch (hwmgr->chip_id) {
		case CHIP_VEGA10:
			hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
			hwmgr->smumgr_funcs = &vega10_smu_funcs;
			vega10_hwmgr_init(hwmgr);
			break;
		case CHIP_VEGA12:
			hwmgr->smumgr_funcs = &vega12_smu_funcs;
			vega12_hwmgr_init(hwmgr);
			break;
		case CHIP_VEGA20:
			hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
			hwmgr->smumgr_funcs = &vega20_smu_funcs;
			vega20_hwmgr_init(hwmgr);
			break;
		default:
			return -EINVAL;
		}
		break;
	case AMDGPU_FAMILY_RV:
		switch (hwmgr->chip_id) {
		case CHIP_RAVEN:
			hwmgr->od_enabled = false;
			hwmgr->smumgr_funcs = &smu10_smu_funcs;
			smu10_init_function_pointers(hwmgr);
			break;
		default:
			return -EINVAL;
		}
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

int hwmgr_sw_init(struct pp_hwmgr *hwmgr)
{
	if (!hwmgr|| !hwmgr->smumgr_funcs || !hwmgr->smumgr_funcs->smu_init)
		return -EINVAL;

	phm_register_irq_handlers(hwmgr);

	return hwmgr->smumgr_funcs->smu_init(hwmgr);
}


int hwmgr_sw_fini(struct pp_hwmgr *hwmgr)
{
	if (hwmgr && hwmgr->smumgr_funcs && hwmgr->smumgr_funcs->smu_fini)
		hwmgr->smumgr_funcs->smu_fini(hwmgr);

	return 0;
}

int hwmgr_hw_init(struct pp_hwmgr *hwmgr)
{
	int ret = 0;

	if (!hwmgr->pm_en)
		return 0;

	if (!hwmgr->pptable_func ||
	    !hwmgr->pptable_func->pptable_init ||
	    !hwmgr->hwmgr_func->backend_init) {
		hwmgr->pm_en = false;
		pr_info("dpm not supported \n");
		return 0;
	}

	ret = hwmgr->pptable_func->pptable_init(hwmgr);
	if (ret)
		goto err;

	((struct amdgpu_device *)hwmgr->adev)->pm.no_fan =
				hwmgr->thermal_controller.fanInfo.bNoFan;

	ret = hwmgr->hwmgr_func->backend_init(hwmgr);
	if (ret)
		goto err1;
 /* make sure dc limits are valid */
	if ((hwmgr->dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
			(hwmgr->dyn_state.max_clock_voltage_on_dc.mclk == 0))
			hwmgr->dyn_state.max_clock_voltage_on_dc =
					hwmgr->dyn_state.max_clock_voltage_on_ac;

	ret = psm_init_power_state_table(hwmgr);
	if (ret)
		goto err2;

	ret = phm_setup_asic(hwmgr);
	if (ret)
		goto err2;

	ret = phm_enable_dynamic_state_management(hwmgr);
	if (ret)
		goto err2;
	ret = phm_start_thermal_controller(hwmgr);
	ret |= psm_set_performance_states(hwmgr);
	if (ret)
		goto err2;

	((struct amdgpu_device *)hwmgr->adev)->pm.dpm_enabled = true;

	return 0;
err2:
	if (hwmgr->hwmgr_func->backend_fini)
		hwmgr->hwmgr_func->backend_fini(hwmgr);
err1:
	if (hwmgr->pptable_func->pptable_fini)
		hwmgr->pptable_func->pptable_fini(hwmgr);
err:
	return ret;
}

int hwmgr_hw_fini(struct pp_hwmgr *hwmgr)
{
	if (!hwmgr || !hwmgr->pm_en)
		return 0;

	phm_stop_thermal_controller(hwmgr);
	psm_set_boot_states(hwmgr);
	psm_adjust_power_state_dynamic(hwmgr, false, NULL);
	phm_disable_dynamic_state_management(hwmgr);
	phm_disable_clock_power_gatings(hwmgr);

	if (hwmgr->hwmgr_func->backend_fini)
		hwmgr->hwmgr_func->backend_fini(hwmgr);
	if (hwmgr->pptable_func->pptable_fini)
		hwmgr->pptable_func->pptable_fini(hwmgr);
	return psm_fini_power_state_table(hwmgr);
}

int hwmgr_suspend(struct pp_hwmgr *hwmgr)
{
	int ret = 0;

	if (!hwmgr || !hwmgr->pm_en)
		return 0;

	phm_disable_smc_firmware_ctf(hwmgr);
	ret = psm_set_boot_states(hwmgr);
	if (ret)
		return ret;
	ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
	if (ret)
		return ret;
	ret = phm_power_down_asic(hwmgr);

	return ret;
}

int hwmgr_resume(struct pp_hwmgr *hwmgr)
{
	int ret = 0;

	if (!hwmgr)
		return -EINVAL;

	if (!hwmgr->pm_en)
		return 0;

	ret = phm_setup_asic(hwmgr);
	if (ret)
		return ret;

	ret = phm_enable_dynamic_state_management(hwmgr);
	if (ret)
		return ret;
	ret = phm_start_thermal_controller(hwmgr);
	ret |= psm_set_performance_states(hwmgr);
	if (ret)
		return ret;

	ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);

	return ret;
}

static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type  state)
{
	switch (state) {
	case POWER_STATE_TYPE_BATTERY:
		return PP_StateUILabel_Battery;
	case POWER_STATE_TYPE_BALANCED:
		return PP_StateUILabel_Balanced;
	case POWER_STATE_TYPE_PERFORMANCE:
		return PP_StateUILabel_Performance;
	default:
		return PP_StateUILabel_None;
	}
}

int hwmgr_handle_task(struct pp_hwmgr *hwmgr, enum amd_pp_task task_id,
		enum amd_pm_state_type *user_state)
{
	int ret = 0;

	if (hwmgr == NULL)
		return -EINVAL;

	switch (task_id) {
	case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
		ret = phm_pre_display_configuration_changed(hwmgr);
		if (ret)
			return ret;
		ret = phm_set_cpu_power_state(hwmgr);
		if (ret)
			return ret;
		ret = psm_set_performance_states(hwmgr);
		if (ret)
			return ret;
		ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
		break;
	case AMD_PP_TASK_ENABLE_USER_STATE:
	{
		enum PP_StateUILabel requested_ui_label;
		struct pp_power_state *requested_ps = NULL;

		if (user_state == NULL) {
			ret = -EINVAL;
			break;
		}

		requested_ui_label = power_state_convert(*user_state);
		ret = psm_set_user_performance_state(hwmgr, requested_ui_label, &requested_ps);
		if (ret)
			return ret;
		ret = psm_adjust_power_state_dynamic(hwmgr, false, requested_ps);
		break;
	}
	case AMD_PP_TASK_COMPLETE_INIT:
	case AMD_PP_TASK_READJUST_POWER_STATE:
		ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
		break;
	default:
		break;
	}
	return ret;
}

void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr)
{
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);

	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM);
	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEDPM);

#if defined(CONFIG_ACPI)
	if (amdgpu_acpi_is_pcie_performance_request_supported(hwmgr->adev))
		phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
#endif

	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
		PHM_PlatformCaps_DynamicPatchPowerState);

	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
		PHM_PlatformCaps_EnableSMU7ThermalManagement);

	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
			PHM_PlatformCaps_DynamicPowerManagement);

	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
					PHM_PlatformCaps_SMC);

	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
					PHM_PlatformCaps_DynamicUVDState);

	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
						PHM_PlatformCaps_FanSpeedInTableIsRPM);
	return;
}

int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr)
{
	if (hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK)
		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
			PHM_PlatformCaps_SclkDeepSleep);
	else
		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
			PHM_PlatformCaps_SclkDeepSleep);

	if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) {
		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
			    PHM_PlatformCaps_PowerContainment);
		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
			PHM_PlatformCaps_CAC);
	} else {
		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
			    PHM_PlatformCaps_PowerContainment);
		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
			PHM_PlatformCaps_CAC);
	}

	if (hwmgr->feature_mask & PP_OVERDRIVE_MASK)
		hwmgr->od_enabled = true;

	return 0;
}

int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr)
{
	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
						PHM_PlatformCaps_EVV);
	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
						PHM_PlatformCaps_SQRamping);
	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
						PHM_PlatformCaps_RegulatorHot);

	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
					PHM_PlatformCaps_AutomaticDCTransition);

	if (hwmgr->chip_id != CHIP_POLARIS10)
		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
					PHM_PlatformCaps_SPLLShutdownSupport);

	if (hwmgr->chip_id != CHIP_POLARIS11) {
		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
							PHM_PlatformCaps_DBRamping);
		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
							PHM_PlatformCaps_TDRamping);
		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
							PHM_PlatformCaps_TCPRamping);
	}
	return 0;
}

int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr)
{
	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
						PHM_PlatformCaps_EVV);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
			PHM_PlatformCaps_SQRamping);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
			PHM_PlatformCaps_DBRamping);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
			PHM_PlatformCaps_TDRamping);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
			PHM_PlatformCaps_TCPRamping);
	return 0;
}

int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr)
{
	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
						PHM_PlatformCaps_EVV);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
			PHM_PlatformCaps_SQRamping);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
			PHM_PlatformCaps_DBRamping);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
			PHM_PlatformCaps_TDRamping);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
			PHM_PlatformCaps_TCPRamping);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
		      PHM_PlatformCaps_UVDPowerGating);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
		      PHM_PlatformCaps_VCEPowerGating);
	return 0;
}

int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr)
{
	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
						PHM_PlatformCaps_EVV);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
			PHM_PlatformCaps_SQRamping);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
			PHM_PlatformCaps_DBRamping);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
			PHM_PlatformCaps_TDRamping);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
			PHM_PlatformCaps_TCPRamping);
	return 0;
}

int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr)
{
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
			PHM_PlatformCaps_SQRamping);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
			PHM_PlatformCaps_DBRamping);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
			PHM_PlatformCaps_TDRamping);
	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
			PHM_PlatformCaps_TCPRamping);
	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
			PHM_PlatformCaps_MemorySpreadSpectrumSupport);
	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
			PHM_PlatformCaps_EngineSpreadSpectrumSupport);
	return 0;
}
Commit	Line	Data
3bace359 JZ	1	/*
	2	* Copyright 2015 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
7bd55429 HR	23
7bd55429 HR	24	#include "pp_debug.h"
f90dee20	25	#include <linux/delay.h>
3bace359 JZ	26	#include <linux/kernel.h>
3bace359 JZ	27	#include <linux/slab.h>
f90dee20	28	#include <linux/types.h>
2a5b64c9	29	#include <linux/pci.h>
bb06d7ef	30	#include <drm/amdgpu_drm.h>
3bace359 JZ	31	#include "power_state.h"
3bace359 JZ	32	#include "hwmgr.h"
8b41e7a0	33	#include "ppsmc.h"
9597f403	34	#include "amd_acpi.h"
df1e6394	35	#include "pp_psm.h"
8b41e7a0	36
b3b03052	37	extern const struct pp_smumgr_func ci_smu_funcs;
47ce4a9f	38	extern const struct pp_smumgr_func smu8_smu_funcs;
b3b03052 RZ	39	extern const struct pp_smumgr_func iceland_smu_funcs;
	40	extern const struct pp_smumgr_func tonga_smu_funcs;
	41	extern const struct pp_smumgr_func fiji_smu_funcs;
	42	extern const struct pp_smumgr_func polaris10_smu_funcs;
ac7822b0	43	extern const struct pp_smumgr_func vegam_smu_funcs;
b3b03052	44	extern const struct pp_smumgr_func vega10_smu_funcs;
2cac05de	45	extern const struct pp_smumgr_func vega12_smu_funcs;
c4256885	46	extern const struct pp_smumgr_func smu10_smu_funcs;
da958630	47	extern const struct pp_smumgr_func vega20_smu_funcs;
b3b03052	48
8e686279	49	extern int smu7_init_function_pointers(struct pp_hwmgr *hwmgr);
47ce4a9f	50	extern int smu8_init_function_pointers(struct pp_hwmgr *hwmgr);
8e686279	51	extern int vega10_hwmgr_init(struct pp_hwmgr *hwmgr);
2cac05de	52	extern int vega12_hwmgr_init(struct pp_hwmgr *hwmgr);
da958630	53	extern int vega20_hwmgr_init(struct pp_hwmgr *hwmgr);
8e686279 RZ	54	extern int smu10_init_function_pointers(struct pp_hwmgr *hwmgr);
8e686279 RZ	55
4be051ae	56	static int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr);
9597f403 RZ	57	static void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr);
9597f403 RZ	58	static int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr);
b859c207	59	static int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr);
fb044ed9	60	static int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr);
ab4f06d3	61	static int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr);
86457c3b	62	static int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr);
af223dfa	63
2a5b64c9	64
052fe96d RZ	65	static void hwmgr_init_workload_prority(struct pp_hwmgr *hwmgr)
052fe96d RZ	66	{
048b9b0f EQ	67	hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
	68	hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
	69	hwmgr->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
	70	hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
	71	hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
	72	hwmgr->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
052fe96d	73
048b9b0f EQ	74	hwmgr->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
	75	hwmgr->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
	76	hwmgr->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
	77	hwmgr->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
	78	hwmgr->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
	79	hwmgr->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
052fe96d RZ	80	}
052fe96d RZ	81
b905090d	82	int hwmgr_early_init(struct pp_hwmgr *hwmgr)
3bace359	83	{
ba8ab90e	84	if (!hwmgr)
3bace359 JZ	85	return -EINVAL;
3bace359 JZ	86
3bace359	87	hwmgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
b1c8e1e2	88	hwmgr->pp_table_version = PP_TABLE_V1;
0d12570a	89	hwmgr->dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
8621bbbb	90	hwmgr->request_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
9597f403 RZ	91	hwmgr_init_default_caps(hwmgr);
9597f403 RZ	92	hwmgr_set_user_specify_caps(hwmgr);
1ab47204	93	hwmgr->fan_ctrl_is_in_default_mode = true;
052fe96d	94	hwmgr_init_workload_prority(hwmgr);
3bace359 JZ	95
3bace359 JZ	96	switch (hwmgr->chip_family) {
86457c3b	97	case AMDGPU_FAMILY_CI:
b3b03052	98	hwmgr->smumgr_funcs = &ci_smu_funcs;
86457c3b RZ	99	ci_set_asic_special_caps(hwmgr);
86457c3b RZ	100	hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK \|
1dedc623 HR	101	PP_ENABLE_GFX_CG_THRU_SMU \|
1dedc623 HR	102	PP_GFXOFF_MASK);
86457c3b	103	hwmgr->pp_table_version = PP_TABLE_V0;
b7e919b9	104	hwmgr->od_enabled = false;
86457c3b RZ	105	smu7_init_function_pointers(hwmgr);
86457c3b RZ	106	break;
bb06d7ef	107	case AMDGPU_FAMILY_CZ:
b7e919b9	108	hwmgr->od_enabled = false;
47ce4a9f	109	hwmgr->smumgr_funcs = &smu8_smu_funcs;
1dedc623	110	hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
47ce4a9f	111	smu8_init_function_pointers(hwmgr);
bdecc20a	112	break;
bb06d7ef	113	case AMDGPU_FAMILY_VI:
1dedc623	114	hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
c82baa28	115	switch (hwmgr->chip_id) {
025f8bfb	116	case CHIP_TOPAZ:
b3b03052	117	hwmgr->smumgr_funcs = &iceland_smu_funcs;
ab4f06d3	118	topaz_set_asic_special_caps(hwmgr);
4c696ecf	119	hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK \|
ab4f06d3 RZ	120	PP_ENABLE_GFX_CG_THRU_SMU);
ab4f06d3 RZ	121	hwmgr->pp_table_version = PP_TABLE_V0;
b7e919b9	122	hwmgr->od_enabled = false;
025f8bfb	123	break;
c82baa28	124	case CHIP_TONGA:
b3b03052	125	hwmgr->smumgr_funcs = &tonga_smu_funcs;
fb044ed9	126	tonga_set_asic_special_caps(hwmgr);
4c696ecf	127	hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK;
c82baa28	128	break;
aabcb7c1	129	case CHIP_FIJI:
b3b03052	130	hwmgr->smumgr_funcs = &fiji_smu_funcs;
b859c207	131	fiji_set_asic_special_caps(hwmgr);
4c696ecf	132	hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK \|
b859c207	133	PP_ENABLE_GFX_CG_THRU_SMU);
aabcb7c1	134	break;
2cc0c0b5 FC	135	case CHIP_POLARIS11:
2cc0c0b5 FC	136	case CHIP_POLARIS10:
f4309526	137	case CHIP_POLARIS12:
b3b03052	138	hwmgr->smumgr_funcs = &polaris10_smu_funcs;
4be051ae RZ	139	polaris_set_asic_special_caps(hwmgr);
4be051ae RZ	140	hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);
b83c4ab9	141	break;
ac7822b0 EH	142	case CHIP_VEGAM:
	143	hwmgr->smumgr_funcs = &vegam_smu_funcs;
	144	polaris_set_asic_special_caps(hwmgr);
	145	hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);
	146	break;
c82baa28	147	default:
	148	return -EINVAL;
	149	}
a5b580e1	150	smu7_init_function_pointers(hwmgr);
c82baa28	151	break;
f83a9991 EH	152	case AMDGPU_FAMILY_AI:
	153	switch (hwmgr->chip_id) {
	154	case CHIP_VEGA10:
3f2e6bf8	155	hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
b3b03052	156	hwmgr->smumgr_funcs = &vega10_smu_funcs;
f83a9991 EH	157	vega10_hwmgr_init(hwmgr);
f83a9991 EH	158	break;
2cac05de EQ	159	case CHIP_VEGA12:
	160	hwmgr->smumgr_funcs = &vega12_smu_funcs;
	161	vega12_hwmgr_init(hwmgr);
	162	break;
da958630 EQ	163	case CHIP_VEGA20:
	164	hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
	165	hwmgr->smumgr_funcs = &vega20_smu_funcs;
	166	vega20_hwmgr_init(hwmgr);
	167	break;
f83a9991 EH	168	default:
	169	return -EINVAL;
	170	}
	171	break;
a960d61c RZ	172	case AMDGPU_FAMILY_RV:
	173	switch (hwmgr->chip_id) {
	174	case CHIP_RAVEN:
b7e919b9	175	hwmgr->od_enabled = false;
c4256885 RZ	176	hwmgr->smumgr_funcs = &smu10_smu_funcs;
c4256885 RZ	177	smu10_init_function_pointers(hwmgr);
a960d61c RZ	178	break;
	179	default:
	180	return -EINVAL;
	181	}
	182	break;
3bace359 JZ	183	default:
	184	return -EINVAL;
	185	}
	186
3bace359 JZ	187	return 0;
	188	}
	189
ba8ab90e RZ	190	int hwmgr_sw_init(struct pp_hwmgr *hwmgr)
	191	{
	192	if (!hwmgr\|\| !hwmgr->smumgr_funcs \|\| !hwmgr->smumgr_funcs->smu_init)
	193	return -EINVAL;
	194
	195	phm_register_irq_handlers(hwmgr);
	196
	197	return hwmgr->smumgr_funcs->smu_init(hwmgr);
	198	}
	199
	200
	201	int hwmgr_sw_fini(struct pp_hwmgr *hwmgr)
	202	{
	203	if (hwmgr && hwmgr->smumgr_funcs && hwmgr->smumgr_funcs->smu_fini)
	204	hwmgr->smumgr_funcs->smu_fini(hwmgr);
	205
	206	return 0;
	207	}
	208
b905090d	209	int hwmgr_hw_init(struct pp_hwmgr *hwmgr)
1c863802	210	{
1c863802 RZ	211	int ret = 0;
1c863802 RZ	212
ba8ab90e RZ	213	if (!hwmgr->pm_en)
	214	return 0;
	215
	216	if (!hwmgr->pptable_func \|\|
	217	!hwmgr->pptable_func->pptable_init \|\|
	218	!hwmgr->hwmgr_func->backend_init) {
	219	hwmgr->pm_en = false;
ba8ab90e RZ	220	pr_info("dpm not supported \n");
	221	return 0;
	222	}
48fad3af	223
1c863802 RZ	224	ret = hwmgr->pptable_func->pptable_init(hwmgr);
	225	if (ret)
	226	goto err;
	227
fc5a136d RZ	228	((struct amdgpu_device *)hwmgr->adev)->pm.no_fan =
	229	hwmgr->thermal_controller.fanInfo.bNoFan;
	230
1c863802 RZ	231	ret = hwmgr->hwmgr_func->backend_init(hwmgr);
	232	if (ret)
	233	goto err1;
e1fa921f RZ	234	/* make sure dc limits are valid */
	235	if ((hwmgr->dyn_state.max_clock_voltage_on_dc.sclk == 0) \|\|
	236	(hwmgr->dyn_state.max_clock_voltage_on_dc.mclk == 0))
	237	hwmgr->dyn_state.max_clock_voltage_on_dc =
	238	hwmgr->dyn_state.max_clock_voltage_on_ac;
1c863802	239
df1e6394 RZ	240	ret = psm_init_power_state_table(hwmgr);
	241	if (ret)
	242	goto err2;
	243
	244	ret = phm_setup_asic(hwmgr);
1c863802 RZ	245	if (ret)
1c863802 RZ	246	goto err2;
df1e6394 RZ	247
	248	ret = phm_enable_dynamic_state_management(hwmgr);
	249	if (ret)
	250	goto err2;
8053e976	251	ret = phm_start_thermal_controller(hwmgr);
df1e6394 RZ	252	ret \|= psm_set_performance_states(hwmgr);
	253	if (ret)
	254	goto err2;
	255
b13aa109 RZ	256	((struct amdgpu_device *)hwmgr->adev)->pm.dpm_enabled = true;
b13aa109 RZ	257
3bace359	258	return 0;
1c863802 RZ	259	err2:
	260	if (hwmgr->hwmgr_func->backend_fini)
	261	hwmgr->hwmgr_func->backend_fini(hwmgr);
	262	err1:
	263	if (hwmgr->pptable_func->pptable_fini)
	264	hwmgr->pptable_func->pptable_fini(hwmgr);
	265	err:
1c863802 RZ	266	return ret;
	267	}
	268
b905090d	269	int hwmgr_hw_fini(struct pp_hwmgr *hwmgr)
1c863802	270	{
ba8ab90e RZ	271	if (!hwmgr \|\| !hwmgr->pm_en)
ba8ab90e RZ	272	return 0;
1c863802	273
df1e6394 RZ	274	phm_stop_thermal_controller(hwmgr);
df1e6394 RZ	275	psm_set_boot_states(hwmgr);
df1e6394 RZ	276	psm_adjust_power_state_dynamic(hwmgr, false, NULL);
	277	phm_disable_dynamic_state_management(hwmgr);
	278	phm_disable_clock_power_gatings(hwmgr);
	279
1c863802 RZ	280	if (hwmgr->hwmgr_func->backend_fini)
	281	hwmgr->hwmgr_func->backend_fini(hwmgr);
	282	if (hwmgr->pptable_func->pptable_fini)
	283	hwmgr->pptable_func->pptable_fini(hwmgr);
df1e6394 RZ	284	return psm_fini_power_state_table(hwmgr);
	285	}
	286
ba8ab90e	287	int hwmgr_suspend(struct pp_hwmgr *hwmgr)
df1e6394	288	{
df1e6394 RZ	289	int ret = 0;
df1e6394 RZ	290
ba8ab90e RZ	291	if (!hwmgr \|\| !hwmgr->pm_en)
ba8ab90e RZ	292	return 0;
df1e6394	293
df1e6394 RZ	294	phm_disable_smc_firmware_ctf(hwmgr);
	295	ret = psm_set_boot_states(hwmgr);
	296	if (ret)
	297	return ret;
	298	ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
	299	if (ret)
	300	return ret;
	301	ret = phm_power_down_asic(hwmgr);
	302
	303	return ret;
	304	}
	305
ba8ab90e	306	int hwmgr_resume(struct pp_hwmgr *hwmgr)
df1e6394	307	{
df1e6394 RZ	308	int ret = 0;
df1e6394 RZ	309
ba8ab90e	310	if (!hwmgr)
df1e6394 RZ	311	return -EINVAL;
df1e6394 RZ	312
ba8ab90e RZ	313	if (!hwmgr->pm_en)
	314	return 0;
	315
df1e6394 RZ	316	ret = phm_setup_asic(hwmgr);
	317	if (ret)
	318	return ret;
	319
	320	ret = phm_enable_dynamic_state_management(hwmgr);
	321	if (ret)
	322	return ret;
8053e976	323	ret = phm_start_thermal_controller(hwmgr);
df1e6394 RZ	324	ret \|= psm_set_performance_states(hwmgr);
	325	if (ret)
	326	return ret;
	327
	328	ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
	329
	330	return ret;
3bace359 JZ	331	}
3bace359 JZ	332
df1e6394 RZ	333	static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type state)
	334	{
	335	switch (state) {
	336	case POWER_STATE_TYPE_BATTERY:
	337	return PP_StateUILabel_Battery;
	338	case POWER_STATE_TYPE_BALANCED:
	339	return PP_StateUILabel_Balanced;
	340	case POWER_STATE_TYPE_PERFORMANCE:
	341	return PP_StateUILabel_Performance;
	342	default:
	343	return PP_StateUILabel_None;
	344	}
	345	}
	346
b905090d	347	int hwmgr_handle_task(struct pp_hwmgr *hwmgr, enum amd_pp_task task_id,
39199b80	348	enum amd_pm_state_type *user_state)
df1e6394 RZ	349	{
df1e6394 RZ	350	int ret = 0;
df1e6394	351
b905090d	352	if (hwmgr == NULL)
df1e6394 RZ	353	return -EINVAL;
df1e6394 RZ	354
df1e6394 RZ	355	switch (task_id) {
df1e6394 RZ	356	case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
10cb3e6b EQ	357	ret = phm_pre_display_configuration_changed(hwmgr);
	358	if (ret)
	359	return ret;
df1e6394 RZ	360	ret = phm_set_cpu_power_state(hwmgr);
	361	if (ret)
	362	return ret;
	363	ret = psm_set_performance_states(hwmgr);
	364	if (ret)
	365	return ret;
	366	ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
	367	break;
	368	case AMD_PP_TASK_ENABLE_USER_STATE:
	369	{
df1e6394	370	enum PP_StateUILabel requested_ui_label;
64d03abe	371	struct pp_power_state *requested_ps = NULL;
df1e6394	372
39199b80	373	if (user_state == NULL) {
df1e6394 RZ	374	ret = -EINVAL;
	375	break;
	376	}
df1e6394	377
39199b80	378	requested_ui_label = power_state_convert(*user_state);
64d03abe	379	ret = psm_set_user_performance_state(hwmgr, requested_ui_label, &requested_ps);
df1e6394 RZ	380	if (ret)
	381	return ret;
	382	ret = psm_adjust_power_state_dynamic(hwmgr, false, requested_ps);
	383	break;
	384	}
	385	case AMD_PP_TASK_COMPLETE_INIT:
	386	case AMD_PP_TASK_READJUST_POWER_STATE:
	387	ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
	388	break;
	389	default:
	390	break;
	391	}
	392	return ret;
	393	}
9597f403 RZ	394
	395	void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr)
	396	{
9597f403 RZ	397	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
9597f403 RZ	398
9597f403 RZ	399	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM);
	400	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEDPM);
	401
37a94791	402	#if defined(CONFIG_ACPI)
e1deba28	403	if (amdgpu_acpi_is_pcie_performance_request_supported(hwmgr->adev))
9597f403	404	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
37a94791	405	#endif
9597f403 RZ	406
	407	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
	408	PHM_PlatformCaps_DynamicPatchPowerState);
	409
9597f403 RZ	410	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
	411	PHM_PlatformCaps_EnableSMU7ThermalManagement);
	412
	413	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
	414	PHM_PlatformCaps_DynamicPowerManagement);
	415
9597f403 RZ	416	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
	417	PHM_PlatformCaps_SMC);
	418
	419	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
	420	PHM_PlatformCaps_DynamicUVDState);
	421
	422	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
	423	PHM_PlatformCaps_FanSpeedInTableIsRPM);
9597f403 RZ	424	return;
	425	}
	426
	427	int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr)
	428	{
6f4dc24a	429	if (hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK)
9597f403 RZ	430	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
	431	PHM_PlatformCaps_SclkDeepSleep);
	432	else
	433	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
	434	PHM_PlatformCaps_SclkDeepSleep);
	435
6f4dc24a	436	if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) {
9597f403 RZ	437	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
9597f403 RZ	438	PHM_PlatformCaps_PowerContainment);
a08d8c92 RZ	439	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
	440	PHM_PlatformCaps_CAC);
	441	} else {
9597f403 RZ	442	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
9597f403 RZ	443	PHM_PlatformCaps_PowerContainment);
a08d8c92 RZ	444	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
	445	PHM_PlatformCaps_CAC);
	446	}
9597f403	447
11f64ff5 RZ	448	if (hwmgr->feature_mask & PP_OVERDRIVE_MASK)
	449	hwmgr->od_enabled = true;
	450
9597f403 RZ	451	return 0;
	452	}
	453
4be051ae RZ	454	int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr)
4be051ae RZ	455	{
86457c3b RZ	456	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
86457c3b RZ	457	PHM_PlatformCaps_EVV);
4be051ae RZ	458	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4be051ae RZ	459	PHM_PlatformCaps_SQRamping);
4be051ae RZ	460	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
	461	PHM_PlatformCaps_RegulatorHot);
	462
	463	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
	464	PHM_PlatformCaps_AutomaticDCTransition);
	465
e31e8a22	466	if (hwmgr->chip_id != CHIP_POLARIS10)
4be051ae RZ	467	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4be051ae RZ	468	PHM_PlatformCaps_SPLLShutdownSupport);
e31e8a22 RZ	469
	470	if (hwmgr->chip_id != CHIP_POLARIS11) {
	471	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
	472	PHM_PlatformCaps_DBRamping);
	473	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
	474	PHM_PlatformCaps_TDRamping);
	475	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
	476	PHM_PlatformCaps_TCPRamping);
	477	}
4be051ae RZ	478	return 0;
	479	}
	480
b859c207 RZ	481	int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr)
b859c207 RZ	482	{
86457c3b RZ	483	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
86457c3b RZ	484	PHM_PlatformCaps_EVV);
b859c207 RZ	485	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
	486	PHM_PlatformCaps_SQRamping);
	487	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
	488	PHM_PlatformCaps_DBRamping);
	489	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
	490	PHM_PlatformCaps_TDRamping);
	491	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
	492	PHM_PlatformCaps_TCPRamping);
b859c207 RZ	493	return 0;
	494	}
	495
fb044ed9 RZ	496	int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr)
fb044ed9 RZ	497	{
86457c3b RZ	498	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
86457c3b RZ	499	PHM_PlatformCaps_EVV);
fb044ed9 RZ	500	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
	501	PHM_PlatformCaps_SQRamping);
	502	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
	503	PHM_PlatformCaps_DBRamping);
	504	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
	505	PHM_PlatformCaps_TDRamping);
	506	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
	507	PHM_PlatformCaps_TCPRamping);
	508
	509	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
	510	PHM_PlatformCaps_UVDPowerGating);
	511	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
	512	PHM_PlatformCaps_VCEPowerGating);
fb044ed9 RZ	513	return 0;
fb044ed9 RZ	514	}
ab4f06d3 RZ	515
ab4f06d3 RZ	516	int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr)
86457c3b RZ	517	{
	518	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
	519	PHM_PlatformCaps_EVV);
	520	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
	521	PHM_PlatformCaps_SQRamping);
	522	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
	523	PHM_PlatformCaps_DBRamping);
	524	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
	525	PHM_PlatformCaps_TDRamping);
	526	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
	527	PHM_PlatformCaps_TCPRamping);
	528	return 0;
	529	}
	530
	531	int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr)
ab4f06d3 RZ	532	{
	533	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
	534	PHM_PlatformCaps_SQRamping);
	535	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
	536	PHM_PlatformCaps_DBRamping);
	537	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
	538	PHM_PlatformCaps_TDRamping);
	539	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
	540	PHM_PlatformCaps_TCPRamping);
ab4f06d3	541	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
86457c3b RZ	542	PHM_PlatformCaps_MemorySpreadSpectrumSupport);
	543	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
	544	PHM_PlatformCaps_EngineSpreadSpectrumSupport);
ab4f06d3 RZ	545	return 0;
ab4f06d3 RZ	546	}