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drm/amd/powerplay: fix some initialize error on polaris10.
[mirror_ubuntu-eoan-kernel.git] / drivers / gpu / drm / amd / powerplay / hwmgr / polaris10_hwmgr.c
CommitLineData
a23eefa2
RZ		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/module.h>
24#include <linux/slab.h>
25#include <linux/fb.h>
ae17c999 26#include <asm/div64.h>
a23eefa2
RZ		 27#include "linux/delay.h"
28#include "pp_acpi.h"
29#include "hwmgr.h"
2cc0c0b5
FC		 30#include "polaris10_hwmgr.h"
31#include "polaris10_powertune.h"
32#include "polaris10_dyn_defaults.h"
33#include "polaris10_smumgr.h"
a23eefa2
RZ		 34#include "pp_debug.h"
35#include "ppatomctrl.h"
36#include "atombios.h"
37#include "tonga_pptable.h"
38#include "pppcielanes.h"
39#include "amd_pcie_helpers.h"
40#include "hardwaremanager.h"
41#include "tonga_processpptables.h"
42#include "cgs_common.h"
43#include "smu74.h"
44#include "smu_ucode_xfer_vi.h"
45#include "smu74_discrete.h"
46#include "smu/smu_7_1_3_d.h"
47#include "smu/smu_7_1_3_sh_mask.h"
48#include "gmc/gmc_8_1_d.h"
49#include "gmc/gmc_8_1_sh_mask.h"
50#include "oss/oss_3_0_d.h"
51#include "gca/gfx_8_0_d.h"
52#include "bif/bif_5_0_d.h"
53#include "bif/bif_5_0_sh_mask.h"
54#include "gmc/gmc_8_1_d.h"
55#include "gmc/gmc_8_1_sh_mask.h"
56#include "bif/bif_5_0_d.h"
57#include "bif/bif_5_0_sh_mask.h"
58#include "dce/dce_10_0_d.h"
59#include "dce/dce_10_0_sh_mask.h"
60
2cc0c0b5
FC		 61#include "polaris10_thermal.h"
62#include "polaris10_clockpowergating.h"
eede5262 63
a23eefa2
RZ		 64#define MC_CG_ARB_FREQ_F0 0x0a
65#define MC_CG_ARB_FREQ_F1 0x0b
66#define MC_CG_ARB_FREQ_F2 0x0c
67#define MC_CG_ARB_FREQ_F3 0x0d
68
69#define MC_CG_SEQ_DRAMCONF_S0 0x05
70#define MC_CG_SEQ_DRAMCONF_S1 0x06
71#define MC_CG_SEQ_YCLK_SUSPEND 0x04
72#define MC_CG_SEQ_YCLK_RESUME 0x0a
73
74
75#define SMC_RAM_END 0x40000
76
77#define SMC_CG_IND_START 0xc0030000
78#define SMC_CG_IND_END 0xc0040000
79
80#define VOLTAGE_SCALE 4
81#define VOLTAGE_VID_OFFSET_SCALE1 625
82#define VOLTAGE_VID_OFFSET_SCALE2 100
83
84#define VDDC_VDDCI_DELTA 200
85
86#define MEM_FREQ_LOW_LATENCY 25000
87#define MEM_FREQ_HIGH_LATENCY 80000
88
89#define MEM_LATENCY_HIGH 45
90#define MEM_LATENCY_LOW 35
91#define MEM_LATENCY_ERR 0xFFFF
92
93#define MC_SEQ_MISC0_GDDR5_SHIFT 28
94#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
95#define MC_SEQ_MISC0_GDDR5_VALUE 5
96
97
98#define PCIE_BUS_CLK 10000
99#define TCLK (PCIE_BUS_CLK / 10)
100
101
2cc0c0b5 102uint16_t polaris10_clock_stretcher_lookup_table[2][4] = { {600, 1050, 3, 0},
a23eefa2
RZ		 103 {600, 1050, 6, 1} };
104
105/* [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */
2cc0c0b5 106uint32_t polaris10_clock_stretcher_ddt_table[2][4][4] = { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
a23eefa2
RZ		 107 { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
108
109/* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */
2cc0c0b5 110uint8_t polaris10_clock_stretch_amount_conversion[2][6] = { {0, 1, 3, 2, 4, 5},
a23eefa2
RZ		 111 {0, 2, 4, 5, 6, 5} };
112
113/** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
114enum DPM_EVENT_SRC {
115 DPM_EVENT_SRC_ANALOG = 0,
116 DPM_EVENT_SRC_EXTERNAL = 1,
117 DPM_EVENT_SRC_DIGITAL = 2,
118 DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
119 DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
120};
121
2cc0c0b5 122const unsigned long PhwPolaris10_Magic = (unsigned long)(PHM_VIslands_Magic);
a23eefa2 123
2cc0c0b5 124struct polaris10_power_state *cast_phw_polaris10_power_state(
a23eefa2
RZ		 125 struct pp_hw_power_state *hw_ps)
126{
2cc0c0b5 127 PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
a23eefa2
RZ		 128 "Invalid Powerstate Type!",
129 return NULL);
130
2cc0c0b5 131 return (struct polaris10_power_state *)hw_ps;
a23eefa2
RZ		 132}
133
2cc0c0b5 134const struct polaris10_power_state *cast_const_phw_polaris10_power_state(
a23eefa2
RZ		 135 const struct pp_hw_power_state *hw_ps)
136{
2cc0c0b5 137 PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
a23eefa2
RZ		 138 "Invalid Powerstate Type!",
139 return NULL);
140
2cc0c0b5 141 return (const struct polaris10_power_state *)hw_ps;
a23eefa2
RZ		 142}
143
2cc0c0b5 144static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 145{
146 return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
147 CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
148 ? true : false;
149}
150
151/**
152 * Find the MC microcode version and store it in the HwMgr struct
153 *
154 * @param hwmgr the address of the powerplay hardware manager.
155 * @return always 0
156 */
157int phm_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
158{
159 cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
160
161 hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
162
163 return 0;
164}
165
166uint16_t phm_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
167{
168 uint32_t speedCntl = 0;
169
170 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
171 speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
172 ixPCIE_LC_SPEED_CNTL);
173 return((uint16_t)PHM_GET_FIELD(speedCntl,
174 PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
175}
176
177int phm_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
178{
179 uint32_t link_width;
180
181 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
182 link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
183 PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
184
185 PP_ASSERT_WITH_CODE((7 >= link_width),
186 "Invalid PCIe lane width!", return 0);
187
188 return decode_pcie_lane_width(link_width);
189}
190
191void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr)
192{
193 struct phm_ppt_v1_information *table_info =
194 (struct phm_ppt_v1_information *)hwmgr->pptable;
195 struct phm_clock_voltage_dependency_table *table =
196 table_info->vddc_dep_on_dal_pwrl;
197 struct phm_ppt_v1_clock_voltage_dependency_table *vddc_table;
198 enum PP_DAL_POWERLEVEL dal_power_level = hwmgr->dal_power_level;
199 uint32_t req_vddc = 0, req_volt, i;
200
201 if (!table && !(dal_power_level >= PP_DAL_POWERLEVEL_ULTRALOW &&
202 dal_power_level <= PP_DAL_POWERLEVEL_PERFORMANCE))
203 return;
204
205 for (i = 0; i < table->count; i++) {
206 if (dal_power_level == table->entries[i].clk) {
207 req_vddc = table->entries[i].v;
208 break;
209 }
210 }
211
212 vddc_table = table_info->vdd_dep_on_sclk;
213 for (i = 0; i < vddc_table->count; i++) {
214 if (req_vddc <= vddc_table->entries[i].vddc) {
215 req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE)
216 << VDDC_SHIFT;
217 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
218 PPSMC_MSG_VddC_Request, req_volt);
219 return;
220 }
221 }
222 printk(KERN_ERR "DAL requested level can not"
223 " found a available voltage in VDDC DPM Table \n");
224}
225
e85c7d66 226/**
227* Enable voltage control
228*
229* @param pHwMgr the address of the powerplay hardware manager.
230* @return always PP_Result_OK
231*/
2cc0c0b5 232int polaris10_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
e85c7d66 233{
234 PP_ASSERT_WITH_CODE(
235 (hwmgr->smumgr->smumgr_funcs->send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable) == 0),
236 "Failed to enable voltage DPM during DPM Start Function!",
237 return 1;
238 );
239
240 return 0;
241}
a23eefa2
RZ		 242
243/**
244* Checks if we want to support voltage control
245*
246* @param hwmgr the address of the powerplay hardware manager.
247*/
2cc0c0b5 248static bool polaris10_voltage_control(const struct pp_hwmgr *hwmgr)
a23eefa2 249{
2cc0c0b5
FC		 250 const struct polaris10_hwmgr *data =
251 (const struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2 252
2cc0c0b5 253 return (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control);
a23eefa2
RZ		 254}
255
256/**
257* Enable voltage control
258*
259* @param hwmgr the address of the powerplay hardware manager.
260* @return always 0
261*/
2cc0c0b5 262static int polaris10_enable_voltage_control(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 263{
264 /* enable voltage control */
265 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
266 GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
267
268 return 0;
269}
270
271/**
272* Create Voltage Tables.
273*
274* @param hwmgr the address of the powerplay hardware manager.
275* @return always 0
276*/
2cc0c0b5 277static int polaris10_construct_voltage_tables(struct pp_hwmgr *hwmgr)
a23eefa2 278{
2cc0c0b5 279 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 280 struct phm_ppt_v1_information *table_info =
281 (struct phm_ppt_v1_information *)hwmgr->pptable;
282 int result;
283
2cc0c0b5 284 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
a23eefa2
RZ		 285 result = atomctrl_get_voltage_table_v3(hwmgr,
286 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT,
287 &(data->mvdd_voltage_table));
288 PP_ASSERT_WITH_CODE((0 == result),
289 "Failed to retrieve MVDD table.",
290 return result);
2cc0c0b5 291 } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
a23eefa2
RZ		 292 result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table),
293 table_info->vdd_dep_on_mclk);
294 PP_ASSERT_WITH_CODE((0 == result),
295 "Failed to retrieve SVI2 MVDD table from dependancy table.",
296 return result;);
297 }
298
2cc0c0b5 299 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
a23eefa2
RZ		 300 result = atomctrl_get_voltage_table_v3(hwmgr,
301 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
302 &(data->vddci_voltage_table));
303 PP_ASSERT_WITH_CODE((0 == result),
304 "Failed to retrieve VDDCI table.",
305 return result);
2cc0c0b5 306 } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
a23eefa2
RZ		 307 result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table),
308 table_info->vdd_dep_on_mclk);
309 PP_ASSERT_WITH_CODE((0 == result),
310 "Failed to retrieve SVI2 VDDCI table from dependancy table.",
311 return result);
312 }
313
2cc0c0b5 314 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
a23eefa2
RZ		 315 result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table),
316 table_info->vddc_lookup_table);
317 PP_ASSERT_WITH_CODE((0 == result),
318 "Failed to retrieve SVI2 VDDC table from lookup table.",
319 return result);
320 }
321
322 PP_ASSERT_WITH_CODE(
323 (data->vddc_voltage_table.count <= (SMU74_MAX_LEVELS_VDDC)),
324 "Too many voltage values for VDDC. Trimming to fit state table.",
325 phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDC,
326 &(data->vddc_voltage_table)));
327
328 PP_ASSERT_WITH_CODE(
329 (data->vddci_voltage_table.count <= (SMU74_MAX_LEVELS_VDDCI)),
330 "Too many voltage values for VDDCI. Trimming to fit state table.",
331 phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDCI,
332 &(data->vddci_voltage_table)));
333
334 PP_ASSERT_WITH_CODE(
335 (data->mvdd_voltage_table.count <= (SMU74_MAX_LEVELS_MVDD)),
336 "Too many voltage values for MVDD. Trimming to fit state table.",
337 phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_MVDD,
338 &(data->mvdd_voltage_table)));
339
340 return 0;
341}
342
343/**
344* Programs static screed detection parameters
345*
346* @param hwmgr the address of the powerplay hardware manager.
347* @return always 0
348*/
2cc0c0b5 349static int polaris10_program_static_screen_threshold_parameters(
a23eefa2
RZ		 350 struct pp_hwmgr *hwmgr)
351{
2cc0c0b5 352 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 353
354 /* Set static screen threshold unit */
355 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
356 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
357 data->static_screen_threshold_unit);
358 /* Set static screen threshold */
359 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
360 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
361 data->static_screen_threshold);
362
363 return 0;
364}
365
366/**
367* Setup display gap for glitch free memory clock switching.
368*
369* @param hwmgr the address of the powerplay hardware manager.
370* @return always 0
371*/
2cc0c0b5 372static int polaris10_enable_display_gap(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 373{
374 uint32_t display_gap =
375 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
376 ixCG_DISPLAY_GAP_CNTL);
377
378 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
379 DISP_GAP, DISPLAY_GAP_IGNORE);
380
381 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
382 DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
383
384 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
385 ixCG_DISPLAY_GAP_CNTL, display_gap);
386
387 return 0;
388}
389
390/**
391* Programs activity state transition voting clients
392*
393* @param hwmgr the address of the powerplay hardware manager.
394* @return always 0
395*/
2cc0c0b5 396static int polaris10_program_voting_clients(struct pp_hwmgr *hwmgr)
a23eefa2 397{
2cc0c0b5 398 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 399
400 /* Clear reset for voting clients before enabling DPM */
401 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
402 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
403 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
404 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
405
406 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
407 ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
408 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
409 ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
410 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
411 ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
412 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
413 ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
414 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
415 ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
416 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
417 ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
418 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
419 ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
420 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
421 ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
422
423 return 0;
424}
425
426/**
427* Get the location of various tables inside the FW image.
428*
429* @param hwmgr the address of the powerplay hardware manager.
430* @return always 0
431*/
2cc0c0b5 432static int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
a23eefa2 433{
2cc0c0b5
FC		 434 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
435 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
a23eefa2
RZ		 436 uint32_t tmp;
437 int result;
438 bool error = false;
439
2cc0c0b5 440 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
a23eefa2
RZ		 441 SMU7_FIRMWARE_HEADER_LOCATION +
442 offsetof(SMU74_Firmware_Header, DpmTable),
443 &tmp, data->sram_end);
444
445 if (0 == result)
446 data->dpm_table_start = tmp;
447
448 error |= (0 != result);
449
2cc0c0b5 450 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
a23eefa2
RZ		 451 SMU7_FIRMWARE_HEADER_LOCATION +
452 offsetof(SMU74_Firmware_Header, SoftRegisters),
453 &tmp, data->sram_end);
454
455 if (!result) {
456 data->soft_regs_start = tmp;
457 smu_data->soft_regs_start = tmp;
458 }
459
460 error |= (0 != result);
461
2cc0c0b5 462 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
a23eefa2
RZ		 463 SMU7_FIRMWARE_HEADER_LOCATION +
464 offsetof(SMU74_Firmware_Header, mcRegisterTable),
465 &tmp, data->sram_end);
466
467 if (!result)
468 data->mc_reg_table_start = tmp;
469
2cc0c0b5 470 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
a23eefa2
RZ		 471 SMU7_FIRMWARE_HEADER_LOCATION +
472 offsetof(SMU74_Firmware_Header, FanTable),
473 &tmp, data->sram_end);
474
475 if (!result)
476 data->fan_table_start = tmp;
477
478 error |= (0 != result);
479
2cc0c0b5 480 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
a23eefa2
RZ		 481 SMU7_FIRMWARE_HEADER_LOCATION +
482 offsetof(SMU74_Firmware_Header, mcArbDramTimingTable),
483 &tmp, data->sram_end);
484
485 if (!result)
486 data->arb_table_start = tmp;
487
488 error |= (0 != result);
489
2cc0c0b5 490 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
a23eefa2
RZ		 491 SMU7_FIRMWARE_HEADER_LOCATION +
492 offsetof(SMU74_Firmware_Header, Version),
493 &tmp, data->sram_end);
494
495 if (!result)
496 hwmgr->microcode_version_info.SMC = tmp;
497
498 error |= (0 != result);
499
500 return error ? -1 : 0;
501}
502
503/* Copy one arb setting to another and then switch the active set.
504 * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
505 */
2cc0c0b5 506static int polaris10_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 507 uint32_t arb_src, uint32_t arb_dest)
508{
509 uint32_t mc_arb_dram_timing;
510 uint32_t mc_arb_dram_timing2;
511 uint32_t burst_time;
512 uint32_t mc_cg_config;
513
514 switch (arb_src) {
515 case MC_CG_ARB_FREQ_F0:
516 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
517 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
518 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
519 break;
520 case MC_CG_ARB_FREQ_F1:
521 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
522 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
523 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
524 break;
525 default:
526 return -EINVAL;
527 }
528
529 switch (arb_dest) {
530 case MC_CG_ARB_FREQ_F0:
531 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
532 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
533 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
534 break;
535 case MC_CG_ARB_FREQ_F1:
536 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
537 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
538 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
539 break;
540 default:
541 return -EINVAL;
542 }
543
544 mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
545 mc_cg_config |= 0x0000000F;
546 cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
547 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
548
549 return 0;
550}
551
552/**
553* Initial switch from ARB F0->F1
554*
555* @param hwmgr the address of the powerplay hardware manager.
556* @return always 0
557* This function is to be called from the SetPowerState table.
558*/
2cc0c0b5 559static int polaris10_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
a23eefa2 560{
2cc0c0b5 561 return polaris10_copy_and_switch_arb_sets(hwmgr,
a23eefa2
RZ		 562 MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
563}
564
2cc0c0b5 565static int polaris10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
a23eefa2 566{
2cc0c0b5 567 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 568 struct phm_ppt_v1_information *table_info =
569 (struct phm_ppt_v1_information *)(hwmgr->pptable);
570 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
571 uint32_t i, max_entry;
572
573 PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
574 data->use_pcie_power_saving_levels), "No pcie performance levels!",
575 return -EINVAL);
576
577 if (data->use_pcie_performance_levels &&
578 !data->use_pcie_power_saving_levels) {
579 data->pcie_gen_power_saving = data->pcie_gen_performance;
580 data->pcie_lane_power_saving = data->pcie_lane_performance;
581 } else if (!data->use_pcie_performance_levels &&
582 data->use_pcie_power_saving_levels) {
583 data->pcie_gen_performance = data->pcie_gen_power_saving;
584 data->pcie_lane_performance = data->pcie_lane_power_saving;
585 }
586
587 phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
588 SMU74_MAX_LEVELS_LINK,
589 MAX_REGULAR_DPM_NUMBER);
590
591 if (pcie_table != NULL) {
592 /* max_entry is used to make sure we reserve one PCIE level
593 * for boot level (fix for A+A PSPP issue).
594 * If PCIE table from PPTable have ULV entry + 8 entries,
595 * then ignore the last entry.*/
596 max_entry = (SMU74_MAX_LEVELS_LINK < pcie_table->count) ?
597 SMU74_MAX_LEVELS_LINK : pcie_table->count;
598 for (i = 1; i < max_entry; i++) {
599 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
600 get_pcie_gen_support(data->pcie_gen_cap,
601 pcie_table->entries[i].gen_speed),
602 get_pcie_lane_support(data->pcie_lane_cap,
603 pcie_table->entries[i].lane_width));
604 }
605 data->dpm_table.pcie_speed_table.count = max_entry - 1;
e85c7d66 606
607 /* Setup BIF_SCLK levels */
608 for (i = 0; i < max_entry; i++)
609 data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
a23eefa2
RZ		 610 } else {
611 /* Hardcode Pcie Table */
612 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
613 get_pcie_gen_support(data->pcie_gen_cap,
614 PP_Min_PCIEGen),
615 get_pcie_lane_support(data->pcie_lane_cap,
616 PP_Max_PCIELane));
617 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
618 get_pcie_gen_support(data->pcie_gen_cap,
619 PP_Min_PCIEGen),
620 get_pcie_lane_support(data->pcie_lane_cap,
621 PP_Max_PCIELane));
622 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
623 get_pcie_gen_support(data->pcie_gen_cap,
624 PP_Max_PCIEGen),
625 get_pcie_lane_support(data->pcie_lane_cap,
626 PP_Max_PCIELane));
627 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
628 get_pcie_gen_support(data->pcie_gen_cap,
629 PP_Max_PCIEGen),
630 get_pcie_lane_support(data->pcie_lane_cap,
631 PP_Max_PCIELane));
632 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
633 get_pcie_gen_support(data->pcie_gen_cap,
634 PP_Max_PCIEGen),
635 get_pcie_lane_support(data->pcie_lane_cap,
636 PP_Max_PCIELane));
637 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
638 get_pcie_gen_support(data->pcie_gen_cap,
639 PP_Max_PCIEGen),
640 get_pcie_lane_support(data->pcie_lane_cap,
641 PP_Max_PCIELane));
642
643 data->dpm_table.pcie_speed_table.count = 6;
644 }
645 /* Populate last level for boot PCIE level, but do not increment count. */
646 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
647 data->dpm_table.pcie_speed_table.count,
648 get_pcie_gen_support(data->pcie_gen_cap,
649 PP_Min_PCIEGen),
650 get_pcie_lane_support(data->pcie_lane_cap,
651 PP_Max_PCIELane));
652
653 return 0;
654}
655
656/*
657 * This function is to initalize all DPM state tables
658 * for SMU7 based on the dependency table.
659 * Dynamic state patching function will then trim these
660 * state tables to the allowed range based
661 * on the power policy or external client requests,
662 * such as UVD request, etc.
663 */
2cc0c0b5 664int polaris10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
a23eefa2 665{
2cc0c0b5 666 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 667 struct phm_ppt_v1_information *table_info =
668 (struct phm_ppt_v1_information *)(hwmgr->pptable);
669 uint32_t i;
670
671 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
672 table_info->vdd_dep_on_sclk;
673 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
674 table_info->vdd_dep_on_mclk;
675
676 PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
677 "SCLK dependency table is missing. This table is mandatory",
678 return -EINVAL);
679 PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
680 "SCLK dependency table has to have is missing."
681 "This table is mandatory",
682 return -EINVAL);
683
684 PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
685 "MCLK dependency table is missing. This table is mandatory",
686 return -EINVAL);
687 PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
688 "MCLK dependency table has to have is missing."
689 "This table is mandatory",
690 return -EINVAL);
691
692 /* clear the state table to reset everything to default */
693 phm_reset_single_dpm_table(
694 &data->dpm_table.sclk_table, SMU74_MAX_LEVELS_GRAPHICS, MAX_REGULAR_DPM_NUMBER);
695 phm_reset_single_dpm_table(
696 &data->dpm_table.mclk_table, SMU74_MAX_LEVELS_MEMORY, MAX_REGULAR_DPM_NUMBER);
697
698
699 /* Initialize Sclk DPM table based on allow Sclk values */
700 data->dpm_table.sclk_table.count = 0;
701 for (i = 0; i < dep_sclk_table->count; i++) {
702 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value !=
703 dep_sclk_table->entries[i].clk) {
704
705 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
706 dep_sclk_table->entries[i].clk;
707
708 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled =
709 (i == 0) ? true : false;
710 data->dpm_table.sclk_table.count++;
711 }
712 }
713
714 /* Initialize Mclk DPM table based on allow Mclk values */
715 data->dpm_table.mclk_table.count = 0;
716 for (i = 0; i < dep_mclk_table->count; i++) {
717 if (i == 0 || data->dpm_table.mclk_table.dpm_levels
718 [data->dpm_table.mclk_table.count - 1].value !=
719 dep_mclk_table->entries[i].clk) {
720 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
721 dep_mclk_table->entries[i].clk;
722 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled =
723 (i == 0) ? true : false;
724 data->dpm_table.mclk_table.count++;
725 }
726 }
727
728 /* setup PCIE gen speed levels */
2cc0c0b5 729 polaris10_setup_default_pcie_table(hwmgr);
a23eefa2
RZ		 730
731 /* save a copy of the default DPM table */
732 memcpy(&(data->golden_dpm_table), &(data->dpm_table),
2cc0c0b5 733 sizeof(struct polaris10_dpm_table));
a23eefa2
RZ		 734
735 return 0;
736}
737
738uint8_t convert_to_vid(uint16_t vddc)
739{
740 return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
741}
742
743/**
744 * Mvdd table preparation for SMC.
745 *
746 * @param *hwmgr The address of the hardware manager.
747 * @param *table The SMC DPM table structure to be populated.
748 * @return 0
749 */
2cc0c0b5 750static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 751 SMU74_Discrete_DpmTable *table)
752{
2cc0c0b5 753 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 754 uint32_t count, level;
755
2cc0c0b5 756 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
a23eefa2
RZ		 757 count = data->mvdd_voltage_table.count;
758 if (count > SMU_MAX_SMIO_LEVELS)
759 count = SMU_MAX_SMIO_LEVELS;
760 for (level = 0; level < count; level++) {
761 table->SmioTable2.Pattern[level].Voltage =
762 PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
763 /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
764 table->SmioTable2.Pattern[level].Smio =
765 (uint8_t) level;
766 table->Smio[level] |=
767 data->mvdd_voltage_table.entries[level].smio_low;
768 }
769 table->SmioMask2 = data->vddci_voltage_table.mask_low;
770
771 table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
772 }
773
774 return 0;
775}
776
2cc0c0b5 777static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 778 struct SMU74_Discrete_DpmTable *table)
779{
780 uint32_t count, level;
2cc0c0b5 781 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 782
783 count = data->vddci_voltage_table.count;
784
2cc0c0b5 785 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
a23eefa2
RZ		 786 if (count > SMU_MAX_SMIO_LEVELS)
787 count = SMU_MAX_SMIO_LEVELS;
788 for (level = 0; level < count; ++level) {
789 table->SmioTable1.Pattern[level].Voltage =
790 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE);
791 table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
792
793 table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
794 }
795 }
796
797 table->SmioMask1 = data->vddci_voltage_table.mask_low;
798
799 return 0;
800}
801
802/**
803* Preparation of vddc and vddgfx CAC tables for SMC.
804*
805* @param hwmgr the address of the hardware manager
806* @param table the SMC DPM table structure to be populated
807* @return always 0
808*/
2cc0c0b5 809static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 810 struct SMU74_Discrete_DpmTable *table)
811{
812 uint32_t count;
813 uint8_t index;
2cc0c0b5 814 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 815 struct phm_ppt_v1_information *table_info =
816 (struct phm_ppt_v1_information *)(hwmgr->pptable);
817 struct phm_ppt_v1_voltage_lookup_table *lookup_table =
818 table_info->vddc_lookup_table;
819 /* tables is already swapped, so in order to use the value from it,
820 * we need to swap it back.
821 * We are populating vddc CAC data to BapmVddc table
822 * in split and merged mode
823 */
824 for (count = 0; count < lookup_table->count; count++) {
825 index = phm_get_voltage_index(lookup_table,
826 data->vddc_voltage_table.entries[count].value);
827 table->BapmVddcVidLoSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_low);
828 table->BapmVddcVidHiSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_mid);
829 table->BapmVddcVidHiSidd2[count] = convert_to_vid(lookup_table->entries[index].us_cac_high);
830 }
831
832 return 0;
833}
834
835/**
836* Preparation of voltage tables for SMC.
837*
838* @param hwmgr the address of the hardware manager
839* @param table the SMC DPM table structure to be populated
840* @return always 0
841*/
842
2cc0c0b5 843int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 844 struct SMU74_Discrete_DpmTable *table)
845{
2cc0c0b5
FC		 846 polaris10_populate_smc_vddci_table(hwmgr, table);
847 polaris10_populate_smc_mvdd_table(hwmgr, table);
848 polaris10_populate_cac_table(hwmgr, table);
a23eefa2
RZ		 849
850 return 0;
851}
852
2cc0c0b5 853static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 854 struct SMU74_Discrete_Ulv *state)
855{
2cc0c0b5 856 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 857 struct phm_ppt_v1_information *table_info =
858 (struct phm_ppt_v1_information *)(hwmgr->pptable);
859
860 state->CcPwrDynRm = 0;
861 state->CcPwrDynRm1 = 0;
862
863 state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
864 state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
865 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
866
867 state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
868
869 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
870 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
871 CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
872
873 return 0;
874}
875
2cc0c0b5 876static int polaris10_populate_ulv_state(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 877 struct SMU74_Discrete_DpmTable *table)
878{
2cc0c0b5 879 return polaris10_populate_ulv_level(hwmgr, &table->Ulv);
a23eefa2
RZ		 880}
881
2cc0c0b5 882static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 883 struct SMU74_Discrete_DpmTable *table)
884{
2cc0c0b5
FC		 885 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
886 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
a23eefa2
RZ		 887 int i;
888
889 /* Index (dpm_table->pcie_speed_table.count)
890 * is reserved for PCIE boot level. */
891 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
892 table->LinkLevel[i].PcieGenSpeed =
893 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
894 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
895 dpm_table->pcie_speed_table.dpm_levels[i].param1);
896 table->LinkLevel[i].EnabledForActivity = 1;
897 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
898 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
899 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
900 }
901
902 data->smc_state_table.LinkLevelCount =
903 (uint8_t)dpm_table->pcie_speed_table.count;
904 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
905 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
906
907 return 0;
908}
909
2cc0c0b5 910static uint32_t polaris10_get_xclk(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 911{
912 uint32_t reference_clock, tmp;
913 struct cgs_display_info info = {0};
914 struct cgs_mode_info mode_info;
915
916 info.mode_info = &mode_info;
917
918 tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK);
919
920 if (tmp)
921 return TCLK;
922
923 cgs_get_active_displays_info(hwmgr->device, &info);
924 reference_clock = mode_info.ref_clock;
925
926 tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE);
927
928 if (0 != tmp)
929 return reference_clock / 4;
930
931 return reference_clock;
932}
933
934/**
935* Calculates the SCLK dividers using the provided engine clock
936*
937* @param hwmgr the address of the hardware manager
938* @param clock the engine clock to use to populate the structure
939* @param sclk the SMC SCLK structure to be populated
940*/
2cc0c0b5 941static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 942 uint32_t clock, SMU_SclkSetting *sclk_setting)
943{
2cc0c0b5 944 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 945 const SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
946 struct pp_atomctrl_clock_dividers_ai dividers;
947
948 uint32_t ref_clock;
949 uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
950 uint8_t i;
951 int result;
952 uint64_t temp;
953
954 sclk_setting->SclkFrequency = clock;
955 /* get the engine clock dividers for this clock value */
956 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, &dividers);
957 if (result == 0) {
958 sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
959 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
960 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
961 sclk_setting->PllRange = dividers.ucSclkPllRange;
e85c7d66 962 sclk_setting->Sclk_slew_rate = 0x400;
963 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
964 sclk_setting->Pcc_down_slew_rate = 0xffff;
a23eefa2
RZ		 965 sclk_setting->SSc_En = dividers.ucSscEnable;
966 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
967 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
e85c7d66 968 sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
a23eefa2
RZ		 969 return result;
970 }
971
2cc0c0b5 972 ref_clock = polaris10_get_xclk(hwmgr);
a23eefa2
RZ		 973
974 for (i = 0; i < NUM_SCLK_RANGE; i++) {
975 if (clock > data->range_table[i].trans_lower_frequency
976 && clock <= data->range_table[i].trans_upper_frequency) {
977 sclk_setting->PllRange = i;
978 break;
979 }
980 }
981
982 sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
983 temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
984 temp <<= 0x10;
ae17c999
SG		 985 do_div(temp, ref_clock);
986 sclk_setting->Fcw_frac = temp & 0xffff;
a23eefa2
RZ		 987
988 pcc_target_percent = 10; /* Hardcode 10% for now. */
989 pcc_target_freq = clock - (clock * pcc_target_percent / 100);
990 sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
991
992 ss_target_percent = 2; /* Hardcode 2% for now. */
993 sclk_setting->SSc_En = 0;
994 if (ss_target_percent) {
995 sclk_setting->SSc_En = 1;
996 ss_target_freq = clock - (clock * ss_target_percent / 100);
997 sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
998 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
999 temp <<= 0x10;
ae17c999
SG		 1000 do_div(temp, ref_clock);
1001 sclk_setting->Fcw1_frac = temp & 0xffff;
a23eefa2
RZ		 1002 }
1003
1004 return 0;
1005}
1006
2cc0c0b5 1007static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1008 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
1009 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
1010{
1011 uint32_t i;
1012 uint16_t vddci;
2cc0c0b5 1013 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1014
1015 *voltage = *mvdd = 0;
1016
1017 /* clock - voltage dependency table is empty table */
1018 if (dep_table->count == 0)
1019 return -EINVAL;
1020
1021 for (i = 0; i < dep_table->count; i++) {
1022 /* find first sclk bigger than request */
1023 if (dep_table->entries[i].clk >= clock) {
1024 *voltage |= (dep_table->entries[i].vddc *
1025 VOLTAGE_SCALE) << VDDC_SHIFT;
2cc0c0b5 1026 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
a23eefa2
RZ		 1027 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1028 VOLTAGE_SCALE) << VDDCI_SHIFT;
1029 else if (dep_table->entries[i].vddci)
1030 *voltage |= (dep_table->entries[i].vddci *
1031 VOLTAGE_SCALE) << VDDCI_SHIFT;
1032 else {
1033 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1034 (dep_table->entries[i].vddc -
1035 (uint16_t)data->vddc_vddci_delta));
1036 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1037 }
1038
2cc0c0b5 1039 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
a23eefa2
RZ		 1040 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
1041 VOLTAGE_SCALE;
1042 else if (dep_table->entries[i].mvdd)
1043 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
1044 VOLTAGE_SCALE;
1045
1046 *voltage |= 1 << PHASES_SHIFT;
1047 return 0;
1048 }
1049 }
1050
1051 /* sclk is bigger than max sclk in the dependence table */
1052 *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1053
2cc0c0b5 1054 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
a23eefa2
RZ		 1055 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1056 VOLTAGE_SCALE) << VDDCI_SHIFT;
1057 else if (dep_table->entries[i-1].vddci) {
1058 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1059 (dep_table->entries[i].vddc -
1060 (uint16_t)data->vddc_vddci_delta));
1061 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1062 }
1063
2cc0c0b5 1064 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
a23eefa2
RZ		 1065 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
1066 else if (dep_table->entries[i].mvdd)
1067 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
1068
1069 return 0;
1070}
1071
1072sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] = { {VCO_2_4, POSTDIV_DIV_BY_16, 75, 160, 112},
1073 {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
1074 {VCO_2_4, POSTDIV_DIV_BY_8, 75, 160, 112},
1075 {VCO_3_6, POSTDIV_DIV_BY_8, 112, 224, 160},
1076 {VCO_2_4, POSTDIV_DIV_BY_4, 75, 160, 112},
1077 {VCO_3_6, POSTDIV_DIV_BY_4, 112, 216, 160},
1078 {VCO_2_4, POSTDIV_DIV_BY_2, 75, 160, 108},
1079 {VCO_3_6, POSTDIV_DIV_BY_2, 112, 216, 160} };
1080
2cc0c0b5 1081static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 1082{
1083 uint32_t i, ref_clk;
2cc0c0b5 1084 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1085 SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
1086 struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
1087
2cc0c0b5 1088 ref_clk = polaris10_get_xclk(hwmgr);
a23eefa2
RZ		 1089
1090 if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
1091 for (i = 0; i < NUM_SCLK_RANGE; i++) {
1092 table->SclkFcwRangeTable[i].vco_setting = range_table_from_vbios.entry[i].ucVco_setting;
1093 table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv;
1094 table->SclkFcwRangeTable[i].fcw_pcc = range_table_from_vbios.entry[i].usFcw_pcc;
1095
1096 table->SclkFcwRangeTable[i].fcw_trans_upper = range_table_from_vbios.entry[i].usFcw_trans_upper;
1097 table->SclkFcwRangeTable[i].fcw_trans_lower = range_table_from_vbios.entry[i].usRcw_trans_lower;
1098
1099 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1100 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1101 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1102 }
1103 return;
1104 }
1105
1106 for (i = 0; i < NUM_SCLK_RANGE; i++) {
1107
1108 data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
1109 data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
1110
1111 table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
1112 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
1113 table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
1114
1115 table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
1116 table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
1117
1118 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1119 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1120 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1121 }
1122}
1123
1124/**
1125* Populates single SMC SCLK structure using the provided engine clock
1126*
1127* @param hwmgr the address of the hardware manager
1128* @param clock the engine clock to use to populate the structure
1129* @param sclk the SMC SCLK structure to be populated
1130*/
1131
2cc0c0b5 1132static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1133 uint32_t clock, uint16_t sclk_al_threshold,
1134 struct SMU74_Discrete_GraphicsLevel *level)
1135{
1136 int result, i, temp;
1137 /* PP_Clocks minClocks; */
1138 uint32_t mvdd;
2cc0c0b5 1139 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1140 struct phm_ppt_v1_information *table_info =
1141 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1142 SMU_SclkSetting curr_sclk_setting = { 0 };
1143
2cc0c0b5 1144 result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
a23eefa2
RZ		 1145
1146 /* populate graphics levels */
2cc0c0b5 1147 result = polaris10_get_dependency_volt_by_clk(hwmgr,
a23eefa2
RZ		 1148 table_info->vdd_dep_on_sclk, clock,
1149 &level->MinVoltage, &mvdd);
1150
1151 PP_ASSERT_WITH_CODE((0 == result),
1152 "can not find VDDC voltage value for "
1153 "VDDC engine clock dependency table",
1154 return result);
1155 level->ActivityLevel = sclk_al_threshold;
1156
1157 level->CcPwrDynRm = 0;
1158 level->CcPwrDynRm1 = 0;
1159 level->EnabledForActivity = 0;
1160 level->EnabledForThrottle = 1;
1161 level->UpHyst = 10;
1162 level->DownHyst = 0;
1163 level->VoltageDownHyst = 0;
1164 level->PowerThrottle = 0;
1165
1166 /*
1167 * TODO: get minimum clocks from dal configaration
1168 * PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks);
1169 */
1170 /* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */
1171
1172 /* get level->DeepSleepDivId
1173 if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
1174 level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR);
1175 */
1176 PP_ASSERT_WITH_CODE((clock >= 2500), "Engine clock can't satisfy stutter requirement!", return 0);
2cc0c0b5 1177 for (i = POLARIS10_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
a23eefa2
RZ		 1178 temp = clock / (1UL << i);
1179
1180 if (temp >= 2500 || i == 0)
1181 break;
1182 }
1183
1184 level->DeepSleepDivId = i;
1185
1186 /* Default to slow, highest DPM level will be
1187 * set to PPSMC_DISPLAY_WATERMARK_LOW later.
1188 */
1189 if (data->update_up_hyst)
1190 level->UpHyst = (uint8_t)data->up_hyst;
1191 if (data->update_down_hyst)
1192 level->DownHyst = (uint8_t)data->down_hyst;
1193
1194 level->SclkSetting = curr_sclk_setting;
1195
1196 CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
1197 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
1198 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
1199 CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
1200 CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
1201 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
1202 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
1203 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
e85c7d66 1204 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
1205 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
1206 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
a23eefa2
RZ		 1207 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
1208 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
e85c7d66 1209 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
a23eefa2
RZ		 1210 return 0;
1211}
1212
1213/**
1214* Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
1215*
1216* @param hwmgr the address of the hardware manager
1217*/
2cc0c0b5 1218static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
a23eefa2 1219{
2cc0c0b5
FC		 1220 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1221 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
a23eefa2
RZ		 1222 struct phm_ppt_v1_information *table_info =
1223 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1224 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1225 uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
1226 int result = 0;
1227 uint32_t array = data->dpm_table_start +
1228 offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
1229 uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
1230 SMU74_MAX_LEVELS_GRAPHICS;
1231 struct SMU74_Discrete_GraphicsLevel *levels =
1232 data->smc_state_table.GraphicsLevel;
1233 uint32_t i, max_entry;
1234 uint8_t hightest_pcie_level_enabled = 0,
1235 lowest_pcie_level_enabled = 0,
1236 mid_pcie_level_enabled = 0,
1237 count = 0;
1238
2cc0c0b5 1239 polaris10_get_sclk_range_table(hwmgr);
a23eefa2
RZ		 1240
1241 for (i = 0; i < dpm_table->sclk_table.count; i++) {
1242
2cc0c0b5 1243 result = polaris10_populate_single_graphic_level(hwmgr,
a23eefa2
RZ		 1244 dpm_table->sclk_table.dpm_levels[i].value,
1245 (uint16_t)data->activity_target[i],
1246 &(data->smc_state_table.GraphicsLevel[i]));
1247 if (result)
1248 return result;
1249
1250 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
1251 if (i > 1)
1252 levels[i].DeepSleepDivId = 0;
1253 }
5de95e55
RZ		 1254 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1255 PHM_PlatformCaps_SPLLShutdownSupport))
1256 data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
a23eefa2
RZ		 1257
1258 data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
1259 data->smc_state_table.GraphicsDpmLevelCount =
1260 (uint8_t)dpm_table->sclk_table.count;
1261 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1262 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1263
1264
1265 if (pcie_table != NULL) {
1266 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
1267 "There must be 1 or more PCIE levels defined in PPTable.",
1268 return -EINVAL);
1269 max_entry = pcie_entry_cnt - 1;
1270 for (i = 0; i < dpm_table->sclk_table.count; i++)
1271 levels[i].pcieDpmLevel =
1272 (uint8_t) ((i < max_entry) ? i : max_entry);
1273 } else {
1274 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1275 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1276 (1 << (hightest_pcie_level_enabled + 1))) != 0))
1277 hightest_pcie_level_enabled++;
1278
1279 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1280 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1281 (1 << lowest_pcie_level_enabled)) == 0))
1282 lowest_pcie_level_enabled++;
1283
1284 while ((count < hightest_pcie_level_enabled) &&
1285 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1286 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
1287 count++;
1288
1289 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
1290 hightest_pcie_level_enabled ?
1291 (lowest_pcie_level_enabled + 1 + count) :
1292 hightest_pcie_level_enabled;
1293
1294 /* set pcieDpmLevel to hightest_pcie_level_enabled */
1295 for (i = 2; i < dpm_table->sclk_table.count; i++)
1296 levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
1297
1298 /* set pcieDpmLevel to lowest_pcie_level_enabled */
1299 levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
1300
1301 /* set pcieDpmLevel to mid_pcie_level_enabled */
1302 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
1303 }
1304 /* level count will send to smc once at init smc table and never change */
2cc0c0b5 1305 result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
a23eefa2
RZ		 1306 (uint32_t)array_size, data->sram_end);
1307
1308 return result;
1309}
1310
2cc0c0b5 1311static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1312 uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level)
1313{
2cc0c0b5 1314 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1315 struct phm_ppt_v1_information *table_info =
1316 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1317 int result = 0;
1318 struct cgs_display_info info = {0, 0, NULL};
1319
1320 cgs_get_active_displays_info(hwmgr->device, &info);
1321
1322 if (table_info->vdd_dep_on_mclk) {
2cc0c0b5 1323 result = polaris10_get_dependency_volt_by_clk(hwmgr,
a23eefa2
RZ		 1324 table_info->vdd_dep_on_mclk, clock,
1325 &mem_level->MinVoltage, &mem_level->MinMvdd);
1326 PP_ASSERT_WITH_CODE((0 == result),
1327 "can not find MinVddc voltage value from memory "
1328 "VDDC voltage dependency table", return result);
1329 }
1330
1331 mem_level->MclkFrequency = clock;
1332 mem_level->StutterEnable = 0;
1333 mem_level->EnabledForThrottle = 1;
1334 mem_level->EnabledForActivity = 0;
1335 mem_level->UpHyst = 0;
1336 mem_level->DownHyst = 100;
1337 mem_level->VoltageDownHyst = 0;
1338 mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
1339 mem_level->StutterEnable = false;
1340
1341 mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1342
1343 data->display_timing.num_existing_displays = info.display_count;
1344
1345 if ((data->mclk_stutter_mode_threshold) &&
1346 (clock <= data->mclk_stutter_mode_threshold) &&
1347 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
1348 STUTTER_ENABLE) & 0x1))
1349 mem_level->StutterEnable = true;
1350
1351 if (!result) {
1352 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
1353 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
1354 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
1355 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
1356 }
1357 return result;
1358}
1359
1360/**
1361* Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
1362*
1363* @param hwmgr the address of the hardware manager
1364*/
2cc0c0b5 1365static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
a23eefa2 1366{
2cc0c0b5
FC		 1367 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1368 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
a23eefa2
RZ		 1369 int result;
1370 /* populate MCLK dpm table to SMU7 */
1371 uint32_t array = data->dpm_table_start +
1372 offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
1373 uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) *
1374 SMU74_MAX_LEVELS_MEMORY;
1375 struct SMU74_Discrete_MemoryLevel *levels =
1376 data->smc_state_table.MemoryLevel;
1377 uint32_t i;
1378
1379 for (i = 0; i < dpm_table->mclk_table.count; i++) {
1380 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1381 "can not populate memory level as memory clock is zero",
1382 return -EINVAL);
2cc0c0b5 1383 result = polaris10_populate_single_memory_level(hwmgr,
a23eefa2
RZ		 1384 dpm_table->mclk_table.dpm_levels[i].value,
1385 &levels[i]);
b4c6f99e
RZ		 1386 if (i == dpm_table->mclk_table.count - 1) {
1387 levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1388 levels[i].EnabledForActivity = 1;
1389 }
a23eefa2
RZ		 1390 if (result)
1391 return result;
1392 }
1393
a23eefa2
RZ		 1394 /* in order to prevent MC activity from stutter mode to push DPM up.
1395 * the UVD change complements this by putting the MCLK in
1396 * a higher state by default such that we are not effected by
1397 * up threshold or and MCLK DPM latency.
1398 */
1399 levels[0].ActivityLevel = (uint16_t)data->mclk_dpm0_activity_target;
1400 CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
1401
1402 data->smc_state_table.MemoryDpmLevelCount =
1403 (uint8_t)dpm_table->mclk_table.count;
1404 data->dpm_level_enable_mask.mclk_dpm_enable_mask =
1405 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
a23eefa2
RZ		 1406
1407 /* level count will send to smc once at init smc table and never change */
2cc0c0b5 1408 result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
a23eefa2
RZ		 1409 (uint32_t)array_size, data->sram_end);
1410
1411 return result;
1412}
1413
1414/**
1415* Populates the SMC MVDD structure using the provided memory clock.
1416*
1417* @param hwmgr the address of the hardware manager
1418* @param mclk the MCLK value to be used in the decision if MVDD should be high or low.
1419* @param voltage the SMC VOLTAGE structure to be populated
1420*/
2cc0c0b5 1421int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1422 uint32_t mclk, SMIO_Pattern *smio_pat)
1423{
2cc0c0b5 1424 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1425 struct phm_ppt_v1_information *table_info =
1426 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1427 uint32_t i = 0;
1428
2cc0c0b5 1429 if (POLARIS10_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
a23eefa2
RZ		 1430 /* find mvdd value which clock is more than request */
1431 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
1432 if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
1433 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
1434 break;
1435 }
1436 }
1437 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
1438 "MVDD Voltage is outside the supported range.",
1439 return -EINVAL);
1440 } else
1441 return -EINVAL;
1442
1443 return 0;
1444}
1445
2cc0c0b5 1446static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1447 SMU74_Discrete_DpmTable *table)
1448{
1449 int result = 0;
1450 uint32_t sclk_frequency;
2cc0c0b5 1451 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1452 struct phm_ppt_v1_information *table_info =
1453 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1454 SMIO_Pattern vol_level;
1455 uint32_t mvdd;
1456 uint16_t us_mvdd;
1457
1458 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1459
1460 if (!data->sclk_dpm_key_disabled) {
1461 /* Get MinVoltage and Frequency from DPM0,
1462 * already converted to SMC_UL */
1463 sclk_frequency = data->dpm_table.sclk_table.dpm_levels[0].value;
2cc0c0b5 1464 result = polaris10_get_dependency_volt_by_clk(hwmgr,
a23eefa2
RZ		 1465 table_info->vdd_dep_on_sclk,
1466 table->ACPILevel.SclkFrequency,
1467 &table->ACPILevel.MinVoltage, &mvdd);
1468 PP_ASSERT_WITH_CODE((0 == result),
1469 "Cannot find ACPI VDDC voltage value "
1470 "in Clock Dependency Table", );
1471 } else {
1472 sclk_frequency = data->vbios_boot_state.sclk_bootup_value;
1473 table->ACPILevel.MinVoltage =
1474 data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE;
1475 }
1476
2cc0c0b5 1477 result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency, &(table->ACPILevel.SclkSetting));
a23eefa2
RZ		 1478 PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);
1479
1480 table->ACPILevel.DeepSleepDivId = 0;
1481 table->ACPILevel.CcPwrDynRm = 0;
1482 table->ACPILevel.CcPwrDynRm1 = 0;
1483
1484 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1485 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
1486 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1487 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1488
1489 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
1490 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
1491 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
1492 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
e85c7d66 1493 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
1494 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
1495 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
a23eefa2
RZ		 1496 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
1497 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
e85c7d66 1498 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
a23eefa2
RZ		 1499
1500 if (!data->mclk_dpm_key_disabled) {
1501 /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
1502 table->MemoryACPILevel.MclkFrequency =
1503 data->dpm_table.mclk_table.dpm_levels[0].value;
2cc0c0b5 1504 result = polaris10_get_dependency_volt_by_clk(hwmgr,
a23eefa2
RZ		 1505 table_info->vdd_dep_on_mclk,
1506 table->MemoryACPILevel.MclkFrequency,
1507 &table->MemoryACPILevel.MinVoltage, &mvdd);
1508 PP_ASSERT_WITH_CODE((0 == result),
1509 "Cannot find ACPI VDDCI voltage value "
1510 "in Clock Dependency Table",
1511 );
1512 } else {
1513 table->MemoryACPILevel.MclkFrequency =
1514 data->vbios_boot_state.mclk_bootup_value;
1515 table->MemoryACPILevel.MinVoltage =
1516 data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE;
1517 }
1518
1519 us_mvdd = 0;
2cc0c0b5 1520 if ((POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
a23eefa2
RZ		 1521 (data->mclk_dpm_key_disabled))
1522 us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
1523 else {
2cc0c0b5 1524 if (!polaris10_populate_mvdd_value(hwmgr,
a23eefa2
RZ		 1525 data->dpm_table.mclk_table.dpm_levels[0].value,
1526 &vol_level))
1527 us_mvdd = vol_level.Voltage;
1528 }
1529
2cc0c0b5 1530 if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level))
a23eefa2
RZ		 1531 table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
1532 else
1533 table->MemoryACPILevel.MinMvdd = 0;
1534
1535 table->MemoryACPILevel.StutterEnable = false;
1536
1537 table->MemoryACPILevel.EnabledForThrottle = 0;
1538 table->MemoryACPILevel.EnabledForActivity = 0;
1539 table->MemoryACPILevel.UpHyst = 0;
1540 table->MemoryACPILevel.DownHyst = 100;
1541 table->MemoryACPILevel.VoltageDownHyst = 0;
1542 table->MemoryACPILevel.ActivityLevel =
1543 PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
1544
1545 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
1546 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
1547
1548 return result;
1549}
1550
2cc0c0b5 1551static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1552 SMU74_Discrete_DpmTable *table)
1553{
1554 int result = -EINVAL;
1555 uint8_t count;
1556 struct pp_atomctrl_clock_dividers_vi dividers;
1557 struct phm_ppt_v1_information *table_info =
1558 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1559 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1560 table_info->mm_dep_table;
2cc0c0b5 1561 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1562
1563 table->VceLevelCount = (uint8_t)(mm_table->count);
1564 table->VceBootLevel = 0;
1565
1566 for (count = 0; count < table->VceLevelCount; count++) {
1567 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
1568 table->VceLevel[count].MinVoltage |=
1569 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1570 table->VceLevel[count].MinVoltage |=
1571 ((mm_table->entries[count].vddc - data->vddc_vddci_delta) *
1572 VOLTAGE_SCALE) << VDDCI_SHIFT;
1573 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1574
1575 /*retrieve divider value for VBIOS */
1576 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1577 table->VceLevel[count].Frequency, &dividers);
1578 PP_ASSERT_WITH_CODE((0 == result),
1579 "can not find divide id for VCE engine clock",
1580 return result);
1581
1582 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1583
1584 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1585 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
1586 }
1587 return result;
1588}
1589
2cc0c0b5 1590static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1591 SMU74_Discrete_DpmTable *table)
1592{
1593 int result = -EINVAL;
1594 uint8_t count;
1595 struct pp_atomctrl_clock_dividers_vi dividers;
1596 struct phm_ppt_v1_information *table_info =
1597 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1598 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1599 table_info->mm_dep_table;
2cc0c0b5 1600 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1601
1602 table->SamuBootLevel = 0;
1603 table->SamuLevelCount = (uint8_t)(mm_table->count);
1604
1605 for (count = 0; count < table->SamuLevelCount; count++) {
1606 /* not sure whether we need evclk or not */
1607 table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
1608 table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1609 VOLTAGE_SCALE) << VDDC_SHIFT;
1610 table->SamuLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
1611 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
1612 table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1613
1614 /* retrieve divider value for VBIOS */
1615 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1616 table->SamuLevel[count].Frequency, &dividers);
1617 PP_ASSERT_WITH_CODE((0 == result),
1618 "can not find divide id for samu clock", return result);
1619
1620 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1621
1622 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
1623 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
1624 }
1625 return result;
1626}
1627
2cc0c0b5 1628static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1629 int32_t eng_clock, int32_t mem_clock,
1630 SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs)
1631{
1632 uint32_t dram_timing;
1633 uint32_t dram_timing2;
1634 uint32_t burst_time;
1635 int result;
1636
1637 result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1638 eng_clock, mem_clock);
1639 PP_ASSERT_WITH_CODE(result == 0,
1640 "Error calling VBIOS to set DRAM_TIMING.", return result);
1641
1642 dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1643 dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1644 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1645
1646
1647 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing);
1648 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
1649 arb_regs->McArbBurstTime = (uint8_t)burst_time;
1650
1651 return 0;
1652}
1653
2cc0c0b5 1654static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
a23eefa2 1655{
2cc0c0b5 1656 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1657 struct SMU74_Discrete_MCArbDramTimingTable arb_regs;
1658 uint32_t i, j;
1659 int result = 0;
1660
1661 for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1662 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
2cc0c0b5 1663 result = polaris10_populate_memory_timing_parameters(hwmgr,
a23eefa2
RZ		 1664 data->dpm_table.sclk_table.dpm_levels[i].value,
1665 data->dpm_table.mclk_table.dpm_levels[j].value,
1666 &arb_regs.entries[i][j]);
1667 if (result == 0)
1668 result = atomctrl_set_ac_timing_ai(hwmgr, data->dpm_table.mclk_table.dpm_levels[j].value, j);
1669 if (result != 0)
1670 return result;
1671 }
1672 }
1673
2cc0c0b5 1674 result = polaris10_copy_bytes_to_smc(
a23eefa2
RZ		 1675 hwmgr->smumgr,
1676 data->arb_table_start,
1677 (uint8_t *)&arb_regs,
1678 sizeof(SMU74_Discrete_MCArbDramTimingTable),
1679 data->sram_end);
1680 return result;
1681}
1682
2cc0c0b5 1683static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1684 struct SMU74_Discrete_DpmTable *table)
1685{
1686 int result = -EINVAL;
1687 uint8_t count;
1688 struct pp_atomctrl_clock_dividers_vi dividers;
1689 struct phm_ppt_v1_information *table_info =
1690 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1691 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1692 table_info->mm_dep_table;
2cc0c0b5 1693 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1694
1695 table->UvdLevelCount = (uint8_t)(mm_table->count);
1696 table->UvdBootLevel = 0;
1697
1698 for (count = 0; count < table->UvdLevelCount; count++) {
1699 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1700 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1701 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1702 VOLTAGE_SCALE) << VDDC_SHIFT;
1703 table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
1704 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
1705 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1706
1707 /* retrieve divider value for VBIOS */
1708 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1709 table->UvdLevel[count].VclkFrequency, &dividers);
1710 PP_ASSERT_WITH_CODE((0 == result),
1711 "can not find divide id for Vclk clock", return result);
1712
1713 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1714
1715 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1716 table->UvdLevel[count].DclkFrequency, &dividers);
1717 PP_ASSERT_WITH_CODE((0 == result),
1718 "can not find divide id for Dclk clock", return result);
1719
1720 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1721
1722 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1723 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1724 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
1725
1726 }
1727 return result;
1728}
1729
2cc0c0b5 1730static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1731 struct SMU74_Discrete_DpmTable *table)
1732{
1733 int result = 0;
2cc0c0b5 1734 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1735
1736 table->GraphicsBootLevel = 0;
1737 table->MemoryBootLevel = 0;
1738
1739 /* find boot level from dpm table */
1740 result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1741 data->vbios_boot_state.sclk_bootup_value,
1742 (uint32_t *)&(table->GraphicsBootLevel));
1743
1744 result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1745 data->vbios_boot_state.mclk_bootup_value,
1746 (uint32_t *)&(table->MemoryBootLevel));
1747
1748 table->BootVddc = data->vbios_boot_state.vddc_bootup_value *
1749 VOLTAGE_SCALE;
1750 table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
1751 VOLTAGE_SCALE;
1752 table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value *
1753 VOLTAGE_SCALE;
1754
1755 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
1756 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
1757 CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
1758
1759 return 0;
1760}
1761
1762
2cc0c0b5 1763static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
a23eefa2 1764{
2cc0c0b5 1765 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1766 struct phm_ppt_v1_information *table_info =
1767 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1768 uint8_t count, level;
1769
1770 count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
1771
1772 for (level = 0; level < count; level++) {
1773 if (table_info->vdd_dep_on_sclk->entries[level].clk >=
1774 data->vbios_boot_state.sclk_bootup_value) {
1775 data->smc_state_table.GraphicsBootLevel = level;
1776 break;
1777 }
1778 }
1779
1780 count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
1781 for (level = 0; level < count; level++) {
1782 if (table_info->vdd_dep_on_mclk->entries[level].clk >=
1783 data->vbios_boot_state.mclk_bootup_value) {
1784 data->smc_state_table.MemoryBootLevel = level;
1785 break;
1786 }
1787 }
1788
1789 return 0;
1790}
1791
2cc0c0b5 1792static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 1793{
1794 uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks,
1795 volt_with_cks, value;
1796 uint16_t clock_freq_u16;
2cc0c0b5 1797 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1798 uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2,
1799 volt_offset = 0;
1800 struct phm_ppt_v1_information *table_info =
1801 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1802 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1803 table_info->vdd_dep_on_sclk;
1804
1805 stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
1806
1807 /* Read SMU_Eefuse to read and calculate RO and determine
1808 * if the part is SS or FF. if RO >= 1660MHz, part is FF.
1809 */
1810 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1811 ixSMU_EFUSE_0 + (146 * 4));
1812 efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1813 ixSMU_EFUSE_0 + (148 * 4));
1814 efuse &= 0xFF000000;
1815 efuse = efuse >> 24;
1816 efuse2 &= 0xF;
1817
1818 if (efuse2 == 1)
1819 ro = (2300 - 1350) * efuse / 255 + 1350;
1820 else
1821 ro = (2500 - 1000) * efuse / 255 + 1000;
1822
1823 if (ro >= 1660)
1824 type = 0;
1825 else
1826 type = 1;
1827
1828 /* Populate Stretch amount */
1829 data->smc_state_table.ClockStretcherAmount = stretch_amount;
1830
1831 /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
1832 for (i = 0; i < sclk_table->count; i++) {
1833 data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1834 sclk_table->entries[i].cks_enable << i;
1835 volt_without_cks = (uint32_t)((14041 *
1836 (sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 /
1837 (4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000)));
1838 volt_with_cks = (uint32_t)((13946 *
1839 (sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 /
1840 (3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000)));
1841 if (volt_without_cks >= volt_with_cks)
1842 volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
1843 sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
1844 data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1845 }
1846
1847 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1848 STRETCH_ENABLE, 0x0);
1849 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1850 masterReset, 0x1);
1851 /* PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE, staticEnable, 0x1); */
1852 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1853 masterReset, 0x0);
1854
1855 /* Populate CKS Lookup Table */
1856 if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
1857 stretch_amount2 = 0;
1858 else if (stretch_amount == 3 || stretch_amount == 4)
1859 stretch_amount2 = 1;
1860 else {
1861 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1862 PHM_PlatformCaps_ClockStretcher);
1863 PP_ASSERT_WITH_CODE(false,
1864 "Stretch Amount in PPTable not supported\n",
1865 return -EINVAL);
1866 }
1867
1868 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1869 ixPWR_CKS_CNTL);
1870 value &= 0xFFC2FF87;
1871 data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq =
2cc0c0b5 1872 polaris10_clock_stretcher_lookup_table[stretch_amount2][0];
a23eefa2 1873 data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq =
2cc0c0b5 1874 polaris10_clock_stretcher_lookup_table[stretch_amount2][1];
a23eefa2
RZ		 1875 clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(data->smc_state_table.
1876 GraphicsLevel[data->smc_state_table.GraphicsDpmLevelCount - 1].SclkSetting.SclkFrequency) / 100);
2cc0c0b5
FC		 1877 if (polaris10_clock_stretcher_lookup_table[stretch_amount2][0] < clock_freq_u16
1878 && polaris10_clock_stretcher_lookup_table[stretch_amount2][1] > clock_freq_u16) {
a23eefa2 1879 /* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */
2cc0c0b5 1880 value |= (polaris10_clock_stretcher_lookup_table[stretch_amount2][3]) << 16;
a23eefa2 1881 /* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */
2cc0c0b5 1882 value |= (polaris10_clock_stretcher_lookup_table[stretch_amount2][2]) << 18;
a23eefa2 1883 /* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */
2cc0c0b5
FC		 1884 value |= (polaris10_clock_stretch_amount_conversion
1885 [polaris10_clock_stretcher_lookup_table[stretch_amount2][3]]
a23eefa2
RZ		 1886 [stretch_amount]) << 3;
1887 }
1888 CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq);
1889 CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq);
1890 data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting =
2cc0c0b5 1891 polaris10_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F;
a23eefa2 1892 data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |=
2cc0c0b5 1893 (polaris10_clock_stretcher_lookup_table[stretch_amount2][3]) << 7;
a23eefa2
RZ		 1894
1895 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1896 ixPWR_CKS_CNTL, value);
1897
1898 /* Populate DDT Lookup Table */
1899 for (i = 0; i < 4; i++) {
1900 /* Assign the minimum and maximum VID stored
1901 * in the last row of Clock Stretcher Voltage Table.
1902 */
1903 data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].minVID =
2cc0c0b5 1904 (uint8_t) polaris10_clock_stretcher_ddt_table[type][i][2];
a23eefa2 1905 data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].maxVID =
2cc0c0b5 1906 (uint8_t) polaris10_clock_stretcher_ddt_table[type][i][3];
a23eefa2
RZ		 1907 /* Loop through each SCLK and check the frequency
1908 * to see if it lies within the frequency for clock stretcher.
1909 */
1910 for (j = 0; j < data->smc_state_table.GraphicsDpmLevelCount; j++) {
1911 cks_setting = 0;
1912 clock_freq = PP_SMC_TO_HOST_UL(
1913 data->smc_state_table.GraphicsLevel[j].SclkSetting.SclkFrequency);
1914 /* Check the allowed frequency against the sclk level[j].
1915 * Sclk's endianness has already been converted,
1916 * and it's in 10Khz unit,
1917 * as opposed to Data table, which is in Mhz unit.
1918 */
2cc0c0b5 1919 if (clock_freq >= (polaris10_clock_stretcher_ddt_table[type][i][0]) * 100) {
a23eefa2 1920 cks_setting |= 0x2;
2cc0c0b5 1921 if (clock_freq < (polaris10_clock_stretcher_ddt_table[type][i][1]) * 100)
a23eefa2
RZ		 1922 cks_setting |= 0x1;
1923 }
1924 data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].setting
1925 |= cks_setting << (j * 2);
1926 }
1927 CONVERT_FROM_HOST_TO_SMC_US(
1928 data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].setting);
1929 }
1930
1931 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
1932 value &= 0xFFFFFFFE;
1933 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
1934
1935 return 0;
1936}
1937
1938/**
1939* Populates the SMC VRConfig field in DPM table.
1940*
1941* @param hwmgr the address of the hardware manager
1942* @param table the SMC DPM table structure to be populated
1943* @return always 0
1944*/
2cc0c0b5 1945static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1946 struct SMU74_Discrete_DpmTable *table)
1947{
2cc0c0b5 1948 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1949 uint16_t config;
1950
1951 config = VR_MERGED_WITH_VDDC;
1952 table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
1953
1954 /* Set Vddc Voltage Controller */
2cc0c0b5 1955 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
a23eefa2
RZ		 1956 config = VR_SVI2_PLANE_1;
1957 table->VRConfig |= config;
1958 } else {
1959 PP_ASSERT_WITH_CODE(false,
1960 "VDDC should be on SVI2 control in merged mode!",
1961 );
1962 }
1963 /* Set Vddci Voltage Controller */
2cc0c0b5 1964 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
a23eefa2
RZ		 1965 config = VR_SVI2_PLANE_2; /* only in merged mode */
1966 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
2cc0c0b5 1967 } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
a23eefa2
RZ		 1968 config = VR_SMIO_PATTERN_1;
1969 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1970 } else {
1971 config = VR_STATIC_VOLTAGE;
1972 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1973 }
1974 /* Set Mvdd Voltage Controller */
2cc0c0b5 1975 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
a23eefa2
RZ		 1976 config = VR_SVI2_PLANE_2;
1977 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
2cc0c0b5 1978 } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
a23eefa2
RZ		 1979 config = VR_SMIO_PATTERN_2;
1980 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1981 } else {
1982 config = VR_STATIC_VOLTAGE;
1983 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1984 }
1985
1986 return 0;
1987}
1988
1989/**
1990* Initializes the SMC table and uploads it
1991*
1992* @param hwmgr the address of the powerplay hardware manager.
1993* @return always 0
1994*/
2cc0c0b5 1995static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 1996{
1997 int result;
2cc0c0b5 1998 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1999 struct phm_ppt_v1_information *table_info =
2000 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2001 struct SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
2cc0c0b5 2002 const struct polaris10_ulv_parm *ulv = &(data->ulv);
a23eefa2
RZ		 2003 uint8_t i;
2004 struct pp_atomctrl_gpio_pin_assignment gpio_pin;
e85c7d66 2005 pp_atomctrl_clock_dividers_vi dividers;
a23eefa2 2006
2cc0c0b5 2007 result = polaris10_setup_default_dpm_tables(hwmgr);
a23eefa2
RZ		 2008 PP_ASSERT_WITH_CODE(0 == result,
2009 "Failed to setup default DPM tables!", return result);
2010
2cc0c0b5
FC		 2011 if (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control)
2012 polaris10_populate_smc_voltage_tables(hwmgr, table);
a23eefa2
RZ		 2013
2014 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2015 PHM_PlatformCaps_AutomaticDCTransition))
2016 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
2017
2018 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2019 PHM_PlatformCaps_StepVddc))
2020 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
2021
2022 if (data->is_memory_gddr5)
2023 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
2024
2025 if (ulv->ulv_supported && table_info->us_ulv_voltage_offset) {
2cc0c0b5 2026 result = polaris10_populate_ulv_state(hwmgr, table);
a23eefa2
RZ		 2027 PP_ASSERT_WITH_CODE(0 == result,
2028 "Failed to initialize ULV state!", return result);
2029 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2cc0c0b5 2030 ixCG_ULV_PARAMETER, PPPOLARIS10_CGULVPARAMETER_DFLT);
a23eefa2
RZ		 2031 }
2032
2cc0c0b5 2033 result = polaris10_populate_smc_link_level(hwmgr, table);
a23eefa2
RZ		 2034 PP_ASSERT_WITH_CODE(0 == result,
2035 "Failed to initialize Link Level!", return result);
2036
2cc0c0b5 2037 result = polaris10_populate_all_graphic_levels(hwmgr);
a23eefa2
RZ		 2038 PP_ASSERT_WITH_CODE(0 == result,
2039 "Failed to initialize Graphics Level!", return result);
2040
2cc0c0b5 2041 result = polaris10_populate_all_memory_levels(hwmgr);
a23eefa2
RZ		 2042 PP_ASSERT_WITH_CODE(0 == result,
2043 "Failed to initialize Memory Level!", return result);
2044
2cc0c0b5 2045 result = polaris10_populate_smc_acpi_level(hwmgr, table);
a23eefa2
RZ		 2046 PP_ASSERT_WITH_CODE(0 == result,
2047 "Failed to initialize ACPI Level!", return result);
2048
2cc0c0b5 2049 result = polaris10_populate_smc_vce_level(hwmgr, table);
a23eefa2
RZ		 2050 PP_ASSERT_WITH_CODE(0 == result,
2051 "Failed to initialize VCE Level!", return result);
2052
2cc0c0b5 2053 result = polaris10_populate_smc_samu_level(hwmgr, table);
a23eefa2
RZ		 2054 PP_ASSERT_WITH_CODE(0 == result,
2055 "Failed to initialize SAMU Level!", return result);
2056
2057 /* Since only the initial state is completely set up at this point
2058 * (the other states are just copies of the boot state) we only
2059 * need to populate the ARB settings for the initial state.
2060 */
2cc0c0b5 2061 result = polaris10_program_memory_timing_parameters(hwmgr);
a23eefa2
RZ		 2062 PP_ASSERT_WITH_CODE(0 == result,
2063 "Failed to Write ARB settings for the initial state.", return result);
2064
2cc0c0b5 2065 result = polaris10_populate_smc_uvd_level(hwmgr, table);
a23eefa2
RZ		 2066 PP_ASSERT_WITH_CODE(0 == result,
2067 "Failed to initialize UVD Level!", return result);
2068
2cc0c0b5 2069 result = polaris10_populate_smc_boot_level(hwmgr, table);
a23eefa2
RZ		 2070 PP_ASSERT_WITH_CODE(0 == result,
2071 "Failed to initialize Boot Level!", return result);
2072
2cc0c0b5 2073 result = polaris10_populate_smc_initailial_state(hwmgr);
a23eefa2
RZ		 2074 PP_ASSERT_WITH_CODE(0 == result,
2075 "Failed to initialize Boot State!", return result);
2076
2cc0c0b5 2077 result = polaris10_populate_bapm_parameters_in_dpm_table(hwmgr);
a23eefa2
RZ		 2078 PP_ASSERT_WITH_CODE(0 == result,
2079 "Failed to populate BAPM Parameters!", return result);
2080
2081 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2082 PHM_PlatformCaps_ClockStretcher)) {
2cc0c0b5 2083 result = polaris10_populate_clock_stretcher_data_table(hwmgr);
a23eefa2
RZ		 2084 PP_ASSERT_WITH_CODE(0 == result,
2085 "Failed to populate Clock Stretcher Data Table!",
2086 return result);
2087 }
2088
2089 table->GraphicsVoltageChangeEnable = 1;
2090 table->GraphicsThermThrottleEnable = 1;
2091 table->GraphicsInterval = 1;
2092 table->VoltageInterval = 1;
2093 table->ThermalInterval = 1;
2094 table->TemperatureLimitHigh =
2095 table_info->cac_dtp_table->usTargetOperatingTemp *
2cc0c0b5 2096 POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
a23eefa2
RZ		 2097 table->TemperatureLimitLow =
2098 (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
2cc0c0b5 2099 POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
a23eefa2
RZ		 2100 table->MemoryVoltageChangeEnable = 1;
2101 table->MemoryInterval = 1;
2102 table->VoltageResponseTime = 0;
2103 table->PhaseResponseTime = 0;
2104 table->MemoryThermThrottleEnable = 1;
2105 table->PCIeBootLinkLevel = 0;
2106 table->PCIeGenInterval = 1;
2107
2cc0c0b5 2108 result = polaris10_populate_vr_config(hwmgr, table);
a23eefa2
RZ		 2109 PP_ASSERT_WITH_CODE(0 == result,
2110 "Failed to populate VRConfig setting!", return result);
2111
2112 table->ThermGpio = 17;
2113 table->SclkStepSize = 0x4000;
2114
2115 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
2116 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
2117 } else {
2cc0c0b5 2118 table->VRHotGpio = POLARIS10_UNUSED_GPIO_PIN;
a23eefa2
RZ		 2119 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2120 PHM_PlatformCaps_RegulatorHot);
2121 }
2122
2123 if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
2124 &gpio_pin)) {
2125 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
2126 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2127 PHM_PlatformCaps_AutomaticDCTransition);
2128 } else {
2cc0c0b5 2129 table->AcDcGpio = POLARIS10_UNUSED_GPIO_PIN;
a23eefa2
RZ		 2130 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2131 PHM_PlatformCaps_AutomaticDCTransition);
2132 }
2133
2134 /* Thermal Output GPIO */
2135 if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
2136 &gpio_pin)) {
2137 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2138 PHM_PlatformCaps_ThermalOutGPIO);
2139
2140 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
2141
2142 /* For porlarity read GPIOPAD_A with assigned Gpio pin
2143 * since VBIOS will program this register to set 'inactive state',
2144 * driver can then determine 'active state' from this and
2145 * program SMU with correct polarity
2146 */
2147 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A)
2148 & (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
2149 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
2150
2151 /* if required, combine VRHot/PCC with thermal out GPIO */
2152 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot)
2153 && phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal))
2154 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
2155 } else {
2156 table->ThermOutGpio = 17;
2157 table->ThermOutPolarity = 1;
2158 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
2159 }
2160
e85c7d66 2161 /* Populate BIF_SCLK levels into SMC DPM table */
2162 for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++) {
2163 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, data->bif_sclk_table[i], &dividers);
2164 PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result);
2165
2166 if (i == 0)
2167 table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2168 else
2169 table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2170 }
2171
a23eefa2
RZ		 2172 for (i = 0; i < SMU74_MAX_ENTRIES_SMIO; i++)
2173 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
2174
2175 CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2176 CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2177 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
2178 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
2179 CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2180 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2181 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2182 CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2183 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2184
2185 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2cc0c0b5 2186 result = polaris10_copy_bytes_to_smc(hwmgr->smumgr,
a23eefa2
RZ		 2187 data->dpm_table_start +
2188 offsetof(SMU74_Discrete_DpmTable, SystemFlags),
2189 (uint8_t *)&(table->SystemFlags),
2190 sizeof(SMU74_Discrete_DpmTable) - 3 * sizeof(SMU74_PIDController),
2191 data->sram_end);
2192 PP_ASSERT_WITH_CODE(0 == result,
2193 "Failed to upload dpm data to SMC memory!", return result);
2194
2195 return 0;
2196}
2197
2198/**
2199* Initialize the ARB DRAM timing table's index field.
2200*
2201* @param hwmgr the address of the powerplay hardware manager.
2202* @return always 0
2203*/
2cc0c0b5 2204static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr)
a23eefa2 2205{
2cc0c0b5 2206 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 2207 uint32_t tmp;
2208 int result;
2209
2210 /* This is a read-modify-write on the first byte of the ARB table.
2211 * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
2212 * is the field 'current'.
2213 * This solution is ugly, but we never write the whole table only
2214 * individual fields in it.
2215 * In reality this field should not be in that structure
2216 * but in a soft register.
2217 */
2cc0c0b5 2218 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
a23eefa2
RZ		 2219 data->arb_table_start, &tmp, data->sram_end);
2220
2221 if (result)
2222 return result;
2223
2224 tmp &= 0x00FFFFFF;
2225 tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
2226
2cc0c0b5 2227 return polaris10_write_smc_sram_dword(hwmgr->smumgr,
a23eefa2
RZ		 2228 data->arb_table_start, tmp, data->sram_end);
2229}
2230
2cc0c0b5 2231static int polaris10_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2232{
2233 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2234 PHM_PlatformCaps_RegulatorHot))
2235 return smum_send_msg_to_smc(hwmgr->smumgr,
2236 PPSMC_MSG_EnableVRHotGPIOInterrupt);
2237
2238 return 0;
2239}
2240
2cc0c0b5 2241static int polaris10_enable_sclk_control(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2242{
2243 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2244 SCLK_PWRMGT_OFF, 0);
2245 return 0;
2246}
2247
2cc0c0b5 2248static int polaris10_enable_ulv(struct pp_hwmgr *hwmgr)
a23eefa2 2249{
2cc0c0b5
FC		 2250 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2251 struct polaris10_ulv_parm *ulv = &(data->ulv);
a23eefa2
RZ		 2252
2253 if (ulv->ulv_supported)
2254 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV);
2255
2256 return 0;
2257}
2258
2cc0c0b5 2259static int polaris10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2260{
2261 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2262 PHM_PlatformCaps_SclkDeepSleep)) {
2263 if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON))
2264 PP_ASSERT_WITH_CODE(false,
2265 "Attempt to enable Master Deep Sleep switch failed!",
2266 return -1);
2267 } else {
2268 if (smum_send_msg_to_smc(hwmgr->smumgr,
2269 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
2270 PP_ASSERT_WITH_CODE(false,
2271 "Attempt to disable Master Deep Sleep switch failed!",
2272 return -1);
2273 }
2274 }
2275
2276 return 0;
2277}
2278
2cc0c0b5 2279static int polaris10_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
a23eefa2 2280{
2cc0c0b5 2281 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 2282
2283 /* enable SCLK dpm */
2284 if (!data->sclk_dpm_key_disabled)
2285 PP_ASSERT_WITH_CODE(
2286 (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)),
2287 "Failed to enable SCLK DPM during DPM Start Function!",
2288 return -1);
2289
2290 /* enable MCLK dpm */
2291 if (0 == data->mclk_dpm_key_disabled) {
2292
2293 PP_ASSERT_WITH_CODE(
2294 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2295 PPSMC_MSG_MCLKDPM_Enable)),
2296 "Failed to enable MCLK DPM during DPM Start Function!",
2297 return -1);
2298
2299
2300 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
2301
2302 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
2303 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
2304 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
2305 udelay(10);
2306 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
2307 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
2308 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
2309 }
2310
2311 return 0;
2312}
2313
2cc0c0b5 2314static int polaris10_start_dpm(struct pp_hwmgr *hwmgr)
a23eefa2 2315{
2cc0c0b5 2316 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 2317
2318 /*enable general power management */
2319
2320 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2321 GLOBAL_PWRMGT_EN, 1);
2322
2323 /* enable sclk deep sleep */
2324
2325 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2326 DYNAMIC_PM_EN, 1);
2327
2328 /* prepare for PCIE DPM */
2329
2330 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2331 data->soft_regs_start + offsetof(SMU74_SoftRegisters,
2332 VoltageChangeTimeout), 0x1000);
2333 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
2334 SWRST_COMMAND_1, RESETLC, 0x0);
e85c7d66 2335/*
a23eefa2
RZ		 2336 PP_ASSERT_WITH_CODE(
2337 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2338 PPSMC_MSG_Voltage_Cntl_Enable)),
2339 "Failed to enable voltage DPM during DPM Start Function!",
2340 return -1);
e85c7d66 2341*/
a23eefa2 2342
2cc0c0b5 2343 if (polaris10_enable_sclk_mclk_dpm(hwmgr)) {
a23eefa2
RZ		 2344 printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!");
2345 return -1;
2346 }
2347
2348 /* enable PCIE dpm */
2349 if (0 == data->pcie_dpm_key_disabled) {
2350 PP_ASSERT_WITH_CODE(
2351 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2352 PPSMC_MSG_PCIeDPM_Enable)),
2353 "Failed to enable pcie DPM during DPM Start Function!",
2354 return -1);
2355 }
2356
c8c67448
EH		 2357 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2358 PHM_PlatformCaps_Falcon_QuickTransition)) {
2359 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr,
2360 PPSMC_MSG_EnableACDCGPIOInterrupt)),
2361 "Failed to enable AC DC GPIO Interrupt!",
2362 );
2363 }
a23eefa2
RZ		 2364
2365 return 0;
2366}
2367
2cc0c0b5 2368static void polaris10_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)
a23eefa2
RZ		 2369{
2370 bool protection;
2371 enum DPM_EVENT_SRC src;
2372
2373 switch (sources) {
2374 default:
2375 printk(KERN_ERR "Unknown throttling event sources.");
2376 /* fall through */
2377 case 0:
2378 protection = false;
2379 /* src is unused */
2380 break;
2381 case (1 << PHM_AutoThrottleSource_Thermal):
2382 protection = true;
2383 src = DPM_EVENT_SRC_DIGITAL;
2384 break;
2385 case (1 << PHM_AutoThrottleSource_External):
2386 protection = true;
2387 src = DPM_EVENT_SRC_EXTERNAL;
2388 break;
2389 case (1 << PHM_AutoThrottleSource_External) |
2390 (1 << PHM_AutoThrottleSource_Thermal):
2391 protection = true;
2392 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
2393 break;
2394 }
2395 /* Order matters - don't enable thermal protection for the wrong source. */
2396 if (protection) {
2397 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
2398 DPM_EVENT_SRC, src);
2399 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2400 THERMAL_PROTECTION_DIS,
f0911de8 2401 !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
a23eefa2
RZ		 2402 PHM_PlatformCaps_ThermalController));
2403 } else
2404 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2405 THERMAL_PROTECTION_DIS, 1);
2406}
2407
2cc0c0b5 2408static int polaris10_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 2409 PHM_AutoThrottleSource source)
2410{
2cc0c0b5 2411 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 2412
2413 if (!(data->active_auto_throttle_sources & (1 << source))) {
2414 data->active_auto_throttle_sources |= 1 << source;
2cc0c0b5 2415 polaris10_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
a23eefa2
RZ		 2416 }
2417 return 0;
2418}
2419
2cc0c0b5 2420static int polaris10_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
a23eefa2 2421{
2cc0c0b5 2422 return polaris10_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
a23eefa2
RZ		 2423}
2424
2cc0c0b5 2425int polaris10_pcie_performance_request(struct pp_hwmgr *hwmgr)
a23eefa2 2426{
2cc0c0b5 2427 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 2428 data->pcie_performance_request = true;
2429
2430 return 0;
2431}
2432
2cc0c0b5 2433int polaris10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2434{
2435 int tmp_result, result = 0;
2cc0c0b5 2436 tmp_result = (!polaris10_is_dpm_running(hwmgr)) ? 0 : -1;
a23eefa2
RZ		 2437 PP_ASSERT_WITH_CODE(result == 0,
2438 "DPM is already running right now, no need to enable DPM!",
2439 return 0);
2440
2cc0c0b5
FC		 2441 if (polaris10_voltage_control(hwmgr)) {
2442 tmp_result = polaris10_enable_voltage_control(hwmgr);
a23eefa2
RZ		 2443 PP_ASSERT_WITH_CODE(tmp_result == 0,
2444 "Failed to enable voltage control!",
2445 result = tmp_result);
2446
2cc0c0b5 2447 tmp_result = polaris10_construct_voltage_tables(hwmgr);
a23eefa2
RZ		 2448 PP_ASSERT_WITH_CODE((0 == tmp_result),
2449 "Failed to contruct voltage tables!",
2450 result = tmp_result);
2451 }
2452
2453 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2454 PHM_PlatformCaps_EngineSpreadSpectrumSupport))
2455 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2456 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
2457
2458 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2459 PHM_PlatformCaps_ThermalController))
2460 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2461 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
2462
2cc0c0b5 2463 tmp_result = polaris10_program_static_screen_threshold_parameters(hwmgr);
a23eefa2
RZ		 2464 PP_ASSERT_WITH_CODE((0 == tmp_result),
2465 "Failed to program static screen threshold parameters!",
2466 result = tmp_result);
2467
2cc0c0b5 2468 tmp_result = polaris10_enable_display_gap(hwmgr);
a23eefa2
RZ		 2469 PP_ASSERT_WITH_CODE((0 == tmp_result),
2470 "Failed to enable display gap!", result = tmp_result);
2471
2cc0c0b5 2472 tmp_result = polaris10_program_voting_clients(hwmgr);
a23eefa2
RZ		 2473 PP_ASSERT_WITH_CODE((0 == tmp_result),
2474 "Failed to program voting clients!", result = tmp_result);
2475
2cc0c0b5 2476 tmp_result = polaris10_process_firmware_header(hwmgr);
a23eefa2
RZ		 2477 PP_ASSERT_WITH_CODE((0 == tmp_result),
2478 "Failed to process firmware header!", result = tmp_result);
2479
2cc0c0b5 2480 tmp_result = polaris10_initial_switch_from_arbf0_to_f1(hwmgr);
a23eefa2
RZ		 2481 PP_ASSERT_WITH_CODE((0 == tmp_result),
2482 "Failed to initialize switch from ArbF0 to F1!",
2483 result = tmp_result);
2484
2cc0c0b5 2485 tmp_result = polaris10_init_smc_table(hwmgr);
a23eefa2
RZ		 2486 PP_ASSERT_WITH_CODE((0 == tmp_result),
2487 "Failed to initialize SMC table!", result = tmp_result);
2488
2cc0c0b5 2489 tmp_result = polaris10_init_arb_table_index(hwmgr);
a23eefa2
RZ		 2490 PP_ASSERT_WITH_CODE((0 == tmp_result),
2491 "Failed to initialize ARB table index!", result = tmp_result);
2492
2cc0c0b5 2493 tmp_result = polaris10_populate_pm_fuses(hwmgr);
a23eefa2
RZ		 2494 PP_ASSERT_WITH_CODE((0 == tmp_result),
2495 "Failed to populate PM fuses!", result = tmp_result);
2496
2cc0c0b5 2497 tmp_result = polaris10_enable_vrhot_gpio_interrupt(hwmgr);
a23eefa2
RZ		 2498 PP_ASSERT_WITH_CODE((0 == tmp_result),
2499 "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
2500
2cc0c0b5 2501 tmp_result = polaris10_enable_sclk_control(hwmgr);
a23eefa2
RZ		 2502 PP_ASSERT_WITH_CODE((0 == tmp_result),
2503 "Failed to enable SCLK control!", result = tmp_result);
2504
2cc0c0b5 2505 tmp_result = polaris10_enable_smc_voltage_controller(hwmgr);
e85c7d66 2506 PP_ASSERT_WITH_CODE((0 == tmp_result),
2507 "Failed to enable voltage control!", result = tmp_result);
2508
2cc0c0b5 2509 tmp_result = polaris10_enable_ulv(hwmgr);
a23eefa2
RZ		 2510 PP_ASSERT_WITH_CODE((0 == tmp_result),
2511 "Failed to enable ULV!", result = tmp_result);
2512
2cc0c0b5 2513 tmp_result = polaris10_enable_deep_sleep_master_switch(hwmgr);
a23eefa2
RZ		 2514 PP_ASSERT_WITH_CODE((0 == tmp_result),
2515 "Failed to enable deep sleep master switch!", result = tmp_result);
2516
2cc0c0b5 2517 tmp_result = polaris10_start_dpm(hwmgr);
a23eefa2
RZ		 2518 PP_ASSERT_WITH_CODE((0 == tmp_result),
2519 "Failed to start DPM!", result = tmp_result);
2520
2cc0c0b5 2521 tmp_result = polaris10_enable_smc_cac(hwmgr);
a23eefa2
RZ		 2522 PP_ASSERT_WITH_CODE((0 == tmp_result),
2523 "Failed to enable SMC CAC!", result = tmp_result);
2524
2cc0c0b5 2525 tmp_result = polaris10_enable_power_containment(hwmgr);
a23eefa2
RZ		 2526 PP_ASSERT_WITH_CODE((0 == tmp_result),
2527 "Failed to enable power containment!", result = tmp_result);
2528
2cc0c0b5 2529 tmp_result = polaris10_power_control_set_level(hwmgr);
a23eefa2
RZ		 2530 PP_ASSERT_WITH_CODE((0 == tmp_result),
2531 "Failed to power control set level!", result = tmp_result);
2532
2cc0c0b5 2533 tmp_result = polaris10_enable_thermal_auto_throttle(hwmgr);
a23eefa2
RZ		 2534 PP_ASSERT_WITH_CODE((0 == tmp_result),
2535 "Failed to enable thermal auto throttle!", result = tmp_result);
2536
2cc0c0b5 2537 tmp_result = polaris10_pcie_performance_request(hwmgr);
a23eefa2 2538 PP_ASSERT_WITH_CODE((0 == tmp_result),
5f88567c 2539 "pcie performance request failed!", result = tmp_result);
a23eefa2
RZ		 2540
2541 return result;
2542}
2543
2cc0c0b5 2544int polaris10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2545{
2546
2547 return 0;
2548}
2549
2cc0c0b5 2550int polaris10_reset_asic_tasks(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2551{
2552
2553 return 0;
2554}
2555
2cc0c0b5 2556int polaris10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2557{
2558 return phm_hwmgr_backend_fini(hwmgr);
2559}
2560
2cc0c0b5 2561int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
a23eefa2 2562{
2cc0c0b5 2563 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 2564
2565 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2566 PHM_PlatformCaps_SclkDeepSleep);
2567
f0911de8
RZ		 2568 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2569 PHM_PlatformCaps_DynamicPatchPowerState);
2570
2cc0c0b5 2571 if (data->mvdd_control == POLARIS10_VOLTAGE_CONTROL_NONE)
a23eefa2
RZ		 2572 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2573 PHM_PlatformCaps_EnableMVDDControl);
2574
2cc0c0b5 2575 if (data->vddci_control == POLARIS10_VOLTAGE_CONTROL_NONE)
a23eefa2
RZ		 2576 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2577 PHM_PlatformCaps_ControlVDDCI);
2578
2579 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2580 PHM_PlatformCaps_TablelessHardwareInterface);
2581
2582 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2583 PHM_PlatformCaps_EnableSMU7ThermalManagement);
2584
2585 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2586 PHM_PlatformCaps_DynamicPowerManagement);
2587
f0911de8
RZ		 2588 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2589 PHM_PlatformCaps_UnTabledHardwareInterface);
2590
a23eefa2
RZ		 2591 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2592 PHM_PlatformCaps_TablelessHardwareInterface);
2593
2594 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2595 PHM_PlatformCaps_SMC);
2596
2597 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2598 PHM_PlatformCaps_NonABMSupportInPPLib);
2599
2600 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2601 PHM_PlatformCaps_DynamicUVDState);
2602
a23eefa2 2603 /* power tune caps Assume disabled */
a23eefa2
RZ		 2604 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2605 PHM_PlatformCaps_SQRamping);
2606 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2607 PHM_PlatformCaps_DBRamping);
2608 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2609 PHM_PlatformCaps_TDRamping);
2610 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2611 PHM_PlatformCaps_TCPRamping);
2612
f0911de8
RZ		 2613 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2614 PHM_PlatformCaps_PowerContainment);
2615 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2616 PHM_PlatformCaps_CAC);
2617
2618 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2619 PHM_PlatformCaps_RegulatorHot);
2620
2621 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2622 PHM_PlatformCaps_AutomaticDCTransition);
2623
2624 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2625 PHM_PlatformCaps_ODFuzzyFanControlSupport);
2626
2627 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2628 PHM_PlatformCaps_FanSpeedInTableIsRPM);
5de95e55
RZ		 2629 if (hwmgr->chip_id == CHIP_POLARIS11)
2630 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2631 PHM_PlatformCaps_SPLLShutdownSupport);
a23eefa2
RZ		 2632 return 0;
2633}
2634
2cc0c0b5 2635static void polaris10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
a23eefa2 2636{
2cc0c0b5 2637 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2 2638
2cc0c0b5 2639 polaris10_initialize_power_tune_defaults(hwmgr);
a23eefa2
RZ		 2640
2641 data->pcie_gen_performance.max = PP_PCIEGen1;
2642 data->pcie_gen_performance.min = PP_PCIEGen3;
2643 data->pcie_gen_power_saving.max = PP_PCIEGen1;
2644 data->pcie_gen_power_saving.min = PP_PCIEGen3;
2645 data->pcie_lane_performance.max = 0;
2646 data->pcie_lane_performance.min = 16;
2647 data->pcie_lane_power_saving.max = 0;
2648 data->pcie_lane_power_saving.min = 16;
2649}
2650
2651/**
2652* Get Leakage VDDC based on leakage ID.
2653*
2654* @param hwmgr the address of the powerplay hardware manager.
2655* @return always 0
2656*/
2cc0c0b5 2657static int polaris10_get_evv_voltages(struct pp_hwmgr *hwmgr)
a23eefa2 2658{
2cc0c0b5 2659 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 2660 uint16_t vv_id;
2661 uint16_t vddc = 0;
2662 uint16_t i, j;
2663 uint32_t sclk = 0;
2664 struct phm_ppt_v1_information *table_info =
2665 (struct phm_ppt_v1_information *)hwmgr->pptable;
2666 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2667 table_info->vdd_dep_on_sclk;
2668 int result;
2669
2cc0c0b5 2670 for (i = 0; i < POLARIS10_MAX_LEAKAGE_COUNT; i++) {
a23eefa2
RZ		 2671 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
2672 if (!phm_get_sclk_for_voltage_evv(hwmgr,
2673 table_info->vddc_lookup_table, vv_id, &sclk)) {
2674 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2675 PHM_PlatformCaps_ClockStretcher)) {
2676 for (j = 1; j < sclk_table->count; j++) {
2677 if (sclk_table->entries[j].clk == sclk &&
2678 sclk_table->entries[j].cks_enable == 0) {
2679 sclk += 5000;
2680 break;
2681 }
2682 }
2683 }
2684
2685
2686 PP_ASSERT_WITH_CODE(0 == atomctrl_get_voltage_evv_on_sclk_ai(hwmgr,
2687 VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc),
2688 "Error retrieving EVV voltage value!",
2689 continue);
2690
2691
2692 /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
2693 PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0),
2694 "Invalid VDDC value", result = -EINVAL;);
2695
2696 /* the voltage should not be zero nor equal to leakage ID */
2697 if (vddc != 0 && vddc != vv_id) {
2698 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100);
2699 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
2700 data->vddc_leakage.count++;
2701 }
2702 }
2703 }
2704
2705 return 0;
2706}
2707
2708/**
2709 * Change virtual leakage voltage to actual value.
2710 *
2711 * @param hwmgr the address of the powerplay hardware manager.
2712 * @param pointer to changing voltage
2713 * @param pointer to leakage table
2714 */
2cc0c0b5
FC		 2715static void polaris10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
2716 uint16_t *voltage, struct polaris10_leakage_voltage *leakage_table)
a23eefa2
RZ		 2717{
2718 uint32_t index;
2719
2720 /* search for leakage voltage ID 0xff01 ~ 0xff08 */
2721 for (index = 0; index < leakage_table->count; index++) {
2722 /* if this voltage matches a leakage voltage ID */
2723 /* patch with actual leakage voltage */
2724 if (leakage_table->leakage_id[index] == *voltage) {
2725 *voltage = leakage_table->actual_voltage[index];
2726 break;
2727 }
2728 }
2729
2730 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
2731 printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n");
2732}
2733
2734/**
2735* Patch voltage lookup table by EVV leakages.
2736*
2737* @param hwmgr the address of the powerplay hardware manager.
2738* @param pointer to voltage lookup table
2739* @param pointer to leakage table
2740* @return always 0
2741*/
2cc0c0b5 2742static int polaris10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
a23eefa2 2743 phm_ppt_v1_voltage_lookup_table *lookup_table,
2cc0c0b5 2744 struct polaris10_leakage_voltage *leakage_table)
a23eefa2
RZ		 2745{
2746 uint32_t i;
2747
2748 for (i = 0; i < lookup_table->count; i++)
2cc0c0b5 2749 polaris10_patch_with_vdd_leakage(hwmgr,
a23eefa2
RZ		 2750 &lookup_table->entries[i].us_vdd, leakage_table);
2751
2752 return 0;
2753}
2754
2cc0c0b5
FC		 2755static int polaris10_patch_clock_voltage_limits_with_vddc_leakage(
2756 struct pp_hwmgr *hwmgr, struct polaris10_leakage_voltage *leakage_table,
a23eefa2
RZ		 2757 uint16_t *vddc)
2758{
2759 struct phm_ppt_v1_information *table_info =
2760 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2cc0c0b5 2761 polaris10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
a23eefa2
RZ		 2762 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
2763 table_info->max_clock_voltage_on_dc.vddc;
2764 return 0;
2765}
2766
2cc0c0b5 2767static int polaris10_patch_voltage_dependency_tables_with_lookup_table(
a23eefa2
RZ		 2768 struct pp_hwmgr *hwmgr)
2769{
2770 uint8_t entryId;
2771 uint8_t voltageId;
2772 struct phm_ppt_v1_information *table_info =
2773 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2774
2775 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2776 table_info->vdd_dep_on_sclk;
2777 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
2778 table_info->vdd_dep_on_mclk;
2779 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2780 table_info->mm_dep_table;
2781
2782 for (entryId = 0; entryId < sclk_table->count; ++entryId) {
2783 voltageId = sclk_table->entries[entryId].vddInd;
2784 sclk_table->entries[entryId].vddc =
2785 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2786 }
2787
2788 for (entryId = 0; entryId < mclk_table->count; ++entryId) {
2789 voltageId = mclk_table->entries[entryId].vddInd;
2790 mclk_table->entries[entryId].vddc =
2791 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2792 }
2793
2794 for (entryId = 0; entryId < mm_table->count; ++entryId) {
2795 voltageId = mm_table->entries[entryId].vddcInd;
2796 mm_table->entries[entryId].vddc =
2797 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2798 }
2799
2800 return 0;
2801
2802}
2803
2cc0c0b5 2804static int polaris10_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2805{
2806 /* Need to determine if we need calculated voltage. */
2807 return 0;
2808}
2809
2cc0c0b5 2810static int polaris10_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2811{
2812 /* Need to determine if we need calculated voltage from mm table. */
2813 return 0;
2814}
2815
2cc0c0b5 2816static int polaris10_sort_lookup_table(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 2817 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
2818{
2819 uint32_t table_size, i, j;
2820 struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
2821 table_size = lookup_table->count;
2822
2823 PP_ASSERT_WITH_CODE(0 != lookup_table->count,
2824 "Lookup table is empty", return -EINVAL);
2825
2826 /* Sorting voltages */
2827 for (i = 0; i < table_size - 1; i++) {
2828 for (j = i + 1; j > 0; j--) {
2829 if (lookup_table->entries[j].us_vdd <
2830 lookup_table->entries[j - 1].us_vdd) {
2831 tmp_voltage_lookup_record = lookup_table->entries[j - 1];
2832 lookup_table->entries[j - 1] = lookup_table->entries[j];
2833 lookup_table->entries[j] = tmp_voltage_lookup_record;
2834 }
2835 }
2836 }
2837
2838 return 0;
2839}
2840
2cc0c0b5 2841static int polaris10_complete_dependency_tables(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2842{
2843 int result = 0;
2844 int tmp_result;
2cc0c0b5 2845 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 2846 struct phm_ppt_v1_information *table_info =
2847 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2848
2cc0c0b5 2849 tmp_result = polaris10_patch_lookup_table_with_leakage(hwmgr,
a23eefa2
RZ		 2850 table_info->vddc_lookup_table, &(data->vddc_leakage));
2851 if (tmp_result)
2852 result = tmp_result;
2853
2cc0c0b5 2854 tmp_result = polaris10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
a23eefa2
RZ		 2855 &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
2856 if (tmp_result)
2857 result = tmp_result;
2858
2cc0c0b5 2859 tmp_result = polaris10_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
a23eefa2
RZ		 2860 if (tmp_result)
2861 result = tmp_result;
2862
2cc0c0b5 2863 tmp_result = polaris10_calc_voltage_dependency_tables(hwmgr);
a23eefa2
RZ		 2864 if (tmp_result)
2865 result = tmp_result;
2866
2cc0c0b5 2867 tmp_result = polaris10_calc_mm_voltage_dependency_table(hwmgr);
a23eefa2
RZ		 2868 if (tmp_result)
2869 result = tmp_result;
2870
2cc0c0b5 2871 tmp_result = polaris10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
a23eefa2
RZ		 2872 if (tmp_result)
2873 result = tmp_result;
2874
2875 return result;
2876}
2877
2cc0c0b5 2878static int polaris10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2879{
2880 struct phm_ppt_v1_information *table_info =
2881 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2882
2883 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
2884 table_info->vdd_dep_on_sclk;
2885 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
2886 table_info->vdd_dep_on_mclk;
2887
2888 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
2889 "VDD dependency on SCLK table is missing. \
2890 This table is mandatory", return -EINVAL);
2891 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
2892 "VDD dependency on SCLK table has to have is missing. \
2893 This table is mandatory", return -EINVAL);
2894
2895 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
2896 "VDD dependency on MCLK table is missing. \
2897 This table is mandatory", return -EINVAL);
2898 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
2899 "VDD dependency on MCLK table has to have is missing. \
2900 This table is mandatory", return -EINVAL);
2901
2902 table_info->max_clock_voltage_on_ac.sclk =
2903 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
2904 table_info->max_clock_voltage_on_ac.mclk =
2905 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
2906 table_info->max_clock_voltage_on_ac.vddc =
2907 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
2908 table_info->max_clock_voltage_on_ac.vddci =
2909 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
2910
f0911de8
RZ		 2911 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk;
2912 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk;
2913 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc;
2914 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =table_info->max_clock_voltage_on_ac.vddci;
2915
a23eefa2
RZ		 2916 return 0;
2917}
2918
2cc0c0b5 2919int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
a23eefa2 2920{
2cc0c0b5 2921 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 2922 struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
2923 uint32_t temp_reg;
2924 int result;
f0911de8
RZ		 2925 struct phm_ppt_v1_information *table_info =
2926 (struct phm_ppt_v1_information *)(hwmgr->pptable);
a23eefa2
RZ		 2927
2928 data->dll_default_on = false;
2929 data->sram_end = SMC_RAM_END;
7d367c2a 2930 data->mclk_dpm0_activity_target = 0xa;
a23eefa2 2931 data->disable_dpm_mask = 0xFF;
2cc0c0b5
FC		 2932 data->static_screen_threshold = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
2933 data->static_screen_threshold_unit = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
2934 data->activity_target[0] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2935 data->activity_target[1] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2936 data->activity_target[2] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2937 data->activity_target[3] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2938 data->activity_target[4] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2939 data->activity_target[5] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2940 data->activity_target[6] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2941 data->activity_target[7] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2942
2943 data->voting_rights_clients0 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT0;
2944 data->voting_rights_clients1 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT1;
2945 data->voting_rights_clients2 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT2;
2946 data->voting_rights_clients3 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT3;
2947 data->voting_rights_clients4 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT4;
2948 data->voting_rights_clients5 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT5;
2949 data->voting_rights_clients6 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT6;
2950 data->voting_rights_clients7 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT7;
a23eefa2
RZ		 2951
2952 data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
2953
2cc0c0b5 2954 data->mclk_activity_target = PPPOLARIS10_MCLK_TARGETACTIVITY_DFLT;
a23eefa2
RZ		 2955
2956 /* need to set voltage control types before EVV patching */
2cc0c0b5
FC		 2957 data->voltage_control = POLARIS10_VOLTAGE_CONTROL_NONE;
2958 data->vddci_control = POLARIS10_VOLTAGE_CONTROL_NONE;
2959 data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_NONE;
a23eefa2
RZ		 2960
2961 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2962 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
2cc0c0b5 2963 data->voltage_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
a23eefa2 2964
a23eefa2
RZ		 2965 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2966 PHM_PlatformCaps_EnableMVDDControl)) {
2967 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2968 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
2cc0c0b5 2969 data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
a23eefa2
RZ		 2970 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2971 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
2cc0c0b5 2972 data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
a23eefa2
RZ		 2973 }
2974
2975 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2976 PHM_PlatformCaps_ControlVDDCI)) {
2977 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2978 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
2cc0c0b5 2979 data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
a23eefa2
RZ		 2980 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2981 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
2cc0c0b5 2982 data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
a23eefa2
RZ		 2983 }
2984
2cc0c0b5 2985 polaris10_set_features_platform_caps(hwmgr);
a23eefa2 2986
2cc0c0b5 2987 polaris10_init_dpm_defaults(hwmgr);
a23eefa2
RZ		 2988
2989 /* Get leakage voltage based on leakage ID. */
2cc0c0b5 2990 result = polaris10_get_evv_voltages(hwmgr);
a23eefa2
RZ		 2991
2992 if (result) {
2993 printk("Get EVV Voltage Failed. Abort Driver loading!\n");
2994 return -1;
2995 }
2996
2cc0c0b5
FC		 2997 polaris10_complete_dependency_tables(hwmgr);
2998 polaris10_set_private_data_based_on_pptable(hwmgr);
a23eefa2
RZ		 2999
3000 /* Initalize Dynamic State Adjustment Rule Settings */
3001 result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
3002
3003 if (0 == result) {
3004 struct cgs_system_info sys_info = {0};
3005
3006 data->is_tlu_enabled = 0;
3007
3008 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
2cc0c0b5 3009 POLARIS10_MAX_HARDWARE_POWERLEVELS;
a23eefa2
RZ		 3010 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
3011 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
f0911de8 3012
a23eefa2
RZ		 3013
3014 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
3015 temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
3016 switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
3017 case 0:
3018 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
3019 break;
3020 case 1:
3021 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
3022 break;
3023 case 2:
3024 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
3025 break;
3026 case 3:
3027 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
3028 break;
3029 case 4:
3030 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
3031 break;
3032 default:
3033 PP_ASSERT_WITH_CODE(0,
3034 "Failed to setup PCC HW register! Wrong GPIO assigned for VDDC_PCC_GPIO_PINID!",
3035 );
3036 break;
3037 }
3038 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg);
3039 }
3040
f0911de8
RZ		 3041 if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp != 0 &&
3042 hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode) {
3043 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit =
3044 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
3045
3046 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMaxLimit =
3047 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
3048
3049 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMStep = 1;
3050
3051 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100;
3052
3053 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMinLimit =
3054 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
3055
3056 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMStep = 1;
3057
3058 table_info->cac_dtp_table->usDefaultTargetOperatingTemp = (table_info->cac_dtp_table->usDefaultTargetOperatingTemp >= 50) ?
3059 (table_info->cac_dtp_table->usDefaultTargetOperatingTemp -50) : 0;
3060
3061 table_info->cac_dtp_table->usOperatingTempMaxLimit = table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
3062 table_info->cac_dtp_table->usOperatingTempStep = 1;
3063 table_info->cac_dtp_table->usOperatingTempHyst = 1;
3064
3065 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM =
3066 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
3067
3068 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
3069 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM;
3070
3071 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit =
3072 table_info->cac_dtp_table->usOperatingTempMinLimit;
3073
3074 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit =
3075 table_info->cac_dtp_table->usOperatingTempMaxLimit;
3076
3077 hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
3078 table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
3079
3080 hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep =
3081 table_info->cac_dtp_table->usOperatingTempStep;
3082
3083 hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
3084 table_info->cac_dtp_table->usTargetOperatingTemp;
3085 }
3086
a23eefa2
RZ		 3087 sys_info.size = sizeof(struct cgs_system_info);
3088 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
3089 result = cgs_query_system_info(hwmgr->device, &sys_info);
3090 if (result)
3091 data->pcie_gen_cap = 0x30007;
3092 else
3093 data->pcie_gen_cap = (uint32_t)sys_info.value;
3094 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
3095 data->pcie_spc_cap = 20;
3096 sys_info.size = sizeof(struct cgs_system_info);
3097 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
3098 result = cgs_query_system_info(hwmgr->device, &sys_info);
3099 if (result)
3100 data->pcie_lane_cap = 0x2f0000;
3101 else
3102 data->pcie_lane_cap = (uint32_t)sys_info.value;
f0911de8
RZ		 3103
3104 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
3105/* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
3106 hwmgr->platform_descriptor.clockStep.engineClock = 500;
3107 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
a23eefa2
RZ		 3108 } else {
3109 /* Ignore return value in here, we are cleaning up a mess. */
2cc0c0b5 3110 polaris10_hwmgr_backend_fini(hwmgr);
a23eefa2
RZ		 3111 }
3112
3113 return 0;
3114}
3115
2cc0c0b5 3116static int polaris10_force_dpm_highest(struct pp_hwmgr *hwmgr)
a23eefa2 3117{
2cc0c0b5 3118 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 3119 uint32_t level, tmp;
3120
3121 if (!data->pcie_dpm_key_disabled) {
3122 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3123 level = 0;
3124 tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
3125 while (tmp >>= 1)
3126 level++;
3127
3128 if (level)
3129 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3130 PPSMC_MSG_PCIeDPM_ForceLevel, level);
3131 }
3132 }
3133
3134 if (!data->sclk_dpm_key_disabled) {
3135 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3136 level = 0;
3137 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
3138 while (tmp >>= 1)
3139 level++;
3140
3141 if (level)
3142 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3143 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3144 (1 << level));
3145 }
3146 }
3147
3148 if (!data->mclk_dpm_key_disabled) {
3149 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3150 level = 0;
3151 tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
3152 while (tmp >>= 1)
3153 level++;
3154
3155 if (level)
3156 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3157 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3158 (1 << level));
3159 }
3160 }
3161
3162 return 0;
3163}
3164
2cc0c0b5 3165static int polaris10_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
a23eefa2 3166{
2cc0c0b5 3167 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 3168
3169 phm_apply_dal_min_voltage_request(hwmgr);
3170
3171 if (!data->sclk_dpm_key_disabled) {
3172 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
3173 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3174 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3175 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3176 }
3177
3178 if (!data->mclk_dpm_key_disabled) {
3179 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
3180 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3181 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3182 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3183 }
3184
3185 return 0;
3186}
3187
2cc0c0b5 3188static int polaris10_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
a23eefa2 3189{
2cc0c0b5 3190 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2 3191
2cc0c0b5 3192 if (!polaris10_is_dpm_running(hwmgr))
a23eefa2
RZ		 3193 return -EINVAL;
3194
3195 if (!data->pcie_dpm_key_disabled) {
3196 smum_send_msg_to_smc(hwmgr->smumgr,
3197 PPSMC_MSG_PCIeDPM_UnForceLevel);
3198 }
3199
2cc0c0b5 3200 return polaris10_upload_dpm_level_enable_mask(hwmgr);
a23eefa2
RZ		 3201}
3202
2cc0c0b5 3203static int polaris10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
a23eefa2 3204{
2cc0c0b5
FC		 3205 struct polaris10_hwmgr *data =
3206 (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 3207 uint32_t level;
3208
3209 if (!data->sclk_dpm_key_disabled)
3210 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3211 level = phm_get_lowest_enabled_level(hwmgr,
3212 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3213 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3214 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3215 (1 << level));
3216
3217 }
2043f43e 3218
a23eefa2
RZ		 3219 if (!data->mclk_dpm_key_disabled) {
3220 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3221 level = phm_get_lowest_enabled_level(hwmgr,
3222 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3223 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3224 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3225 (1 << level));
3226 }
3227 }
2043f43e 3228
a23eefa2
RZ		 3229 if (!data->pcie_dpm_key_disabled) {
3230 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3231 level = phm_get_lowest_enabled_level(hwmgr,
3232 data->dpm_level_enable_mask.pcie_dpm_enable_mask);
3233 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3234 PPSMC_MSG_PCIeDPM_ForceLevel,
3235 (level));
3236 }
3237 }
3238
3239 return 0;
3240
3241}
2cc0c0b5 3242static int polaris10_force_dpm_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 3243 enum amd_dpm_forced_level level)
3244{
3245 int ret = 0;
3246
3247 switch (level) {
3248 case AMD_DPM_FORCED_LEVEL_HIGH:
2cc0c0b5 3249 ret = polaris10_force_dpm_highest(hwmgr);
a23eefa2
RZ		 3250 if (ret)
3251 return ret;
3252 break;
3253 case AMD_DPM_FORCED_LEVEL_LOW:
2cc0c0b5 3254 ret = polaris10_force_dpm_lowest(hwmgr);
a23eefa2
RZ		 3255 if (ret)
3256 return ret;
3257 break;
3258 case AMD_DPM_FORCED_LEVEL_AUTO:
2cc0c0b5 3259 ret = polaris10_unforce_dpm_levels(hwmgr);
a23eefa2
RZ		 3260 if (ret)
3261 return ret;
3262 break;
3263 default:
3264 break;
3265 }
3266
3267 hwmgr->dpm_level = level;
3268
3269 return ret;
3270}
3271
2cc0c0b5 3272static int polaris10_get_power_state_size(struct pp_hwmgr *hwmgr)
a23eefa2 3273{
2cc0c0b5 3274 return sizeof(struct polaris10_power_state);
a23eefa2
RZ		 3275}
3276
3277
2cc0c0b5 3278static int polaris10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 3279 struct pp_power_state *request_ps,
3280 const struct pp_power_state *current_ps)
3281{
3282
2cc0c0b5
FC		 3283 struct polaris10_power_state *polaris10_ps =
3284 cast_phw_polaris10_power_state(&request_ps->hardware);
a23eefa2
RZ		 3285 uint32_t sclk;
3286 uint32_t mclk;
3287 struct PP_Clocks minimum_clocks = {0};
3288 bool disable_mclk_switching;
3289 bool disable_mclk_switching_for_frame_lock;
3290 struct cgs_display_info info = {0};
3291 const struct phm_clock_and_voltage_limits *max_limits;
3292 uint32_t i;
2cc0c0b5 3293 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 3294 struct phm_ppt_v1_information *table_info =
3295 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3296 int32_t count;
3297 int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3298
3299 data->battery_state = (PP_StateUILabel_Battery ==
3300 request_ps->classification.ui_label);
3301
2cc0c0b5 3302 PP_ASSERT_WITH_CODE(polaris10_ps->performance_level_count == 2,
a23eefa2
RZ		 3303 "VI should always have 2 performance levels",
3304 );
3305
3306 max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
3307 &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3308 &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3309
3310 /* Cap clock DPM tables at DC MAX if it is in DC. */
3311 if (PP_PowerSource_DC == hwmgr->power_source) {
2cc0c0b5
FC		 3312 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3313 if (polaris10_ps->performance_levels[i].memory_clock > max_limits->mclk)
3314 polaris10_ps->performance_levels[i].memory_clock = max_limits->mclk;
3315 if (polaris10_ps->performance_levels[i].engine_clock > max_limits->sclk)
3316 polaris10_ps->performance_levels[i].engine_clock = max_limits->sclk;
a23eefa2
RZ		 3317 }
3318 }
3319
2cc0c0b5
FC		 3320 polaris10_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
3321 polaris10_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
a23eefa2
RZ		 3322
3323 cgs_get_active_displays_info(hwmgr->device, &info);
3324
3325 /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3326
3327 /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
3328
3329 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3330 PHM_PlatformCaps_StablePState)) {
3331 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3332 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
3333
3334 for (count = table_info->vdd_dep_on_sclk->count - 1;
3335 count >= 0; count--) {
3336 if (stable_pstate_sclk >=
3337 table_info->vdd_dep_on_sclk->entries[count].clk) {
3338 stable_pstate_sclk =
3339 table_info->vdd_dep_on_sclk->entries[count].clk;
3340 break;
3341 }
3342 }
3343
3344 if (count < 0)
3345 stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3346
3347 stable_pstate_mclk = max_limits->mclk;
3348
3349 minimum_clocks.engineClock = stable_pstate_sclk;
3350 minimum_clocks.memoryClock = stable_pstate_mclk;
3351 }
3352
3353 if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
3354 minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
3355
3356 if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
3357 minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
3358
2cc0c0b5 3359 polaris10_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
a23eefa2
RZ		 3360
3361 if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
3362 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=
3363 hwmgr->platform_descriptor.overdriveLimit.engineClock),
3364 "Overdrive sclk exceeds limit",
3365 hwmgr->gfx_arbiter.sclk_over_drive =
3366 hwmgr->platform_descriptor.overdriveLimit.engineClock);
3367
3368 if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
2cc0c0b5 3369 polaris10_ps->performance_levels[1].engine_clock =
a23eefa2
RZ		 3370 hwmgr->gfx_arbiter.sclk_over_drive;
3371 }
3372
3373 if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
3374 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=
3375 hwmgr->platform_descriptor.overdriveLimit.memoryClock),
3376 "Overdrive mclk exceeds limit",
3377 hwmgr->gfx_arbiter.mclk_over_drive =
3378 hwmgr->platform_descriptor.overdriveLimit.memoryClock);
3379
3380 if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
2cc0c0b5 3381 polaris10_ps->performance_levels[1].memory_clock =
a23eefa2
RZ		 3382 hwmgr->gfx_arbiter.mclk_over_drive;
3383 }
3384
3385 disable_mclk_switching_for_frame_lock = phm_cap_enabled(
3386 hwmgr->platform_descriptor.platformCaps,
3387 PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
3388
3389 disable_mclk_switching = (1 < info.display_count) ||
3390 disable_mclk_switching_for_frame_lock;
3391
2cc0c0b5
FC		 3392 sclk = polaris10_ps->performance_levels[0].engine_clock;
3393 mclk = polaris10_ps->performance_levels[0].memory_clock;
a23eefa2
RZ		 3394
3395 if (disable_mclk_switching)
2cc0c0b5
FC		 3396 mclk = polaris10_ps->performance_levels
3397 [polaris10_ps->performance_level_count - 1].memory_clock;
a23eefa2
RZ		 3398
3399 if (sclk < minimum_clocks.engineClock)
3400 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
3401 max_limits->sclk : minimum_clocks.engineClock;
3402
3403 if (mclk < minimum_clocks.memoryClock)
3404 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
3405 max_limits->mclk : minimum_clocks.memoryClock;
3406
2cc0c0b5
FC		 3407 polaris10_ps->performance_levels[0].engine_clock = sclk;
3408 polaris10_ps->performance_levels[0].memory_clock = mclk;
a23eefa2 3409
2cc0c0b5
FC		 3410 polaris10_ps->performance_levels[1].engine_clock =
3411 (polaris10_ps->performance_levels[1].engine_clock >=
3412 polaris10_ps->performance_levels[0].engine_clock) ?
3413 polaris10_ps->performance_levels[1].engine_clock :
3414 polaris10_ps->performance_levels[0].engine_clock;
a23eefa2
RZ		 3415
3416 if (disable_mclk_switching) {
2cc0c0b5
FC		 3417 if (mclk < polaris10_ps->performance_levels[1].memory_clock)
3418 mclk = polaris10_ps->performance_levels[1].memory_clock;
a23eefa2 3419
2cc0c0b5
FC		 3420 polaris10_ps->performance_levels[0].memory_clock = mclk;
3421 polaris10_ps->performance_levels[1].memory_clock = mclk;
a23eefa2 3422 } else {
2cc0c0b5
FC		 3423 if (polaris10_ps->performance_levels[1].memory_clock <
3424 polaris10_ps->performance_levels[0].memory_clock)
3425 polaris10_ps->performance_levels[1].memory_clock =
3426 polaris10_ps->performance_levels[0].memory_clock;
a23eefa2
RZ		 3427 }
3428
3429 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3430 PHM_PlatformCaps_StablePState)) {
2cc0c0b5
FC		 3431 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3432 polaris10_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
3433 polaris10_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
3434 polaris10_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
3435 polaris10_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
a23eefa2
RZ		 3436 }
3437 }
3438 return 0;
3439}
3440
3441
2cc0c0b5 3442static int polaris10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
a23eefa2
RZ		 3443{
3444 struct pp_power_state *ps;
2cc0c0b5 3445 struct polaris10_power_state *polaris10_ps;
a23eefa2
RZ		 3446
3447 if (hwmgr == NULL)
3448 return -EINVAL;
3449
3450 ps = hwmgr->request_ps;
3451
3452 if (ps == NULL)
3453 return -EINVAL;
3454
2cc0c0b5 3455 polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
a23eefa2
RZ		 3456
3457 if (low)
2cc0c0b5 3458 return polaris10_ps->performance_levels[0].memory_clock;
a23eefa2 3459 else
2cc0c0b5
FC		 3460 return polaris10_ps->performance_levels
3461 [polaris10_ps->performance_level_count-1].memory_clock;
a23eefa2
RZ		 3462}
3463
2cc0c0b5 3464static int polaris10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
a23eefa2
RZ		 3465{
3466 struct pp_power_state *ps;
2cc0c0b5 3467 struct polaris10_power_state *polaris10_ps;
a23eefa2
RZ		 3468
3469 if (hwmgr == NULL)
3470 return -EINVAL;
3471
3472 ps = hwmgr->request_ps;
3473
3474 if (ps == NULL)
3475 return -EINVAL;
3476
2cc0c0b5 3477 polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
a23eefa2
RZ		 3478
3479 if (low)
2cc0c0b5 3480 return polaris10_ps->performance_levels[0].engine_clock;
a23eefa2 3481 else
2cc0c0b5
FC		 3482 return polaris10_ps->performance_levels
3483 [polaris10_ps->performance_level_count-1].engine_clock;
a23eefa2
RZ		 3484}
3485
2cc0c0b5 3486static int polaris10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 3487 struct pp_hw_power_state *hw_ps)
3488{
2cc0c0b5
FC		 3489 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3490 struct polaris10_power_state *ps = (struct polaris10_power_state *)hw_ps;
a23eefa2
RZ		 3491 ATOM_FIRMWARE_INFO_V2_2 *fw_info;
3492 uint16_t size;
3493 uint8_t frev, crev;
3494 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
3495
3496 /* First retrieve the Boot clocks and VDDC from the firmware info table.
3497 * We assume here that fw_info is unchanged if this call fails.
3498 */
3499 fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
3500 hwmgr->device, index,
3501 &size, &frev, &crev);
3502 if (!fw_info)
3503 /* During a test, there is no firmware info table. */
3504 return 0;
3505
3506 /* Patch the state. */
3507 data->vbios_boot_state.sclk_bootup_value =
3508 le32_to_cpu(fw_info->ulDefaultEngineClock);
3509 data->vbios_boot_state.mclk_bootup_value =
3510 le32_to_cpu(fw_info->ulDefaultMemoryClock);
3511 data->vbios_boot_state.mvdd_bootup_value =
3512 le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
3513 data->vbios_boot_state.vddc_bootup_value =
3514 le16_to_cpu(fw_info->usBootUpVDDCVoltage);
3515 data->vbios_boot_state.vddci_bootup_value =
3516 le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
3517 data->vbios_boot_state.pcie_gen_bootup_value =
3518 phm_get_current_pcie_speed(hwmgr);
3519
3520 data->vbios_boot_state.pcie_lane_bootup_value =
3521 (uint16_t)phm_get_current_pcie_lane_number(hwmgr);
3522
3523 /* set boot power state */
3524 ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
3525 ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
3526 ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
3527 ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
3528
3529 return 0;
3530}
3531
2cc0c0b5 3532static int polaris10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 3533 void *state, struct pp_power_state *power_state,
3534 void *pp_table, uint32_t classification_flag)
3535{
2cc0c0b5
FC		 3536 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3537 struct polaris10_power_state *polaris10_power_state =
3538 (struct polaris10_power_state *)(&(power_state->hardware));
3539 struct polaris10_performance_level *performance_level;
a23eefa2
RZ		 3540 ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
3541 ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
3542 (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
3543 ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table =
3544 (ATOM_Tonga_SCLK_Dependency_Table *)
3545 (((unsigned long)powerplay_table) +
3546 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
3547 ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
3548 (ATOM_Tonga_MCLK_Dependency_Table *)
3549 (((unsigned long)powerplay_table) +
3550 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3551
3552 /* The following fields are not initialized here: id orderedList allStatesList */
3553 power_state->classification.ui_label =
3554 (le16_to_cpu(state_entry->usClassification) &
3555 ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3556 ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3557 power_state->classification.flags = classification_flag;
3558 /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
3559
3560 power_state->classification.temporary_state = false;
3561 power_state->classification.to_be_deleted = false;
3562
3563 power_state->validation.disallowOnDC =
3564 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3565 ATOM_Tonga_DISALLOW_ON_DC));
3566
3567 power_state->pcie.lanes = 0;
3568
3569 power_state->display.disableFrameModulation = false;
3570 power_state->display.limitRefreshrate = false;
3571 power_state->display.enableVariBright =
3572 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3573 ATOM_Tonga_ENABLE_VARIBRIGHT));
3574
3575 power_state->validation.supportedPowerLevels = 0;
3576 power_state->uvd_clocks.VCLK = 0;
3577 power_state->uvd_clocks.DCLK = 0;
3578 power_state->temperatures.min = 0;
3579 power_state->temperatures.max = 0;
3580
2cc0c0b5
FC		 3581 performance_level = &(polaris10_power_state->performance_levels
3582 [polaris10_power_state->performance_level_count++]);
a23eefa2
RZ		 3583
3584 PP_ASSERT_WITH_CODE(
2cc0c0b5 3585 (polaris10_power_state->performance_level_count < SMU74_MAX_LEVELS_GRAPHICS),
a23eefa2
RZ		 3586 "Performance levels exceeds SMC limit!",
3587 return -1);
3588
3589 PP_ASSERT_WITH_CODE(
2cc0c0b5 3590 (polaris10_power_state->performance_level_count <=
a23eefa2
RZ		 3591 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3592 "Performance levels exceeds Driver limit!",
3593 return -1);
3594
3595 /* Performance levels are arranged from low to high. */
3596 performance_level->memory_clock = mclk_dep_table->entries
3597 [state_entry->ucMemoryClockIndexLow].ulMclk;
3598 performance_level->engine_clock = sclk_dep_table->entries
3599 [state_entry->ucEngineClockIndexLow].ulSclk;
3600 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3601 state_entry->ucPCIEGenLow);
3602 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3603 state_entry->ucPCIELaneHigh);
3604
2cc0c0b5
FC		 3605 performance_level = &(polaris10_power_state->performance_levels
3606 [polaris10_power_state->performance_level_count++]);
a23eefa2
RZ		 3607 performance_level->memory_clock = mclk_dep_table->entries
3608 [state_entry->ucMemoryClockIndexHigh].ulMclk;
3609 performance_level->engine_clock = sclk_dep_table->entries
3610 [state_entry->ucEngineClockIndexHigh].ulSclk;
3611 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3612 state_entry->ucPCIEGenHigh);
3613 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3614 state_entry->ucPCIELaneHigh);
3615
3616 return 0;
3617}
3618
2cc0c0b5 3619static int polaris10_get_pp_table_entry(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 3620 unsigned long entry_index, struct pp_power_state *state)
3621{
3622 int result;
2cc0c0b5
FC		 3623 struct polaris10_power_state *ps;
3624 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 3625 struct phm_ppt_v1_information *table_info =
3626 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3627 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
3628 table_info->vdd_dep_on_mclk;
3629
3630 state->hardware.magic = PHM_VIslands_Magic;
3631
2cc0c0b5 3632 ps = (struct polaris10_power_state *)(&state->hardware);
a23eefa2
RZ		 3633
3634 result = tonga_get_powerplay_table_entry(hwmgr, entry_index, state,
2cc0c0b5 3635 polaris10_get_pp_table_entry_callback_func);
a23eefa2
RZ		 3636
3637 /* This is the earliest time we have all the dependency table and the VBIOS boot state
3638 * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
3639 * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
3640 */
3641 if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3642 if (dep_mclk_table->entries[0].clk !=
3643 data->vbios_boot_state.mclk_bootup_value)
3644 printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
3645 "does not match VBIOS boot MCLK level");
3646 if (dep_mclk_table->entries[0].vddci !=
3647 data->vbios_boot_state.vddci_bootup_value)
3648 printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
3649 "does not match VBIOS boot VDDCI level");
3650 }
3651
3652 /* set DC compatible flag if this state supports DC */
3653 if (!state->validation.disallowOnDC)
3654 ps->dc_compatible = true;
3655
3656 if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3657 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3658
3659 ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3660 ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3661
3662 if (!result) {
3663 uint32_t i;
3664
3665 switch (state->classification.ui_label) {
3666 case PP_StateUILabel_Performance:
3667 data->use_pcie_performance_levels = true;
3668
3669 for (i = 0; i < ps->performance_level_count; i++) {
3670 if (data->pcie_gen_performance.max <
3671 ps->performance_levels[i].pcie_gen)
3672 data->pcie_gen_performance.max =
3673 ps->performance_levels[i].pcie_gen;
3674
3675 if (data->pcie_gen_performance.min >
3676 ps->performance_levels[i].pcie_gen)
3677 data->pcie_gen_performance.min =
3678 ps->performance_levels[i].pcie_gen;
3679
3680 if (data->pcie_lane_performance.max <
3681 ps->performance_levels[i].pcie_lane)
3682 data->pcie_lane_performance.max =
3683 ps->performance_levels[i].pcie_lane;
3684
3685 if (data->pcie_lane_performance.min >
3686 ps->performance_levels[i].pcie_lane)
3687 data->pcie_lane_performance.min =
3688 ps->performance_levels[i].pcie_lane;
3689 }
3690 break;
3691 case PP_StateUILabel_Battery:
3692 data->use_pcie_power_saving_levels = true;
3693
3694 for (i = 0; i < ps->performance_level_count; i++) {
3695 if (data->pcie_gen_power_saving.max <
3696 ps->performance_levels[i].pcie_gen)
3697 data->pcie_gen_power_saving.max =
3698 ps->performance_levels[i].pcie_gen;
3699
3700 if (data->pcie_gen_power_saving.min >
3701 ps->performance_levels[i].pcie_gen)
3702 data->pcie_gen_power_saving.min =
3703 ps->performance_levels[i].pcie_gen;
3704
3705 if (data->pcie_lane_power_saving.max <
3706 ps->performance_levels[i].pcie_lane)
3707 data->pcie_lane_power_saving.max =
3708 ps->performance_levels[i].pcie_lane;
3709
3710 if (data->pcie_lane_power_saving.min >
3711 ps->performance_levels[i].pcie_lane)
3712 data->pcie_lane_power_saving.min =
3713 ps->performance_levels[i].pcie_lane;
3714 }
3715 break;
3716 default:
3717 break;
3718 }
3719 }
3720 return 0;
3721}
3722
3723static void
2cc0c0b5 3724polaris10_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
a23eefa2 3725{
b2d96143
RZ		 3726 uint32_t sclk, mclk, activity_percent;
3727 uint32_t offset;
3728 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 3729
3730 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
3731
3732 sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3733
3734 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
3735
3736 mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3737 seq_printf(m, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n",
3738 mclk / 100, sclk / 100);
b2d96143
RZ		 3739
3740 offset = data->soft_regs_start + offsetof(SMU74_SoftRegisters, AverageGraphicsActivity);
3741 activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
3742 activity_percent += 0x80;
3743 activity_percent >>= 8;
3744
3745 seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
3746
3747 seq_printf(m, "uvd %sabled\n", data->uvd_power_gated ? "dis" : "en");
3748
3749 seq_printf(m, "vce %sabled\n", data->vce_power_gated ? "dis" : "en");
a23eefa2
RZ		 3750}
3751
2cc0c0b5 3752static int polaris10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
a23eefa2
RZ		 3753{
3754 const struct phm_set_power_state_input *states =
3755 (const struct phm_set_power_state_input *)input;
2cc0c0b5
FC		 3756 const struct polaris10_power_state *polaris10_ps =
3757 cast_const_phw_polaris10_power_state(states->pnew_state);
3758 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3759 struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
3760 uint32_t sclk = polaris10_ps->performance_levels
3761 [polaris10_ps->performance_level_count - 1].engine_clock;
3762 struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
3763 uint32_t mclk = polaris10_ps->performance_levels
3764 [polaris10_ps->performance_level_count - 1].memory_clock;
a23eefa2
RZ		 3765 struct PP_Clocks min_clocks = {0};
3766 uint32_t i;
3767 struct cgs_display_info info = {0};
3768
3769 data->need_update_smu7_dpm_table = 0;
3770
3771 for (i = 0; i < sclk_table->count; i++) {
3772 if (sclk == sclk_table->dpm_levels[i].value)
3773 break;
3774 }
3775
3776 if (i >= sclk_table->count)
3777 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3778 else {
3779 /* TODO: Check SCLK in DAL's minimum clocks
3780 * in case DeepSleep divider update is required.
3781 */
2cc0c0b5
FC		 3782 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR &&
3783 (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
3784 data->display_timing.min_clock_in_sr >= POLARIS10_MINIMUM_ENGINE_CLOCK))
a23eefa2
RZ		 3785 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3786 }
3787
3788 for (i = 0; i < mclk_table->count; i++) {
3789 if (mclk == mclk_table->dpm_levels[i].value)
3790 break;
3791 }
3792
3793 if (i >= mclk_table->count)
3794 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3795
3796 cgs_get_active_displays_info(hwmgr->device, &info);
3797
3798 if (data->display_timing.num_existing_displays != info.display_count)
3799 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3800
3801 return 0;
3802}
3803
2cc0c0b5
FC		 3804static uint16_t polaris10_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
3805 const struct polaris10_power_state *polaris10_ps)
a23eefa2
RZ		 3806{
3807 uint32_t i;
3808 uint32_t sclk, max_sclk = 0;
2cc0c0b5
FC		 3809 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3810 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
a23eefa2 3811
2cc0c0b5
FC		 3812 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3813 sclk = polaris10_ps->performance_levels[i].engine_clock;
a23eefa2
RZ		 3814 if (max_sclk < sclk)
3815 max_sclk = sclk;
3816 }
3817
3818 for (i = 0; i < dpm_table->sclk_table.count; i++) {
3819 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
3820 return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
3821 dpm_table->pcie_speed_table.dpm_levels
3822 [dpm_table->pcie_speed_table.count - 1].value :
3823 dpm_table->pcie_speed_table.dpm_levels[i].value);
3824 }
3825
3826 return 0;
3827}
3828
2cc0c0b5 3829static int polaris10_request_link_speed_change_before_state_change(
a23eefa2
RZ		 3830 struct pp_hwmgr *hwmgr, const void *input)
3831{
3832 const struct phm_set_power_state_input *states =
3833 (const struct phm_set_power_state_input *)input;
2cc0c0b5
FC		 3834 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3835 const struct polaris10_power_state *polaris10_nps =
3836 cast_const_phw_polaris10_power_state(states->pnew_state);
3837 const struct polaris10_power_state *polaris10_cps =
3838 cast_const_phw_polaris10_power_state(states->pcurrent_state);
a23eefa2 3839
2cc0c0b5 3840 uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_nps);
a23eefa2
RZ		 3841 uint16_t current_link_speed;
3842
3843 if (data->force_pcie_gen == PP_PCIEGenInvalid)
2cc0c0b5 3844 current_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_cps);
a23eefa2
RZ		 3845 else
3846 current_link_speed = data->force_pcie_gen;
3847
3848 data->force_pcie_gen = PP_PCIEGenInvalid;
3849 data->pspp_notify_required = false;
3850
3851 if (target_link_speed > current_link_speed) {
3852 switch (target_link_speed) {
3853 case PP_PCIEGen3:
3854 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
3855 break;
3856 data->force_pcie_gen = PP_PCIEGen2;
3857 if (current_link_speed == PP_PCIEGen2)
3858 break;
3859 case PP_PCIEGen2:
3860 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
3861 break;
3862 default:
3863 data->force_pcie_gen = phm_get_current_pcie_speed(hwmgr);
3864 break;
3865 }
3866 } else {
3867 if (target_link_speed < current_link_speed)
3868 data->pspp_notify_required = true;
3869 }
3870
3871 return 0;
3872}
3873
2cc0c0b5 3874static int polaris10_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
a23eefa2 3875{
2cc0c0b5 3876 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 3877
3878 if (0 == data->need_update_smu7_dpm_table)
3879 return 0;
3880
3881 if ((0 == data->sclk_dpm_key_disabled) &&
3882 (data->need_update_smu7_dpm_table &
3883 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
2cc0c0b5 3884 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
a23eefa2
RZ		 3885 "Trying to freeze SCLK DPM when DPM is disabled",
3886 );
3887 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
3888 PPSMC_MSG_SCLKDPM_FreezeLevel),
3889 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
3890 return -1);
3891 }
3892
3893 if ((0 == data->mclk_dpm_key_disabled) &&
3894 (data->need_update_smu7_dpm_table &
3895 DPMTABLE_OD_UPDATE_MCLK)) {
2cc0c0b5 3896 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
a23eefa2
RZ		 3897 "Trying to freeze MCLK DPM when DPM is disabled",
3898 );
3899 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
3900 PPSMC_MSG_MCLKDPM_FreezeLevel),
3901 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
3902 return -1);
3903 }
3904
3905 return 0;
3906}
3907
2cc0c0b5 3908static int polaris10_populate_and_upload_sclk_mclk_dpm_levels(
a23eefa2
RZ		 3909 struct pp_hwmgr *hwmgr, const void *input)
3910{
3911 int result = 0;
3912 const struct phm_set_power_state_input *states =
3913 (const struct phm_set_power_state_input *)input;
2cc0c0b5
FC		 3914 const struct polaris10_power_state *polaris10_ps =
3915 cast_const_phw_polaris10_power_state(states->pnew_state);
3916 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3917 uint32_t sclk = polaris10_ps->performance_levels
3918 [polaris10_ps->performance_level_count - 1].engine_clock;
3919 uint32_t mclk = polaris10_ps->performance_levels
3920 [polaris10_ps->performance_level_count - 1].memory_clock;
3921 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
3922
3923 struct polaris10_dpm_table *golden_dpm_table = &data->golden_dpm_table;
a23eefa2
RZ		 3924 uint32_t dpm_count, clock_percent;
3925 uint32_t i;
3926
3927 if (0 == data->need_update_smu7_dpm_table)
3928 return 0;
3929
3930 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
3931 dpm_table->sclk_table.dpm_levels
3932 [dpm_table->sclk_table.count - 1].value = sclk;
3933
3934 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
3935 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
3936 /* Need to do calculation based on the golden DPM table
3937 * as the Heatmap GPU Clock axis is also based on the default values
3938 */
3939 PP_ASSERT_WITH_CODE(
3940 (golden_dpm_table->sclk_table.dpm_levels
3941 [golden_dpm_table->sclk_table.count - 1].value != 0),
3942 "Divide by 0!",
3943 return -1);
3944 dpm_count = dpm_table->sclk_table.count < 2 ? 0 : dpm_table->sclk_table.count - 2;
3945
3946 for (i = dpm_count; i > 1; i--) {
3947 if (sclk > golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value) {
3948 clock_percent =
3949 ((sclk
3950 - golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value
3951 ) * 100)
3952 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
3953
3954 dpm_table->sclk_table.dpm_levels[i].value =
3955 golden_dpm_table->sclk_table.dpm_levels[i].value +
3956 (golden_dpm_table->sclk_table.dpm_levels[i].value *
3957 clock_percent)/100;
3958
3959 } else if (golden_dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value > sclk) {
3960 clock_percent =
3961 ((golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value
3962 - sclk) * 100)
3963 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
3964
3965 dpm_table->sclk_table.dpm_levels[i].value =
3966 golden_dpm_table->sclk_table.dpm_levels[i].value -
3967 (golden_dpm_table->sclk_table.dpm_levels[i].value *
3968 clock_percent) / 100;
3969 } else
3970 dpm_table->sclk_table.dpm_levels[i].value =
3971 golden_dpm_table->sclk_table.dpm_levels[i].value;
3972 }
3973 }
3974 }
3975
3976 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
3977 dpm_table->mclk_table.dpm_levels
3978 [dpm_table->mclk_table.count - 1].value = mclk;
3979
3980 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
3981 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
3982
3983 PP_ASSERT_WITH_CODE(
3984 (golden_dpm_table->mclk_table.dpm_levels
3985 [golden_dpm_table->mclk_table.count-1].value != 0),
3986 "Divide by 0!",
3987 return -1);
3988 dpm_count = dpm_table->mclk_table.count < 2 ? 0 : dpm_table->mclk_table.count - 2;
3989 for (i = dpm_count; i > 1; i--) {
3990 if (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value < mclk) {
3991 clock_percent = ((mclk -
3992 golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value) * 100)
3993 / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
3994
3995 dpm_table->mclk_table.dpm_levels[i].value =
3996 golden_dpm_table->mclk_table.dpm_levels[i].value +
3997 (golden_dpm_table->mclk_table.dpm_levels[i].value *
3998 clock_percent) / 100;
3999
4000 } else if (golden_dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value > mclk) {
4001 clock_percent = (
4002 (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value - mclk)
4003 * 100)
4004 / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
4005
4006 dpm_table->mclk_table.dpm_levels[i].value =
4007 golden_dpm_table->mclk_table.dpm_levels[i].value -
4008 (golden_dpm_table->mclk_table.dpm_levels[i].value *
4009 clock_percent) / 100;
4010 } else
4011 dpm_table->mclk_table.dpm_levels[i].value =
4012 golden_dpm_table->mclk_table.dpm_levels[i].value;
4013 }
4014 }
4015 }
4016
4017 if (data->need_update_smu7_dpm_table &
4018 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
2cc0c0b5 4019 result = polaris10_populate_all_graphic_levels(hwmgr);
a23eefa2
RZ		 4020 PP_ASSERT_WITH_CODE((0 == result),
4021 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
4022 return result);
4023 }
4024
4025 if (data->need_update_smu7_dpm_table &
4026 (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
4027 /*populate MCLK dpm table to SMU7 */
2cc0c0b5 4028 result = polaris10_populate_all_memory_levels(hwmgr);
a23eefa2
RZ		 4029 PP_ASSERT_WITH_CODE((0 == result),
4030 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
4031 return result);
4032 }
4033
4034 return result;
4035}
4036
2cc0c0b5
FC		 4037static int polaris10_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
4038 struct polaris10_single_dpm_table *dpm_table,
a23eefa2
RZ		 4039 uint32_t low_limit, uint32_t high_limit)
4040{
4041 uint32_t i;
a23eefa2
RZ		 4042
4043 for (i = 0; i < dpm_table->count; i++) {
4044 if ((dpm_table->dpm_levels[i].value < low_limit)
4045 || (dpm_table->dpm_levels[i].value > high_limit))
4046 dpm_table->dpm_levels[i].enabled = false;
a23eefa2
RZ		 4047 else
4048 dpm_table->dpm_levels[i].enabled = true;
4049 }
4050
4051 return 0;
4052}
4053
2cc0c0b5
FC		 4054static int polaris10_trim_dpm_states(struct pp_hwmgr *hwmgr,
4055 const struct polaris10_power_state *polaris10_ps)
a23eefa2
RZ		 4056{
4057 int result = 0;
2cc0c0b5 4058 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4059 uint32_t high_limit_count;
4060
2cc0c0b5 4061 PP_ASSERT_WITH_CODE((polaris10_ps->performance_level_count >= 1),
a23eefa2
RZ		 4062 "power state did not have any performance level",
4063 return -1);
4064
2cc0c0b5 4065 high_limit_count = (1 == polaris10_ps->performance_level_count) ? 0 : 1;
a23eefa2 4066
2cc0c0b5 4067 polaris10_trim_single_dpm_states(hwmgr,
a23eefa2 4068 &(data->dpm_table.sclk_table),
2cc0c0b5
FC		 4069 polaris10_ps->performance_levels[0].engine_clock,
4070 polaris10_ps->performance_levels[high_limit_count].engine_clock);
a23eefa2 4071
2cc0c0b5 4072 polaris10_trim_single_dpm_states(hwmgr,
a23eefa2 4073 &(data->dpm_table.mclk_table),
2cc0c0b5
FC		 4074 polaris10_ps->performance_levels[0].memory_clock,
4075 polaris10_ps->performance_levels[high_limit_count].memory_clock);
a23eefa2
RZ		 4076
4077 return result;
4078}
4079
2cc0c0b5 4080static int polaris10_generate_dpm_level_enable_mask(
a23eefa2
RZ		 4081 struct pp_hwmgr *hwmgr, const void *input)
4082{
4083 int result;
4084 const struct phm_set_power_state_input *states =
4085 (const struct phm_set_power_state_input *)input;
2cc0c0b5
FC		 4086 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4087 const struct polaris10_power_state *polaris10_ps =
4088 cast_const_phw_polaris10_power_state(states->pnew_state);
a23eefa2 4089
2cc0c0b5 4090 result = polaris10_trim_dpm_states(hwmgr, polaris10_ps);
a23eefa2
RZ		 4091 if (result)
4092 return result;
4093
4094 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
4095 phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
4096 data->dpm_level_enable_mask.mclk_dpm_enable_mask =
4097 phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
4098 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
4099 phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
4100
4101 return 0;
4102}
4103
2cc0c0b5 4104int polaris10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
a23eefa2
RZ		 4105{
4106 return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
92c6d645
EH		 4107 PPSMC_MSG_UVDDPM_Enable :
4108 PPSMC_MSG_UVDDPM_Disable);
4109}
4110
2cc0c0b5 4111int polaris10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
92c6d645
EH		 4112{
4113 return smum_send_msg_to_smc(hwmgr->smumgr, enable?
a23eefa2
RZ		 4114 PPSMC_MSG_VCEDPM_Enable :
4115 PPSMC_MSG_VCEDPM_Disable);
4116}
4117
2cc0c0b5 4118int polaris10_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
92c6d645
EH		 4119{
4120 return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4121 PPSMC_MSG_SAMUDPM_Enable :
4122 PPSMC_MSG_SAMUDPM_Disable);
4123}
4124
2cc0c0b5 4125int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
92c6d645 4126{
2cc0c0b5 4127 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
92c6d645
EH		 4128 uint32_t mm_boot_level_offset, mm_boot_level_value;
4129 struct phm_ppt_v1_information *table_info =
4130 (struct phm_ppt_v1_information *)(hwmgr->pptable);
4131
4132 if (!bgate) {
4133 data->smc_state_table.UvdBootLevel = 0;
4134 if (table_info->mm_dep_table->count > 0)
4135 data->smc_state_table.UvdBootLevel =
4136 (uint8_t) (table_info->mm_dep_table->count - 1);
4137 mm_boot_level_offset = data->dpm_table_start +
4138 offsetof(SMU74_Discrete_DpmTable, UvdBootLevel);
4139 mm_boot_level_offset /= 4;
4140 mm_boot_level_offset *= 4;
4141 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4142 CGS_IND_REG__SMC, mm_boot_level_offset);
4143 mm_boot_level_value &= 0x00FFFFFF;
4144 mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24;
4145 cgs_write_ind_register(hwmgr->device,
4146 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4147
4148 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4149 PHM_PlatformCaps_UVDDPM) ||
4150 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4151 PHM_PlatformCaps_StablePState))
4152 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4153 PPSMC_MSG_UVDDPM_SetEnabledMask,
4154 (uint32_t)(1 << data->smc_state_table.UvdBootLevel));
4155 }
4156
2cc0c0b5 4157 return polaris10_enable_disable_uvd_dpm(hwmgr, !bgate);
92c6d645
EH		 4158}
4159
2cc0c0b5 4160static int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
a23eefa2
RZ		 4161{
4162 const struct phm_set_power_state_input *states =
4163 (const struct phm_set_power_state_input *)input;
2cc0c0b5
FC		 4164 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4165 const struct polaris10_power_state *polaris10_nps =
4166 cast_const_phw_polaris10_power_state(states->pnew_state);
4167 const struct polaris10_power_state *polaris10_cps =
4168 cast_const_phw_polaris10_power_state(states->pcurrent_state);
a23eefa2
RZ		 4169
4170 uint32_t mm_boot_level_offset, mm_boot_level_value;
4171 struct phm_ppt_v1_information *table_info =
4172 (struct phm_ppt_v1_information *)(hwmgr->pptable);
4173
2cc0c0b5
FC		 4174 if (polaris10_nps->vce_clks.evclk > 0 &&
4175 (polaris10_cps == NULL || polaris10_cps->vce_clks.evclk == 0)) {
a23eefa2
RZ		 4176
4177 data->smc_state_table.VceBootLevel =
4178 (uint8_t) (table_info->mm_dep_table->count - 1);
4179
4180 mm_boot_level_offset = data->dpm_table_start +
4181 offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
4182 mm_boot_level_offset /= 4;
4183 mm_boot_level_offset *= 4;
4184 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4185 CGS_IND_REG__SMC, mm_boot_level_offset);
4186 mm_boot_level_value &= 0xFF00FFFF;
4187 mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
4188 cgs_write_ind_register(hwmgr->device,
4189 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4190
4191 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
4192 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4193 PPSMC_MSG_VCEDPM_SetEnabledMask,
4194 (uint32_t)1 << data->smc_state_table.VceBootLevel);
4195
2cc0c0b5
FC		 4196 polaris10_enable_disable_vce_dpm(hwmgr, true);
4197 } else if (polaris10_nps->vce_clks.evclk == 0 &&
4198 polaris10_cps != NULL &&
4199 polaris10_cps->vce_clks.evclk > 0)
4200 polaris10_enable_disable_vce_dpm(hwmgr, false);
a23eefa2
RZ		 4201 }
4202
4203 return 0;
4204}
4205
2cc0c0b5 4206int polaris10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
92c6d645 4207{
2cc0c0b5 4208 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
92c6d645
EH		 4209 uint32_t mm_boot_level_offset, mm_boot_level_value;
4210 struct phm_ppt_v1_information *table_info =
4211 (struct phm_ppt_v1_information *)(hwmgr->pptable);
4212
4213 if (!bgate) {
4214 data->smc_state_table.SamuBootLevel =
4215 (uint8_t) (table_info->mm_dep_table->count - 1);
4216 mm_boot_level_offset = data->dpm_table_start +
4217 offsetof(SMU74_Discrete_DpmTable, SamuBootLevel);
4218 mm_boot_level_offset /= 4;
4219 mm_boot_level_offset *= 4;
4220 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4221 CGS_IND_REG__SMC, mm_boot_level_offset);
4222 mm_boot_level_value &= 0xFFFFFF00;
4223 mm_boot_level_value |= data->smc_state_table.SamuBootLevel << 0;
4224 cgs_write_ind_register(hwmgr->device,
4225 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4226
4227 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4228 PHM_PlatformCaps_StablePState))
4229 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4230 PPSMC_MSG_SAMUDPM_SetEnabledMask,
4231 (uint32_t)(1 << data->smc_state_table.SamuBootLevel));
4232 }
4233
2cc0c0b5 4234 return polaris10_enable_disable_samu_dpm(hwmgr, !bgate);
92c6d645
EH		 4235}
4236
2cc0c0b5 4237static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
a23eefa2 4238{
2cc0c0b5 4239 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4240
4241 int result = 0;
4242 uint32_t low_sclk_interrupt_threshold = 0;
4243
4244 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4245 PHM_PlatformCaps_SclkThrottleLowNotification)
4246 && (hwmgr->gfx_arbiter.sclk_threshold !=
4247 data->low_sclk_interrupt_threshold)) {
4248 data->low_sclk_interrupt_threshold =
4249 hwmgr->gfx_arbiter.sclk_threshold;
4250 low_sclk_interrupt_threshold =
4251 data->low_sclk_interrupt_threshold;
4252
4253 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
4254
2cc0c0b5 4255 result = polaris10_copy_bytes_to_smc(
a23eefa2
RZ		 4256 hwmgr->smumgr,
4257 data->dpm_table_start +
4258 offsetof(SMU74_Discrete_DpmTable,
4259 LowSclkInterruptThreshold),
4260 (uint8_t *)&low_sclk_interrupt_threshold,
4261 sizeof(uint32_t),
4262 data->sram_end);
4263 }
4264
4265 return result;
4266}
4267
2cc0c0b5 4268static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
a23eefa2 4269{
2cc0c0b5 4270 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4271
4272 if (data->need_update_smu7_dpm_table &
4273 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
2cc0c0b5 4274 return polaris10_program_memory_timing_parameters(hwmgr);
a23eefa2
RZ		 4275
4276 return 0;
4277}
4278
2cc0c0b5 4279static int polaris10_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
a23eefa2 4280{
2cc0c0b5 4281 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4282
4283 if (0 == data->need_update_smu7_dpm_table)
4284 return 0;
4285
4286 if ((0 == data->sclk_dpm_key_disabled) &&
4287 (data->need_update_smu7_dpm_table &
4288 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4289
2cc0c0b5 4290 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
a23eefa2
RZ		 4291 "Trying to Unfreeze SCLK DPM when DPM is disabled",
4292 );
4293 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4294 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4295 "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
4296 return -1);
4297 }
4298
4299 if ((0 == data->mclk_dpm_key_disabled) &&
4300 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
4301
2cc0c0b5 4302 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
a23eefa2
RZ		 4303 "Trying to Unfreeze MCLK DPM when DPM is disabled",
4304 );
4305 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4306 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4307 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
4308 return -1);
4309 }
4310
4311 data->need_update_smu7_dpm_table = 0;
4312
4313 return 0;
4314}
4315
2cc0c0b5 4316static int polaris10_notify_link_speed_change_after_state_change(
a23eefa2
RZ		 4317 struct pp_hwmgr *hwmgr, const void *input)
4318{
4319 const struct phm_set_power_state_input *states =
4320 (const struct phm_set_power_state_input *)input;
2cc0c0b5
FC		 4321 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4322 const struct polaris10_power_state *polaris10_ps =
4323 cast_const_phw_polaris10_power_state(states->pnew_state);
4324 uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_ps);
a23eefa2
RZ		 4325 uint8_t request;
4326
4327 if (data->pspp_notify_required) {
4328 if (target_link_speed == PP_PCIEGen3)
4329 request = PCIE_PERF_REQ_GEN3;
4330 else if (target_link_speed == PP_PCIEGen2)
4331 request = PCIE_PERF_REQ_GEN2;
4332 else
4333 request = PCIE_PERF_REQ_GEN1;
4334
4335 if (request == PCIE_PERF_REQ_GEN1 &&
4336 phm_get_current_pcie_speed(hwmgr) > 0)
4337 return 0;
4338
4339 if (acpi_pcie_perf_request(hwmgr->device, request, false)) {
4340 if (PP_PCIEGen2 == target_link_speed)
4341 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
4342 else
4343 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
4344 }
4345 }
4346
4347 return 0;
4348}
4349
2cc0c0b5 4350static int polaris10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
a23eefa2
RZ		 4351{
4352 int tmp_result, result = 0;
2cc0c0b5 4353 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2 4354
2cc0c0b5 4355 tmp_result = polaris10_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
a23eefa2
RZ		 4356 PP_ASSERT_WITH_CODE((0 == tmp_result),
4357 "Failed to find DPM states clocks in DPM table!",
4358 result = tmp_result);
4359
4360 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4361 PHM_PlatformCaps_PCIEPerformanceRequest)) {
4362 tmp_result =
2cc0c0b5 4363 polaris10_request_link_speed_change_before_state_change(hwmgr, input);
a23eefa2
RZ		 4364 PP_ASSERT_WITH_CODE((0 == tmp_result),
4365 "Failed to request link speed change before state change!",
4366 result = tmp_result);
4367 }
4368
2cc0c0b5 4369 tmp_result = polaris10_freeze_sclk_mclk_dpm(hwmgr);
a23eefa2
RZ		 4370 PP_ASSERT_WITH_CODE((0 == tmp_result),
4371 "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
4372
2cc0c0b5 4373 tmp_result = polaris10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
a23eefa2
RZ		 4374 PP_ASSERT_WITH_CODE((0 == tmp_result),
4375 "Failed to populate and upload SCLK MCLK DPM levels!",
4376 result = tmp_result);
4377
2cc0c0b5 4378 tmp_result = polaris10_generate_dpm_level_enable_mask(hwmgr, input);
a23eefa2
RZ		 4379 PP_ASSERT_WITH_CODE((0 == tmp_result),
4380 "Failed to generate DPM level enabled mask!",
4381 result = tmp_result);
4382
2cc0c0b5 4383 tmp_result = polaris10_update_vce_dpm(hwmgr, input);
a23eefa2
RZ		 4384 PP_ASSERT_WITH_CODE((0 == tmp_result),
4385 "Failed to update VCE DPM!",
4386 result = tmp_result);
4387
2cc0c0b5 4388 tmp_result = polaris10_update_sclk_threshold(hwmgr);
a23eefa2
RZ		 4389 PP_ASSERT_WITH_CODE((0 == tmp_result),
4390 "Failed to update SCLK threshold!",
4391 result = tmp_result);
4392
2cc0c0b5 4393 tmp_result = polaris10_program_mem_timing_parameters(hwmgr);
a23eefa2
RZ		 4394 PP_ASSERT_WITH_CODE((0 == tmp_result),
4395 "Failed to program memory timing parameters!",
4396 result = tmp_result);
4397
2cc0c0b5 4398 tmp_result = polaris10_unfreeze_sclk_mclk_dpm(hwmgr);
a23eefa2
RZ		 4399 PP_ASSERT_WITH_CODE((0 == tmp_result),
4400 "Failed to unfreeze SCLK MCLK DPM!",
4401 result = tmp_result);
4402
2cc0c0b5 4403 tmp_result = polaris10_upload_dpm_level_enable_mask(hwmgr);
a23eefa2
RZ		 4404 PP_ASSERT_WITH_CODE((0 == tmp_result),
4405 "Failed to upload DPM level enabled mask!",
4406 result = tmp_result);
4407
4408 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4409 PHM_PlatformCaps_PCIEPerformanceRequest)) {
4410 tmp_result =
2cc0c0b5 4411 polaris10_notify_link_speed_change_after_state_change(hwmgr, input);
a23eefa2
RZ		 4412 PP_ASSERT_WITH_CODE((0 == tmp_result),
4413 "Failed to notify link speed change after state change!",
4414 result = tmp_result);
4415 }
4416 data->apply_optimized_settings = false;
4417 return result;
4418}
4419
2cc0c0b5 4420static int polaris10_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
a23eefa2 4421{
eede5262
EH		 4422 hwmgr->thermal_controller.
4423 advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
a23eefa2 4424
eede5262 4425 if (phm_is_hw_access_blocked(hwmgr))
a23eefa2 4426 return 0;
eede5262
EH		 4427
4428 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4429 PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
a23eefa2
RZ		 4430}
4431
2cc0c0b5 4432int polaris10_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
a23eefa2
RZ		 4433{
4434 PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
4435
4436 return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ? 0 : -1;
4437}
4438
2cc0c0b5 4439int polaris10_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 4440{
4441 uint32_t num_active_displays = 0;
4442 struct cgs_display_info info = {0};
4443 info.mode_info = NULL;
4444
4445 cgs_get_active_displays_info(hwmgr->device, &info);
4446
4447 num_active_displays = info.display_count;
4448
4449 if (num_active_displays > 1) /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */
2cc0c0b5 4450 polaris10_notify_smc_display_change(hwmgr, false);
a23eefa2 4451 else
2cc0c0b5 4452 polaris10_notify_smc_display_change(hwmgr, true);
a23eefa2
RZ		 4453
4454 return 0;
4455}
4456
4457/**
4458* Programs the display gap
4459*
4460* @param hwmgr the address of the powerplay hardware manager.
4461* @return always OK
4462*/
2cc0c0b5 4463int polaris10_program_display_gap(struct pp_hwmgr *hwmgr)
a23eefa2 4464{
2cc0c0b5 4465 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4466 uint32_t num_active_displays = 0;
4467 uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
4468 uint32_t display_gap2;
4469 uint32_t pre_vbi_time_in_us;
4470 uint32_t frame_time_in_us;
4471 uint32_t ref_clock;
4472 uint32_t refresh_rate = 0;
4473 struct cgs_display_info info = {0};
4474 struct cgs_mode_info mode_info;
4475
4476 info.mode_info = &mode_info;
4477
4478 cgs_get_active_displays_info(hwmgr->device, &info);
4479 num_active_displays = info.display_count;
4480
4481 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
4482 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
4483
4484 ref_clock = mode_info.ref_clock;
4485 refresh_rate = mode_info.refresh_rate;
4486
4487 if (0 == refresh_rate)
4488 refresh_rate = 60;
4489
4490 frame_time_in_us = 1000000 / refresh_rate;
4491
4492 pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
4493 display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
4494
4495 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
4496
4497 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, PreVBlankGap), 0x64);
4498
4499 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
4500
2cc0c0b5 4501 polaris10_notify_smc_display_change(hwmgr, num_active_displays != 0);
a23eefa2
RZ		 4502
4503 return 0;
4504}
4505
4506
2cc0c0b5 4507int polaris10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
a23eefa2 4508{
2cc0c0b5 4509 return polaris10_program_display_gap(hwmgr);
a23eefa2
RZ		 4510}
4511
4512/**
4513* Set maximum target operating fan output RPM
4514*
4515* @param hwmgr: the address of the powerplay hardware manager.
4516* @param usMaxFanRpm: max operating fan RPM value.
4517* @return The response that came from the SMC.
4518*/
2cc0c0b5 4519static int polaris10_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm)
a23eefa2 4520{
eede5262
EH		 4521 hwmgr->thermal_controller.
4522 advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
4523
4524 if (phm_is_hw_access_blocked(hwmgr))
4525 return 0;
4526
4527 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4528 PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
a23eefa2
RZ		 4529}
4530
2cc0c0b5 4531int polaris10_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 4532 const void *thermal_interrupt_info)
4533{
4534 return 0;
4535}
4536
2cc0c0b5 4537bool polaris10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
a23eefa2 4538{
2cc0c0b5 4539 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4540 bool is_update_required = false;
4541 struct cgs_display_info info = {0, 0, NULL};
4542
4543 cgs_get_active_displays_info(hwmgr->device, &info);
4544
4545 if (data->display_timing.num_existing_displays != info.display_count)
4546 is_update_required = true;
4547/* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
4548 if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
4549 cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
2cc0c0b5
FC		 4550 if (min_clocks.engineClockInSR != data->display_timing.minClockInSR &&
4551 (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
4552 data->display_timing.minClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK))
a23eefa2
RZ		 4553 is_update_required = true;
4554*/
4555 return is_update_required;
4556}
4557
2cc0c0b5
FC		 4558static inline bool polaris10_are_power_levels_equal(const struct polaris10_performance_level *pl1,
4559 const struct polaris10_performance_level *pl2)
a23eefa2
RZ		 4560{
4561 return ((pl1->memory_clock == pl2->memory_clock) &&
4562 (pl1->engine_clock == pl2->engine_clock) &&
4563 (pl1->pcie_gen == pl2->pcie_gen) &&
4564 (pl1->pcie_lane == pl2->pcie_lane));
4565}
4566
2cc0c0b5 4567int polaris10_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
a23eefa2 4568{
2cc0c0b5
FC		 4569 const struct polaris10_power_state *psa = cast_const_phw_polaris10_power_state(pstate1);
4570 const struct polaris10_power_state *psb = cast_const_phw_polaris10_power_state(pstate2);
a23eefa2
RZ		 4571 int i;
4572
4573 if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
4574 return -EINVAL;
4575
4576 /* If the two states don't even have the same number of performance levels they cannot be the same state. */
4577 if (psa->performance_level_count != psb->performance_level_count) {
4578 *equal = false;
4579 return 0;
4580 }
4581
4582 for (i = 0; i < psa->performance_level_count; i++) {
2cc0c0b5 4583 if (!polaris10_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
a23eefa2
RZ		 4584 /* If we have found even one performance level pair that is different the states are different. */
4585 *equal = false;
4586 return 0;
4587 }
4588 }
4589
4590 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
4591 *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
4592 *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
4593 *equal &= (psa->sclk_threshold == psb->sclk_threshold);
4594
4595 return 0;
4596}
4597
2cc0c0b5 4598int polaris10_upload_mc_firmware(struct pp_hwmgr *hwmgr)
a23eefa2 4599{
2cc0c0b5 4600 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4601
4602 uint32_t vbios_version;
4603
4604 /* Read MC indirect register offset 0x9F bits [3:0] to see if VBIOS has already loaded a full version of MC ucode or not.*/
4605
4606 phm_get_mc_microcode_version(hwmgr);
4607 vbios_version = hwmgr->microcode_version_info.MC & 0xf;
4608 /* Full version of MC ucode has already been loaded. */
4609 if (vbios_version == 0) {
4610 data->need_long_memory_training = false;
4611 return 0;
4612 }
4613
4614 data->need_long_memory_training = true;
4615
4616/*
4617 * PPMCME_FirmwareDescriptorEntry *pfd = NULL;
4618 pfd = &tonga_mcmeFirmware;
4619 if (0 == PHM_READ_FIELD(hwmgr->device, MC_SEQ_SUP_CNTL, RUN))
2cc0c0b5 4620 polaris10_load_mc_microcode(hwmgr, pfd->dpmThreshold,
a23eefa2
RZ		 4621 pfd->cfgArray, pfd->cfgSize, pfd->ioDebugArray,
4622 pfd->ioDebugSize, pfd->ucodeArray, pfd->ucodeSize);
4623*/
4624 return 0;
4625}
4626
4627/**
4628 * Read clock related registers.
4629 *
4630 * @param hwmgr the address of the powerplay hardware manager.
4631 * @return always 0
4632 */
2cc0c0b5 4633static int polaris10_read_clock_registers(struct pp_hwmgr *hwmgr)
a23eefa2 4634{
2cc0c0b5 4635 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4636
4637 data->clock_registers.vCG_SPLL_FUNC_CNTL = cgs_read_ind_register(hwmgr->device,
4638 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL)
4639 & CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK;
4640
4641 data->clock_registers.vCG_SPLL_FUNC_CNTL_2 = cgs_read_ind_register(hwmgr->device,
4642 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2)
4643 & CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
4644
4645 data->clock_registers.vCG_SPLL_FUNC_CNTL_4 = cgs_read_ind_register(hwmgr->device,
4646 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4)
4647 & CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK;
4648
4649 return 0;
4650}
4651
4652/**
4653 * Find out if memory is GDDR5.
4654 *
4655 * @param hwmgr the address of the powerplay hardware manager.
4656 * @return always 0
4657 */
2cc0c0b5 4658static int polaris10_get_memory_type(struct pp_hwmgr *hwmgr)
a23eefa2 4659{
2cc0c0b5 4660 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4661 uint32_t temp;
4662
4663 temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
4664
4665 data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
4666 ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
4667 MC_SEQ_MISC0_GDDR5_SHIFT));
4668
4669 return 0;
4670}
4671
4672/**
4673 * Enables Dynamic Power Management by SMC
4674 *
4675 * @param hwmgr the address of the powerplay hardware manager.
4676 * @return always 0
4677 */
2cc0c0b5 4678static int polaris10_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 4679{
4680 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4681 GENERAL_PWRMGT, STATIC_PM_EN, 1);
4682
4683 return 0;
4684}
4685
4686/**
4687 * Initialize PowerGating States for different engines
4688 *
4689 * @param hwmgr the address of the powerplay hardware manager.
4690 * @return always 0
4691 */
2cc0c0b5 4692static int polaris10_init_power_gate_state(struct pp_hwmgr *hwmgr)
a23eefa2 4693{
2cc0c0b5 4694 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4695
4696 data->uvd_power_gated = false;
4697 data->vce_power_gated = false;
4698 data->samu_power_gated = false;
4699
4700 return 0;
4701}
4702
2cc0c0b5 4703static int polaris10_init_sclk_threshold(struct pp_hwmgr *hwmgr)
a23eefa2 4704{
2cc0c0b5 4705 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4706 data->low_sclk_interrupt_threshold = 0;
4707
4708 return 0;
4709}
4710
2cc0c0b5 4711int polaris10_setup_asic_task(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 4712{
4713 int tmp_result, result = 0;
4714
2cc0c0b5 4715 polaris10_upload_mc_firmware(hwmgr);
a23eefa2 4716
2cc0c0b5 4717 tmp_result = polaris10_read_clock_registers(hwmgr);
a23eefa2
RZ		 4718 PP_ASSERT_WITH_CODE((0 == tmp_result),
4719 "Failed to read clock registers!", result = tmp_result);
4720
2cc0c0b5 4721 tmp_result = polaris10_get_memory_type(hwmgr);
a23eefa2
RZ		 4722 PP_ASSERT_WITH_CODE((0 == tmp_result),
4723 "Failed to get memory type!", result = tmp_result);
4724
2cc0c0b5 4725 tmp_result = polaris10_enable_acpi_power_management(hwmgr);
a23eefa2
RZ		 4726 PP_ASSERT_WITH_CODE((0 == tmp_result),
4727 "Failed to enable ACPI power management!", result = tmp_result);
4728
2cc0c0b5 4729 tmp_result = polaris10_init_power_gate_state(hwmgr);
a23eefa2
RZ		 4730 PP_ASSERT_WITH_CODE((0 == tmp_result),
4731 "Failed to init power gate state!", result = tmp_result);
4732
4733 tmp_result = phm_get_mc_microcode_version(hwmgr);
4734 PP_ASSERT_WITH_CODE((0 == tmp_result),
4735 "Failed to get MC microcode version!", result = tmp_result);
4736
2cc0c0b5 4737 tmp_result = polaris10_init_sclk_threshold(hwmgr);
a23eefa2
RZ		 4738 PP_ASSERT_WITH_CODE((0 == tmp_result),
4739 "Failed to init sclk threshold!", result = tmp_result);
4740
4741 return result;
4742}
4743
2cc0c0b5
FC		 4744static int polaris10_get_pp_table(struct pp_hwmgr *hwmgr, char **table)
4745{
4746 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4747
4748 *table = (char *)&data->smc_state_table;
4749
4750 return sizeof(struct SMU74_Discrete_DpmTable);
4751}
4752
4753static int polaris10_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t size)
4754{
4755 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4756
4757 void *table = (void *)&data->smc_state_table;
4758
4759 memcpy(table, buf, size);
4760
4761 return 0;
4762}
4763
4764static int polaris10_force_clock_level(struct pp_hwmgr *hwmgr,
4765 enum pp_clock_type type, int level)
4766{
4767 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4768
4769 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
4770 return -EINVAL;
4771
4772 switch (type) {
4773 case PP_SCLK:
4774 if (!data->sclk_dpm_key_disabled)
4775 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4776 PPSMC_MSG_SCLKDPM_SetEnabledMask,
4777 (1 << level));
4778 break;
4779 case PP_MCLK:
4780 if (!data->mclk_dpm_key_disabled)
4781 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4782 PPSMC_MSG_MCLKDPM_SetEnabledMask,
4783 (1 << level));
4784 break;
4785 case PP_PCIE:
4786 if (!data->pcie_dpm_key_disabled)
4787 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4788 PPSMC_MSG_PCIeDPM_ForceLevel,
4789 (1 << level));
4790 break;
4791 default:
4792 break;
4793 }
4794
4795 return 0;
4796}
4797
4798static uint16_t polaris10_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
4799{
4800 uint32_t speedCntl = 0;
4801
4802 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
4803 speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
4804 ixPCIE_LC_SPEED_CNTL);
4805 return((uint16_t)PHM_GET_FIELD(speedCntl,
4806 PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
4807}
4808
4809static int polaris10_print_clock_levels(struct pp_hwmgr *hwmgr,
4810 enum pp_clock_type type, char *buf)
4811{
4812 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4813 struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4814 struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4815 struct polaris10_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
4816 int i, now, size = 0;
4817 uint32_t clock, pcie_speed;
4818
4819 switch (type) {
4820 case PP_SCLK:
4821 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
4822 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4823
4824 for (i = 0; i < sclk_table->count; i++) {
4825 if (clock > sclk_table->dpm_levels[i].value)
4826 continue;
4827 break;
4828 }
4829 now = i;
4830
4831 for (i = 0; i < sclk_table->count; i++)
4832 size += sprintf(buf + size, "%d: %uMhz %s\n",
4833 i, sclk_table->dpm_levels[i].value / 100,
4834 (i == now) ? "*" : "");
4835 break;
4836 case PP_MCLK:
4837 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
4838 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4839
4840 for (i = 0; i < mclk_table->count; i++) {
4841 if (clock > mclk_table->dpm_levels[i].value)
4842 continue;
4843 break;
4844 }
4845 now = i;
4846
4847 for (i = 0; i < mclk_table->count; i++)
4848 size += sprintf(buf + size, "%d: %uMhz %s\n",
4849 i, mclk_table->dpm_levels[i].value / 100,
4850 (i == now) ? "*" : "");
4851 break;
4852 case PP_PCIE:
4853 pcie_speed = polaris10_get_current_pcie_speed(hwmgr);
4854 for (i = 0; i < pcie_table->count; i++) {
4855 if (pcie_speed != pcie_table->dpm_levels[i].value)
4856 continue;
4857 break;
4858 }
4859 now = i;
4860
4861 for (i = 0; i < pcie_table->count; i++)
4862 size += sprintf(buf + size, "%d: %s %s\n", i,
4863 (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" :
4864 (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
4865 (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
4866 (i == now) ? "*" : "");
4867 break;
4868 default:
4869 break;
4870 }
4871 return size;
4872}
4873
9e26bbb3
RZ		 4874static int polaris10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
4875{
4876 if (mode) {
4877 /* stop auto-manage */
4878 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4879 PHM_PlatformCaps_MicrocodeFanControl))
4880 polaris10_fan_ctrl_stop_smc_fan_control(hwmgr);
4881 polaris10_fan_ctrl_set_static_mode(hwmgr, mode);
4882 } else
4883 /* restart auto-manage */
4884 polaris10_fan_ctrl_reset_fan_speed_to_default(hwmgr);
4885
4886 return 0;
4887}
4888
4889static int polaris10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
4890{
4891 if (hwmgr->fan_ctrl_is_in_default_mode)
4892 return hwmgr->fan_ctrl_default_mode;
4893 else
4894 return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4895 CG_FDO_CTRL2, FDO_PWM_MODE);
4896}
4897
2cc0c0b5
FC		 4898static const struct pp_hwmgr_func polaris10_hwmgr_funcs = {
4899 .backend_init = &polaris10_hwmgr_backend_init,
4900 .backend_fini = &polaris10_hwmgr_backend_fini,
4901 .asic_setup = &polaris10_setup_asic_task,
4902 .dynamic_state_management_enable = &polaris10_enable_dpm_tasks,
4903 .apply_state_adjust_rules = polaris10_apply_state_adjust_rules,
4904 .force_dpm_level = &polaris10_force_dpm_level,
4905 .power_state_set = polaris10_set_power_state_tasks,
4906 .get_power_state_size = polaris10_get_power_state_size,
4907 .get_mclk = polaris10_dpm_get_mclk,
4908 .get_sclk = polaris10_dpm_get_sclk,
4909 .patch_boot_state = polaris10_dpm_patch_boot_state,
4910 .get_pp_table_entry = polaris10_get_pp_table_entry,
a23eefa2 4911 .get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries,
2cc0c0b5
FC		 4912 .print_current_perforce_level = polaris10_print_current_perforce_level,
4913 .powerdown_uvd = polaris10_phm_powerdown_uvd,
4914 .powergate_uvd = polaris10_phm_powergate_uvd,
4915 .powergate_vce = polaris10_phm_powergate_vce,
4916 .disable_clock_power_gating = polaris10_phm_disable_clock_power_gating,
4917 .update_clock_gatings = polaris10_phm_update_clock_gatings,
4918 .notify_smc_display_config_after_ps_adjustment = polaris10_notify_smc_display_config_after_ps_adjustment,
4919 .display_config_changed = polaris10_display_configuration_changed_task,
4920 .set_max_fan_pwm_output = polaris10_set_max_fan_pwm_output,
4921 .set_max_fan_rpm_output = polaris10_set_max_fan_rpm_output,
4922 .get_temperature = polaris10_thermal_get_temperature,
4923 .stop_thermal_controller = polaris10_thermal_stop_thermal_controller,
4924 .get_fan_speed_info = polaris10_fan_ctrl_get_fan_speed_info,
4925 .get_fan_speed_percent = polaris10_fan_ctrl_get_fan_speed_percent,
4926 .set_fan_speed_percent = polaris10_fan_ctrl_set_fan_speed_percent,
4927 .reset_fan_speed_to_default = polaris10_fan_ctrl_reset_fan_speed_to_default,
4928 .get_fan_speed_rpm = polaris10_fan_ctrl_get_fan_speed_rpm,
4929 .set_fan_speed_rpm = polaris10_fan_ctrl_set_fan_speed_rpm,
4930 .uninitialize_thermal_controller = polaris10_thermal_ctrl_uninitialize_thermal_controller,
4931 .register_internal_thermal_interrupt = polaris10_register_internal_thermal_interrupt,
4932 .check_smc_update_required_for_display_configuration = polaris10_check_smc_update_required_for_display_configuration,
4933 .check_states_equal = polaris10_check_states_equal,
9e26bbb3
RZ		 4934 .set_fan_control_mode = polaris10_set_fan_control_mode,
4935 .get_fan_control_mode = polaris10_get_fan_control_mode,
2cc0c0b5
FC		 4936 .get_pp_table = polaris10_get_pp_table,
4937 .set_pp_table = polaris10_set_pp_table,
4938 .force_clock_level = polaris10_force_clock_level,
4939 .print_clock_levels = polaris10_print_clock_levels,
4940 .enable_per_cu_power_gating = polaris10_phm_enable_per_cu_power_gating,
a23eefa2
RZ		 4941};
4942
2cc0c0b5 4943int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr)
a23eefa2 4944{
2cc0c0b5 4945 struct polaris10_hwmgr *data;
a23eefa2 4946
2cc0c0b5 4947 data = kzalloc (sizeof(struct polaris10_hwmgr), GFP_KERNEL);
a23eefa2
RZ		 4948 if (data == NULL)
4949 return -ENOMEM;
4950
4951 hwmgr->backend = data;
2cc0c0b5 4952 hwmgr->hwmgr_func = &polaris10_hwmgr_funcs;
a23eefa2 4953 hwmgr->pptable_func = &tonga_pptable_funcs;
2cc0c0b5 4954 pp_polaris10_thermal_initialize(hwmgr);
a23eefa2
RZ		 4955
4956 return 0;
4957}
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