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drm/amd/powerplay: enable PowerContainment feature for polaris10/11.
[mirror_ubuntu-eoan-kernel.git] / drivers / gpu / drm / amd / powerplay / hwmgr / polaris10_hwmgr.c
CommitLineData
a23eefa2
RZ		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/module.h>
24#include <linux/slab.h>
25#include <linux/fb.h>
ae17c999 26#include <asm/div64.h>
a23eefa2
RZ		 27#include "linux/delay.h"
28#include "pp_acpi.h"
29#include "hwmgr.h"
2cc0c0b5
FC		 30#include "polaris10_hwmgr.h"
31#include "polaris10_powertune.h"
32#include "polaris10_dyn_defaults.h"
33#include "polaris10_smumgr.h"
a23eefa2
RZ		 34#include "pp_debug.h"
35#include "ppatomctrl.h"
36#include "atombios.h"
37#include "tonga_pptable.h"
38#include "pppcielanes.h"
39#include "amd_pcie_helpers.h"
40#include "hardwaremanager.h"
41#include "tonga_processpptables.h"
42#include "cgs_common.h"
43#include "smu74.h"
44#include "smu_ucode_xfer_vi.h"
45#include "smu74_discrete.h"
46#include "smu/smu_7_1_3_d.h"
47#include "smu/smu_7_1_3_sh_mask.h"
48#include "gmc/gmc_8_1_d.h"
49#include "gmc/gmc_8_1_sh_mask.h"
50#include "oss/oss_3_0_d.h"
51#include "gca/gfx_8_0_d.h"
52#include "bif/bif_5_0_d.h"
53#include "bif/bif_5_0_sh_mask.h"
54#include "gmc/gmc_8_1_d.h"
55#include "gmc/gmc_8_1_sh_mask.h"
56#include "bif/bif_5_0_d.h"
57#include "bif/bif_5_0_sh_mask.h"
58#include "dce/dce_10_0_d.h"
59#include "dce/dce_10_0_sh_mask.h"
60
2cc0c0b5
FC		 61#include "polaris10_thermal.h"
62#include "polaris10_clockpowergating.h"
eede5262 63
a23eefa2
RZ		 64#define MC_CG_ARB_FREQ_F0 0x0a
65#define MC_CG_ARB_FREQ_F1 0x0b
66#define MC_CG_ARB_FREQ_F2 0x0c
67#define MC_CG_ARB_FREQ_F3 0x0d
68
69#define MC_CG_SEQ_DRAMCONF_S0 0x05
70#define MC_CG_SEQ_DRAMCONF_S1 0x06
71#define MC_CG_SEQ_YCLK_SUSPEND 0x04
72#define MC_CG_SEQ_YCLK_RESUME 0x0a
73
74
75#define SMC_RAM_END 0x40000
76
77#define SMC_CG_IND_START 0xc0030000
78#define SMC_CG_IND_END 0xc0040000
79
80#define VOLTAGE_SCALE 4
81#define VOLTAGE_VID_OFFSET_SCALE1 625
82#define VOLTAGE_VID_OFFSET_SCALE2 100
83
84#define VDDC_VDDCI_DELTA 200
85
86#define MEM_FREQ_LOW_LATENCY 25000
87#define MEM_FREQ_HIGH_LATENCY 80000
88
89#define MEM_LATENCY_HIGH 45
90#define MEM_LATENCY_LOW 35
91#define MEM_LATENCY_ERR 0xFFFF
92
93#define MC_SEQ_MISC0_GDDR5_SHIFT 28
94#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
95#define MC_SEQ_MISC0_GDDR5_VALUE 5
96
97
98#define PCIE_BUS_CLK 10000
99#define TCLK (PCIE_BUS_CLK / 10)
100
101
909a0631
NW		 102static const uint16_t polaris10_clock_stretcher_lookup_table[2][4] =
103{ {600, 1050, 3, 0}, {600, 1050, 6, 1} };
a23eefa2
RZ		 104
105/* [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */
909a0631
NW		 106static const uint32_t polaris10_clock_stretcher_ddt_table[2][4][4] =
107{ { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
108 { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
a23eefa2
RZ		 109
110/* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */
909a0631
NW		 111static const uint8_t polaris10_clock_stretch_amount_conversion[2][6] =
112{ {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} };
a23eefa2
RZ		 113
114/** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
115enum DPM_EVENT_SRC {
116 DPM_EVENT_SRC_ANALOG = 0,
117 DPM_EVENT_SRC_EXTERNAL = 1,
118 DPM_EVENT_SRC_DIGITAL = 2,
119 DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
120 DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
121};
122
909a0631 123static const unsigned long PhwPolaris10_Magic = (unsigned long)(PHM_VIslands_Magic);
a23eefa2 124
2cc0c0b5 125struct polaris10_power_state *cast_phw_polaris10_power_state(
a23eefa2
RZ		 126 struct pp_hw_power_state *hw_ps)
127{
2cc0c0b5 128 PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
a23eefa2
RZ		 129 "Invalid Powerstate Type!",
130 return NULL);
131
2cc0c0b5 132 return (struct polaris10_power_state *)hw_ps;
a23eefa2
RZ		 133}
134
2cc0c0b5 135const struct polaris10_power_state *cast_const_phw_polaris10_power_state(
a23eefa2
RZ		 136 const struct pp_hw_power_state *hw_ps)
137{
2cc0c0b5 138 PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
a23eefa2
RZ		 139 "Invalid Powerstate Type!",
140 return NULL);
141
2cc0c0b5 142 return (const struct polaris10_power_state *)hw_ps;
a23eefa2
RZ		 143}
144
2cc0c0b5 145static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 146{
147 return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
148 CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
149 ? true : false;
150}
151
152/**
153 * Find the MC microcode version and store it in the HwMgr struct
154 *
155 * @param hwmgr the address of the powerplay hardware manager.
156 * @return always 0
157 */
158int phm_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
159{
160 cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
161
162 hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
163
164 return 0;
165}
166
167uint16_t phm_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
168{
169 uint32_t speedCntl = 0;
170
171 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
172 speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
173 ixPCIE_LC_SPEED_CNTL);
174 return((uint16_t)PHM_GET_FIELD(speedCntl,
175 PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
176}
177
178int phm_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
179{
180 uint32_t link_width;
181
182 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
183 link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
184 PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
185
186 PP_ASSERT_WITH_CODE((7 >= link_width),
187 "Invalid PCIe lane width!", return 0);
188
189 return decode_pcie_lane_width(link_width);
190}
191
e85c7d66 192/**
193* Enable voltage control
194*
195* @param pHwMgr the address of the powerplay hardware manager.
196* @return always PP_Result_OK
197*/
2cc0c0b5 198int polaris10_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
e85c7d66 199{
200 PP_ASSERT_WITH_CODE(
201 (hwmgr->smumgr->smumgr_funcs->send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable) == 0),
202 "Failed to enable voltage DPM during DPM Start Function!",
203 return 1;
204 );
205
206 return 0;
207}
a23eefa2
RZ		 208
209/**
210* Checks if we want to support voltage control
211*
212* @param hwmgr the address of the powerplay hardware manager.
213*/
2cc0c0b5 214static bool polaris10_voltage_control(const struct pp_hwmgr *hwmgr)
a23eefa2 215{
2cc0c0b5
FC		 216 const struct polaris10_hwmgr *data =
217 (const struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2 218
2cc0c0b5 219 return (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control);
a23eefa2
RZ		 220}
221
222/**
223* Enable voltage control
224*
225* @param hwmgr the address of the powerplay hardware manager.
226* @return always 0
227*/
2cc0c0b5 228static int polaris10_enable_voltage_control(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 229{
230 /* enable voltage control */
231 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
232 GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
233
234 return 0;
235}
236
237/**
238* Create Voltage Tables.
239*
240* @param hwmgr the address of the powerplay hardware manager.
241* @return always 0
242*/
2cc0c0b5 243static int polaris10_construct_voltage_tables(struct pp_hwmgr *hwmgr)
a23eefa2 244{
2cc0c0b5 245 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 246 struct phm_ppt_v1_information *table_info =
247 (struct phm_ppt_v1_information *)hwmgr->pptable;
248 int result;
249
2cc0c0b5 250 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
a23eefa2
RZ		 251 result = atomctrl_get_voltage_table_v3(hwmgr,
252 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT,
253 &(data->mvdd_voltage_table));
254 PP_ASSERT_WITH_CODE((0 == result),
255 "Failed to retrieve MVDD table.",
256 return result);
2cc0c0b5 257 } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
a23eefa2
RZ		 258 result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table),
259 table_info->vdd_dep_on_mclk);
260 PP_ASSERT_WITH_CODE((0 == result),
261 "Failed to retrieve SVI2 MVDD table from dependancy table.",
262 return result;);
263 }
264
2cc0c0b5 265 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
a23eefa2
RZ		 266 result = atomctrl_get_voltage_table_v3(hwmgr,
267 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
268 &(data->vddci_voltage_table));
269 PP_ASSERT_WITH_CODE((0 == result),
270 "Failed to retrieve VDDCI table.",
271 return result);
2cc0c0b5 272 } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
a23eefa2
RZ		 273 result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table),
274 table_info->vdd_dep_on_mclk);
275 PP_ASSERT_WITH_CODE((0 == result),
276 "Failed to retrieve SVI2 VDDCI table from dependancy table.",
277 return result);
278 }
279
2cc0c0b5 280 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
a23eefa2
RZ		 281 result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table),
282 table_info->vddc_lookup_table);
283 PP_ASSERT_WITH_CODE((0 == result),
284 "Failed to retrieve SVI2 VDDC table from lookup table.",
285 return result);
286 }
287
288 PP_ASSERT_WITH_CODE(
289 (data->vddc_voltage_table.count <= (SMU74_MAX_LEVELS_VDDC)),
290 "Too many voltage values for VDDC. Trimming to fit state table.",
291 phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDC,
292 &(data->vddc_voltage_table)));
293
294 PP_ASSERT_WITH_CODE(
295 (data->vddci_voltage_table.count <= (SMU74_MAX_LEVELS_VDDCI)),
296 "Too many voltage values for VDDCI. Trimming to fit state table.",
297 phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDCI,
298 &(data->vddci_voltage_table)));
299
300 PP_ASSERT_WITH_CODE(
301 (data->mvdd_voltage_table.count <= (SMU74_MAX_LEVELS_MVDD)),
302 "Too many voltage values for MVDD. Trimming to fit state table.",
303 phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_MVDD,
304 &(data->mvdd_voltage_table)));
305
306 return 0;
307}
308
309/**
310* Programs static screed detection parameters
311*
312* @param hwmgr the address of the powerplay hardware manager.
313* @return always 0
314*/
2cc0c0b5 315static int polaris10_program_static_screen_threshold_parameters(
a23eefa2
RZ		 316 struct pp_hwmgr *hwmgr)
317{
2cc0c0b5 318 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 319
320 /* Set static screen threshold unit */
321 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
322 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
323 data->static_screen_threshold_unit);
324 /* Set static screen threshold */
325 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
326 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
327 data->static_screen_threshold);
328
329 return 0;
330}
331
332/**
333* Setup display gap for glitch free memory clock switching.
334*
335* @param hwmgr the address of the powerplay hardware manager.
336* @return always 0
337*/
2cc0c0b5 338static int polaris10_enable_display_gap(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 339{
340 uint32_t display_gap =
341 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
342 ixCG_DISPLAY_GAP_CNTL);
343
344 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
345 DISP_GAP, DISPLAY_GAP_IGNORE);
346
347 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
348 DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
349
350 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
351 ixCG_DISPLAY_GAP_CNTL, display_gap);
352
353 return 0;
354}
355
356/**
357* Programs activity state transition voting clients
358*
359* @param hwmgr the address of the powerplay hardware manager.
360* @return always 0
361*/
2cc0c0b5 362static int polaris10_program_voting_clients(struct pp_hwmgr *hwmgr)
a23eefa2 363{
2cc0c0b5 364 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 365
366 /* Clear reset for voting clients before enabling DPM */
367 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
368 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
369 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
370 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
371
372 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
373 ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
374 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
375 ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
376 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
377 ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
378 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
379 ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
380 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
381 ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
382 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
383 ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
384 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
385 ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
386 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
387 ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
388
389 return 0;
390}
391
392/**
393* Get the location of various tables inside the FW image.
394*
395* @param hwmgr the address of the powerplay hardware manager.
396* @return always 0
397*/
2cc0c0b5 398static int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
a23eefa2 399{
2cc0c0b5
FC		 400 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
401 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
a23eefa2
RZ		 402 uint32_t tmp;
403 int result;
404 bool error = false;
405
2cc0c0b5 406 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
a23eefa2
RZ		 407 SMU7_FIRMWARE_HEADER_LOCATION +
408 offsetof(SMU74_Firmware_Header, DpmTable),
409 &tmp, data->sram_end);
410
411 if (0 == result)
412 data->dpm_table_start = tmp;
413
414 error |= (0 != result);
415
2cc0c0b5 416 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
a23eefa2
RZ		 417 SMU7_FIRMWARE_HEADER_LOCATION +
418 offsetof(SMU74_Firmware_Header, SoftRegisters),
419 &tmp, data->sram_end);
420
421 if (!result) {
422 data->soft_regs_start = tmp;
423 smu_data->soft_regs_start = tmp;
424 }
425
426 error |= (0 != result);
427
2cc0c0b5 428 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
a23eefa2
RZ		 429 SMU7_FIRMWARE_HEADER_LOCATION +
430 offsetof(SMU74_Firmware_Header, mcRegisterTable),
431 &tmp, data->sram_end);
432
433 if (!result)
434 data->mc_reg_table_start = tmp;
435
2cc0c0b5 436 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
a23eefa2
RZ		 437 SMU7_FIRMWARE_HEADER_LOCATION +
438 offsetof(SMU74_Firmware_Header, FanTable),
439 &tmp, data->sram_end);
440
441 if (!result)
442 data->fan_table_start = tmp;
443
444 error |= (0 != result);
445
2cc0c0b5 446 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
a23eefa2
RZ		 447 SMU7_FIRMWARE_HEADER_LOCATION +
448 offsetof(SMU74_Firmware_Header, mcArbDramTimingTable),
449 &tmp, data->sram_end);
450
451 if (!result)
452 data->arb_table_start = tmp;
453
454 error |= (0 != result);
455
2cc0c0b5 456 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
a23eefa2
RZ		 457 SMU7_FIRMWARE_HEADER_LOCATION +
458 offsetof(SMU74_Firmware_Header, Version),
459 &tmp, data->sram_end);
460
461 if (!result)
462 hwmgr->microcode_version_info.SMC = tmp;
463
464 error |= (0 != result);
465
466 return error ? -1 : 0;
467}
468
469/* Copy one arb setting to another and then switch the active set.
470 * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
471 */
2cc0c0b5 472static int polaris10_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 473 uint32_t arb_src, uint32_t arb_dest)
474{
475 uint32_t mc_arb_dram_timing;
476 uint32_t mc_arb_dram_timing2;
477 uint32_t burst_time;
478 uint32_t mc_cg_config;
479
480 switch (arb_src) {
481 case MC_CG_ARB_FREQ_F0:
482 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
483 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
484 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
485 break;
486 case MC_CG_ARB_FREQ_F1:
487 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
488 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
489 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
490 break;
491 default:
492 return -EINVAL;
493 }
494
495 switch (arb_dest) {
496 case MC_CG_ARB_FREQ_F0:
497 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
498 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
499 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
500 break;
501 case MC_CG_ARB_FREQ_F1:
502 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
503 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
504 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
505 break;
506 default:
507 return -EINVAL;
508 }
509
510 mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
511 mc_cg_config |= 0x0000000F;
512 cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
513 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
514
515 return 0;
516}
517
518/**
519* Initial switch from ARB F0->F1
520*
521* @param hwmgr the address of the powerplay hardware manager.
522* @return always 0
523* This function is to be called from the SetPowerState table.
524*/
2cc0c0b5 525static int polaris10_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
a23eefa2 526{
2cc0c0b5 527 return polaris10_copy_and_switch_arb_sets(hwmgr,
a23eefa2
RZ		 528 MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
529}
530
2cc0c0b5 531static int polaris10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
a23eefa2 532{
2cc0c0b5 533 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 534 struct phm_ppt_v1_information *table_info =
535 (struct phm_ppt_v1_information *)(hwmgr->pptable);
536 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
537 uint32_t i, max_entry;
538
539 PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
540 data->use_pcie_power_saving_levels), "No pcie performance levels!",
541 return -EINVAL);
542
543 if (data->use_pcie_performance_levels &&
544 !data->use_pcie_power_saving_levels) {
545 data->pcie_gen_power_saving = data->pcie_gen_performance;
546 data->pcie_lane_power_saving = data->pcie_lane_performance;
547 } else if (!data->use_pcie_performance_levels &&
548 data->use_pcie_power_saving_levels) {
549 data->pcie_gen_performance = data->pcie_gen_power_saving;
550 data->pcie_lane_performance = data->pcie_lane_power_saving;
551 }
552
553 phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
554 SMU74_MAX_LEVELS_LINK,
555 MAX_REGULAR_DPM_NUMBER);
556
557 if (pcie_table != NULL) {
558 /* max_entry is used to make sure we reserve one PCIE level
559 * for boot level (fix for A+A PSPP issue).
560 * If PCIE table from PPTable have ULV entry + 8 entries,
561 * then ignore the last entry.*/
562 max_entry = (SMU74_MAX_LEVELS_LINK < pcie_table->count) ?
563 SMU74_MAX_LEVELS_LINK : pcie_table->count;
564 for (i = 1; i < max_entry; i++) {
565 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
566 get_pcie_gen_support(data->pcie_gen_cap,
567 pcie_table->entries[i].gen_speed),
568 get_pcie_lane_support(data->pcie_lane_cap,
569 pcie_table->entries[i].lane_width));
570 }
571 data->dpm_table.pcie_speed_table.count = max_entry - 1;
e85c7d66 572
573 /* Setup BIF_SCLK levels */
574 for (i = 0; i < max_entry; i++)
575 data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
a23eefa2
RZ		 576 } else {
577 /* Hardcode Pcie Table */
578 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
579 get_pcie_gen_support(data->pcie_gen_cap,
580 PP_Min_PCIEGen),
581 get_pcie_lane_support(data->pcie_lane_cap,
582 PP_Max_PCIELane));
583 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
584 get_pcie_gen_support(data->pcie_gen_cap,
585 PP_Min_PCIEGen),
586 get_pcie_lane_support(data->pcie_lane_cap,
587 PP_Max_PCIELane));
588 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
589 get_pcie_gen_support(data->pcie_gen_cap,
590 PP_Max_PCIEGen),
591 get_pcie_lane_support(data->pcie_lane_cap,
592 PP_Max_PCIELane));
593 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
594 get_pcie_gen_support(data->pcie_gen_cap,
595 PP_Max_PCIEGen),
596 get_pcie_lane_support(data->pcie_lane_cap,
597 PP_Max_PCIELane));
598 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
599 get_pcie_gen_support(data->pcie_gen_cap,
600 PP_Max_PCIEGen),
601 get_pcie_lane_support(data->pcie_lane_cap,
602 PP_Max_PCIELane));
603 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
604 get_pcie_gen_support(data->pcie_gen_cap,
605 PP_Max_PCIEGen),
606 get_pcie_lane_support(data->pcie_lane_cap,
607 PP_Max_PCIELane));
608
609 data->dpm_table.pcie_speed_table.count = 6;
610 }
611 /* Populate last level for boot PCIE level, but do not increment count. */
612 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
613 data->dpm_table.pcie_speed_table.count,
614 get_pcie_gen_support(data->pcie_gen_cap,
615 PP_Min_PCIEGen),
616 get_pcie_lane_support(data->pcie_lane_cap,
617 PP_Max_PCIELane));
618
619 return 0;
620}
621
622/*
623 * This function is to initalize all DPM state tables
624 * for SMU7 based on the dependency table.
625 * Dynamic state patching function will then trim these
626 * state tables to the allowed range based
627 * on the power policy or external client requests,
628 * such as UVD request, etc.
629 */
2cc0c0b5 630int polaris10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
a23eefa2 631{
2cc0c0b5 632 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 633 struct phm_ppt_v1_information *table_info =
634 (struct phm_ppt_v1_information *)(hwmgr->pptable);
635 uint32_t i;
636
637 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
638 table_info->vdd_dep_on_sclk;
639 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
640 table_info->vdd_dep_on_mclk;
641
642 PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
643 "SCLK dependency table is missing. This table is mandatory",
644 return -EINVAL);
645 PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
646 "SCLK dependency table has to have is missing."
647 "This table is mandatory",
648 return -EINVAL);
649
650 PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
651 "MCLK dependency table is missing. This table is mandatory",
652 return -EINVAL);
653 PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
654 "MCLK dependency table has to have is missing."
655 "This table is mandatory",
656 return -EINVAL);
657
658 /* clear the state table to reset everything to default */
659 phm_reset_single_dpm_table(
660 &data->dpm_table.sclk_table, SMU74_MAX_LEVELS_GRAPHICS, MAX_REGULAR_DPM_NUMBER);
661 phm_reset_single_dpm_table(
662 &data->dpm_table.mclk_table, SMU74_MAX_LEVELS_MEMORY, MAX_REGULAR_DPM_NUMBER);
663
664
665 /* Initialize Sclk DPM table based on allow Sclk values */
666 data->dpm_table.sclk_table.count = 0;
667 for (i = 0; i < dep_sclk_table->count; i++) {
668 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value !=
669 dep_sclk_table->entries[i].clk) {
670
671 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
672 dep_sclk_table->entries[i].clk;
673
674 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled =
675 (i == 0) ? true : false;
676 data->dpm_table.sclk_table.count++;
677 }
678 }
679
680 /* Initialize Mclk DPM table based on allow Mclk values */
681 data->dpm_table.mclk_table.count = 0;
682 for (i = 0; i < dep_mclk_table->count; i++) {
683 if (i == 0 || data->dpm_table.mclk_table.dpm_levels
684 [data->dpm_table.mclk_table.count - 1].value !=
685 dep_mclk_table->entries[i].clk) {
686 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
687 dep_mclk_table->entries[i].clk;
688 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled =
689 (i == 0) ? true : false;
690 data->dpm_table.mclk_table.count++;
691 }
692 }
693
694 /* setup PCIE gen speed levels */
2cc0c0b5 695 polaris10_setup_default_pcie_table(hwmgr);
a23eefa2
RZ		 696
697 /* save a copy of the default DPM table */
698 memcpy(&(data->golden_dpm_table), &(data->dpm_table),
2cc0c0b5 699 sizeof(struct polaris10_dpm_table));
a23eefa2
RZ		 700
701 return 0;
702}
703
704uint8_t convert_to_vid(uint16_t vddc)
705{
706 return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
707}
708
709/**
710 * Mvdd table preparation for SMC.
711 *
712 * @param *hwmgr The address of the hardware manager.
713 * @param *table The SMC DPM table structure to be populated.
714 * @return 0
715 */
2cc0c0b5 716static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 717 SMU74_Discrete_DpmTable *table)
718{
2cc0c0b5 719 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 720 uint32_t count, level;
721
2cc0c0b5 722 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
a23eefa2
RZ		 723 count = data->mvdd_voltage_table.count;
724 if (count > SMU_MAX_SMIO_LEVELS)
725 count = SMU_MAX_SMIO_LEVELS;
726 for (level = 0; level < count; level++) {
727 table->SmioTable2.Pattern[level].Voltage =
728 PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
729 /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
730 table->SmioTable2.Pattern[level].Smio =
731 (uint8_t) level;
732 table->Smio[level] |=
733 data->mvdd_voltage_table.entries[level].smio_low;
734 }
735 table->SmioMask2 = data->vddci_voltage_table.mask_low;
736
737 table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
738 }
739
740 return 0;
741}
742
2cc0c0b5 743static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 744 struct SMU74_Discrete_DpmTable *table)
745{
746 uint32_t count, level;
2cc0c0b5 747 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 748
749 count = data->vddci_voltage_table.count;
750
2cc0c0b5 751 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
a23eefa2
RZ		 752 if (count > SMU_MAX_SMIO_LEVELS)
753 count = SMU_MAX_SMIO_LEVELS;
754 for (level = 0; level < count; ++level) {
755 table->SmioTable1.Pattern[level].Voltage =
756 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE);
757 table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
758
759 table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
760 }
761 }
762
763 table->SmioMask1 = data->vddci_voltage_table.mask_low;
764
765 return 0;
766}
767
768/**
769* Preparation of vddc and vddgfx CAC tables for SMC.
770*
771* @param hwmgr the address of the hardware manager
772* @param table the SMC DPM table structure to be populated
773* @return always 0
774*/
2cc0c0b5 775static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 776 struct SMU74_Discrete_DpmTable *table)
777{
778 uint32_t count;
779 uint8_t index;
2cc0c0b5 780 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 781 struct phm_ppt_v1_information *table_info =
782 (struct phm_ppt_v1_information *)(hwmgr->pptable);
783 struct phm_ppt_v1_voltage_lookup_table *lookup_table =
784 table_info->vddc_lookup_table;
785 /* tables is already swapped, so in order to use the value from it,
786 * we need to swap it back.
787 * We are populating vddc CAC data to BapmVddc table
788 * in split and merged mode
789 */
790 for (count = 0; count < lookup_table->count; count++) {
791 index = phm_get_voltage_index(lookup_table,
792 data->vddc_voltage_table.entries[count].value);
793 table->BapmVddcVidLoSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_low);
794 table->BapmVddcVidHiSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_mid);
795 table->BapmVddcVidHiSidd2[count] = convert_to_vid(lookup_table->entries[index].us_cac_high);
796 }
797
798 return 0;
799}
800
801/**
802* Preparation of voltage tables for SMC.
803*
804* @param hwmgr the address of the hardware manager
805* @param table the SMC DPM table structure to be populated
806* @return always 0
807*/
808
2cc0c0b5 809int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 810 struct SMU74_Discrete_DpmTable *table)
811{
2cc0c0b5
FC		 812 polaris10_populate_smc_vddci_table(hwmgr, table);
813 polaris10_populate_smc_mvdd_table(hwmgr, table);
814 polaris10_populate_cac_table(hwmgr, table);
a23eefa2
RZ		 815
816 return 0;
817}
818
2cc0c0b5 819static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 820 struct SMU74_Discrete_Ulv *state)
821{
2cc0c0b5 822 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 823 struct phm_ppt_v1_information *table_info =
824 (struct phm_ppt_v1_information *)(hwmgr->pptable);
825
826 state->CcPwrDynRm = 0;
827 state->CcPwrDynRm1 = 0;
828
829 state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
830 state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
831 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
832
833 state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
834
835 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
836 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
837 CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
838
839 return 0;
840}
841
2cc0c0b5 842static int polaris10_populate_ulv_state(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 843 struct SMU74_Discrete_DpmTable *table)
844{
2cc0c0b5 845 return polaris10_populate_ulv_level(hwmgr, &table->Ulv);
a23eefa2
RZ		 846}
847
2cc0c0b5 848static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 849 struct SMU74_Discrete_DpmTable *table)
850{
2cc0c0b5
FC		 851 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
852 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
a23eefa2
RZ		 853 int i;
854
855 /* Index (dpm_table->pcie_speed_table.count)
856 * is reserved for PCIE boot level. */
857 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
858 table->LinkLevel[i].PcieGenSpeed =
859 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
860 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
861 dpm_table->pcie_speed_table.dpm_levels[i].param1);
862 table->LinkLevel[i].EnabledForActivity = 1;
863 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
864 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
865 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
866 }
867
868 data->smc_state_table.LinkLevelCount =
869 (uint8_t)dpm_table->pcie_speed_table.count;
870 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
871 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
872
873 return 0;
874}
875
2cc0c0b5 876static uint32_t polaris10_get_xclk(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 877{
878 uint32_t reference_clock, tmp;
879 struct cgs_display_info info = {0};
880 struct cgs_mode_info mode_info;
881
882 info.mode_info = &mode_info;
883
884 tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK);
885
886 if (tmp)
887 return TCLK;
888
889 cgs_get_active_displays_info(hwmgr->device, &info);
890 reference_clock = mode_info.ref_clock;
891
892 tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE);
893
894 if (0 != tmp)
895 return reference_clock / 4;
896
897 return reference_clock;
898}
899
900/**
901* Calculates the SCLK dividers using the provided engine clock
902*
903* @param hwmgr the address of the hardware manager
904* @param clock the engine clock to use to populate the structure
905* @param sclk the SMC SCLK structure to be populated
906*/
2cc0c0b5 907static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 908 uint32_t clock, SMU_SclkSetting *sclk_setting)
909{
2cc0c0b5 910 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 911 const SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
912 struct pp_atomctrl_clock_dividers_ai dividers;
913
914 uint32_t ref_clock;
915 uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
916 uint8_t i;
917 int result;
918 uint64_t temp;
919
920 sclk_setting->SclkFrequency = clock;
921 /* get the engine clock dividers for this clock value */
922 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, &dividers);
923 if (result == 0) {
924 sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
925 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
926 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
927 sclk_setting->PllRange = dividers.ucSclkPllRange;
e85c7d66 928 sclk_setting->Sclk_slew_rate = 0x400;
929 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
930 sclk_setting->Pcc_down_slew_rate = 0xffff;
a23eefa2
RZ		 931 sclk_setting->SSc_En = dividers.ucSscEnable;
932 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
933 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
e85c7d66 934 sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
a23eefa2
RZ		 935 return result;
936 }
937
2cc0c0b5 938 ref_clock = polaris10_get_xclk(hwmgr);
a23eefa2
RZ		 939
940 for (i = 0; i < NUM_SCLK_RANGE; i++) {
941 if (clock > data->range_table[i].trans_lower_frequency
942 && clock <= data->range_table[i].trans_upper_frequency) {
943 sclk_setting->PllRange = i;
944 break;
945 }
946 }
947
948 sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
949 temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
950 temp <<= 0x10;
ae17c999
SG		 951 do_div(temp, ref_clock);
952 sclk_setting->Fcw_frac = temp & 0xffff;
a23eefa2
RZ		 953
954 pcc_target_percent = 10; /* Hardcode 10% for now. */
955 pcc_target_freq = clock - (clock * pcc_target_percent / 100);
956 sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
957
958 ss_target_percent = 2; /* Hardcode 2% for now. */
959 sclk_setting->SSc_En = 0;
960 if (ss_target_percent) {
961 sclk_setting->SSc_En = 1;
962 ss_target_freq = clock - (clock * ss_target_percent / 100);
963 sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
964 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
965 temp <<= 0x10;
ae17c999
SG		 966 do_div(temp, ref_clock);
967 sclk_setting->Fcw1_frac = temp & 0xffff;
a23eefa2
RZ		 968 }
969
970 return 0;
971}
972
2cc0c0b5 973static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 974 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
975 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
976{
977 uint32_t i;
978 uint16_t vddci;
2cc0c0b5 979 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 980
981 *voltage = *mvdd = 0;
982
983 /* clock - voltage dependency table is empty table */
984 if (dep_table->count == 0)
985 return -EINVAL;
986
987 for (i = 0; i < dep_table->count; i++) {
988 /* find first sclk bigger than request */
989 if (dep_table->entries[i].clk >= clock) {
990 *voltage |= (dep_table->entries[i].vddc *
991 VOLTAGE_SCALE) << VDDC_SHIFT;
2cc0c0b5 992 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
a23eefa2
RZ		 993 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
994 VOLTAGE_SCALE) << VDDCI_SHIFT;
995 else if (dep_table->entries[i].vddci)
996 *voltage |= (dep_table->entries[i].vddci *
997 VOLTAGE_SCALE) << VDDCI_SHIFT;
998 else {
999 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1000 (dep_table->entries[i].vddc -
1001 (uint16_t)data->vddc_vddci_delta));
3ff21127 1002 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
a23eefa2
RZ		 1003 }
1004
2cc0c0b5 1005 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
a23eefa2
RZ		 1006 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
1007 VOLTAGE_SCALE;
1008 else if (dep_table->entries[i].mvdd)
1009 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
1010 VOLTAGE_SCALE;
1011
1012 *voltage |= 1 << PHASES_SHIFT;
1013 return 0;
1014 }
1015 }
1016
1017 /* sclk is bigger than max sclk in the dependence table */
1018 *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1019
2cc0c0b5 1020 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
a23eefa2
RZ		 1021 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1022 VOLTAGE_SCALE) << VDDCI_SHIFT;
1023 else if (dep_table->entries[i-1].vddci) {
1024 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1025 (dep_table->entries[i].vddc -
1026 (uint16_t)data->vddc_vddci_delta));
1027 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1028 }
1029
2cc0c0b5 1030 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
a23eefa2
RZ		 1031 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
1032 else if (dep_table->entries[i].mvdd)
1033 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
1034
1035 return 0;
1036}
1037
909a0631
NW		 1038static const sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] =
1039{ {VCO_2_4, POSTDIV_DIV_BY_16, 75, 160, 112},
1040 {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
1041 {VCO_2_4, POSTDIV_DIV_BY_8, 75, 160, 112},
1042 {VCO_3_6, POSTDIV_DIV_BY_8, 112, 224, 160},
1043 {VCO_2_4, POSTDIV_DIV_BY_4, 75, 160, 112},
1044 {VCO_3_6, POSTDIV_DIV_BY_4, 112, 216, 160},
1045 {VCO_2_4, POSTDIV_DIV_BY_2, 75, 160, 108},
1046 {VCO_3_6, POSTDIV_DIV_BY_2, 112, 216, 160} };
a23eefa2 1047
2cc0c0b5 1048static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 1049{
1050 uint32_t i, ref_clk;
2cc0c0b5 1051 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1052 SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
1053 struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
1054
2cc0c0b5 1055 ref_clk = polaris10_get_xclk(hwmgr);
a23eefa2
RZ		 1056
1057 if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
1058 for (i = 0; i < NUM_SCLK_RANGE; i++) {
1059 table->SclkFcwRangeTable[i].vco_setting = range_table_from_vbios.entry[i].ucVco_setting;
1060 table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv;
1061 table->SclkFcwRangeTable[i].fcw_pcc = range_table_from_vbios.entry[i].usFcw_pcc;
1062
1063 table->SclkFcwRangeTable[i].fcw_trans_upper = range_table_from_vbios.entry[i].usFcw_trans_upper;
1064 table->SclkFcwRangeTable[i].fcw_trans_lower = range_table_from_vbios.entry[i].usRcw_trans_lower;
1065
1066 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1067 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1068 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1069 }
1070 return;
1071 }
1072
1073 for (i = 0; i < NUM_SCLK_RANGE; i++) {
1074
1075 data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
1076 data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
1077
1078 table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
1079 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
1080 table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
1081
1082 table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
1083 table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
1084
1085 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1086 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1087 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1088 }
1089}
1090
1091/**
1092* Populates single SMC SCLK structure using the provided engine clock
1093*
1094* @param hwmgr the address of the hardware manager
1095* @param clock the engine clock to use to populate the structure
1096* @param sclk the SMC SCLK structure to be populated
1097*/
1098
2cc0c0b5 1099static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1100 uint32_t clock, uint16_t sclk_al_threshold,
1101 struct SMU74_Discrete_GraphicsLevel *level)
1102{
1103 int result, i, temp;
1104 /* PP_Clocks minClocks; */
1105 uint32_t mvdd;
2cc0c0b5 1106 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1107 struct phm_ppt_v1_information *table_info =
1108 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1109 SMU_SclkSetting curr_sclk_setting = { 0 };
1110
2cc0c0b5 1111 result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
a23eefa2
RZ		 1112
1113 /* populate graphics levels */
2cc0c0b5 1114 result = polaris10_get_dependency_volt_by_clk(hwmgr,
a23eefa2
RZ		 1115 table_info->vdd_dep_on_sclk, clock,
1116 &level->MinVoltage, &mvdd);
1117
1118 PP_ASSERT_WITH_CODE((0 == result),
1119 "can not find VDDC voltage value for "
1120 "VDDC engine clock dependency table",
1121 return result);
1122 level->ActivityLevel = sclk_al_threshold;
1123
1124 level->CcPwrDynRm = 0;
1125 level->CcPwrDynRm1 = 0;
1126 level->EnabledForActivity = 0;
1127 level->EnabledForThrottle = 1;
1128 level->UpHyst = 10;
1129 level->DownHyst = 0;
1130 level->VoltageDownHyst = 0;
1131 level->PowerThrottle = 0;
1132
1133 /*
1134 * TODO: get minimum clocks from dal configaration
1135 * PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks);
1136 */
1137 /* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */
1138
1139 /* get level->DeepSleepDivId
1140 if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
1141 level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR);
1142 */
859b8b6a 1143 PP_ASSERT_WITH_CODE((clock >= POLARIS10_MINIMUM_ENGINE_CLOCK), "Engine clock can't satisfy stutter requirement!", return 0);
2cc0c0b5 1144 for (i = POLARIS10_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
354ef928 1145 temp = clock >> i;
a23eefa2 1146
859b8b6a 1147 if (temp >= POLARIS10_MINIMUM_ENGINE_CLOCK || i == 0)
a23eefa2
RZ		 1148 break;
1149 }
1150
1151 level->DeepSleepDivId = i;
1152
1153 /* Default to slow, highest DPM level will be
1154 * set to PPSMC_DISPLAY_WATERMARK_LOW later.
1155 */
1156 if (data->update_up_hyst)
1157 level->UpHyst = (uint8_t)data->up_hyst;
1158 if (data->update_down_hyst)
1159 level->DownHyst = (uint8_t)data->down_hyst;
1160
1161 level->SclkSetting = curr_sclk_setting;
1162
1163 CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
1164 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
1165 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
1166 CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
1167 CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
1168 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
1169 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
1170 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
e85c7d66 1171 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
1172 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
1173 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
a23eefa2
RZ		 1174 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
1175 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
e85c7d66 1176 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
a23eefa2
RZ		 1177 return 0;
1178}
1179
1180/**
1181* Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
1182*
1183* @param hwmgr the address of the hardware manager
1184*/
2cc0c0b5 1185static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
a23eefa2 1186{
2cc0c0b5
FC		 1187 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1188 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
a23eefa2
RZ		 1189 struct phm_ppt_v1_information *table_info =
1190 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1191 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1192 uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
1193 int result = 0;
1194 uint32_t array = data->dpm_table_start +
1195 offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
1196 uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
1197 SMU74_MAX_LEVELS_GRAPHICS;
1198 struct SMU74_Discrete_GraphicsLevel *levels =
1199 data->smc_state_table.GraphicsLevel;
1200 uint32_t i, max_entry;
1201 uint8_t hightest_pcie_level_enabled = 0,
1202 lowest_pcie_level_enabled = 0,
1203 mid_pcie_level_enabled = 0,
1204 count = 0;
1205
2cc0c0b5 1206 polaris10_get_sclk_range_table(hwmgr);
a23eefa2
RZ		 1207
1208 for (i = 0; i < dpm_table->sclk_table.count; i++) {
1209
2cc0c0b5 1210 result = polaris10_populate_single_graphic_level(hwmgr,
a23eefa2
RZ		 1211 dpm_table->sclk_table.dpm_levels[i].value,
1212 (uint16_t)data->activity_target[i],
1213 &(data->smc_state_table.GraphicsLevel[i]));
1214 if (result)
1215 return result;
1216
1217 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
1218 if (i > 1)
1219 levels[i].DeepSleepDivId = 0;
1220 }
5de95e55
RZ		 1221 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1222 PHM_PlatformCaps_SPLLShutdownSupport))
1223 data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
a23eefa2
RZ		 1224
1225 data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
1226 data->smc_state_table.GraphicsDpmLevelCount =
1227 (uint8_t)dpm_table->sclk_table.count;
1228 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1229 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1230
1231
1232 if (pcie_table != NULL) {
1233 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
1234 "There must be 1 or more PCIE levels defined in PPTable.",
1235 return -EINVAL);
1236 max_entry = pcie_entry_cnt - 1;
1237 for (i = 0; i < dpm_table->sclk_table.count; i++)
1238 levels[i].pcieDpmLevel =
1239 (uint8_t) ((i < max_entry) ? i : max_entry);
1240 } else {
1241 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1242 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1243 (1 << (hightest_pcie_level_enabled + 1))) != 0))
1244 hightest_pcie_level_enabled++;
1245
1246 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1247 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1248 (1 << lowest_pcie_level_enabled)) == 0))
1249 lowest_pcie_level_enabled++;
1250
1251 while ((count < hightest_pcie_level_enabled) &&
1252 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1253 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
1254 count++;
1255
1256 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
1257 hightest_pcie_level_enabled ?
1258 (lowest_pcie_level_enabled + 1 + count) :
1259 hightest_pcie_level_enabled;
1260
1261 /* set pcieDpmLevel to hightest_pcie_level_enabled */
1262 for (i = 2; i < dpm_table->sclk_table.count; i++)
1263 levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
1264
1265 /* set pcieDpmLevel to lowest_pcie_level_enabled */
1266 levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
1267
1268 /* set pcieDpmLevel to mid_pcie_level_enabled */
1269 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
1270 }
1271 /* level count will send to smc once at init smc table and never change */
2cc0c0b5 1272 result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
a23eefa2
RZ		 1273 (uint32_t)array_size, data->sram_end);
1274
1275 return result;
1276}
1277
2cc0c0b5 1278static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1279 uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level)
1280{
2cc0c0b5 1281 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1282 struct phm_ppt_v1_information *table_info =
1283 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1284 int result = 0;
1285 struct cgs_display_info info = {0, 0, NULL};
1286
1287 cgs_get_active_displays_info(hwmgr->device, &info);
1288
1289 if (table_info->vdd_dep_on_mclk) {
2cc0c0b5 1290 result = polaris10_get_dependency_volt_by_clk(hwmgr,
a23eefa2
RZ		 1291 table_info->vdd_dep_on_mclk, clock,
1292 &mem_level->MinVoltage, &mem_level->MinMvdd);
1293 PP_ASSERT_WITH_CODE((0 == result),
1294 "can not find MinVddc voltage value from memory "
1295 "VDDC voltage dependency table", return result);
1296 }
1297
1298 mem_level->MclkFrequency = clock;
1299 mem_level->StutterEnable = 0;
1300 mem_level->EnabledForThrottle = 1;
1301 mem_level->EnabledForActivity = 0;
1302 mem_level->UpHyst = 0;
1303 mem_level->DownHyst = 100;
1304 mem_level->VoltageDownHyst = 0;
1305 mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
1306 mem_level->StutterEnable = false;
1307
1308 mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1309
1310 data->display_timing.num_existing_displays = info.display_count;
1311
1312 if ((data->mclk_stutter_mode_threshold) &&
1313 (clock <= data->mclk_stutter_mode_threshold) &&
1314 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
1315 STUTTER_ENABLE) & 0x1))
1316 mem_level->StutterEnable = true;
1317
1318 if (!result) {
1319 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
1320 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
1321 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
1322 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
1323 }
1324 return result;
1325}
1326
1327/**
1328* Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
1329*
1330* @param hwmgr the address of the hardware manager
1331*/
2cc0c0b5 1332static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
a23eefa2 1333{
2cc0c0b5
FC		 1334 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1335 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
a23eefa2
RZ		 1336 int result;
1337 /* populate MCLK dpm table to SMU7 */
1338 uint32_t array = data->dpm_table_start +
1339 offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
1340 uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) *
1341 SMU74_MAX_LEVELS_MEMORY;
1342 struct SMU74_Discrete_MemoryLevel *levels =
1343 data->smc_state_table.MemoryLevel;
1344 uint32_t i;
1345
1346 for (i = 0; i < dpm_table->mclk_table.count; i++) {
1347 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1348 "can not populate memory level as memory clock is zero",
1349 return -EINVAL);
2cc0c0b5 1350 result = polaris10_populate_single_memory_level(hwmgr,
a23eefa2
RZ		 1351 dpm_table->mclk_table.dpm_levels[i].value,
1352 &levels[i]);
b4c6f99e
RZ		 1353 if (i == dpm_table->mclk_table.count - 1) {
1354 levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1355 levels[i].EnabledForActivity = 1;
1356 }
a23eefa2
RZ		 1357 if (result)
1358 return result;
1359 }
1360
a23eefa2
RZ		 1361 /* in order to prevent MC activity from stutter mode to push DPM up.
1362 * the UVD change complements this by putting the MCLK in
1363 * a higher state by default such that we are not effected by
1364 * up threshold or and MCLK DPM latency.
1365 */
1366 levels[0].ActivityLevel = (uint16_t)data->mclk_dpm0_activity_target;
1367 CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
1368
1369 data->smc_state_table.MemoryDpmLevelCount =
1370 (uint8_t)dpm_table->mclk_table.count;
1371 data->dpm_level_enable_mask.mclk_dpm_enable_mask =
1372 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
a23eefa2
RZ		 1373
1374 /* level count will send to smc once at init smc table and never change */
2cc0c0b5 1375 result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
a23eefa2
RZ		 1376 (uint32_t)array_size, data->sram_end);
1377
1378 return result;
1379}
1380
1381/**
1382* Populates the SMC MVDD structure using the provided memory clock.
1383*
1384* @param hwmgr the address of the hardware manager
1385* @param mclk the MCLK value to be used in the decision if MVDD should be high or low.
1386* @param voltage the SMC VOLTAGE structure to be populated
1387*/
2cc0c0b5 1388int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1389 uint32_t mclk, SMIO_Pattern *smio_pat)
1390{
2cc0c0b5 1391 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1392 struct phm_ppt_v1_information *table_info =
1393 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1394 uint32_t i = 0;
1395
2cc0c0b5 1396 if (POLARIS10_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
a23eefa2
RZ		 1397 /* find mvdd value which clock is more than request */
1398 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
1399 if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
1400 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
1401 break;
1402 }
1403 }
1404 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
1405 "MVDD Voltage is outside the supported range.",
1406 return -EINVAL);
1407 } else
1408 return -EINVAL;
1409
1410 return 0;
1411}
1412
2cc0c0b5 1413static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1414 SMU74_Discrete_DpmTable *table)
1415{
1416 int result = 0;
1417 uint32_t sclk_frequency;
2cc0c0b5 1418 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1419 struct phm_ppt_v1_information *table_info =
1420 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1421 SMIO_Pattern vol_level;
1422 uint32_t mvdd;
1423 uint16_t us_mvdd;
1424
1425 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1426
1427 if (!data->sclk_dpm_key_disabled) {
1428 /* Get MinVoltage and Frequency from DPM0,
1429 * already converted to SMC_UL */
1430 sclk_frequency = data->dpm_table.sclk_table.dpm_levels[0].value;
2cc0c0b5 1431 result = polaris10_get_dependency_volt_by_clk(hwmgr,
a23eefa2
RZ		 1432 table_info->vdd_dep_on_sclk,
1433 table->ACPILevel.SclkFrequency,
1434 &table->ACPILevel.MinVoltage, &mvdd);
1435 PP_ASSERT_WITH_CODE((0 == result),
1436 "Cannot find ACPI VDDC voltage value "
1437 "in Clock Dependency Table", );
1438 } else {
1439 sclk_frequency = data->vbios_boot_state.sclk_bootup_value;
1440 table->ACPILevel.MinVoltage =
1441 data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE;
1442 }
1443
2cc0c0b5 1444 result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency, &(table->ACPILevel.SclkSetting));
a23eefa2
RZ		 1445 PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);
1446
1447 table->ACPILevel.DeepSleepDivId = 0;
1448 table->ACPILevel.CcPwrDynRm = 0;
1449 table->ACPILevel.CcPwrDynRm1 = 0;
1450
1451 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1452 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
1453 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1454 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1455
1456 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
1457 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
1458 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
1459 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
e85c7d66 1460 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
1461 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
1462 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
a23eefa2
RZ		 1463 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
1464 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
e85c7d66 1465 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
a23eefa2
RZ		 1466
1467 if (!data->mclk_dpm_key_disabled) {
1468 /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
1469 table->MemoryACPILevel.MclkFrequency =
1470 data->dpm_table.mclk_table.dpm_levels[0].value;
2cc0c0b5 1471 result = polaris10_get_dependency_volt_by_clk(hwmgr,
a23eefa2
RZ		 1472 table_info->vdd_dep_on_mclk,
1473 table->MemoryACPILevel.MclkFrequency,
1474 &table->MemoryACPILevel.MinVoltage, &mvdd);
1475 PP_ASSERT_WITH_CODE((0 == result),
1476 "Cannot find ACPI VDDCI voltage value "
1477 "in Clock Dependency Table",
1478 );
1479 } else {
1480 table->MemoryACPILevel.MclkFrequency =
1481 data->vbios_boot_state.mclk_bootup_value;
1482 table->MemoryACPILevel.MinVoltage =
1483 data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE;
1484 }
1485
1486 us_mvdd = 0;
2cc0c0b5 1487 if ((POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
a23eefa2
RZ		 1488 (data->mclk_dpm_key_disabled))
1489 us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
1490 else {
2cc0c0b5 1491 if (!polaris10_populate_mvdd_value(hwmgr,
a23eefa2
RZ		 1492 data->dpm_table.mclk_table.dpm_levels[0].value,
1493 &vol_level))
1494 us_mvdd = vol_level.Voltage;
1495 }
1496
2cc0c0b5 1497 if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level))
a23eefa2
RZ		 1498 table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
1499 else
1500 table->MemoryACPILevel.MinMvdd = 0;
1501
1502 table->MemoryACPILevel.StutterEnable = false;
1503
1504 table->MemoryACPILevel.EnabledForThrottle = 0;
1505 table->MemoryACPILevel.EnabledForActivity = 0;
1506 table->MemoryACPILevel.UpHyst = 0;
1507 table->MemoryACPILevel.DownHyst = 100;
1508 table->MemoryACPILevel.VoltageDownHyst = 0;
1509 table->MemoryACPILevel.ActivityLevel =
1510 PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
1511
1512 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
1513 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
1514
1515 return result;
1516}
1517
2cc0c0b5 1518static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1519 SMU74_Discrete_DpmTable *table)
1520{
1521 int result = -EINVAL;
1522 uint8_t count;
1523 struct pp_atomctrl_clock_dividers_vi dividers;
1524 struct phm_ppt_v1_information *table_info =
1525 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1526 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1527 table_info->mm_dep_table;
2cc0c0b5 1528 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1529
1530 table->VceLevelCount = (uint8_t)(mm_table->count);
1531 table->VceBootLevel = 0;
1532
1533 for (count = 0; count < table->VceLevelCount; count++) {
1534 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
681ed01c 1535 table->VceLevel[count].MinVoltage = 0;
a23eefa2
RZ		 1536 table->VceLevel[count].MinVoltage |=
1537 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1538 table->VceLevel[count].MinVoltage |=
1539 ((mm_table->entries[count].vddc - data->vddc_vddci_delta) *
1540 VOLTAGE_SCALE) << VDDCI_SHIFT;
1541 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1542
1543 /*retrieve divider value for VBIOS */
1544 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1545 table->VceLevel[count].Frequency, &dividers);
1546 PP_ASSERT_WITH_CODE((0 == result),
1547 "can not find divide id for VCE engine clock",
1548 return result);
1549
1550 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1551
1552 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1553 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
1554 }
1555 return result;
1556}
1557
2cc0c0b5 1558static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1559 SMU74_Discrete_DpmTable *table)
1560{
1561 int result = -EINVAL;
1562 uint8_t count;
1563 struct pp_atomctrl_clock_dividers_vi dividers;
1564 struct phm_ppt_v1_information *table_info =
1565 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1566 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1567 table_info->mm_dep_table;
2cc0c0b5 1568 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1569
1570 table->SamuBootLevel = 0;
1571 table->SamuLevelCount = (uint8_t)(mm_table->count);
1572
1573 for (count = 0; count < table->SamuLevelCount; count++) {
1574 /* not sure whether we need evclk or not */
681ed01c 1575 table->SamuLevel[count].MinVoltage = 0;
a23eefa2
RZ		 1576 table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
1577 table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1578 VOLTAGE_SCALE) << VDDC_SHIFT;
1579 table->SamuLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
1580 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
1581 table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1582
1583 /* retrieve divider value for VBIOS */
1584 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1585 table->SamuLevel[count].Frequency, &dividers);
1586 PP_ASSERT_WITH_CODE((0 == result),
1587 "can not find divide id for samu clock", return result);
1588
1589 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1590
1591 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
1592 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
1593 }
1594 return result;
1595}
1596
2cc0c0b5 1597static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1598 int32_t eng_clock, int32_t mem_clock,
1599 SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs)
1600{
1601 uint32_t dram_timing;
1602 uint32_t dram_timing2;
1603 uint32_t burst_time;
1604 int result;
1605
1606 result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1607 eng_clock, mem_clock);
1608 PP_ASSERT_WITH_CODE(result == 0,
1609 "Error calling VBIOS to set DRAM_TIMING.", return result);
1610
1611 dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1612 dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1613 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1614
1615
1616 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing);
1617 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
1618 arb_regs->McArbBurstTime = (uint8_t)burst_time;
1619
1620 return 0;
1621}
1622
2cc0c0b5 1623static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
a23eefa2 1624{
2cc0c0b5 1625 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1626 struct SMU74_Discrete_MCArbDramTimingTable arb_regs;
1627 uint32_t i, j;
1628 int result = 0;
1629
1630 for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1631 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
2cc0c0b5 1632 result = polaris10_populate_memory_timing_parameters(hwmgr,
a23eefa2
RZ		 1633 data->dpm_table.sclk_table.dpm_levels[i].value,
1634 data->dpm_table.mclk_table.dpm_levels[j].value,
1635 &arb_regs.entries[i][j]);
1636 if (result == 0)
1637 result = atomctrl_set_ac_timing_ai(hwmgr, data->dpm_table.mclk_table.dpm_levels[j].value, j);
1638 if (result != 0)
1639 return result;
1640 }
1641 }
1642
2cc0c0b5 1643 result = polaris10_copy_bytes_to_smc(
a23eefa2
RZ		 1644 hwmgr->smumgr,
1645 data->arb_table_start,
1646 (uint8_t *)&arb_regs,
1647 sizeof(SMU74_Discrete_MCArbDramTimingTable),
1648 data->sram_end);
1649 return result;
1650}
1651
2cc0c0b5 1652static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1653 struct SMU74_Discrete_DpmTable *table)
1654{
1655 int result = -EINVAL;
1656 uint8_t count;
1657 struct pp_atomctrl_clock_dividers_vi dividers;
1658 struct phm_ppt_v1_information *table_info =
1659 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1660 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1661 table_info->mm_dep_table;
2cc0c0b5 1662 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1663
1664 table->UvdLevelCount = (uint8_t)(mm_table->count);
1665 table->UvdBootLevel = 0;
1666
1667 for (count = 0; count < table->UvdLevelCount; count++) {
681ed01c 1668 table->UvdLevel[count].MinVoltage = 0;
a23eefa2
RZ		 1669 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1670 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1671 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1672 VOLTAGE_SCALE) << VDDC_SHIFT;
1673 table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
1674 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
1675 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1676
1677 /* retrieve divider value for VBIOS */
1678 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1679 table->UvdLevel[count].VclkFrequency, &dividers);
1680 PP_ASSERT_WITH_CODE((0 == result),
1681 "can not find divide id for Vclk clock", return result);
1682
1683 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1684
1685 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1686 table->UvdLevel[count].DclkFrequency, &dividers);
1687 PP_ASSERT_WITH_CODE((0 == result),
1688 "can not find divide id for Dclk clock", return result);
1689
1690 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1691
1692 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1693 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1694 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
1695
1696 }
1697 return result;
1698}
1699
2cc0c0b5 1700static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1701 struct SMU74_Discrete_DpmTable *table)
1702{
1703 int result = 0;
2cc0c0b5 1704 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1705
1706 table->GraphicsBootLevel = 0;
1707 table->MemoryBootLevel = 0;
1708
1709 /* find boot level from dpm table */
1710 result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1711 data->vbios_boot_state.sclk_bootup_value,
1712 (uint32_t *)&(table->GraphicsBootLevel));
1713
1714 result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1715 data->vbios_boot_state.mclk_bootup_value,
1716 (uint32_t *)&(table->MemoryBootLevel));
1717
1718 table->BootVddc = data->vbios_boot_state.vddc_bootup_value *
1719 VOLTAGE_SCALE;
1720 table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
1721 VOLTAGE_SCALE;
1722 table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value *
1723 VOLTAGE_SCALE;
1724
1725 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
1726 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
1727 CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
1728
1729 return 0;
1730}
1731
1732
2cc0c0b5 1733static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
a23eefa2 1734{
2cc0c0b5 1735 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1736 struct phm_ppt_v1_information *table_info =
1737 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1738 uint8_t count, level;
1739
1740 count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
1741
1742 for (level = 0; level < count; level++) {
1743 if (table_info->vdd_dep_on_sclk->entries[level].clk >=
1744 data->vbios_boot_state.sclk_bootup_value) {
1745 data->smc_state_table.GraphicsBootLevel = level;
1746 break;
1747 }
1748 }
1749
1750 count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
1751 for (level = 0; level < count; level++) {
1752 if (table_info->vdd_dep_on_mclk->entries[level].clk >=
1753 data->vbios_boot_state.mclk_bootup_value) {
1754 data->smc_state_table.MemoryBootLevel = level;
1755 break;
1756 }
1757 }
1758
1759 return 0;
1760}
1761
2cc0c0b5 1762static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 1763{
1764 uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks,
1765 volt_with_cks, value;
1766 uint16_t clock_freq_u16;
2cc0c0b5 1767 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1768 uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2,
1769 volt_offset = 0;
1770 struct phm_ppt_v1_information *table_info =
1771 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1772 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1773 table_info->vdd_dep_on_sclk;
1774
1775 stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
1776
1777 /* Read SMU_Eefuse to read and calculate RO and determine
1778 * if the part is SS or FF. if RO >= 1660MHz, part is FF.
1779 */
1780 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1781 ixSMU_EFUSE_0 + (146 * 4));
1782 efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1783 ixSMU_EFUSE_0 + (148 * 4));
1784 efuse &= 0xFF000000;
1785 efuse = efuse >> 24;
1786 efuse2 &= 0xF;
1787
1788 if (efuse2 == 1)
1789 ro = (2300 - 1350) * efuse / 255 + 1350;
1790 else
1791 ro = (2500 - 1000) * efuse / 255 + 1000;
1792
1793 if (ro >= 1660)
1794 type = 0;
1795 else
1796 type = 1;
1797
1798 /* Populate Stretch amount */
1799 data->smc_state_table.ClockStretcherAmount = stretch_amount;
1800
1801 /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
1802 for (i = 0; i < sclk_table->count; i++) {
1803 data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1804 sclk_table->entries[i].cks_enable << i;
1805 volt_without_cks = (uint32_t)((14041 *
1806 (sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 /
1807 (4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000)));
1808 volt_with_cks = (uint32_t)((13946 *
1809 (sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 /
1810 (3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000)));
1811 if (volt_without_cks >= volt_with_cks)
1812 volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
1813 sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
1814 data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1815 }
1816
1817 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1818 STRETCH_ENABLE, 0x0);
1819 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1820 masterReset, 0x1);
1821 /* PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE, staticEnable, 0x1); */
1822 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1823 masterReset, 0x0);
1824
1825 /* Populate CKS Lookup Table */
1826 if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
1827 stretch_amount2 = 0;
1828 else if (stretch_amount == 3 || stretch_amount == 4)
1829 stretch_amount2 = 1;
1830 else {
1831 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1832 PHM_PlatformCaps_ClockStretcher);
1833 PP_ASSERT_WITH_CODE(false,
1834 "Stretch Amount in PPTable not supported\n",
1835 return -EINVAL);
1836 }
1837
1838 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1839 ixPWR_CKS_CNTL);
1840 value &= 0xFFC2FF87;
1841 data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq =
2cc0c0b5 1842 polaris10_clock_stretcher_lookup_table[stretch_amount2][0];
a23eefa2 1843 data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq =
2cc0c0b5 1844 polaris10_clock_stretcher_lookup_table[stretch_amount2][1];
a23eefa2
RZ		 1845 clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(data->smc_state_table.
1846 GraphicsLevel[data->smc_state_table.GraphicsDpmLevelCount - 1].SclkSetting.SclkFrequency) / 100);
2cc0c0b5
FC		 1847 if (polaris10_clock_stretcher_lookup_table[stretch_amount2][0] < clock_freq_u16
1848 && polaris10_clock_stretcher_lookup_table[stretch_amount2][1] > clock_freq_u16) {
a23eefa2 1849 /* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */
2cc0c0b5 1850 value |= (polaris10_clock_stretcher_lookup_table[stretch_amount2][3]) << 16;
a23eefa2 1851 /* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */
2cc0c0b5 1852 value |= (polaris10_clock_stretcher_lookup_table[stretch_amount2][2]) << 18;
a23eefa2 1853 /* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */
2cc0c0b5
FC		 1854 value |= (polaris10_clock_stretch_amount_conversion
1855 [polaris10_clock_stretcher_lookup_table[stretch_amount2][3]]
a23eefa2
RZ		 1856 [stretch_amount]) << 3;
1857 }
1858 CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq);
1859 CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq);
1860 data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting =
2cc0c0b5 1861 polaris10_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F;
a23eefa2 1862 data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |=
2cc0c0b5 1863 (polaris10_clock_stretcher_lookup_table[stretch_amount2][3]) << 7;
a23eefa2
RZ		 1864
1865 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1866 ixPWR_CKS_CNTL, value);
1867
1868 /* Populate DDT Lookup Table */
1869 for (i = 0; i < 4; i++) {
1870 /* Assign the minimum and maximum VID stored
1871 * in the last row of Clock Stretcher Voltage Table.
1872 */
1873 data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].minVID =
2cc0c0b5 1874 (uint8_t) polaris10_clock_stretcher_ddt_table[type][i][2];
a23eefa2 1875 data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].maxVID =
2cc0c0b5 1876 (uint8_t) polaris10_clock_stretcher_ddt_table[type][i][3];
a23eefa2
RZ		 1877 /* Loop through each SCLK and check the frequency
1878 * to see if it lies within the frequency for clock stretcher.
1879 */
1880 for (j = 0; j < data->smc_state_table.GraphicsDpmLevelCount; j++) {
1881 cks_setting = 0;
1882 clock_freq = PP_SMC_TO_HOST_UL(
1883 data->smc_state_table.GraphicsLevel[j].SclkSetting.SclkFrequency);
1884 /* Check the allowed frequency against the sclk level[j].
1885 * Sclk's endianness has already been converted,
1886 * and it's in 10Khz unit,
1887 * as opposed to Data table, which is in Mhz unit.
1888 */
2cc0c0b5 1889 if (clock_freq >= (polaris10_clock_stretcher_ddt_table[type][i][0]) * 100) {
a23eefa2 1890 cks_setting |= 0x2;
2cc0c0b5 1891 if (clock_freq < (polaris10_clock_stretcher_ddt_table[type][i][1]) * 100)
a23eefa2
RZ		 1892 cks_setting |= 0x1;
1893 }
1894 data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].setting
1895 |= cks_setting << (j * 2);
1896 }
1897 CONVERT_FROM_HOST_TO_SMC_US(
1898 data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].setting);
1899 }
1900
1901 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
1902 value &= 0xFFFFFFFE;
1903 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
1904
1905 return 0;
1906}
1907
1908/**
1909* Populates the SMC VRConfig field in DPM table.
1910*
1911* @param hwmgr the address of the hardware manager
1912* @param table the SMC DPM table structure to be populated
1913* @return always 0
1914*/
2cc0c0b5 1915static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1916 struct SMU74_Discrete_DpmTable *table)
1917{
2cc0c0b5 1918 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1919 uint16_t config;
1920
1921 config = VR_MERGED_WITH_VDDC;
1922 table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
1923
1924 /* Set Vddc Voltage Controller */
2cc0c0b5 1925 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
a23eefa2
RZ		 1926 config = VR_SVI2_PLANE_1;
1927 table->VRConfig |= config;
1928 } else {
1929 PP_ASSERT_WITH_CODE(false,
1930 "VDDC should be on SVI2 control in merged mode!",
1931 );
1932 }
1933 /* Set Vddci Voltage Controller */
2cc0c0b5 1934 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
a23eefa2
RZ		 1935 config = VR_SVI2_PLANE_2; /* only in merged mode */
1936 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
2cc0c0b5 1937 } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
a23eefa2
RZ		 1938 config = VR_SMIO_PATTERN_1;
1939 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1940 } else {
1941 config = VR_STATIC_VOLTAGE;
1942 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1943 }
1944 /* Set Mvdd Voltage Controller */
2cc0c0b5 1945 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
a23eefa2
RZ		 1946 config = VR_SVI2_PLANE_2;
1947 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
2cc0c0b5 1948 } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
a23eefa2
RZ		 1949 config = VR_SMIO_PATTERN_2;
1950 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1951 } else {
1952 config = VR_STATIC_VOLTAGE;
1953 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1954 }
1955
1956 return 0;
1957}
1958
1959/**
1960* Initializes the SMC table and uploads it
1961*
1962* @param hwmgr the address of the powerplay hardware manager.
1963* @return always 0
1964*/
2cc0c0b5 1965static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 1966{
1967 int result;
2cc0c0b5 1968 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1969 struct phm_ppt_v1_information *table_info =
1970 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1971 struct SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
2cc0c0b5 1972 const struct polaris10_ulv_parm *ulv = &(data->ulv);
a23eefa2
RZ		 1973 uint8_t i;
1974 struct pp_atomctrl_gpio_pin_assignment gpio_pin;
e85c7d66 1975 pp_atomctrl_clock_dividers_vi dividers;
a23eefa2 1976
2cc0c0b5 1977 result = polaris10_setup_default_dpm_tables(hwmgr);
a23eefa2
RZ		 1978 PP_ASSERT_WITH_CODE(0 == result,
1979 "Failed to setup default DPM tables!", return result);
1980
2cc0c0b5
FC		 1981 if (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control)
1982 polaris10_populate_smc_voltage_tables(hwmgr, table);
a23eefa2 1983
681ed01c 1984 table->SystemFlags = 0;
a23eefa2
RZ		 1985 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1986 PHM_PlatformCaps_AutomaticDCTransition))
1987 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
1988
1989 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1990 PHM_PlatformCaps_StepVddc))
1991 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
1992
1993 if (data->is_memory_gddr5)
1994 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
1995
1996 if (ulv->ulv_supported && table_info->us_ulv_voltage_offset) {
2cc0c0b5 1997 result = polaris10_populate_ulv_state(hwmgr, table);
a23eefa2
RZ		 1998 PP_ASSERT_WITH_CODE(0 == result,
1999 "Failed to initialize ULV state!", return result);
2000 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2cc0c0b5 2001 ixCG_ULV_PARAMETER, PPPOLARIS10_CGULVPARAMETER_DFLT);
a23eefa2
RZ		 2002 }
2003
2cc0c0b5 2004 result = polaris10_populate_smc_link_level(hwmgr, table);
a23eefa2
RZ		 2005 PP_ASSERT_WITH_CODE(0 == result,
2006 "Failed to initialize Link Level!", return result);
2007
2cc0c0b5 2008 result = polaris10_populate_all_graphic_levels(hwmgr);
a23eefa2
RZ		 2009 PP_ASSERT_WITH_CODE(0 == result,
2010 "Failed to initialize Graphics Level!", return result);
2011
2cc0c0b5 2012 result = polaris10_populate_all_memory_levels(hwmgr);
a23eefa2
RZ		 2013 PP_ASSERT_WITH_CODE(0 == result,
2014 "Failed to initialize Memory Level!", return result);
2015
2cc0c0b5 2016 result = polaris10_populate_smc_acpi_level(hwmgr, table);
a23eefa2
RZ		 2017 PP_ASSERT_WITH_CODE(0 == result,
2018 "Failed to initialize ACPI Level!", return result);
2019
2cc0c0b5 2020 result = polaris10_populate_smc_vce_level(hwmgr, table);
a23eefa2
RZ		 2021 PP_ASSERT_WITH_CODE(0 == result,
2022 "Failed to initialize VCE Level!", return result);
2023
2cc0c0b5 2024 result = polaris10_populate_smc_samu_level(hwmgr, table);
a23eefa2
RZ		 2025 PP_ASSERT_WITH_CODE(0 == result,
2026 "Failed to initialize SAMU Level!", return result);
2027
2028 /* Since only the initial state is completely set up at this point
2029 * (the other states are just copies of the boot state) we only
2030 * need to populate the ARB settings for the initial state.
2031 */
2cc0c0b5 2032 result = polaris10_program_memory_timing_parameters(hwmgr);
a23eefa2
RZ		 2033 PP_ASSERT_WITH_CODE(0 == result,
2034 "Failed to Write ARB settings for the initial state.", return result);
2035
2cc0c0b5 2036 result = polaris10_populate_smc_uvd_level(hwmgr, table);
a23eefa2
RZ		 2037 PP_ASSERT_WITH_CODE(0 == result,
2038 "Failed to initialize UVD Level!", return result);
2039
2cc0c0b5 2040 result = polaris10_populate_smc_boot_level(hwmgr, table);
a23eefa2
RZ		 2041 PP_ASSERT_WITH_CODE(0 == result,
2042 "Failed to initialize Boot Level!", return result);
2043
2cc0c0b5 2044 result = polaris10_populate_smc_initailial_state(hwmgr);
a23eefa2
RZ		 2045 PP_ASSERT_WITH_CODE(0 == result,
2046 "Failed to initialize Boot State!", return result);
2047
2cc0c0b5 2048 result = polaris10_populate_bapm_parameters_in_dpm_table(hwmgr);
a23eefa2
RZ		 2049 PP_ASSERT_WITH_CODE(0 == result,
2050 "Failed to populate BAPM Parameters!", return result);
2051
2052 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2053 PHM_PlatformCaps_ClockStretcher)) {
2cc0c0b5 2054 result = polaris10_populate_clock_stretcher_data_table(hwmgr);
a23eefa2
RZ		 2055 PP_ASSERT_WITH_CODE(0 == result,
2056 "Failed to populate Clock Stretcher Data Table!",
2057 return result);
2058 }
9ab9cf05 2059 table->CurrSclkPllRange = 0xff;
a23eefa2
RZ		 2060 table->GraphicsVoltageChangeEnable = 1;
2061 table->GraphicsThermThrottleEnable = 1;
2062 table->GraphicsInterval = 1;
2063 table->VoltageInterval = 1;
2064 table->ThermalInterval = 1;
2065 table->TemperatureLimitHigh =
2066 table_info->cac_dtp_table->usTargetOperatingTemp *
2cc0c0b5 2067 POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
a23eefa2
RZ		 2068 table->TemperatureLimitLow =
2069 (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
2cc0c0b5 2070 POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
a23eefa2
RZ		 2071 table->MemoryVoltageChangeEnable = 1;
2072 table->MemoryInterval = 1;
2073 table->VoltageResponseTime = 0;
2074 table->PhaseResponseTime = 0;
2075 table->MemoryThermThrottleEnable = 1;
2076 table->PCIeBootLinkLevel = 0;
2077 table->PCIeGenInterval = 1;
681ed01c 2078 table->VRConfig = 0;
a23eefa2 2079
2cc0c0b5 2080 result = polaris10_populate_vr_config(hwmgr, table);
a23eefa2
RZ		 2081 PP_ASSERT_WITH_CODE(0 == result,
2082 "Failed to populate VRConfig setting!", return result);
2083
2084 table->ThermGpio = 17;
2085 table->SclkStepSize = 0x4000;
2086
2087 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
2088 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
2089 } else {
2cc0c0b5 2090 table->VRHotGpio = POLARIS10_UNUSED_GPIO_PIN;
a23eefa2
RZ		 2091 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2092 PHM_PlatformCaps_RegulatorHot);
2093 }
2094
2095 if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
2096 &gpio_pin)) {
2097 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
2098 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2099 PHM_PlatformCaps_AutomaticDCTransition);
2100 } else {
2cc0c0b5 2101 table->AcDcGpio = POLARIS10_UNUSED_GPIO_PIN;
a23eefa2
RZ		 2102 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2103 PHM_PlatformCaps_AutomaticDCTransition);
2104 }
2105
2106 /* Thermal Output GPIO */
2107 if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
2108 &gpio_pin)) {
2109 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2110 PHM_PlatformCaps_ThermalOutGPIO);
2111
2112 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
2113
2114 /* For porlarity read GPIOPAD_A with assigned Gpio pin
2115 * since VBIOS will program this register to set 'inactive state',
2116 * driver can then determine 'active state' from this and
2117 * program SMU with correct polarity
2118 */
2119 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A)
2120 & (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
2121 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
2122
2123 /* if required, combine VRHot/PCC with thermal out GPIO */
2124 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot)
2125 && phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal))
2126 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
2127 } else {
2128 table->ThermOutGpio = 17;
2129 table->ThermOutPolarity = 1;
2130 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
2131 }
2132
e85c7d66 2133 /* Populate BIF_SCLK levels into SMC DPM table */
2134 for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++) {
2135 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, data->bif_sclk_table[i], &dividers);
2136 PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result);
2137
2138 if (i == 0)
2139 table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2140 else
2141 table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2142 }
2143
a23eefa2
RZ		 2144 for (i = 0; i < SMU74_MAX_ENTRIES_SMIO; i++)
2145 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
2146
2147 CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2148 CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2149 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
2150 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
2151 CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
9ab9cf05 2152 CONVERT_FROM_HOST_TO_SMC_UL(table->CurrSclkPllRange);
a23eefa2
RZ		 2153 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2154 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2155 CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2156 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2157
2158 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2cc0c0b5 2159 result = polaris10_copy_bytes_to_smc(hwmgr->smumgr,
a23eefa2
RZ		 2160 data->dpm_table_start +
2161 offsetof(SMU74_Discrete_DpmTable, SystemFlags),
2162 (uint8_t *)&(table->SystemFlags),
2163 sizeof(SMU74_Discrete_DpmTable) - 3 * sizeof(SMU74_PIDController),
2164 data->sram_end);
2165 PP_ASSERT_WITH_CODE(0 == result,
2166 "Failed to upload dpm data to SMC memory!", return result);
2167
2168 return 0;
2169}
2170
2171/**
2172* Initialize the ARB DRAM timing table's index field.
2173*
2174* @param hwmgr the address of the powerplay hardware manager.
2175* @return always 0
2176*/
2cc0c0b5 2177static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr)
a23eefa2 2178{
2cc0c0b5 2179 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 2180 uint32_t tmp;
2181 int result;
2182
2183 /* This is a read-modify-write on the first byte of the ARB table.
2184 * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
2185 * is the field 'current'.
2186 * This solution is ugly, but we never write the whole table only
2187 * individual fields in it.
2188 * In reality this field should not be in that structure
2189 * but in a soft register.
2190 */
2cc0c0b5 2191 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
a23eefa2
RZ		 2192 data->arb_table_start, &tmp, data->sram_end);
2193
2194 if (result)
2195 return result;
2196
2197 tmp &= 0x00FFFFFF;
2198 tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
2199
2cc0c0b5 2200 return polaris10_write_smc_sram_dword(hwmgr->smumgr,
a23eefa2
RZ		 2201 data->arb_table_start, tmp, data->sram_end);
2202}
2203
2cc0c0b5 2204static int polaris10_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2205{
2206 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2207 PHM_PlatformCaps_RegulatorHot))
2208 return smum_send_msg_to_smc(hwmgr->smumgr,
2209 PPSMC_MSG_EnableVRHotGPIOInterrupt);
2210
2211 return 0;
2212}
2213
2cc0c0b5 2214static int polaris10_enable_sclk_control(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2215{
2216 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2217 SCLK_PWRMGT_OFF, 0);
2218 return 0;
2219}
2220
2cc0c0b5 2221static int polaris10_enable_ulv(struct pp_hwmgr *hwmgr)
a23eefa2 2222{
2cc0c0b5
FC		 2223 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2224 struct polaris10_ulv_parm *ulv = &(data->ulv);
a23eefa2
RZ		 2225
2226 if (ulv->ulv_supported)
2227 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV);
2228
2229 return 0;
2230}
2231
2cc0c0b5 2232static int polaris10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2233{
2234 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2235 PHM_PlatformCaps_SclkDeepSleep)) {
2236 if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON))
2237 PP_ASSERT_WITH_CODE(false,
2238 "Attempt to enable Master Deep Sleep switch failed!",
2239 return -1);
2240 } else {
2241 if (smum_send_msg_to_smc(hwmgr->smumgr,
2242 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
2243 PP_ASSERT_WITH_CODE(false,
2244 "Attempt to disable Master Deep Sleep switch failed!",
2245 return -1);
2246 }
2247 }
2248
2249 return 0;
2250}
2251
2cc0c0b5 2252static int polaris10_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
a23eefa2 2253{
2cc0c0b5 2254 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 2255
2256 /* enable SCLK dpm */
2257 if (!data->sclk_dpm_key_disabled)
2258 PP_ASSERT_WITH_CODE(
2259 (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)),
2260 "Failed to enable SCLK DPM during DPM Start Function!",
2261 return -1);
2262
2263 /* enable MCLK dpm */
2264 if (0 == data->mclk_dpm_key_disabled) {
2265
2266 PP_ASSERT_WITH_CODE(
2267 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2268 PPSMC_MSG_MCLKDPM_Enable)),
2269 "Failed to enable MCLK DPM during DPM Start Function!",
2270 return -1);
2271
2272
2273 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
2274
2275 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
2276 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
2277 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
2278 udelay(10);
2279 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
2280 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
2281 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
2282 }
2283
2284 return 0;
2285}
2286
2cc0c0b5 2287static int polaris10_start_dpm(struct pp_hwmgr *hwmgr)
a23eefa2 2288{
2cc0c0b5 2289 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 2290
2291 /*enable general power management */
2292
2293 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2294 GLOBAL_PWRMGT_EN, 1);
2295
2296 /* enable sclk deep sleep */
2297
2298 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2299 DYNAMIC_PM_EN, 1);
2300
2301 /* prepare for PCIE DPM */
2302
2303 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2304 data->soft_regs_start + offsetof(SMU74_SoftRegisters,
2305 VoltageChangeTimeout), 0x1000);
2306 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
2307 SWRST_COMMAND_1, RESETLC, 0x0);
e85c7d66 2308/*
a23eefa2
RZ		 2309 PP_ASSERT_WITH_CODE(
2310 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2311 PPSMC_MSG_Voltage_Cntl_Enable)),
2312 "Failed to enable voltage DPM during DPM Start Function!",
2313 return -1);
e85c7d66 2314*/
a23eefa2 2315
2cc0c0b5 2316 if (polaris10_enable_sclk_mclk_dpm(hwmgr)) {
a23eefa2
RZ		 2317 printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!");
2318 return -1;
2319 }
2320
2321 /* enable PCIE dpm */
2322 if (0 == data->pcie_dpm_key_disabled) {
2323 PP_ASSERT_WITH_CODE(
2324 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2325 PPSMC_MSG_PCIeDPM_Enable)),
2326 "Failed to enable pcie DPM during DPM Start Function!",
2327 return -1);
2328 }
2329
c8c67448
EH		 2330 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2331 PHM_PlatformCaps_Falcon_QuickTransition)) {
2332 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr,
2333 PPSMC_MSG_EnableACDCGPIOInterrupt)),
2334 "Failed to enable AC DC GPIO Interrupt!",
2335 );
2336 }
a23eefa2
RZ		 2337
2338 return 0;
2339}
2340
2cc0c0b5 2341static void polaris10_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)
a23eefa2
RZ		 2342{
2343 bool protection;
2344 enum DPM_EVENT_SRC src;
2345
2346 switch (sources) {
2347 default:
2348 printk(KERN_ERR "Unknown throttling event sources.");
2349 /* fall through */
2350 case 0:
2351 protection = false;
2352 /* src is unused */
2353 break;
2354 case (1 << PHM_AutoThrottleSource_Thermal):
2355 protection = true;
2356 src = DPM_EVENT_SRC_DIGITAL;
2357 break;
2358 case (1 << PHM_AutoThrottleSource_External):
2359 protection = true;
2360 src = DPM_EVENT_SRC_EXTERNAL;
2361 break;
2362 case (1 << PHM_AutoThrottleSource_External) |
2363 (1 << PHM_AutoThrottleSource_Thermal):
2364 protection = true;
2365 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
2366 break;
2367 }
2368 /* Order matters - don't enable thermal protection for the wrong source. */
2369 if (protection) {
2370 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
2371 DPM_EVENT_SRC, src);
2372 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2373 THERMAL_PROTECTION_DIS,
f0911de8 2374 !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
a23eefa2
RZ		 2375 PHM_PlatformCaps_ThermalController));
2376 } else
2377 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2378 THERMAL_PROTECTION_DIS, 1);
2379}
2380
2cc0c0b5 2381static int polaris10_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 2382 PHM_AutoThrottleSource source)
2383{
2cc0c0b5 2384 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 2385
2386 if (!(data->active_auto_throttle_sources & (1 << source))) {
2387 data->active_auto_throttle_sources |= 1 << source;
2cc0c0b5 2388 polaris10_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
a23eefa2
RZ		 2389 }
2390 return 0;
2391}
2392
2cc0c0b5 2393static int polaris10_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
a23eefa2 2394{
2cc0c0b5 2395 return polaris10_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
a23eefa2
RZ		 2396}
2397
2cc0c0b5 2398int polaris10_pcie_performance_request(struct pp_hwmgr *hwmgr)
a23eefa2 2399{
2cc0c0b5 2400 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 2401 data->pcie_performance_request = true;
2402
2403 return 0;
2404}
2405
2cc0c0b5 2406int polaris10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2407{
2408 int tmp_result, result = 0;
2cc0c0b5 2409 tmp_result = (!polaris10_is_dpm_running(hwmgr)) ? 0 : -1;
a23eefa2
RZ		 2410 PP_ASSERT_WITH_CODE(result == 0,
2411 "DPM is already running right now, no need to enable DPM!",
2412 return 0);
2413
2cc0c0b5
FC		 2414 if (polaris10_voltage_control(hwmgr)) {
2415 tmp_result = polaris10_enable_voltage_control(hwmgr);
a23eefa2
RZ		 2416 PP_ASSERT_WITH_CODE(tmp_result == 0,
2417 "Failed to enable voltage control!",
2418 result = tmp_result);
2419
2cc0c0b5 2420 tmp_result = polaris10_construct_voltage_tables(hwmgr);
a23eefa2
RZ		 2421 PP_ASSERT_WITH_CODE((0 == tmp_result),
2422 "Failed to contruct voltage tables!",
2423 result = tmp_result);
2424 }
2425
2426 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2427 PHM_PlatformCaps_EngineSpreadSpectrumSupport))
2428 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2429 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
2430
2431 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2432 PHM_PlatformCaps_ThermalController))
2433 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2434 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
2435
2cc0c0b5 2436 tmp_result = polaris10_program_static_screen_threshold_parameters(hwmgr);
a23eefa2
RZ		 2437 PP_ASSERT_WITH_CODE((0 == tmp_result),
2438 "Failed to program static screen threshold parameters!",
2439 result = tmp_result);
2440
2cc0c0b5 2441 tmp_result = polaris10_enable_display_gap(hwmgr);
a23eefa2
RZ		 2442 PP_ASSERT_WITH_CODE((0 == tmp_result),
2443 "Failed to enable display gap!", result = tmp_result);
2444
2cc0c0b5 2445 tmp_result = polaris10_program_voting_clients(hwmgr);
a23eefa2
RZ		 2446 PP_ASSERT_WITH_CODE((0 == tmp_result),
2447 "Failed to program voting clients!", result = tmp_result);
2448
2cc0c0b5 2449 tmp_result = polaris10_process_firmware_header(hwmgr);
a23eefa2
RZ		 2450 PP_ASSERT_WITH_CODE((0 == tmp_result),
2451 "Failed to process firmware header!", result = tmp_result);
2452
2cc0c0b5 2453 tmp_result = polaris10_initial_switch_from_arbf0_to_f1(hwmgr);
a23eefa2
RZ		 2454 PP_ASSERT_WITH_CODE((0 == tmp_result),
2455 "Failed to initialize switch from ArbF0 to F1!",
2456 result = tmp_result);
2457
2cc0c0b5 2458 tmp_result = polaris10_init_smc_table(hwmgr);
a23eefa2
RZ		 2459 PP_ASSERT_WITH_CODE((0 == tmp_result),
2460 "Failed to initialize SMC table!", result = tmp_result);
2461
2cc0c0b5 2462 tmp_result = polaris10_init_arb_table_index(hwmgr);
a23eefa2
RZ		 2463 PP_ASSERT_WITH_CODE((0 == tmp_result),
2464 "Failed to initialize ARB table index!", result = tmp_result);
2465
2cc0c0b5 2466 tmp_result = polaris10_populate_pm_fuses(hwmgr);
a23eefa2
RZ		 2467 PP_ASSERT_WITH_CODE((0 == tmp_result),
2468 "Failed to populate PM fuses!", result = tmp_result);
2469
2cc0c0b5 2470 tmp_result = polaris10_enable_vrhot_gpio_interrupt(hwmgr);
a23eefa2
RZ		 2471 PP_ASSERT_WITH_CODE((0 == tmp_result),
2472 "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
2473
2cc0c0b5 2474 tmp_result = polaris10_enable_sclk_control(hwmgr);
a23eefa2
RZ		 2475 PP_ASSERT_WITH_CODE((0 == tmp_result),
2476 "Failed to enable SCLK control!", result = tmp_result);
2477
2cc0c0b5 2478 tmp_result = polaris10_enable_smc_voltage_controller(hwmgr);
e85c7d66 2479 PP_ASSERT_WITH_CODE((0 == tmp_result),
2480 "Failed to enable voltage control!", result = tmp_result);
2481
2cc0c0b5 2482 tmp_result = polaris10_enable_ulv(hwmgr);
a23eefa2
RZ		 2483 PP_ASSERT_WITH_CODE((0 == tmp_result),
2484 "Failed to enable ULV!", result = tmp_result);
2485
2cc0c0b5 2486 tmp_result = polaris10_enable_deep_sleep_master_switch(hwmgr);
a23eefa2
RZ		 2487 PP_ASSERT_WITH_CODE((0 == tmp_result),
2488 "Failed to enable deep sleep master switch!", result = tmp_result);
2489
2cc0c0b5 2490 tmp_result = polaris10_start_dpm(hwmgr);
a23eefa2
RZ		 2491 PP_ASSERT_WITH_CODE((0 == tmp_result),
2492 "Failed to start DPM!", result = tmp_result);
2493
2cc0c0b5 2494 tmp_result = polaris10_enable_smc_cac(hwmgr);
a23eefa2
RZ		 2495 PP_ASSERT_WITH_CODE((0 == tmp_result),
2496 "Failed to enable SMC CAC!", result = tmp_result);
2497
2cc0c0b5 2498 tmp_result = polaris10_enable_power_containment(hwmgr);
a23eefa2
RZ		 2499 PP_ASSERT_WITH_CODE((0 == tmp_result),
2500 "Failed to enable power containment!", result = tmp_result);
2501
2cc0c0b5 2502 tmp_result = polaris10_power_control_set_level(hwmgr);
a23eefa2
RZ		 2503 PP_ASSERT_WITH_CODE((0 == tmp_result),
2504 "Failed to power control set level!", result = tmp_result);
2505
2cc0c0b5 2506 tmp_result = polaris10_enable_thermal_auto_throttle(hwmgr);
a23eefa2
RZ		 2507 PP_ASSERT_WITH_CODE((0 == tmp_result),
2508 "Failed to enable thermal auto throttle!", result = tmp_result);
2509
2cc0c0b5 2510 tmp_result = polaris10_pcie_performance_request(hwmgr);
a23eefa2 2511 PP_ASSERT_WITH_CODE((0 == tmp_result),
5f88567c 2512 "pcie performance request failed!", result = tmp_result);
a23eefa2
RZ		 2513
2514 return result;
2515}
2516
2cc0c0b5 2517int polaris10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2518{
2519
2520 return 0;
2521}
2522
2cc0c0b5 2523int polaris10_reset_asic_tasks(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2524{
2525
2526 return 0;
2527}
2528
2cc0c0b5 2529int polaris10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
a23eefa2 2530{
a72d5604
EH		 2531 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2532
2533 if (data->soft_pp_table) {
2534 kfree(data->soft_pp_table);
2535 data->soft_pp_table = NULL;
2536 }
2537
a23eefa2
RZ		 2538 return phm_hwmgr_backend_fini(hwmgr);
2539}
2540
2cc0c0b5 2541int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
a23eefa2 2542{
2cc0c0b5 2543 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 2544
2545 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2546 PHM_PlatformCaps_SclkDeepSleep);
2547
f0911de8
RZ		 2548 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2549 PHM_PlatformCaps_DynamicPatchPowerState);
2550
2cc0c0b5 2551 if (data->mvdd_control == POLARIS10_VOLTAGE_CONTROL_NONE)
a23eefa2
RZ		 2552 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2553 PHM_PlatformCaps_EnableMVDDControl);
2554
2cc0c0b5 2555 if (data->vddci_control == POLARIS10_VOLTAGE_CONTROL_NONE)
a23eefa2
RZ		 2556 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2557 PHM_PlatformCaps_ControlVDDCI);
2558
2559 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2560 PHM_PlatformCaps_TablelessHardwareInterface);
2561
2562 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2563 PHM_PlatformCaps_EnableSMU7ThermalManagement);
2564
2565 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2566 PHM_PlatformCaps_DynamicPowerManagement);
2567
f0911de8
RZ		 2568 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2569 PHM_PlatformCaps_UnTabledHardwareInterface);
2570
a23eefa2
RZ		 2571 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2572 PHM_PlatformCaps_TablelessHardwareInterface);
2573
2574 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2575 PHM_PlatformCaps_SMC);
2576
2577 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2578 PHM_PlatformCaps_NonABMSupportInPPLib);
2579
2580 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2581 PHM_PlatformCaps_DynamicUVDState);
2582
a23eefa2 2583 /* power tune caps Assume disabled */
a23eefa2
RZ		 2584 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2585 PHM_PlatformCaps_SQRamping);
2586 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2587 PHM_PlatformCaps_DBRamping);
2588 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2589 PHM_PlatformCaps_TDRamping);
2590 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2591 PHM_PlatformCaps_TCPRamping);
2592
f0911de8
RZ		 2593 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2594 PHM_PlatformCaps_PowerContainment);
2595 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2596 PHM_PlatformCaps_CAC);
2597
2598 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2599 PHM_PlatformCaps_RegulatorHot);
2600
2601 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2602 PHM_PlatformCaps_AutomaticDCTransition);
2603
2604 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2605 PHM_PlatformCaps_ODFuzzyFanControlSupport);
2606
2607 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2608 PHM_PlatformCaps_FanSpeedInTableIsRPM);
919e334d 2609
5de95e55
RZ		 2610 if (hwmgr->chip_id == CHIP_POLARIS11)
2611 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2612 PHM_PlatformCaps_SPLLShutdownSupport);
a23eefa2
RZ		 2613 return 0;
2614}
2615
2cc0c0b5 2616static void polaris10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
a23eefa2 2617{
2cc0c0b5 2618 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2 2619
2cc0c0b5 2620 polaris10_initialize_power_tune_defaults(hwmgr);
a23eefa2
RZ		 2621
2622 data->pcie_gen_performance.max = PP_PCIEGen1;
2623 data->pcie_gen_performance.min = PP_PCIEGen3;
2624 data->pcie_gen_power_saving.max = PP_PCIEGen1;
2625 data->pcie_gen_power_saving.min = PP_PCIEGen3;
2626 data->pcie_lane_performance.max = 0;
2627 data->pcie_lane_performance.min = 16;
2628 data->pcie_lane_power_saving.max = 0;
2629 data->pcie_lane_power_saving.min = 16;
2630}
2631
2632/**
2633* Get Leakage VDDC based on leakage ID.
2634*
2635* @param hwmgr the address of the powerplay hardware manager.
2636* @return always 0
2637*/
2cc0c0b5 2638static int polaris10_get_evv_voltages(struct pp_hwmgr *hwmgr)
a23eefa2 2639{
2cc0c0b5 2640 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 2641 uint16_t vv_id;
2642 uint16_t vddc = 0;
2643 uint16_t i, j;
2644 uint32_t sclk = 0;
2645 struct phm_ppt_v1_information *table_info =
2646 (struct phm_ppt_v1_information *)hwmgr->pptable;
2647 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2648 table_info->vdd_dep_on_sclk;
2649 int result;
2650
2cc0c0b5 2651 for (i = 0; i < POLARIS10_MAX_LEAKAGE_COUNT; i++) {
a23eefa2
RZ		 2652 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
2653 if (!phm_get_sclk_for_voltage_evv(hwmgr,
2654 table_info->vddc_lookup_table, vv_id, &sclk)) {
2655 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2656 PHM_PlatformCaps_ClockStretcher)) {
2657 for (j = 1; j < sclk_table->count; j++) {
2658 if (sclk_table->entries[j].clk == sclk &&
2659 sclk_table->entries[j].cks_enable == 0) {
2660 sclk += 5000;
2661 break;
2662 }
2663 }
2664 }
2665
2666
2667 PP_ASSERT_WITH_CODE(0 == atomctrl_get_voltage_evv_on_sclk_ai(hwmgr,
2668 VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc),
2669 "Error retrieving EVV voltage value!",
2670 continue);
2671
2672
2673 /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
2674 PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0),
2675 "Invalid VDDC value", result = -EINVAL;);
2676
2677 /* the voltage should not be zero nor equal to leakage ID */
2678 if (vddc != 0 && vddc != vv_id) {
2679 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100);
2680 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
2681 data->vddc_leakage.count++;
2682 }
2683 }
2684 }
2685
2686 return 0;
2687}
2688
2689/**
2690 * Change virtual leakage voltage to actual value.
2691 *
2692 * @param hwmgr the address of the powerplay hardware manager.
2693 * @param pointer to changing voltage
2694 * @param pointer to leakage table
2695 */
2cc0c0b5
FC		 2696static void polaris10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
2697 uint16_t *voltage, struct polaris10_leakage_voltage *leakage_table)
a23eefa2
RZ		 2698{
2699 uint32_t index;
2700
2701 /* search for leakage voltage ID 0xff01 ~ 0xff08 */
2702 for (index = 0; index < leakage_table->count; index++) {
2703 /* if this voltage matches a leakage voltage ID */
2704 /* patch with actual leakage voltage */
2705 if (leakage_table->leakage_id[index] == *voltage) {
2706 *voltage = leakage_table->actual_voltage[index];
2707 break;
2708 }
2709 }
2710
2711 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
2712 printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n");
2713}
2714
2715/**
2716* Patch voltage lookup table by EVV leakages.
2717*
2718* @param hwmgr the address of the powerplay hardware manager.
2719* @param pointer to voltage lookup table
2720* @param pointer to leakage table
2721* @return always 0
2722*/
2cc0c0b5 2723static int polaris10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
a23eefa2 2724 phm_ppt_v1_voltage_lookup_table *lookup_table,
2cc0c0b5 2725 struct polaris10_leakage_voltage *leakage_table)
a23eefa2
RZ		 2726{
2727 uint32_t i;
2728
2729 for (i = 0; i < lookup_table->count; i++)
2cc0c0b5 2730 polaris10_patch_with_vdd_leakage(hwmgr,
a23eefa2
RZ		 2731 &lookup_table->entries[i].us_vdd, leakage_table);
2732
2733 return 0;
2734}
2735
2cc0c0b5
FC		 2736static int polaris10_patch_clock_voltage_limits_with_vddc_leakage(
2737 struct pp_hwmgr *hwmgr, struct polaris10_leakage_voltage *leakage_table,
a23eefa2
RZ		 2738 uint16_t *vddc)
2739{
2740 struct phm_ppt_v1_information *table_info =
2741 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2cc0c0b5 2742 polaris10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
a23eefa2
RZ		 2743 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
2744 table_info->max_clock_voltage_on_dc.vddc;
2745 return 0;
2746}
2747
2cc0c0b5 2748static int polaris10_patch_voltage_dependency_tables_with_lookup_table(
a23eefa2
RZ		 2749 struct pp_hwmgr *hwmgr)
2750{
2751 uint8_t entryId;
2752 uint8_t voltageId;
2753 struct phm_ppt_v1_information *table_info =
2754 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2755
2756 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2757 table_info->vdd_dep_on_sclk;
2758 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
2759 table_info->vdd_dep_on_mclk;
2760 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2761 table_info->mm_dep_table;
2762
2763 for (entryId = 0; entryId < sclk_table->count; ++entryId) {
2764 voltageId = sclk_table->entries[entryId].vddInd;
2765 sclk_table->entries[entryId].vddc =
2766 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2767 }
2768
2769 for (entryId = 0; entryId < mclk_table->count; ++entryId) {
2770 voltageId = mclk_table->entries[entryId].vddInd;
2771 mclk_table->entries[entryId].vddc =
2772 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2773 }
2774
2775 for (entryId = 0; entryId < mm_table->count; ++entryId) {
2776 voltageId = mm_table->entries[entryId].vddcInd;
2777 mm_table->entries[entryId].vddc =
2778 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2779 }
2780
2781 return 0;
2782
2783}
2784
2cc0c0b5 2785static int polaris10_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2786{
2787 /* Need to determine if we need calculated voltage. */
2788 return 0;
2789}
2790
2cc0c0b5 2791static int polaris10_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2792{
2793 /* Need to determine if we need calculated voltage from mm table. */
2794 return 0;
2795}
2796
2cc0c0b5 2797static int polaris10_sort_lookup_table(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 2798 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
2799{
2800 uint32_t table_size, i, j;
2801 struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
2802 table_size = lookup_table->count;
2803
2804 PP_ASSERT_WITH_CODE(0 != lookup_table->count,
2805 "Lookup table is empty", return -EINVAL);
2806
2807 /* Sorting voltages */
2808 for (i = 0; i < table_size - 1; i++) {
2809 for (j = i + 1; j > 0; j--) {
2810 if (lookup_table->entries[j].us_vdd <
2811 lookup_table->entries[j - 1].us_vdd) {
2812 tmp_voltage_lookup_record = lookup_table->entries[j - 1];
2813 lookup_table->entries[j - 1] = lookup_table->entries[j];
2814 lookup_table->entries[j] = tmp_voltage_lookup_record;
2815 }
2816 }
2817 }
2818
2819 return 0;
2820}
2821
2cc0c0b5 2822static int polaris10_complete_dependency_tables(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2823{
2824 int result = 0;
2825 int tmp_result;
2cc0c0b5 2826 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 2827 struct phm_ppt_v1_information *table_info =
2828 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2829
2cc0c0b5 2830 tmp_result = polaris10_patch_lookup_table_with_leakage(hwmgr,
a23eefa2
RZ		 2831 table_info->vddc_lookup_table, &(data->vddc_leakage));
2832 if (tmp_result)
2833 result = tmp_result;
2834
2cc0c0b5 2835 tmp_result = polaris10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
a23eefa2
RZ		 2836 &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
2837 if (tmp_result)
2838 result = tmp_result;
2839
2cc0c0b5 2840 tmp_result = polaris10_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
a23eefa2
RZ		 2841 if (tmp_result)
2842 result = tmp_result;
2843
2cc0c0b5 2844 tmp_result = polaris10_calc_voltage_dependency_tables(hwmgr);
a23eefa2
RZ		 2845 if (tmp_result)
2846 result = tmp_result;
2847
2cc0c0b5 2848 tmp_result = polaris10_calc_mm_voltage_dependency_table(hwmgr);
a23eefa2
RZ		 2849 if (tmp_result)
2850 result = tmp_result;
2851
2cc0c0b5 2852 tmp_result = polaris10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
a23eefa2
RZ		 2853 if (tmp_result)
2854 result = tmp_result;
2855
2856 return result;
2857}
2858
2cc0c0b5 2859static int polaris10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2860{
2861 struct phm_ppt_v1_information *table_info =
2862 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2863
2864 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
2865 table_info->vdd_dep_on_sclk;
2866 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
2867 table_info->vdd_dep_on_mclk;
2868
2869 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
edf600da 2870 "VDD dependency on SCLK table is missing. \
a23eefa2
RZ		 2871 This table is mandatory", return -EINVAL);
2872 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
edf600da 2873 "VDD dependency on SCLK table has to have is missing. \
a23eefa2
RZ		 2874 This table is mandatory", return -EINVAL);
2875
2876 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
edf600da 2877 "VDD dependency on MCLK table is missing. \
a23eefa2
RZ		 2878 This table is mandatory", return -EINVAL);
2879 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
2880 "VDD dependency on MCLK table has to have is missing. \
2881 This table is mandatory", return -EINVAL);
2882
2883 table_info->max_clock_voltage_on_ac.sclk =
2884 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
2885 table_info->max_clock_voltage_on_ac.mclk =
2886 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
2887 table_info->max_clock_voltage_on_ac.vddc =
2888 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
2889 table_info->max_clock_voltage_on_ac.vddci =
2890 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
2891
f0911de8
RZ		 2892 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk;
2893 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk;
2894 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc;
2895 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =table_info->max_clock_voltage_on_ac.vddci;
2896
a23eefa2
RZ		 2897 return 0;
2898}
2899
2cc0c0b5 2900int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
a23eefa2 2901{
2cc0c0b5 2902 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 2903 struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
2904 uint32_t temp_reg;
2905 int result;
f0911de8
RZ		 2906 struct phm_ppt_v1_information *table_info =
2907 (struct phm_ppt_v1_information *)(hwmgr->pptable);
a23eefa2
RZ		 2908
2909 data->dll_default_on = false;
2910 data->sram_end = SMC_RAM_END;
7d367c2a 2911 data->mclk_dpm0_activity_target = 0xa;
a23eefa2 2912 data->disable_dpm_mask = 0xFF;
2cc0c0b5
FC		 2913 data->static_screen_threshold = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
2914 data->static_screen_threshold_unit = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
2915 data->activity_target[0] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2916 data->activity_target[1] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2917 data->activity_target[2] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2918 data->activity_target[3] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2919 data->activity_target[4] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2920 data->activity_target[5] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2921 data->activity_target[6] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2922 data->activity_target[7] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2923
2924 data->voting_rights_clients0 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT0;
2925 data->voting_rights_clients1 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT1;
2926 data->voting_rights_clients2 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT2;
2927 data->voting_rights_clients3 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT3;
2928 data->voting_rights_clients4 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT4;
2929 data->voting_rights_clients5 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT5;
2930 data->voting_rights_clients6 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT6;
2931 data->voting_rights_clients7 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT7;
a23eefa2
RZ		 2932
2933 data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
2934
2cc0c0b5 2935 data->mclk_activity_target = PPPOLARIS10_MCLK_TARGETACTIVITY_DFLT;
a23eefa2
RZ		 2936
2937 /* need to set voltage control types before EVV patching */
2cc0c0b5
FC		 2938 data->voltage_control = POLARIS10_VOLTAGE_CONTROL_NONE;
2939 data->vddci_control = POLARIS10_VOLTAGE_CONTROL_NONE;
2940 data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_NONE;
a23eefa2 2941
919e334d
RZ		 2942 data->enable_tdc_limit_feature = true;
2943 data->enable_pkg_pwr_tracking_feature = true;
2944
a23eefa2
RZ		 2945 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2946 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
2cc0c0b5 2947 data->voltage_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
a23eefa2 2948
a23eefa2
RZ		 2949 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2950 PHM_PlatformCaps_EnableMVDDControl)) {
2951 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2952 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
2cc0c0b5 2953 data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
a23eefa2
RZ		 2954 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2955 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
2cc0c0b5 2956 data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
a23eefa2
RZ		 2957 }
2958
2959 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2960 PHM_PlatformCaps_ControlVDDCI)) {
2961 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2962 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
2cc0c0b5 2963 data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
a23eefa2
RZ		 2964 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2965 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
2cc0c0b5 2966 data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
a23eefa2
RZ		 2967 }
2968
2cc0c0b5 2969 polaris10_set_features_platform_caps(hwmgr);
a23eefa2 2970
2cc0c0b5 2971 polaris10_init_dpm_defaults(hwmgr);
a23eefa2
RZ		 2972
2973 /* Get leakage voltage based on leakage ID. */
2cc0c0b5 2974 result = polaris10_get_evv_voltages(hwmgr);
a23eefa2
RZ		 2975
2976 if (result) {
2977 printk("Get EVV Voltage Failed. Abort Driver loading!\n");
2978 return -1;
2979 }
2980
2cc0c0b5
FC		 2981 polaris10_complete_dependency_tables(hwmgr);
2982 polaris10_set_private_data_based_on_pptable(hwmgr);
a23eefa2
RZ		 2983
2984 /* Initalize Dynamic State Adjustment Rule Settings */
2985 result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
2986
2987 if (0 == result) {
2988 struct cgs_system_info sys_info = {0};
2989
2990 data->is_tlu_enabled = 0;
2991
2992 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
2cc0c0b5 2993 POLARIS10_MAX_HARDWARE_POWERLEVELS;
a23eefa2
RZ		 2994 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
2995 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
f0911de8 2996
a23eefa2
RZ		 2997
2998 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
2999 temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
3000 switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
3001 case 0:
3002 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
3003 break;
3004 case 1:
3005 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
3006 break;
3007 case 2:
3008 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
3009 break;
3010 case 3:
3011 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
3012 break;
3013 case 4:
3014 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
3015 break;
3016 default:
3017 PP_ASSERT_WITH_CODE(0,
3018 "Failed to setup PCC HW register! Wrong GPIO assigned for VDDC_PCC_GPIO_PINID!",
3019 );
3020 break;
3021 }
3022 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg);
3023 }
3024
f0911de8
RZ		 3025 if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp != 0 &&
3026 hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode) {
3027 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit =
3028 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
3029
3030 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMaxLimit =
3031 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
3032
3033 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMStep = 1;
3034
3035 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100;
3036
3037 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMinLimit =
3038 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
3039
3040 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMStep = 1;
3041
3042 table_info->cac_dtp_table->usDefaultTargetOperatingTemp = (table_info->cac_dtp_table->usDefaultTargetOperatingTemp >= 50) ?
3043 (table_info->cac_dtp_table->usDefaultTargetOperatingTemp -50) : 0;
3044
3045 table_info->cac_dtp_table->usOperatingTempMaxLimit = table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
3046 table_info->cac_dtp_table->usOperatingTempStep = 1;
3047 table_info->cac_dtp_table->usOperatingTempHyst = 1;
3048
3049 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM =
3050 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
3051
3052 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
3053 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM;
3054
3055 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit =
3056 table_info->cac_dtp_table->usOperatingTempMinLimit;
3057
3058 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit =
3059 table_info->cac_dtp_table->usOperatingTempMaxLimit;
3060
3061 hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
3062 table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
3063
3064 hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep =
3065 table_info->cac_dtp_table->usOperatingTempStep;
3066
3067 hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
3068 table_info->cac_dtp_table->usTargetOperatingTemp;
3069 }
3070
a23eefa2
RZ		 3071 sys_info.size = sizeof(struct cgs_system_info);
3072 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
3073 result = cgs_query_system_info(hwmgr->device, &sys_info);
3074 if (result)
3075 data->pcie_gen_cap = 0x30007;
3076 else
3077 data->pcie_gen_cap = (uint32_t)sys_info.value;
3078 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
3079 data->pcie_spc_cap = 20;
3080 sys_info.size = sizeof(struct cgs_system_info);
3081 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
3082 result = cgs_query_system_info(hwmgr->device, &sys_info);
3083 if (result)
3084 data->pcie_lane_cap = 0x2f0000;
3085 else
3086 data->pcie_lane_cap = (uint32_t)sys_info.value;
f0911de8
RZ		 3087
3088 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
3089/* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
3090 hwmgr->platform_descriptor.clockStep.engineClock = 500;
3091 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
a23eefa2
RZ		 3092 } else {
3093 /* Ignore return value in here, we are cleaning up a mess. */
2cc0c0b5 3094 polaris10_hwmgr_backend_fini(hwmgr);
a23eefa2
RZ		 3095 }
3096
3097 return 0;
3098}
3099
2cc0c0b5 3100static int polaris10_force_dpm_highest(struct pp_hwmgr *hwmgr)
a23eefa2 3101{
2cc0c0b5 3102 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 3103 uint32_t level, tmp;
3104
3105 if (!data->pcie_dpm_key_disabled) {
3106 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3107 level = 0;
3108 tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
3109 while (tmp >>= 1)
3110 level++;
3111
3112 if (level)
3113 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3114 PPSMC_MSG_PCIeDPM_ForceLevel, level);
3115 }
3116 }
3117
3118 if (!data->sclk_dpm_key_disabled) {
3119 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3120 level = 0;
3121 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
3122 while (tmp >>= 1)
3123 level++;
3124
3125 if (level)
3126 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3127 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3128 (1 << level));
3129 }
3130 }
3131
3132 if (!data->mclk_dpm_key_disabled) {
3133 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3134 level = 0;
3135 tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
3136 while (tmp >>= 1)
3137 level++;
3138
3139 if (level)
3140 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3141 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3142 (1 << level));
3143 }
3144 }
3145
3146 return 0;
3147}
3148
2cc0c0b5 3149static int polaris10_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
a23eefa2 3150{
2cc0c0b5 3151 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 3152
3153 phm_apply_dal_min_voltage_request(hwmgr);
3154
3155 if (!data->sclk_dpm_key_disabled) {
3156 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
3157 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3158 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3159 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3160 }
3161
3162 if (!data->mclk_dpm_key_disabled) {
3163 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
3164 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3165 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3166 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3167 }
3168
3169 return 0;
3170}
3171
2cc0c0b5 3172static int polaris10_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
a23eefa2 3173{
2cc0c0b5 3174 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2 3175
2cc0c0b5 3176 if (!polaris10_is_dpm_running(hwmgr))
a23eefa2
RZ		 3177 return -EINVAL;
3178
3179 if (!data->pcie_dpm_key_disabled) {
3180 smum_send_msg_to_smc(hwmgr->smumgr,
3181 PPSMC_MSG_PCIeDPM_UnForceLevel);
3182 }
3183
2cc0c0b5 3184 return polaris10_upload_dpm_level_enable_mask(hwmgr);
a23eefa2
RZ		 3185}
3186
2cc0c0b5 3187static int polaris10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
a23eefa2 3188{
2cc0c0b5
FC		 3189 struct polaris10_hwmgr *data =
3190 (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 3191 uint32_t level;
3192
3193 if (!data->sclk_dpm_key_disabled)
3194 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3195 level = phm_get_lowest_enabled_level(hwmgr,
3196 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3197 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3198 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3199 (1 << level));
3200
3201 }
2043f43e 3202
a23eefa2
RZ		 3203 if (!data->mclk_dpm_key_disabled) {
3204 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3205 level = phm_get_lowest_enabled_level(hwmgr,
3206 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3207 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3208 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3209 (1 << level));
3210 }
3211 }
2043f43e 3212
a23eefa2
RZ		 3213 if (!data->pcie_dpm_key_disabled) {
3214 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3215 level = phm_get_lowest_enabled_level(hwmgr,
3216 data->dpm_level_enable_mask.pcie_dpm_enable_mask);
3217 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3218 PPSMC_MSG_PCIeDPM_ForceLevel,
3219 (level));
3220 }
3221 }
3222
3223 return 0;
3224
3225}
2cc0c0b5 3226static int polaris10_force_dpm_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 3227 enum amd_dpm_forced_level level)
3228{
3229 int ret = 0;
3230
3231 switch (level) {
3232 case AMD_DPM_FORCED_LEVEL_HIGH:
2cc0c0b5 3233 ret = polaris10_force_dpm_highest(hwmgr);
a23eefa2
RZ		 3234 if (ret)
3235 return ret;
3236 break;
3237 case AMD_DPM_FORCED_LEVEL_LOW:
2cc0c0b5 3238 ret = polaris10_force_dpm_lowest(hwmgr);
a23eefa2
RZ		 3239 if (ret)
3240 return ret;
3241 break;
3242 case AMD_DPM_FORCED_LEVEL_AUTO:
2cc0c0b5 3243 ret = polaris10_unforce_dpm_levels(hwmgr);
a23eefa2
RZ		 3244 if (ret)
3245 return ret;
3246 break;
3247 default:
3248 break;
3249 }
3250
3251 hwmgr->dpm_level = level;
3252
3253 return ret;
3254}
3255
2cc0c0b5 3256static int polaris10_get_power_state_size(struct pp_hwmgr *hwmgr)
a23eefa2 3257{
2cc0c0b5 3258 return sizeof(struct polaris10_power_state);
a23eefa2
RZ		 3259}
3260
3261
2cc0c0b5 3262static int polaris10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 3263 struct pp_power_state *request_ps,
3264 const struct pp_power_state *current_ps)
3265{
3266
2cc0c0b5
FC		 3267 struct polaris10_power_state *polaris10_ps =
3268 cast_phw_polaris10_power_state(&request_ps->hardware);
a23eefa2
RZ		 3269 uint32_t sclk;
3270 uint32_t mclk;
3271 struct PP_Clocks minimum_clocks = {0};
3272 bool disable_mclk_switching;
3273 bool disable_mclk_switching_for_frame_lock;
3274 struct cgs_display_info info = {0};
3275 const struct phm_clock_and_voltage_limits *max_limits;
3276 uint32_t i;
2cc0c0b5 3277 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 3278 struct phm_ppt_v1_information *table_info =
3279 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3280 int32_t count;
3281 int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3282
3283 data->battery_state = (PP_StateUILabel_Battery ==
3284 request_ps->classification.ui_label);
3285
2cc0c0b5 3286 PP_ASSERT_WITH_CODE(polaris10_ps->performance_level_count == 2,
a23eefa2
RZ		 3287 "VI should always have 2 performance levels",
3288 );
3289
3290 max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
3291 &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3292 &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3293
3294 /* Cap clock DPM tables at DC MAX if it is in DC. */
3295 if (PP_PowerSource_DC == hwmgr->power_source) {
2cc0c0b5
FC		 3296 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3297 if (polaris10_ps->performance_levels[i].memory_clock > max_limits->mclk)
3298 polaris10_ps->performance_levels[i].memory_clock = max_limits->mclk;
3299 if (polaris10_ps->performance_levels[i].engine_clock > max_limits->sclk)
3300 polaris10_ps->performance_levels[i].engine_clock = max_limits->sclk;
a23eefa2
RZ		 3301 }
3302 }
3303
2cc0c0b5
FC		 3304 polaris10_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
3305 polaris10_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
a23eefa2
RZ		 3306
3307 cgs_get_active_displays_info(hwmgr->device, &info);
3308
3309 /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3310
3311 /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
3312
3313 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3314 PHM_PlatformCaps_StablePState)) {
3315 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3316 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
3317
3318 for (count = table_info->vdd_dep_on_sclk->count - 1;
3319 count >= 0; count--) {
3320 if (stable_pstate_sclk >=
3321 table_info->vdd_dep_on_sclk->entries[count].clk) {
3322 stable_pstate_sclk =
3323 table_info->vdd_dep_on_sclk->entries[count].clk;
3324 break;
3325 }
3326 }
3327
3328 if (count < 0)
3329 stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3330
3331 stable_pstate_mclk = max_limits->mclk;
3332
3333 minimum_clocks.engineClock = stable_pstate_sclk;
3334 minimum_clocks.memoryClock = stable_pstate_mclk;
3335 }
3336
3337 if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
3338 minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
3339
3340 if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
3341 minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
3342
2cc0c0b5 3343 polaris10_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
a23eefa2
RZ		 3344
3345 if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
3346 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=
3347 hwmgr->platform_descriptor.overdriveLimit.engineClock),
3348 "Overdrive sclk exceeds limit",
3349 hwmgr->gfx_arbiter.sclk_over_drive =
3350 hwmgr->platform_descriptor.overdriveLimit.engineClock);
3351
3352 if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
2cc0c0b5 3353 polaris10_ps->performance_levels[1].engine_clock =
a23eefa2
RZ		 3354 hwmgr->gfx_arbiter.sclk_over_drive;
3355 }
3356
3357 if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
3358 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=
3359 hwmgr->platform_descriptor.overdriveLimit.memoryClock),
3360 "Overdrive mclk exceeds limit",
3361 hwmgr->gfx_arbiter.mclk_over_drive =
3362 hwmgr->platform_descriptor.overdriveLimit.memoryClock);
3363
3364 if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
2cc0c0b5 3365 polaris10_ps->performance_levels[1].memory_clock =
a23eefa2
RZ		 3366 hwmgr->gfx_arbiter.mclk_over_drive;
3367 }
3368
3369 disable_mclk_switching_for_frame_lock = phm_cap_enabled(
3370 hwmgr->platform_descriptor.platformCaps,
3371 PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
3372
3373 disable_mclk_switching = (1 < info.display_count) ||
3374 disable_mclk_switching_for_frame_lock;
3375
2cc0c0b5
FC		 3376 sclk = polaris10_ps->performance_levels[0].engine_clock;
3377 mclk = polaris10_ps->performance_levels[0].memory_clock;
a23eefa2
RZ		 3378
3379 if (disable_mclk_switching)
2cc0c0b5
FC		 3380 mclk = polaris10_ps->performance_levels
3381 [polaris10_ps->performance_level_count - 1].memory_clock;
a23eefa2
RZ		 3382
3383 if (sclk < minimum_clocks.engineClock)
3384 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
3385 max_limits->sclk : minimum_clocks.engineClock;
3386
3387 if (mclk < minimum_clocks.memoryClock)
3388 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
3389 max_limits->mclk : minimum_clocks.memoryClock;
3390
2cc0c0b5
FC		 3391 polaris10_ps->performance_levels[0].engine_clock = sclk;
3392 polaris10_ps->performance_levels[0].memory_clock = mclk;
a23eefa2 3393
2cc0c0b5
FC		 3394 polaris10_ps->performance_levels[1].engine_clock =
3395 (polaris10_ps->performance_levels[1].engine_clock >=
3396 polaris10_ps->performance_levels[0].engine_clock) ?
3397 polaris10_ps->performance_levels[1].engine_clock :
3398 polaris10_ps->performance_levels[0].engine_clock;
a23eefa2
RZ		 3399
3400 if (disable_mclk_switching) {
2cc0c0b5
FC		 3401 if (mclk < polaris10_ps->performance_levels[1].memory_clock)
3402 mclk = polaris10_ps->performance_levels[1].memory_clock;
a23eefa2 3403
2cc0c0b5
FC		 3404 polaris10_ps->performance_levels[0].memory_clock = mclk;
3405 polaris10_ps->performance_levels[1].memory_clock = mclk;
a23eefa2 3406 } else {
2cc0c0b5
FC		 3407 if (polaris10_ps->performance_levels[1].memory_clock <
3408 polaris10_ps->performance_levels[0].memory_clock)
3409 polaris10_ps->performance_levels[1].memory_clock =
3410 polaris10_ps->performance_levels[0].memory_clock;
a23eefa2
RZ		 3411 }
3412
3413 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3414 PHM_PlatformCaps_StablePState)) {
2cc0c0b5
FC		 3415 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3416 polaris10_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
3417 polaris10_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
3418 polaris10_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
3419 polaris10_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
a23eefa2
RZ		 3420 }
3421 }
3422 return 0;
3423}
3424
3425
2cc0c0b5 3426static int polaris10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
a23eefa2
RZ		 3427{
3428 struct pp_power_state *ps;
2cc0c0b5 3429 struct polaris10_power_state *polaris10_ps;
a23eefa2
RZ		 3430
3431 if (hwmgr == NULL)
3432 return -EINVAL;
3433
3434 ps = hwmgr->request_ps;
3435
3436 if (ps == NULL)
3437 return -EINVAL;
3438
2cc0c0b5 3439 polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
a23eefa2
RZ		 3440
3441 if (low)
2cc0c0b5 3442 return polaris10_ps->performance_levels[0].memory_clock;
a23eefa2 3443 else
2cc0c0b5
FC		 3444 return polaris10_ps->performance_levels
3445 [polaris10_ps->performance_level_count-1].memory_clock;
a23eefa2
RZ		 3446}
3447
2cc0c0b5 3448static int polaris10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
a23eefa2
RZ		 3449{
3450 struct pp_power_state *ps;
2cc0c0b5 3451 struct polaris10_power_state *polaris10_ps;
a23eefa2
RZ		 3452
3453 if (hwmgr == NULL)
3454 return -EINVAL;
3455
3456 ps = hwmgr->request_ps;
3457
3458 if (ps == NULL)
3459 return -EINVAL;
3460
2cc0c0b5 3461 polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
a23eefa2
RZ		 3462
3463 if (low)
2cc0c0b5 3464 return polaris10_ps->performance_levels[0].engine_clock;
a23eefa2 3465 else
2cc0c0b5
FC		 3466 return polaris10_ps->performance_levels
3467 [polaris10_ps->performance_level_count-1].engine_clock;
a23eefa2
RZ		 3468}
3469
2cc0c0b5 3470static int polaris10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 3471 struct pp_hw_power_state *hw_ps)
3472{
2cc0c0b5
FC		 3473 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3474 struct polaris10_power_state *ps = (struct polaris10_power_state *)hw_ps;
a23eefa2
RZ		 3475 ATOM_FIRMWARE_INFO_V2_2 *fw_info;
3476 uint16_t size;
3477 uint8_t frev, crev;
3478 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
3479
3480 /* First retrieve the Boot clocks and VDDC from the firmware info table.
3481 * We assume here that fw_info is unchanged if this call fails.
3482 */
3483 fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
3484 hwmgr->device, index,
3485 &size, &frev, &crev);
3486 if (!fw_info)
3487 /* During a test, there is no firmware info table. */
3488 return 0;
3489
3490 /* Patch the state. */
3491 data->vbios_boot_state.sclk_bootup_value =
3492 le32_to_cpu(fw_info->ulDefaultEngineClock);
3493 data->vbios_boot_state.mclk_bootup_value =
3494 le32_to_cpu(fw_info->ulDefaultMemoryClock);
3495 data->vbios_boot_state.mvdd_bootup_value =
3496 le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
3497 data->vbios_boot_state.vddc_bootup_value =
3498 le16_to_cpu(fw_info->usBootUpVDDCVoltage);
3499 data->vbios_boot_state.vddci_bootup_value =
3500 le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
3501 data->vbios_boot_state.pcie_gen_bootup_value =
3502 phm_get_current_pcie_speed(hwmgr);
3503
3504 data->vbios_boot_state.pcie_lane_bootup_value =
3505 (uint16_t)phm_get_current_pcie_lane_number(hwmgr);
3506
3507 /* set boot power state */
3508 ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
3509 ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
3510 ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
3511 ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
3512
3513 return 0;
3514}
3515
2cc0c0b5 3516static int polaris10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 3517 void *state, struct pp_power_state *power_state,
3518 void *pp_table, uint32_t classification_flag)
3519{
2cc0c0b5
FC		 3520 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3521 struct polaris10_power_state *polaris10_power_state =
3522 (struct polaris10_power_state *)(&(power_state->hardware));
3523 struct polaris10_performance_level *performance_level;
a23eefa2
RZ		 3524 ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
3525 ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
3526 (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
3ff21127
RZ		 3527 PPTable_Generic_SubTable_Header *sclk_dep_table =
3528 (PPTable_Generic_SubTable_Header *)
a23eefa2
RZ		 3529 (((unsigned long)powerplay_table) +
3530 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
3ff21127 3531
a23eefa2
RZ		 3532 ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
3533 (ATOM_Tonga_MCLK_Dependency_Table *)
3534 (((unsigned long)powerplay_table) +
3535 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3536
3537 /* The following fields are not initialized here: id orderedList allStatesList */
3538 power_state->classification.ui_label =
3539 (le16_to_cpu(state_entry->usClassification) &
3540 ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3541 ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3542 power_state->classification.flags = classification_flag;
3543 /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
3544
3545 power_state->classification.temporary_state = false;
3546 power_state->classification.to_be_deleted = false;
3547
3548 power_state->validation.disallowOnDC =
3549 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3550 ATOM_Tonga_DISALLOW_ON_DC));
3551
3552 power_state->pcie.lanes = 0;
3553
3554 power_state->display.disableFrameModulation = false;
3555 power_state->display.limitRefreshrate = false;
3556 power_state->display.enableVariBright =
3557 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3558 ATOM_Tonga_ENABLE_VARIBRIGHT));
3559
3560 power_state->validation.supportedPowerLevels = 0;
3561 power_state->uvd_clocks.VCLK = 0;
3562 power_state->uvd_clocks.DCLK = 0;
3563 power_state->temperatures.min = 0;
3564 power_state->temperatures.max = 0;
3565
2cc0c0b5
FC		 3566 performance_level = &(polaris10_power_state->performance_levels
3567 [polaris10_power_state->performance_level_count++]);
a23eefa2
RZ		 3568
3569 PP_ASSERT_WITH_CODE(
2cc0c0b5 3570 (polaris10_power_state->performance_level_count < SMU74_MAX_LEVELS_GRAPHICS),
a23eefa2
RZ		 3571 "Performance levels exceeds SMC limit!",
3572 return -1);
3573
3574 PP_ASSERT_WITH_CODE(
2cc0c0b5 3575 (polaris10_power_state->performance_level_count <=
a23eefa2
RZ		 3576 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3577 "Performance levels exceeds Driver limit!",
3578 return -1);
3579
3580 /* Performance levels are arranged from low to high. */
3581 performance_level->memory_clock = mclk_dep_table->entries
3582 [state_entry->ucMemoryClockIndexLow].ulMclk;
3ff21127
RZ		 3583 if (sclk_dep_table->ucRevId == 0)
3584 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3585 [state_entry->ucEngineClockIndexLow].ulSclk;
3586 else if (sclk_dep_table->ucRevId == 1)
3587 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
a23eefa2
RZ		 3588 [state_entry->ucEngineClockIndexLow].ulSclk;
3589 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3590 state_entry->ucPCIEGenLow);
3591 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3592 state_entry->ucPCIELaneHigh);
3593
2cc0c0b5
FC		 3594 performance_level = &(polaris10_power_state->performance_levels
3595 [polaris10_power_state->performance_level_count++]);
a23eefa2
RZ		 3596 performance_level->memory_clock = mclk_dep_table->entries
3597 [state_entry->ucMemoryClockIndexHigh].ulMclk;
3ff21127
RZ		 3598
3599 if (sclk_dep_table->ucRevId == 0)
3600 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3601 [state_entry->ucEngineClockIndexHigh].ulSclk;
3602 else if (sclk_dep_table->ucRevId == 1)
3603 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
a23eefa2 3604 [state_entry->ucEngineClockIndexHigh].ulSclk;
3ff21127 3605
a23eefa2
RZ		 3606 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3607 state_entry->ucPCIEGenHigh);
3608 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3609 state_entry->ucPCIELaneHigh);
3610
3611 return 0;
3612}
3613
2cc0c0b5 3614static int polaris10_get_pp_table_entry(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 3615 unsigned long entry_index, struct pp_power_state *state)
3616{
3617 int result;
2cc0c0b5
FC		 3618 struct polaris10_power_state *ps;
3619 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 3620 struct phm_ppt_v1_information *table_info =
3621 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3622 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
3623 table_info->vdd_dep_on_mclk;
3624
3625 state->hardware.magic = PHM_VIslands_Magic;
3626
2cc0c0b5 3627 ps = (struct polaris10_power_state *)(&state->hardware);
a23eefa2
RZ		 3628
3629 result = tonga_get_powerplay_table_entry(hwmgr, entry_index, state,
2cc0c0b5 3630 polaris10_get_pp_table_entry_callback_func);
a23eefa2
RZ		 3631
3632 /* This is the earliest time we have all the dependency table and the VBIOS boot state
3633 * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
3634 * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
3635 */
3636 if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3637 if (dep_mclk_table->entries[0].clk !=
3638 data->vbios_boot_state.mclk_bootup_value)
3639 printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
3640 "does not match VBIOS boot MCLK level");
3641 if (dep_mclk_table->entries[0].vddci !=
3642 data->vbios_boot_state.vddci_bootup_value)
3643 printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
3644 "does not match VBIOS boot VDDCI level");
3645 }
3646
3647 /* set DC compatible flag if this state supports DC */
3648 if (!state->validation.disallowOnDC)
3649 ps->dc_compatible = true;
3650
3651 if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3652 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3653
3654 ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3655 ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3656
3657 if (!result) {
3658 uint32_t i;
3659
3660 switch (state->classification.ui_label) {
3661 case PP_StateUILabel_Performance:
3662 data->use_pcie_performance_levels = true;
a23eefa2
RZ		 3663 for (i = 0; i < ps->performance_level_count; i++) {
3664 if (data->pcie_gen_performance.max <
3665 ps->performance_levels[i].pcie_gen)
3666 data->pcie_gen_performance.max =
3667 ps->performance_levels[i].pcie_gen;
3668
3669 if (data->pcie_gen_performance.min >
3670 ps->performance_levels[i].pcie_gen)
3671 data->pcie_gen_performance.min =
3672 ps->performance_levels[i].pcie_gen;
3673
3674 if (data->pcie_lane_performance.max <
3675 ps->performance_levels[i].pcie_lane)
3676 data->pcie_lane_performance.max =
3677 ps->performance_levels[i].pcie_lane;
a23eefa2
RZ		 3678 if (data->pcie_lane_performance.min >
3679 ps->performance_levels[i].pcie_lane)
3680 data->pcie_lane_performance.min =
3681 ps->performance_levels[i].pcie_lane;
3682 }
3683 break;
3684 case PP_StateUILabel_Battery:
3685 data->use_pcie_power_saving_levels = true;
3686
3687 for (i = 0; i < ps->performance_level_count; i++) {
3688 if (data->pcie_gen_power_saving.max <
3689 ps->performance_levels[i].pcie_gen)
3690 data->pcie_gen_power_saving.max =
3691 ps->performance_levels[i].pcie_gen;
3692
3693 if (data->pcie_gen_power_saving.min >
3694 ps->performance_levels[i].pcie_gen)
3695 data->pcie_gen_power_saving.min =
3696 ps->performance_levels[i].pcie_gen;
3697
3698 if (data->pcie_lane_power_saving.max <
3699 ps->performance_levels[i].pcie_lane)
3700 data->pcie_lane_power_saving.max =
3701 ps->performance_levels[i].pcie_lane;
3702
3703 if (data->pcie_lane_power_saving.min >
3704 ps->performance_levels[i].pcie_lane)
3705 data->pcie_lane_power_saving.min =
3706 ps->performance_levels[i].pcie_lane;
3707 }
3708 break;
3709 default:
3710 break;
3711 }
3712 }
3713 return 0;
3714}
3715
3716static void
2cc0c0b5 3717polaris10_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
a23eefa2 3718{
b2d96143
RZ		 3719 uint32_t sclk, mclk, activity_percent;
3720 uint32_t offset;
3721 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 3722
3723 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
3724
3725 sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3726
3727 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
3728
3729 mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3730 seq_printf(m, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n",
3731 mclk / 100, sclk / 100);
b2d96143
RZ		 3732
3733 offset = data->soft_regs_start + offsetof(SMU74_SoftRegisters, AverageGraphicsActivity);
3734 activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
3735 activity_percent += 0x80;
3736 activity_percent >>= 8;
3737
3738 seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
3739
3740 seq_printf(m, "uvd %sabled\n", data->uvd_power_gated ? "dis" : "en");
3741
3742 seq_printf(m, "vce %sabled\n", data->vce_power_gated ? "dis" : "en");
a23eefa2
RZ		 3743}
3744
2cc0c0b5 3745static int polaris10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
a23eefa2
RZ		 3746{
3747 const struct phm_set_power_state_input *states =
3748 (const struct phm_set_power_state_input *)input;
2cc0c0b5
FC		 3749 const struct polaris10_power_state *polaris10_ps =
3750 cast_const_phw_polaris10_power_state(states->pnew_state);
3751 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3752 struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
3753 uint32_t sclk = polaris10_ps->performance_levels
3754 [polaris10_ps->performance_level_count - 1].engine_clock;
3755 struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
3756 uint32_t mclk = polaris10_ps->performance_levels
3757 [polaris10_ps->performance_level_count - 1].memory_clock;
a23eefa2
RZ		 3758 struct PP_Clocks min_clocks = {0};
3759 uint32_t i;
3760 struct cgs_display_info info = {0};
3761
3762 data->need_update_smu7_dpm_table = 0;
3763
3764 for (i = 0; i < sclk_table->count; i++) {
3765 if (sclk == sclk_table->dpm_levels[i].value)
3766 break;
3767 }
3768
3769 if (i >= sclk_table->count)
3770 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3771 else {
3772 /* TODO: Check SCLK in DAL's minimum clocks
3773 * in case DeepSleep divider update is required.
3774 */
2cc0c0b5
FC		 3775 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR &&
3776 (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
3777 data->display_timing.min_clock_in_sr >= POLARIS10_MINIMUM_ENGINE_CLOCK))
a23eefa2
RZ		 3778 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3779 }
3780
3781 for (i = 0; i < mclk_table->count; i++) {
3782 if (mclk == mclk_table->dpm_levels[i].value)
3783 break;
3784 }
3785
3786 if (i >= mclk_table->count)
3787 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3788
3789 cgs_get_active_displays_info(hwmgr->device, &info);
3790
3791 if (data->display_timing.num_existing_displays != info.display_count)
3792 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3793
3794 return 0;
3795}
3796
2cc0c0b5
FC		 3797static uint16_t polaris10_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
3798 const struct polaris10_power_state *polaris10_ps)
a23eefa2
RZ		 3799{
3800 uint32_t i;
3801 uint32_t sclk, max_sclk = 0;
2cc0c0b5
FC		 3802 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3803 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
a23eefa2 3804
2cc0c0b5
FC		 3805 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3806 sclk = polaris10_ps->performance_levels[i].engine_clock;
a23eefa2
RZ		 3807 if (max_sclk < sclk)
3808 max_sclk = sclk;
3809 }
3810
3811 for (i = 0; i < dpm_table->sclk_table.count; i++) {
3812 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
3813 return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
3814 dpm_table->pcie_speed_table.dpm_levels
3815 [dpm_table->pcie_speed_table.count - 1].value :
3816 dpm_table->pcie_speed_table.dpm_levels[i].value);
3817 }
3818
3819 return 0;
3820}
3821
2cc0c0b5 3822static int polaris10_request_link_speed_change_before_state_change(
a23eefa2
RZ		 3823 struct pp_hwmgr *hwmgr, const void *input)
3824{
3825 const struct phm_set_power_state_input *states =
3826 (const struct phm_set_power_state_input *)input;
2cc0c0b5
FC		 3827 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3828 const struct polaris10_power_state *polaris10_nps =
3829 cast_const_phw_polaris10_power_state(states->pnew_state);
3830 const struct polaris10_power_state *polaris10_cps =
3831 cast_const_phw_polaris10_power_state(states->pcurrent_state);
a23eefa2 3832
2cc0c0b5 3833 uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_nps);
a23eefa2
RZ		 3834 uint16_t current_link_speed;
3835
3836 if (data->force_pcie_gen == PP_PCIEGenInvalid)
2cc0c0b5 3837 current_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_cps);
a23eefa2
RZ		 3838 else
3839 current_link_speed = data->force_pcie_gen;
3840
3841 data->force_pcie_gen = PP_PCIEGenInvalid;
3842 data->pspp_notify_required = false;
3843
3844 if (target_link_speed > current_link_speed) {
3845 switch (target_link_speed) {
3846 case PP_PCIEGen3:
3847 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
3848 break;
3849 data->force_pcie_gen = PP_PCIEGen2;
3850 if (current_link_speed == PP_PCIEGen2)
3851 break;
3852 case PP_PCIEGen2:
3853 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
3854 break;
3855 default:
3856 data->force_pcie_gen = phm_get_current_pcie_speed(hwmgr);
3857 break;
3858 }
3859 } else {
3860 if (target_link_speed < current_link_speed)
3861 data->pspp_notify_required = true;
3862 }
3863
3864 return 0;
3865}
3866
2cc0c0b5 3867static int polaris10_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
a23eefa2 3868{
2cc0c0b5 3869 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 3870
3871 if (0 == data->need_update_smu7_dpm_table)
3872 return 0;
3873
3874 if ((0 == data->sclk_dpm_key_disabled) &&
3875 (data->need_update_smu7_dpm_table &
3876 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
2cc0c0b5 3877 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
a23eefa2
RZ		 3878 "Trying to freeze SCLK DPM when DPM is disabled",
3879 );
3880 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
3881 PPSMC_MSG_SCLKDPM_FreezeLevel),
3882 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
3883 return -1);
3884 }
3885
3886 if ((0 == data->mclk_dpm_key_disabled) &&
3887 (data->need_update_smu7_dpm_table &
3888 DPMTABLE_OD_UPDATE_MCLK)) {
2cc0c0b5 3889 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
a23eefa2
RZ		 3890 "Trying to freeze MCLK DPM when DPM is disabled",
3891 );
3892 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
3893 PPSMC_MSG_MCLKDPM_FreezeLevel),
3894 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
3895 return -1);
3896 }
3897
3898 return 0;
3899}
3900
2cc0c0b5 3901static int polaris10_populate_and_upload_sclk_mclk_dpm_levels(
a23eefa2
RZ		 3902 struct pp_hwmgr *hwmgr, const void *input)
3903{
3904 int result = 0;
3905 const struct phm_set_power_state_input *states =
3906 (const struct phm_set_power_state_input *)input;
2cc0c0b5
FC		 3907 const struct polaris10_power_state *polaris10_ps =
3908 cast_const_phw_polaris10_power_state(states->pnew_state);
3909 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3910 uint32_t sclk = polaris10_ps->performance_levels
3911 [polaris10_ps->performance_level_count - 1].engine_clock;
3912 uint32_t mclk = polaris10_ps->performance_levels
3913 [polaris10_ps->performance_level_count - 1].memory_clock;
3914 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
3915
3916 struct polaris10_dpm_table *golden_dpm_table = &data->golden_dpm_table;
a23eefa2
RZ		 3917 uint32_t dpm_count, clock_percent;
3918 uint32_t i;
3919
3920 if (0 == data->need_update_smu7_dpm_table)
3921 return 0;
3922
3923 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
3924 dpm_table->sclk_table.dpm_levels
3925 [dpm_table->sclk_table.count - 1].value = sclk;
3926
3927 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
3928 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
3929 /* Need to do calculation based on the golden DPM table
3930 * as the Heatmap GPU Clock axis is also based on the default values
3931 */
3932 PP_ASSERT_WITH_CODE(
3933 (golden_dpm_table->sclk_table.dpm_levels
3934 [golden_dpm_table->sclk_table.count - 1].value != 0),
3935 "Divide by 0!",
3936 return -1);
3937 dpm_count = dpm_table->sclk_table.count < 2 ? 0 : dpm_table->sclk_table.count - 2;
3938
3939 for (i = dpm_count; i > 1; i--) {
3940 if (sclk > golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value) {
3941 clock_percent =
3942 ((sclk
3943 - golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value
3944 ) * 100)
3945 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
3946
3947 dpm_table->sclk_table.dpm_levels[i].value =
3948 golden_dpm_table->sclk_table.dpm_levels[i].value +
3949 (golden_dpm_table->sclk_table.dpm_levels[i].value *
3950 clock_percent)/100;
3951
3952 } else if (golden_dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value > sclk) {
3953 clock_percent =
3954 ((golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value
3955 - sclk) * 100)
3956 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
3957
3958 dpm_table->sclk_table.dpm_levels[i].value =
3959 golden_dpm_table->sclk_table.dpm_levels[i].value -
3960 (golden_dpm_table->sclk_table.dpm_levels[i].value *
3961 clock_percent) / 100;
3962 } else
3963 dpm_table->sclk_table.dpm_levels[i].value =
3964 golden_dpm_table->sclk_table.dpm_levels[i].value;
3965 }
3966 }
3967 }
3968
3969 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
3970 dpm_table->mclk_table.dpm_levels
3971 [dpm_table->mclk_table.count - 1].value = mclk;
3972
3973 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
3974 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
3975
3976 PP_ASSERT_WITH_CODE(
3977 (golden_dpm_table->mclk_table.dpm_levels
3978 [golden_dpm_table->mclk_table.count-1].value != 0),
3979 "Divide by 0!",
3980 return -1);
3981 dpm_count = dpm_table->mclk_table.count < 2 ? 0 : dpm_table->mclk_table.count - 2;
3982 for (i = dpm_count; i > 1; i--) {
3983 if (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value < mclk) {
3984 clock_percent = ((mclk -
3985 golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value) * 100)
3986 / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
3987
3988 dpm_table->mclk_table.dpm_levels[i].value =
3989 golden_dpm_table->mclk_table.dpm_levels[i].value +
3990 (golden_dpm_table->mclk_table.dpm_levels[i].value *
3991 clock_percent) / 100;
3992
3993 } else if (golden_dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value > mclk) {
3994 clock_percent = (
3995 (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value - mclk)
3996 * 100)
3997 / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
3998
3999 dpm_table->mclk_table.dpm_levels[i].value =
4000 golden_dpm_table->mclk_table.dpm_levels[i].value -
4001 (golden_dpm_table->mclk_table.dpm_levels[i].value *
4002 clock_percent) / 100;
4003 } else
4004 dpm_table->mclk_table.dpm_levels[i].value =
4005 golden_dpm_table->mclk_table.dpm_levels[i].value;
4006 }
4007 }
4008 }
4009
4010 if (data->need_update_smu7_dpm_table &
4011 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
2cc0c0b5 4012 result = polaris10_populate_all_graphic_levels(hwmgr);
a23eefa2
RZ		 4013 PP_ASSERT_WITH_CODE((0 == result),
4014 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
4015 return result);
4016 }
4017
4018 if (data->need_update_smu7_dpm_table &
4019 (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
4020 /*populate MCLK dpm table to SMU7 */
2cc0c0b5 4021 result = polaris10_populate_all_memory_levels(hwmgr);
a23eefa2
RZ		 4022 PP_ASSERT_WITH_CODE((0 == result),
4023 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
4024 return result);
4025 }
4026
4027 return result;
4028}
4029
2cc0c0b5
FC		 4030static int polaris10_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
4031 struct polaris10_single_dpm_table *dpm_table,
a23eefa2
RZ		 4032 uint32_t low_limit, uint32_t high_limit)
4033{
4034 uint32_t i;
a23eefa2
RZ		 4035
4036 for (i = 0; i < dpm_table->count; i++) {
4037 if ((dpm_table->dpm_levels[i].value < low_limit)
4038 || (dpm_table->dpm_levels[i].value > high_limit))
4039 dpm_table->dpm_levels[i].enabled = false;
a23eefa2
RZ		 4040 else
4041 dpm_table->dpm_levels[i].enabled = true;
4042 }
4043
4044 return 0;
4045}
4046
2cc0c0b5
FC		 4047static int polaris10_trim_dpm_states(struct pp_hwmgr *hwmgr,
4048 const struct polaris10_power_state *polaris10_ps)
a23eefa2
RZ		 4049{
4050 int result = 0;
2cc0c0b5 4051 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4052 uint32_t high_limit_count;
4053
2cc0c0b5 4054 PP_ASSERT_WITH_CODE((polaris10_ps->performance_level_count >= 1),
a23eefa2
RZ		 4055 "power state did not have any performance level",
4056 return -1);
4057
2cc0c0b5 4058 high_limit_count = (1 == polaris10_ps->performance_level_count) ? 0 : 1;
a23eefa2 4059
2cc0c0b5 4060 polaris10_trim_single_dpm_states(hwmgr,
a23eefa2 4061 &(data->dpm_table.sclk_table),
2cc0c0b5
FC		 4062 polaris10_ps->performance_levels[0].engine_clock,
4063 polaris10_ps->performance_levels[high_limit_count].engine_clock);
a23eefa2 4064
2cc0c0b5 4065 polaris10_trim_single_dpm_states(hwmgr,
a23eefa2 4066 &(data->dpm_table.mclk_table),
2cc0c0b5
FC		 4067 polaris10_ps->performance_levels[0].memory_clock,
4068 polaris10_ps->performance_levels[high_limit_count].memory_clock);
a23eefa2
RZ		 4069
4070 return result;
4071}
4072
2cc0c0b5 4073static int polaris10_generate_dpm_level_enable_mask(
a23eefa2
RZ		 4074 struct pp_hwmgr *hwmgr, const void *input)
4075{
4076 int result;
4077 const struct phm_set_power_state_input *states =
4078 (const struct phm_set_power_state_input *)input;
2cc0c0b5
FC		 4079 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4080 const struct polaris10_power_state *polaris10_ps =
4081 cast_const_phw_polaris10_power_state(states->pnew_state);
a23eefa2 4082
2cc0c0b5 4083 result = polaris10_trim_dpm_states(hwmgr, polaris10_ps);
a23eefa2
RZ		 4084 if (result)
4085 return result;
4086
4087 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
4088 phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
4089 data->dpm_level_enable_mask.mclk_dpm_enable_mask =
4090 phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
4091 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
4092 phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
4093
4094 return 0;
4095}
4096
2cc0c0b5 4097int polaris10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
a23eefa2
RZ		 4098{
4099 return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
92c6d645
EH		 4100 PPSMC_MSG_UVDDPM_Enable :
4101 PPSMC_MSG_UVDDPM_Disable);
4102}
4103
2cc0c0b5 4104int polaris10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
92c6d645
EH		 4105{
4106 return smum_send_msg_to_smc(hwmgr->smumgr, enable?
a23eefa2
RZ		 4107 PPSMC_MSG_VCEDPM_Enable :
4108 PPSMC_MSG_VCEDPM_Disable);
4109}
4110
2cc0c0b5 4111int polaris10_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
92c6d645
EH		 4112{
4113 return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4114 PPSMC_MSG_SAMUDPM_Enable :
4115 PPSMC_MSG_SAMUDPM_Disable);
4116}
4117
2cc0c0b5 4118int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
92c6d645 4119{
2cc0c0b5 4120 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
92c6d645
EH		 4121 uint32_t mm_boot_level_offset, mm_boot_level_value;
4122 struct phm_ppt_v1_information *table_info =
4123 (struct phm_ppt_v1_information *)(hwmgr->pptable);
4124
4125 if (!bgate) {
4126 data->smc_state_table.UvdBootLevel = 0;
4127 if (table_info->mm_dep_table->count > 0)
4128 data->smc_state_table.UvdBootLevel =
4129 (uint8_t) (table_info->mm_dep_table->count - 1);
4130 mm_boot_level_offset = data->dpm_table_start +
4131 offsetof(SMU74_Discrete_DpmTable, UvdBootLevel);
4132 mm_boot_level_offset /= 4;
4133 mm_boot_level_offset *= 4;
4134 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4135 CGS_IND_REG__SMC, mm_boot_level_offset);
4136 mm_boot_level_value &= 0x00FFFFFF;
4137 mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24;
4138 cgs_write_ind_register(hwmgr->device,
4139 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4140
4141 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4142 PHM_PlatformCaps_UVDDPM) ||
4143 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4144 PHM_PlatformCaps_StablePState))
4145 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4146 PPSMC_MSG_UVDDPM_SetEnabledMask,
4147 (uint32_t)(1 << data->smc_state_table.UvdBootLevel));
4148 }
4149
2cc0c0b5 4150 return polaris10_enable_disable_uvd_dpm(hwmgr, !bgate);
92c6d645
EH		 4151}
4152
2cc0c0b5 4153static int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
a23eefa2
RZ		 4154{
4155 const struct phm_set_power_state_input *states =
4156 (const struct phm_set_power_state_input *)input;
2cc0c0b5
FC		 4157 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4158 const struct polaris10_power_state *polaris10_nps =
4159 cast_const_phw_polaris10_power_state(states->pnew_state);
4160 const struct polaris10_power_state *polaris10_cps =
4161 cast_const_phw_polaris10_power_state(states->pcurrent_state);
a23eefa2
RZ		 4162
4163 uint32_t mm_boot_level_offset, mm_boot_level_value;
4164 struct phm_ppt_v1_information *table_info =
4165 (struct phm_ppt_v1_information *)(hwmgr->pptable);
4166
2cc0c0b5
FC		 4167 if (polaris10_nps->vce_clks.evclk > 0 &&
4168 (polaris10_cps == NULL || polaris10_cps->vce_clks.evclk == 0)) {
a23eefa2
RZ		 4169
4170 data->smc_state_table.VceBootLevel =
4171 (uint8_t) (table_info->mm_dep_table->count - 1);
4172
4173 mm_boot_level_offset = data->dpm_table_start +
4174 offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
4175 mm_boot_level_offset /= 4;
4176 mm_boot_level_offset *= 4;
4177 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4178 CGS_IND_REG__SMC, mm_boot_level_offset);
4179 mm_boot_level_value &= 0xFF00FFFF;
4180 mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
4181 cgs_write_ind_register(hwmgr->device,
4182 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4183
4184 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
4185 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4186 PPSMC_MSG_VCEDPM_SetEnabledMask,
4187 (uint32_t)1 << data->smc_state_table.VceBootLevel);
4188
2cc0c0b5
FC		 4189 polaris10_enable_disable_vce_dpm(hwmgr, true);
4190 } else if (polaris10_nps->vce_clks.evclk == 0 &&
4191 polaris10_cps != NULL &&
4192 polaris10_cps->vce_clks.evclk > 0)
4193 polaris10_enable_disable_vce_dpm(hwmgr, false);
a23eefa2
RZ		 4194 }
4195
4196 return 0;
4197}
4198
2cc0c0b5 4199int polaris10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
92c6d645 4200{
2cc0c0b5 4201 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
92c6d645 4202 uint32_t mm_boot_level_offset, mm_boot_level_value;
92c6d645
EH		 4203
4204 if (!bgate) {
871fd840 4205 data->smc_state_table.SamuBootLevel = 0;
92c6d645
EH		 4206 mm_boot_level_offset = data->dpm_table_start +
4207 offsetof(SMU74_Discrete_DpmTable, SamuBootLevel);
4208 mm_boot_level_offset /= 4;
4209 mm_boot_level_offset *= 4;
4210 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4211 CGS_IND_REG__SMC, mm_boot_level_offset);
4212 mm_boot_level_value &= 0xFFFFFF00;
4213 mm_boot_level_value |= data->smc_state_table.SamuBootLevel << 0;
4214 cgs_write_ind_register(hwmgr->device,
4215 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4216
4217 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4218 PHM_PlatformCaps_StablePState))
4219 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4220 PPSMC_MSG_SAMUDPM_SetEnabledMask,
4221 (uint32_t)(1 << data->smc_state_table.SamuBootLevel));
4222 }
4223
2cc0c0b5 4224 return polaris10_enable_disable_samu_dpm(hwmgr, !bgate);
92c6d645
EH		 4225}
4226
2cc0c0b5 4227static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
a23eefa2 4228{
2cc0c0b5 4229 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4230
4231 int result = 0;
4232 uint32_t low_sclk_interrupt_threshold = 0;
4233
4234 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4235 PHM_PlatformCaps_SclkThrottleLowNotification)
4236 && (hwmgr->gfx_arbiter.sclk_threshold !=
4237 data->low_sclk_interrupt_threshold)) {
4238 data->low_sclk_interrupt_threshold =
4239 hwmgr->gfx_arbiter.sclk_threshold;
4240 low_sclk_interrupt_threshold =
4241 data->low_sclk_interrupt_threshold;
4242
4243 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
4244
2cc0c0b5 4245 result = polaris10_copy_bytes_to_smc(
a23eefa2
RZ		 4246 hwmgr->smumgr,
4247 data->dpm_table_start +
4248 offsetof(SMU74_Discrete_DpmTable,
4249 LowSclkInterruptThreshold),
4250 (uint8_t *)&low_sclk_interrupt_threshold,
4251 sizeof(uint32_t),
4252 data->sram_end);
4253 }
4254
4255 return result;
4256}
4257
2cc0c0b5 4258static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
a23eefa2 4259{
2cc0c0b5 4260 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4261
4262 if (data->need_update_smu7_dpm_table &
4263 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
2cc0c0b5 4264 return polaris10_program_memory_timing_parameters(hwmgr);
a23eefa2
RZ		 4265
4266 return 0;
4267}
4268
2cc0c0b5 4269static int polaris10_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
a23eefa2 4270{
2cc0c0b5 4271 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4272
4273 if (0 == data->need_update_smu7_dpm_table)
4274 return 0;
4275
4276 if ((0 == data->sclk_dpm_key_disabled) &&
4277 (data->need_update_smu7_dpm_table &
4278 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4279
2cc0c0b5 4280 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
a23eefa2
RZ		 4281 "Trying to Unfreeze SCLK DPM when DPM is disabled",
4282 );
4283 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4284 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4285 "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
4286 return -1);
4287 }
4288
4289 if ((0 == data->mclk_dpm_key_disabled) &&
4290 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
4291
2cc0c0b5 4292 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
a23eefa2
RZ		 4293 "Trying to Unfreeze MCLK DPM when DPM is disabled",
4294 );
4295 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4296 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4297 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
4298 return -1);
4299 }
4300
4301 data->need_update_smu7_dpm_table = 0;
4302
4303 return 0;
4304}
4305
2cc0c0b5 4306static int polaris10_notify_link_speed_change_after_state_change(
a23eefa2
RZ		 4307 struct pp_hwmgr *hwmgr, const void *input)
4308{
4309 const struct phm_set_power_state_input *states =
4310 (const struct phm_set_power_state_input *)input;
2cc0c0b5
FC		 4311 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4312 const struct polaris10_power_state *polaris10_ps =
4313 cast_const_phw_polaris10_power_state(states->pnew_state);
4314 uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_ps);
a23eefa2
RZ		 4315 uint8_t request;
4316
4317 if (data->pspp_notify_required) {
4318 if (target_link_speed == PP_PCIEGen3)
4319 request = PCIE_PERF_REQ_GEN3;
4320 else if (target_link_speed == PP_PCIEGen2)
4321 request = PCIE_PERF_REQ_GEN2;
4322 else
4323 request = PCIE_PERF_REQ_GEN1;
4324
4325 if (request == PCIE_PERF_REQ_GEN1 &&
4326 phm_get_current_pcie_speed(hwmgr) > 0)
4327 return 0;
4328
4329 if (acpi_pcie_perf_request(hwmgr->device, request, false)) {
4330 if (PP_PCIEGen2 == target_link_speed)
4331 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
4332 else
4333 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
4334 }
4335 }
4336
4337 return 0;
4338}
4339
2cc0c0b5 4340static int polaris10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
a23eefa2
RZ		 4341{
4342 int tmp_result, result = 0;
2cc0c0b5 4343 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2 4344
2cc0c0b5 4345 tmp_result = polaris10_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
a23eefa2
RZ		 4346 PP_ASSERT_WITH_CODE((0 == tmp_result),
4347 "Failed to find DPM states clocks in DPM table!",
4348 result = tmp_result);
4349
4350 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4351 PHM_PlatformCaps_PCIEPerformanceRequest)) {
4352 tmp_result =
2cc0c0b5 4353 polaris10_request_link_speed_change_before_state_change(hwmgr, input);
a23eefa2
RZ		 4354 PP_ASSERT_WITH_CODE((0 == tmp_result),
4355 "Failed to request link speed change before state change!",
4356 result = tmp_result);
4357 }
4358
2cc0c0b5 4359 tmp_result = polaris10_freeze_sclk_mclk_dpm(hwmgr);
a23eefa2
RZ		 4360 PP_ASSERT_WITH_CODE((0 == tmp_result),
4361 "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
4362
2cc0c0b5 4363 tmp_result = polaris10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
a23eefa2
RZ		 4364 PP_ASSERT_WITH_CODE((0 == tmp_result),
4365 "Failed to populate and upload SCLK MCLK DPM levels!",
4366 result = tmp_result);
4367
2cc0c0b5 4368 tmp_result = polaris10_generate_dpm_level_enable_mask(hwmgr, input);
a23eefa2
RZ		 4369 PP_ASSERT_WITH_CODE((0 == tmp_result),
4370 "Failed to generate DPM level enabled mask!",
4371 result = tmp_result);
4372
2cc0c0b5 4373 tmp_result = polaris10_update_vce_dpm(hwmgr, input);
a23eefa2
RZ		 4374 PP_ASSERT_WITH_CODE((0 == tmp_result),
4375 "Failed to update VCE DPM!",
4376 result = tmp_result);
4377
2cc0c0b5 4378 tmp_result = polaris10_update_sclk_threshold(hwmgr);
a23eefa2
RZ		 4379 PP_ASSERT_WITH_CODE((0 == tmp_result),
4380 "Failed to update SCLK threshold!",
4381 result = tmp_result);
4382
2cc0c0b5 4383 tmp_result = polaris10_program_mem_timing_parameters(hwmgr);
a23eefa2
RZ		 4384 PP_ASSERT_WITH_CODE((0 == tmp_result),
4385 "Failed to program memory timing parameters!",
4386 result = tmp_result);
4387
2cc0c0b5 4388 tmp_result = polaris10_unfreeze_sclk_mclk_dpm(hwmgr);
a23eefa2
RZ		 4389 PP_ASSERT_WITH_CODE((0 == tmp_result),
4390 "Failed to unfreeze SCLK MCLK DPM!",
4391 result = tmp_result);
4392
2cc0c0b5 4393 tmp_result = polaris10_upload_dpm_level_enable_mask(hwmgr);
a23eefa2
RZ		 4394 PP_ASSERT_WITH_CODE((0 == tmp_result),
4395 "Failed to upload DPM level enabled mask!",
4396 result = tmp_result);
4397
4398 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4399 PHM_PlatformCaps_PCIEPerformanceRequest)) {
4400 tmp_result =
2cc0c0b5 4401 polaris10_notify_link_speed_change_after_state_change(hwmgr, input);
a23eefa2
RZ		 4402 PP_ASSERT_WITH_CODE((0 == tmp_result),
4403 "Failed to notify link speed change after state change!",
4404 result = tmp_result);
4405 }
4406 data->apply_optimized_settings = false;
4407 return result;
4408}
4409
2cc0c0b5 4410static int polaris10_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
a23eefa2 4411{
eede5262
EH		 4412 hwmgr->thermal_controller.
4413 advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
a23eefa2 4414
eede5262 4415 if (phm_is_hw_access_blocked(hwmgr))
a23eefa2 4416 return 0;
eede5262
EH		 4417
4418 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4419 PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
a23eefa2
RZ		 4420}
4421
2cc0c0b5 4422int polaris10_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
a23eefa2
RZ		 4423{
4424 PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
4425
4426 return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ? 0 : -1;
4427}
4428
2cc0c0b5 4429int polaris10_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 4430{
4431 uint32_t num_active_displays = 0;
4432 struct cgs_display_info info = {0};
4433 info.mode_info = NULL;
4434
4435 cgs_get_active_displays_info(hwmgr->device, &info);
4436
4437 num_active_displays = info.display_count;
4438
4439 if (num_active_displays > 1) /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */
2cc0c0b5 4440 polaris10_notify_smc_display_change(hwmgr, false);
a23eefa2 4441 else
2cc0c0b5 4442 polaris10_notify_smc_display_change(hwmgr, true);
a23eefa2
RZ		 4443
4444 return 0;
4445}
4446
4447/**
4448* Programs the display gap
4449*
4450* @param hwmgr the address of the powerplay hardware manager.
4451* @return always OK
4452*/
2cc0c0b5 4453int polaris10_program_display_gap(struct pp_hwmgr *hwmgr)
a23eefa2 4454{
2cc0c0b5 4455 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4456 uint32_t num_active_displays = 0;
4457 uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
4458 uint32_t display_gap2;
4459 uint32_t pre_vbi_time_in_us;
4460 uint32_t frame_time_in_us;
4461 uint32_t ref_clock;
4462 uint32_t refresh_rate = 0;
4463 struct cgs_display_info info = {0};
4464 struct cgs_mode_info mode_info;
4465
4466 info.mode_info = &mode_info;
4467
4468 cgs_get_active_displays_info(hwmgr->device, &info);
4469 num_active_displays = info.display_count;
4470
4471 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
4472 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
4473
4474 ref_clock = mode_info.ref_clock;
4475 refresh_rate = mode_info.refresh_rate;
4476
4477 if (0 == refresh_rate)
4478 refresh_rate = 60;
4479
4480 frame_time_in_us = 1000000 / refresh_rate;
4481
4482 pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
4483 display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
4484
4485 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
4486
4487 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, PreVBlankGap), 0x64);
4488
4489 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
4490
2cc0c0b5 4491 polaris10_notify_smc_display_change(hwmgr, num_active_displays != 0);
a23eefa2
RZ		 4492
4493 return 0;
4494}
4495
4496
2cc0c0b5 4497int polaris10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
a23eefa2 4498{
2cc0c0b5 4499 return polaris10_program_display_gap(hwmgr);
a23eefa2
RZ		 4500}
4501
4502/**
4503* Set maximum target operating fan output RPM
4504*
4505* @param hwmgr: the address of the powerplay hardware manager.
4506* @param usMaxFanRpm: max operating fan RPM value.
4507* @return The response that came from the SMC.
4508*/
2cc0c0b5 4509static int polaris10_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm)
a23eefa2 4510{
eede5262
EH		 4511 hwmgr->thermal_controller.
4512 advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
4513
4514 if (phm_is_hw_access_blocked(hwmgr))
4515 return 0;
4516
4517 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4518 PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
a23eefa2
RZ		 4519}
4520
2cc0c0b5 4521int polaris10_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 4522 const void *thermal_interrupt_info)
4523{
4524 return 0;
4525}
4526
2cc0c0b5 4527bool polaris10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
a23eefa2 4528{
2cc0c0b5 4529 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4530 bool is_update_required = false;
4531 struct cgs_display_info info = {0, 0, NULL};
4532
4533 cgs_get_active_displays_info(hwmgr->device, &info);
4534
4535 if (data->display_timing.num_existing_displays != info.display_count)
4536 is_update_required = true;
4537/* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
4538 if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
4539 cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
2cc0c0b5
FC		 4540 if (min_clocks.engineClockInSR != data->display_timing.minClockInSR &&
4541 (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
4542 data->display_timing.minClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK))
a23eefa2
RZ		 4543 is_update_required = true;
4544*/
4545 return is_update_required;
4546}
4547
2cc0c0b5
FC		 4548static inline bool polaris10_are_power_levels_equal(const struct polaris10_performance_level *pl1,
4549 const struct polaris10_performance_level *pl2)
a23eefa2
RZ		 4550{
4551 return ((pl1->memory_clock == pl2->memory_clock) &&
4552 (pl1->engine_clock == pl2->engine_clock) &&
4553 (pl1->pcie_gen == pl2->pcie_gen) &&
4554 (pl1->pcie_lane == pl2->pcie_lane));
4555}
4556
2cc0c0b5 4557int polaris10_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
a23eefa2 4558{
2cc0c0b5
FC		 4559 const struct polaris10_power_state *psa = cast_const_phw_polaris10_power_state(pstate1);
4560 const struct polaris10_power_state *psb = cast_const_phw_polaris10_power_state(pstate2);
a23eefa2
RZ		 4561 int i;
4562
4563 if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
4564 return -EINVAL;
4565
4566 /* If the two states don't even have the same number of performance levels they cannot be the same state. */
4567 if (psa->performance_level_count != psb->performance_level_count) {
4568 *equal = false;
4569 return 0;
4570 }
4571
4572 for (i = 0; i < psa->performance_level_count; i++) {
2cc0c0b5 4573 if (!polaris10_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
a23eefa2
RZ		 4574 /* If we have found even one performance level pair that is different the states are different. */
4575 *equal = false;
4576 return 0;
4577 }
4578 }
4579
4580 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
4581 *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
4582 *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
4583 *equal &= (psa->sclk_threshold == psb->sclk_threshold);
4584
4585 return 0;
4586}
4587
2cc0c0b5 4588int polaris10_upload_mc_firmware(struct pp_hwmgr *hwmgr)
a23eefa2 4589{
2cc0c0b5 4590 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4591
4592 uint32_t vbios_version;
4593
4594 /* Read MC indirect register offset 0x9F bits [3:0] to see if VBIOS has already loaded a full version of MC ucode or not.*/
4595
4596 phm_get_mc_microcode_version(hwmgr);
4597 vbios_version = hwmgr->microcode_version_info.MC & 0xf;
4598 /* Full version of MC ucode has already been loaded. */
4599 if (vbios_version == 0) {
4600 data->need_long_memory_training = false;
4601 return 0;
4602 }
4603
4604 data->need_long_memory_training = true;
4605
4606/*
edf600da 4607 * PPMCME_FirmwareDescriptorEntry *pfd = NULL;
a23eefa2
RZ		 4608 pfd = &tonga_mcmeFirmware;
4609 if (0 == PHM_READ_FIELD(hwmgr->device, MC_SEQ_SUP_CNTL, RUN))
2cc0c0b5 4610 polaris10_load_mc_microcode(hwmgr, pfd->dpmThreshold,
a23eefa2
RZ		 4611 pfd->cfgArray, pfd->cfgSize, pfd->ioDebugArray,
4612 pfd->ioDebugSize, pfd->ucodeArray, pfd->ucodeSize);
4613*/
4614 return 0;
4615}
4616
4617/**
4618 * Read clock related registers.
4619 *
4620 * @param hwmgr the address of the powerplay hardware manager.
4621 * @return always 0
4622 */
2cc0c0b5 4623static int polaris10_read_clock_registers(struct pp_hwmgr *hwmgr)
a23eefa2 4624{
2cc0c0b5 4625 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4626
4627 data->clock_registers.vCG_SPLL_FUNC_CNTL = cgs_read_ind_register(hwmgr->device,
4628 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL)
4629 & CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK;
4630
4631 data->clock_registers.vCG_SPLL_FUNC_CNTL_2 = cgs_read_ind_register(hwmgr->device,
4632 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2)
4633 & CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
4634
4635 data->clock_registers.vCG_SPLL_FUNC_CNTL_4 = cgs_read_ind_register(hwmgr->device,
4636 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4)
4637 & CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK;
4638
4639 return 0;
4640}
4641
4642/**
4643 * Find out if memory is GDDR5.
4644 *
4645 * @param hwmgr the address of the powerplay hardware manager.
4646 * @return always 0
4647 */
2cc0c0b5 4648static int polaris10_get_memory_type(struct pp_hwmgr *hwmgr)
a23eefa2 4649{
2cc0c0b5 4650 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4651 uint32_t temp;
4652
4653 temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
4654
4655 data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
4656 ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
4657 MC_SEQ_MISC0_GDDR5_SHIFT));
4658
4659 return 0;
4660}
4661
4662/**
4663 * Enables Dynamic Power Management by SMC
4664 *
4665 * @param hwmgr the address of the powerplay hardware manager.
4666 * @return always 0
4667 */
2cc0c0b5 4668static int polaris10_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 4669{
4670 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4671 GENERAL_PWRMGT, STATIC_PM_EN, 1);
4672
4673 return 0;
4674}
4675
4676/**
4677 * Initialize PowerGating States for different engines
4678 *
4679 * @param hwmgr the address of the powerplay hardware manager.
4680 * @return always 0
4681 */
2cc0c0b5 4682static int polaris10_init_power_gate_state(struct pp_hwmgr *hwmgr)
a23eefa2 4683{
2cc0c0b5 4684 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4685
4686 data->uvd_power_gated = false;
4687 data->vce_power_gated = false;
4688 data->samu_power_gated = false;
4689
4690 return 0;
4691}
4692
2cc0c0b5 4693static int polaris10_init_sclk_threshold(struct pp_hwmgr *hwmgr)
a23eefa2 4694{
2cc0c0b5 4695 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4696 data->low_sclk_interrupt_threshold = 0;
4697
4698 return 0;
4699}
4700
2cc0c0b5 4701int polaris10_setup_asic_task(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 4702{
4703 int tmp_result, result = 0;
4704
2cc0c0b5 4705 polaris10_upload_mc_firmware(hwmgr);
a23eefa2 4706
2cc0c0b5 4707 tmp_result = polaris10_read_clock_registers(hwmgr);
a23eefa2
RZ		 4708 PP_ASSERT_WITH_CODE((0 == tmp_result),
4709 "Failed to read clock registers!", result = tmp_result);
4710
2cc0c0b5 4711 tmp_result = polaris10_get_memory_type(hwmgr);
a23eefa2
RZ		 4712 PP_ASSERT_WITH_CODE((0 == tmp_result),
4713 "Failed to get memory type!", result = tmp_result);
4714
2cc0c0b5 4715 tmp_result = polaris10_enable_acpi_power_management(hwmgr);
a23eefa2
RZ		 4716 PP_ASSERT_WITH_CODE((0 == tmp_result),
4717 "Failed to enable ACPI power management!", result = tmp_result);
4718
2cc0c0b5 4719 tmp_result = polaris10_init_power_gate_state(hwmgr);
a23eefa2
RZ		 4720 PP_ASSERT_WITH_CODE((0 == tmp_result),
4721 "Failed to init power gate state!", result = tmp_result);
4722
4723 tmp_result = phm_get_mc_microcode_version(hwmgr);
4724 PP_ASSERT_WITH_CODE((0 == tmp_result),
4725 "Failed to get MC microcode version!", result = tmp_result);
4726
2cc0c0b5 4727 tmp_result = polaris10_init_sclk_threshold(hwmgr);
a23eefa2
RZ		 4728 PP_ASSERT_WITH_CODE((0 == tmp_result),
4729 "Failed to init sclk threshold!", result = tmp_result);
4730
4731 return result;
4732}
4733
2cc0c0b5
FC		 4734static int polaris10_get_pp_table(struct pp_hwmgr *hwmgr, char **table)
4735{
4736 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4737
a72d5604 4738 if (!data->soft_pp_table) {
c688c641
MFW		 4739 data->soft_pp_table = kmemdup(hwmgr->soft_pp_table,
4740 hwmgr->soft_pp_table_size,
4741 GFP_KERNEL);
a72d5604
EH		 4742 if (!data->soft_pp_table)
4743 return -ENOMEM;
a72d5604 4744 }
2cc0c0b5 4745
a72d5604
EH		 4746 *table = (char *)&data->soft_pp_table;
4747
4748 return hwmgr->soft_pp_table_size;
2cc0c0b5
FC		 4749}
4750
4751static int polaris10_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t size)
4752{
4753 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4754
a72d5604
EH		 4755 if (!data->soft_pp_table) {
4756 data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
4757 if (!data->soft_pp_table)
4758 return -ENOMEM;
4759 }
4760
4761 memcpy(data->soft_pp_table, buf, size);
4762
4763 hwmgr->soft_pp_table = data->soft_pp_table;
2cc0c0b5 4764
a72d5604 4765 /* TODO: re-init powerplay to implement modified pptable */
2cc0c0b5
FC		 4766
4767 return 0;
4768}
4769
4770static int polaris10_force_clock_level(struct pp_hwmgr *hwmgr,
5632708f 4771 enum pp_clock_type type, uint32_t mask)
2cc0c0b5
FC		 4772{
4773 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4774
4775 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
4776 return -EINVAL;
4777
4778 switch (type) {
4779 case PP_SCLK:
4780 if (!data->sclk_dpm_key_disabled)
4781 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4782 PPSMC_MSG_SCLKDPM_SetEnabledMask,
5632708f 4783 data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
2cc0c0b5
FC		 4784 break;
4785 case PP_MCLK:
4786 if (!data->mclk_dpm_key_disabled)
4787 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4788 PPSMC_MSG_MCLKDPM_SetEnabledMask,
5632708f 4789 data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
2cc0c0b5
FC		 4790 break;
4791 case PP_PCIE:
5632708f
EH		 4792 {
4793 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
4794 uint32_t level = 0;
4795
4796 while (tmp >>= 1)
4797 level++;
4798
2cc0c0b5
FC		 4799 if (!data->pcie_dpm_key_disabled)
4800 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4801 PPSMC_MSG_PCIeDPM_ForceLevel,
5632708f 4802 level);
2cc0c0b5 4803 break;
5632708f 4804 }
2cc0c0b5
FC		 4805 default:
4806 break;
4807 }
4808
4809 return 0;
4810}
4811
4812static uint16_t polaris10_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
4813{
4814 uint32_t speedCntl = 0;
4815
4816 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
4817 speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
4818 ixPCIE_LC_SPEED_CNTL);
4819 return((uint16_t)PHM_GET_FIELD(speedCntl,
4820 PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
4821}
4822
4823static int polaris10_print_clock_levels(struct pp_hwmgr *hwmgr,
4824 enum pp_clock_type type, char *buf)
4825{
4826 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4827 struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4828 struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4829 struct polaris10_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
4830 int i, now, size = 0;
4831 uint32_t clock, pcie_speed;
4832
4833 switch (type) {
4834 case PP_SCLK:
4835 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
4836 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4837
4838 for (i = 0; i < sclk_table->count; i++) {
4839 if (clock > sclk_table->dpm_levels[i].value)
4840 continue;
4841 break;
4842 }
4843 now = i;
4844
4845 for (i = 0; i < sclk_table->count; i++)
4846 size += sprintf(buf + size, "%d: %uMhz %s\n",
4847 i, sclk_table->dpm_levels[i].value / 100,
4848 (i == now) ? "*" : "");
4849 break;
4850 case PP_MCLK:
4851 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
4852 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4853
4854 for (i = 0; i < mclk_table->count; i++) {
4855 if (clock > mclk_table->dpm_levels[i].value)
4856 continue;
4857 break;
4858 }
4859 now = i;
4860
4861 for (i = 0; i < mclk_table->count; i++)
4862 size += sprintf(buf + size, "%d: %uMhz %s\n",
4863 i, mclk_table->dpm_levels[i].value / 100,
4864 (i == now) ? "*" : "");
4865 break;
4866 case PP_PCIE:
4867 pcie_speed = polaris10_get_current_pcie_speed(hwmgr);
4868 for (i = 0; i < pcie_table->count; i++) {
4869 if (pcie_speed != pcie_table->dpm_levels[i].value)
4870 continue;
4871 break;
4872 }
4873 now = i;
4874
4875 for (i = 0; i < pcie_table->count; i++)
4876 size += sprintf(buf + size, "%d: %s %s\n", i,
4877 (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" :
4878 (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
4879 (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
4880 (i == now) ? "*" : "");
4881 break;
4882 default:
4883 break;
4884 }
4885 return size;
4886}
4887
9e26bbb3
RZ		 4888static int polaris10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
4889{
4890 if (mode) {
4891 /* stop auto-manage */
4892 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4893 PHM_PlatformCaps_MicrocodeFanControl))
4894 polaris10_fan_ctrl_stop_smc_fan_control(hwmgr);
4895 polaris10_fan_ctrl_set_static_mode(hwmgr, mode);
4896 } else
4897 /* restart auto-manage */
4898 polaris10_fan_ctrl_reset_fan_speed_to_default(hwmgr);
4899
4900 return 0;
4901}
4902
4903static int polaris10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
4904{
4905 if (hwmgr->fan_ctrl_is_in_default_mode)
4906 return hwmgr->fan_ctrl_default_mode;
4907 else
4908 return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4909 CG_FDO_CTRL2, FDO_PWM_MODE);
4910}
4911
2cc0c0b5
FC		 4912static const struct pp_hwmgr_func polaris10_hwmgr_funcs = {
4913 .backend_init = &polaris10_hwmgr_backend_init,
4914 .backend_fini = &polaris10_hwmgr_backend_fini,
4915 .asic_setup = &polaris10_setup_asic_task,
4916 .dynamic_state_management_enable = &polaris10_enable_dpm_tasks,
4917 .apply_state_adjust_rules = polaris10_apply_state_adjust_rules,
4918 .force_dpm_level = &polaris10_force_dpm_level,
4919 .power_state_set = polaris10_set_power_state_tasks,
4920 .get_power_state_size = polaris10_get_power_state_size,
4921 .get_mclk = polaris10_dpm_get_mclk,
4922 .get_sclk = polaris10_dpm_get_sclk,
4923 .patch_boot_state = polaris10_dpm_patch_boot_state,
4924 .get_pp_table_entry = polaris10_get_pp_table_entry,
a23eefa2 4925 .get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries,
2cc0c0b5
FC		 4926 .print_current_perforce_level = polaris10_print_current_perforce_level,
4927 .powerdown_uvd = polaris10_phm_powerdown_uvd,
4928 .powergate_uvd = polaris10_phm_powergate_uvd,
4929 .powergate_vce = polaris10_phm_powergate_vce,
4930 .disable_clock_power_gating = polaris10_phm_disable_clock_power_gating,
4931 .update_clock_gatings = polaris10_phm_update_clock_gatings,
4932 .notify_smc_display_config_after_ps_adjustment = polaris10_notify_smc_display_config_after_ps_adjustment,
4933 .display_config_changed = polaris10_display_configuration_changed_task,
4934 .set_max_fan_pwm_output = polaris10_set_max_fan_pwm_output,
4935 .set_max_fan_rpm_output = polaris10_set_max_fan_rpm_output,
4936 .get_temperature = polaris10_thermal_get_temperature,
4937 .stop_thermal_controller = polaris10_thermal_stop_thermal_controller,
4938 .get_fan_speed_info = polaris10_fan_ctrl_get_fan_speed_info,
4939 .get_fan_speed_percent = polaris10_fan_ctrl_get_fan_speed_percent,
4940 .set_fan_speed_percent = polaris10_fan_ctrl_set_fan_speed_percent,
4941 .reset_fan_speed_to_default = polaris10_fan_ctrl_reset_fan_speed_to_default,
4942 .get_fan_speed_rpm = polaris10_fan_ctrl_get_fan_speed_rpm,
4943 .set_fan_speed_rpm = polaris10_fan_ctrl_set_fan_speed_rpm,
4944 .uninitialize_thermal_controller = polaris10_thermal_ctrl_uninitialize_thermal_controller,
4945 .register_internal_thermal_interrupt = polaris10_register_internal_thermal_interrupt,
4946 .check_smc_update_required_for_display_configuration = polaris10_check_smc_update_required_for_display_configuration,
4947 .check_states_equal = polaris10_check_states_equal,
9e26bbb3
RZ		 4948 .set_fan_control_mode = polaris10_set_fan_control_mode,
4949 .get_fan_control_mode = polaris10_get_fan_control_mode,
2cc0c0b5
FC		 4950 .get_pp_table = polaris10_get_pp_table,
4951 .set_pp_table = polaris10_set_pp_table,
4952 .force_clock_level = polaris10_force_clock_level,
4953 .print_clock_levels = polaris10_print_clock_levels,
4954 .enable_per_cu_power_gating = polaris10_phm_enable_per_cu_power_gating,
a23eefa2
RZ		 4955};
4956
2cc0c0b5 4957int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr)
a23eefa2 4958{
2cc0c0b5 4959 struct polaris10_hwmgr *data;
a23eefa2 4960
2cc0c0b5 4961 data = kzalloc (sizeof(struct polaris10_hwmgr), GFP_KERNEL);
a23eefa2
RZ		 4962 if (data == NULL)
4963 return -ENOMEM;
4964
4965 hwmgr->backend = data;
2cc0c0b5 4966 hwmgr->hwmgr_func = &polaris10_hwmgr_funcs;
a23eefa2 4967 hwmgr->pptable_func = &tonga_pptable_funcs;
2cc0c0b5 4968 pp_polaris10_thermal_initialize(hwmgr);
a23eefa2
RZ		 4969
4970 return 0;
4971}
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