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drm/amd/powerplay: fix fan speed percent setting error on Polaris10
[mirror_ubuntu-focal-kernel.git] / drivers / gpu / drm / amd / powerplay / hwmgr / tonga_hwmgr.c
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c82baa28 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/module.h>
24#include <linux/slab.h>
25#include <linux/fb.h>
26#include "linux/delay.h"
27#include "pp_acpi.h"
28#include "hwmgr.h"
29#include <atombios.h>
30#include "tonga_hwmgr.h"
31#include "pptable.h"
32#include "processpptables.h"
33#include "tonga_processpptables.h"
34#include "tonga_pptable.h"
35#include "pp_debug.h"
36#include "tonga_ppsmc.h"
37#include "cgs_common.h"
38#include "pppcielanes.h"
39#include "tonga_dyn_defaults.h"
40#include "smumgr.h"
41#include "tonga_smumgr.h"
0859ed3d 42#include "tonga_clockpowergating.h"
1e4854e9 43#include "tonga_thermal.h"
c82baa28 44
45#include "smu/smu_7_1_2_d.h"
46#include "smu/smu_7_1_2_sh_mask.h"
47
48#include "gmc/gmc_8_1_d.h"
49#include "gmc/gmc_8_1_sh_mask.h"
50
51#include "bif/bif_5_0_d.h"
52#include "bif/bif_5_0_sh_mask.h"
53
7e8d1fbd
AD		 54#include "dce/dce_10_0_d.h"
55#include "dce/dce_10_0_sh_mask.h"
56
1e4854e9
RZ		 57#include "cgs_linux.h"
58#include "eventmgr.h"
16881da6 59#include "amd_pcie_helpers.h"
1e4854e9 60
c82baa28 61#define MC_CG_ARB_FREQ_F0 0x0a
62#define MC_CG_ARB_FREQ_F1 0x0b
63#define MC_CG_ARB_FREQ_F2 0x0c
64#define MC_CG_ARB_FREQ_F3 0x0d
65
66#define MC_CG_SEQ_DRAMCONF_S0 0x05
67#define MC_CG_SEQ_DRAMCONF_S1 0x06
68#define MC_CG_SEQ_YCLK_SUSPEND 0x04
69#define MC_CG_SEQ_YCLK_RESUME 0x0a
70
71#define PCIE_BUS_CLK 10000
72#define TCLK (PCIE_BUS_CLK / 10)
73
74#define SMC_RAM_END 0x40000
75#define SMC_CG_IND_START 0xc0030000
76#define SMC_CG_IND_END 0xc0040000 /* First byte after SMC_CG_IND*/
77
78#define VOLTAGE_SCALE 4
79#define VOLTAGE_VID_OFFSET_SCALE1 625
80#define VOLTAGE_VID_OFFSET_SCALE2 100
81
82#define VDDC_VDDCI_DELTA 200
83#define VDDC_VDDGFX_DELTA 300
84
85#define MC_SEQ_MISC0_GDDR5_SHIFT 28
86#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
87#define MC_SEQ_MISC0_GDDR5_VALUE 5
88
89typedef uint32_t PECI_RegistryValue;
90
91/* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ] */
f498d9ed 92static const uint16_t PP_ClockStretcherLookupTable[2][4] = {
c82baa28 93 {600, 1050, 3, 0},
94 {600, 1050, 6, 1} };
95
96/* [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */
f498d9ed 97static const uint32_t PP_ClockStretcherDDTTable[2][4][4] = {
c82baa28 98 { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
99 { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
100
101/* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */
f498d9ed 102static const uint8_t PP_ClockStretchAmountConversion[2][6] = {
c82baa28 103 {0, 1, 3, 2, 4, 5},
104 {0, 2, 4, 5, 6, 5} };
105
106/* Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
107enum DPM_EVENT_SRC {
108 DPM_EVENT_SRC_ANALOG = 0, /* Internal analog trip point */
109 DPM_EVENT_SRC_EXTERNAL = 1, /* External (GPIO 17) signal */
110 DPM_EVENT_SRC_DIGITAL = 2, /* Internal digital trip point (DIG_THERM_DPM) */
111 DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, /* Internal analog or external */
112 DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4 /* Internal digital or external */
113};
114typedef enum DPM_EVENT_SRC DPM_EVENT_SRC;
115
f498d9ed 116static const unsigned long PhwTonga_Magic = (unsigned long)(PHM_VIslands_Magic);
c82baa28 117
118struct tonga_power_state *cast_phw_tonga_power_state(
119 struct pp_hw_power_state *hw_ps)
120{
c15c8d70
RZ		 121 if (hw_ps == NULL)
122 return NULL;
123
c82baa28 124 PP_ASSERT_WITH_CODE((PhwTonga_Magic == hw_ps->magic),
125 "Invalid Powerstate Type!",
c15c8d70 126 return NULL);
c82baa28 127
128 return (struct tonga_power_state *)hw_ps;
129}
130
131const struct tonga_power_state *cast_const_phw_tonga_power_state(
132 const struct pp_hw_power_state *hw_ps)
133{
c15c8d70
RZ		 134 if (hw_ps == NULL)
135 return NULL;
136
c82baa28 137 PP_ASSERT_WITH_CODE((PhwTonga_Magic == hw_ps->magic),
138 "Invalid Powerstate Type!",
c15c8d70 139 return NULL);
c82baa28 140
141 return (const struct tonga_power_state *)hw_ps;
142}
143
144int tonga_add_voltage(struct pp_hwmgr *hwmgr,
145 phm_ppt_v1_voltage_lookup_table *look_up_table,
146 phm_ppt_v1_voltage_lookup_record *record)
147{
148 uint32_t i;
149 PP_ASSERT_WITH_CODE((NULL != look_up_table),
150 "Lookup Table empty.", return -1;);
151 PP_ASSERT_WITH_CODE((0 != look_up_table->count),
152 "Lookup Table empty.", return -1;);
153 PP_ASSERT_WITH_CODE((SMU72_MAX_LEVELS_VDDGFX >= look_up_table->count),
154 "Lookup Table is full.", return -1;);
155
156 /* This is to avoid entering duplicate calculated records. */
157 for (i = 0; i < look_up_table->count; i++) {
158 if (look_up_table->entries[i].us_vdd == record->us_vdd) {
159 if (look_up_table->entries[i].us_calculated == 1)
160 return 0;
161 else
162 break;
163 }
164 }
165
166 look_up_table->entries[i].us_calculated = 1;
167 look_up_table->entries[i].us_vdd = record->us_vdd;
168 look_up_table->entries[i].us_cac_low = record->us_cac_low;
169 look_up_table->entries[i].us_cac_mid = record->us_cac_mid;
170 look_up_table->entries[i].us_cac_high = record->us_cac_high;
171 /* Only increment the count when we're appending, not replacing duplicate entry. */
172 if (i == look_up_table->count)
173 look_up_table->count++;
174
175 return 0;
176}
177
bbb207f3
RZ		 178int tonga_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
179{
180 PPSMC_Msg msg = has_display? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
181
182 return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ? 0 : -1;
183}
184
c82baa28 185uint8_t tonga_get_voltage_id(pp_atomctrl_voltage_table *voltage_table,
186 uint32_t voltage)
187{
188 uint8_t count = (uint8_t) (voltage_table->count);
189 uint8_t i = 0;
190
191 PP_ASSERT_WITH_CODE((NULL != voltage_table),
192 "Voltage Table empty.", return 0;);
193 PP_ASSERT_WITH_CODE((0 != count),
194 "Voltage Table empty.", return 0;);
195
196 for (i = 0; i < count; i++) {
197 /* find first voltage bigger than requested */
198 if (voltage_table->entries[i].value >= voltage)
199 return i;
200 }
201
202 /* voltage is bigger than max voltage in the table */
203 return i - 1;
204}
205
206/**
207 * @brief PhwTonga_GetVoltageOrder
208 * Returns index of requested voltage record in lookup(table)
209 * @param hwmgr - pointer to hardware manager
210 * @param lookupTable - lookup list to search in
211 * @param voltage - voltage to look for
212 * @return 0 on success
213 */
214uint8_t tonga_get_voltage_index(phm_ppt_v1_voltage_lookup_table *look_up_table,
215 uint16_t voltage)
216{
217 uint8_t count = (uint8_t) (look_up_table->count);
218 uint8_t i;
219
220 PP_ASSERT_WITH_CODE((NULL != look_up_table), "Lookup Table empty.", return 0;);
221 PP_ASSERT_WITH_CODE((0 != count), "Lookup Table empty.", return 0;);
222
223 for (i = 0; i < count; i++) {
224 /* find first voltage equal or bigger than requested */
225 if (look_up_table->entries[i].us_vdd >= voltage)
226 return i;
227 }
228
229 /* voltage is bigger than max voltage in the table */
230 return i-1;
231}
232
233bool tonga_is_dpm_running(struct pp_hwmgr *hwmgr)
234{
235 /*
236 * We return the status of Voltage Control instead of checking SCLK/MCLK DPM
237 * because we may have test scenarios that need us intentionly disable SCLK/MCLK DPM,
238 * whereas voltage control is a fundemental change that will not be disabled
239 */
240
241 return (0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
242 FEATURE_STATUS, VOLTAGE_CONTROLLER_ON) ? 1 : 0);
243}
244
245/**
246 * Re-generate the DPM level mask value
247 * @param hwmgr the address of the hardware manager
248 */
249static uint32_t tonga_get_dpm_level_enable_mask_value(
250 struct tonga_single_dpm_table * dpm_table)
251{
252 uint32_t i;
253 uint32_t mask_value = 0;
254
255 for (i = dpm_table->count; i > 0; i--) {
256 mask_value = mask_value << 1;
257
258 if (dpm_table->dpm_levels[i-1].enabled)
259 mask_value |= 0x1;
260 else
261 mask_value &= 0xFFFFFFFE;
262 }
263 return mask_value;
264}
265
266/**
267 * Retrieve DPM default values from registry (if available)
268 *
269 * @param hwmgr the address of the powerplay hardware manager.
270 */
271void tonga_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
272{
273 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
274 phw_tonga_ulv_parm *ulv = &(data->ulv);
275 uint32_t tmp;
276
277 ulv->ch_ulv_parameter = PPTONGA_CGULVPARAMETER_DFLT;
278 data->voting_rights_clients0 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT0;
279 data->voting_rights_clients1 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT1;
280 data->voting_rights_clients2 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT2;
281 data->voting_rights_clients3 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT3;
282 data->voting_rights_clients4 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT4;
283 data->voting_rights_clients5 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT5;
284 data->voting_rights_clients6 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT6;
285 data->voting_rights_clients7 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT7;
286
287 data->static_screen_threshold_unit = PPTONGA_STATICSCREENTHRESHOLDUNIT_DFLT;
288 data->static_screen_threshold = PPTONGA_STATICSCREENTHRESHOLD_DFLT;
289
290 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
291 PHM_PlatformCaps_ABM);
292 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
293 PHM_PlatformCaps_NonABMSupportInPPLib);
294
295 tmp = 0;
296 if (tmp == 0)
297 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
298 PHM_PlatformCaps_DynamicACTiming);
299
300 tmp = 0;
301 if (0 != tmp)
302 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
303 PHM_PlatformCaps_DisableMemoryTransition);
304
305 data->mclk_strobe_mode_threshold = 40000;
306 data->mclk_stutter_mode_threshold = 30000;
307 data->mclk_edc_enable_threshold = 40000;
308 data->mclk_edc_wr_enable_threshold = 40000;
309
310 tmp = 0;
311 if (tmp != 0)
312 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
313 PHM_PlatformCaps_DisableMCLS);
314
315 data->pcie_gen_performance.max = PP_PCIEGen1;
316 data->pcie_gen_performance.min = PP_PCIEGen3;
317 data->pcie_gen_power_saving.max = PP_PCIEGen1;
318 data->pcie_gen_power_saving.min = PP_PCIEGen3;
319
320 data->pcie_lane_performance.max = 0;
321 data->pcie_lane_performance.min = 16;
322 data->pcie_lane_power_saving.max = 0;
323 data->pcie_lane_power_saving.min = 16;
324
325 tmp = 0;
326
327 if (tmp)
328 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
329 PHM_PlatformCaps_SclkThrottleLowNotification);
330
331 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
332 PHM_PlatformCaps_DynamicUVDState);
333
334}
335
336int tonga_update_sclk_threshold(struct pp_hwmgr *hwmgr)
337{
338 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
339
340 int result = 0;
341 uint32_t low_sclk_interrupt_threshold = 0;
342
343 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
344 PHM_PlatformCaps_SclkThrottleLowNotification)
345 && (hwmgr->gfx_arbiter.sclk_threshold != data->low_sclk_interrupt_threshold)) {
346 data->low_sclk_interrupt_threshold = hwmgr->gfx_arbiter.sclk_threshold;
347 low_sclk_interrupt_threshold = data->low_sclk_interrupt_threshold;
348
349 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
350
351 result = tonga_copy_bytes_to_smc(
352 hwmgr->smumgr,
353 data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable,
354 LowSclkInterruptThreshold),
355 (uint8_t *)&low_sclk_interrupt_threshold,
356 sizeof(uint32_t),
357 data->sram_end
358 );
359 }
360
361 return result;
362}
363
364/**
365 * Find SCLK value that is associated with specified virtual_voltage_Id.
366 *
367 * @param hwmgr the address of the powerplay hardware manager.
368 * @param virtual_voltage_Id voltageId to look for.
369 * @param sclk output value .
370 * @return always 0 if success and 2 if association not found
371 */
372static int tonga_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
373 phm_ppt_v1_voltage_lookup_table *lookup_table,
374 uint16_t virtual_voltage_id, uint32_t *sclk)
375{
376 uint8_t entryId;
377 uint8_t voltageId;
378 struct phm_ppt_v1_information *pptable_info =
379 (struct phm_ppt_v1_information *)(hwmgr->pptable);
380
381 PP_ASSERT_WITH_CODE(lookup_table->count != 0, "Lookup table is empty", return -1);
382
383 /* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */
384 for (entryId = 0; entryId < pptable_info->vdd_dep_on_sclk->count; entryId++) {
385 voltageId = pptable_info->vdd_dep_on_sclk->entries[entryId].vddInd;
386 if (lookup_table->entries[voltageId].us_vdd == virtual_voltage_id)
387 break;
388 }
389
390 PP_ASSERT_WITH_CODE(entryId < pptable_info->vdd_dep_on_sclk->count,
391 "Can't find requested voltage id in vdd_dep_on_sclk table!",
392 return -1;
393 );
394
395 *sclk = pptable_info->vdd_dep_on_sclk->entries[entryId].clk;
396
397 return 0;
398}
399
400/**
401 * Get Leakage VDDC based on leakage ID.
402 *
403 * @param hwmgr the address of the powerplay hardware manager.
404 * @return 2 if vddgfx returned is greater than 2V or if BIOS
405 */
406int tonga_get_evv_voltage(struct pp_hwmgr *hwmgr)
407{
408 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
409 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
410 phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk;
411 uint16_t virtual_voltage_id;
412 uint16_t vddc = 0;
413 uint16_t vddgfx = 0;
414 uint16_t i, j;
415 uint32_t sclk = 0;
416
417 /* retrieve voltage for leakage ID (0xff01 + i) */
418 for (i = 0; i < TONGA_MAX_LEAKAGE_COUNT; i++) {
419 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
420
421 /* in split mode we should have only vddgfx EVV leakages */
422 if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
423 if (0 == tonga_get_sclk_for_voltage_evv(hwmgr,
424 pptable_info->vddgfx_lookup_table, virtual_voltage_id, &sclk)) {
425 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
426 PHM_PlatformCaps_ClockStretcher)) {
427 for (j = 1; j < sclk_table->count; j++) {
428 if (sclk_table->entries[j].clk == sclk &&
429 sclk_table->entries[j].cks_enable == 0) {
430 sclk += 5000;
431 break;
432 }
433 }
434 }
435 PP_ASSERT_WITH_CODE(0 == atomctrl_get_voltage_evv_on_sclk
436 (hwmgr, VOLTAGE_TYPE_VDDGFX, sclk,
437 virtual_voltage_id, &vddgfx),
438 "Error retrieving EVV voltage value!", continue);
439
440 /* need to make sure vddgfx is less than 2v or else, it could burn the ASIC. */
441 PP_ASSERT_WITH_CODE((vddgfx < 2000 && vddgfx != 0), "Invalid VDDGFX value!", return -1);
442
443 /* the voltage should not be zero nor equal to leakage ID */
444 if (vddgfx != 0 && vddgfx != virtual_voltage_id) {
445 data->vddcgfx_leakage.actual_voltage[data->vddcgfx_leakage.count] = vddgfx;
446 data->vddcgfx_leakage.leakage_id[data->vddcgfx_leakage.count] = virtual_voltage_id;
447 data->vddcgfx_leakage.count++;
448 }
449 }
450 } else {
451 /* in merged mode we have only vddc EVV leakages */
452 if (0 == tonga_get_sclk_for_voltage_evv(hwmgr,
453 pptable_info->vddc_lookup_table,
454 virtual_voltage_id, &sclk)) {
455 PP_ASSERT_WITH_CODE(0 == atomctrl_get_voltage_evv_on_sclk
456 (hwmgr, VOLTAGE_TYPE_VDDC, sclk,
457 virtual_voltage_id, &vddc),
458 "Error retrieving EVV voltage value!", continue);
459
460 /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
461 if (vddc > 2000)
462 printk(KERN_ERR "[ powerplay ] Invalid VDDC value! \n");
463
464 /* the voltage should not be zero nor equal to leakage ID */
465 if (vddc != 0 && vddc != virtual_voltage_id) {
466 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = vddc;
467 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = virtual_voltage_id;
468 data->vddc_leakage.count++;
469 }
470 }
471 }
472 }
473
474 return 0;
475}
476
477int tonga_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
478{
479 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
480
481 /* enable SCLK dpm */
482 if (0 == data->sclk_dpm_key_disabled) {
483 PP_ASSERT_WITH_CODE(
484 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
485 PPSMC_MSG_DPM_Enable)),
486 "Failed to enable SCLK DPM during DPM Start Function!",
487 return -1);
488 }
489
490 /* enable MCLK dpm */
491 if (0 == data->mclk_dpm_key_disabled) {
492 PP_ASSERT_WITH_CODE(
493 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
494 PPSMC_MSG_MCLKDPM_Enable)),
495 "Failed to enable MCLK DPM during DPM Start Function!",
496 return -1);
497
498 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
499
500 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
501 ixLCAC_MC0_CNTL, 0x05);/* CH0,1 read */
502 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
503 ixLCAC_MC1_CNTL, 0x05);/* CH2,3 read */
504 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
505 ixLCAC_CPL_CNTL, 0x100005);/*Read */
506
507 udelay(10);
508
509 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
510 ixLCAC_MC0_CNTL, 0x400005);/* CH0,1 write */
511 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
512 ixLCAC_MC1_CNTL, 0x400005);/* CH2,3 write */
513 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
514 ixLCAC_CPL_CNTL, 0x500005);/* write */
515
516 }
517
518 return 0;
519}
520
521int tonga_start_dpm(struct pp_hwmgr *hwmgr)
522{
523 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
524
525 /* enable general power management */
526 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, 1);
527 /* enable sclk deep sleep */
528 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, DYNAMIC_PM_EN, 1);
529
530 /* prepare for PCIE DPM */
531 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start +
532 offsetof(SMU72_SoftRegisters, VoltageChangeTimeout), 0x1000);
533
534 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, SWRST_COMMAND_1, RESETLC, 0x0);
535
536 PP_ASSERT_WITH_CODE(
537 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
538 PPSMC_MSG_Voltage_Cntl_Enable)),
539 "Failed to enable voltage DPM during DPM Start Function!",
540 return -1);
541
542 if (0 != tonga_enable_sclk_mclk_dpm(hwmgr)) {
543 PP_ASSERT_WITH_CODE(0, "Failed to enable Sclk DPM and Mclk DPM!", return -1);
544 }
545
546 /* enable PCIE dpm */
547 if (0 == data->pcie_dpm_key_disabled) {
548 PP_ASSERT_WITH_CODE(
549 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
550 PPSMC_MSG_PCIeDPM_Enable)),
551 "Failed to enable pcie DPM during DPM Start Function!",
552 return -1
553 );
554 }
555
556 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
557 PHM_PlatformCaps_Falcon_QuickTransition)) {
558 smum_send_msg_to_smc(hwmgr->smumgr,
559 PPSMC_MSG_EnableACDCGPIOInterrupt);
560 }
561
562 return 0;
563}
564
565int tonga_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
566{
567 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
568
569 /* disable SCLK dpm */
570 if (0 == data->sclk_dpm_key_disabled) {
571 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
572 PP_ASSERT_WITH_CODE(
573 (0 == tonga_is_dpm_running(hwmgr)),
574 "Trying to Disable SCLK DPM when DPM is disabled",
575 return -1
576 );
577
578 PP_ASSERT_WITH_CODE(
579 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
580 PPSMC_MSG_DPM_Disable)),
581 "Failed to disable SCLK DPM during DPM stop Function!",
582 return -1);
583 }
584
585 /* disable MCLK dpm */
586 if (0 == data->mclk_dpm_key_disabled) {
587 /* Checking if DPM is running. If we discover hang because of this, we should skip this message. */
588 PP_ASSERT_WITH_CODE(
589 (0 == tonga_is_dpm_running(hwmgr)),
590 "Trying to Disable MCLK DPM when DPM is disabled",
591 return -1
592 );
593
594 PP_ASSERT_WITH_CODE(
595 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
596 PPSMC_MSG_MCLKDPM_Disable)),
597 "Failed to Disable MCLK DPM during DPM stop Function!",
598 return -1);
599 }
600
601 return 0;
602}
603
604int tonga_stop_dpm(struct pp_hwmgr *hwmgr)
605{
606 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
607
608 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, 0);
609 /* disable sclk deep sleep*/
610 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, DYNAMIC_PM_EN, 0);
611
612 /* disable PCIE dpm */
613 if (0 == data->pcie_dpm_key_disabled) {
614 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
615 PP_ASSERT_WITH_CODE(
616 (0 == tonga_is_dpm_running(hwmgr)),
617 "Trying to Disable PCIE DPM when DPM is disabled",
618 return -1
619 );
620 PP_ASSERT_WITH_CODE(
621 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
622 PPSMC_MSG_PCIeDPM_Disable)),
623 "Failed to disable pcie DPM during DPM stop Function!",
624 return -1);
625 }
626
627 if (0 != tonga_disable_sclk_mclk_dpm(hwmgr))
628 PP_ASSERT_WITH_CODE(0, "Failed to disable Sclk DPM and Mclk DPM!", return -1);
629
630 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
631 PP_ASSERT_WITH_CODE(
632 (0 == tonga_is_dpm_running(hwmgr)),
633 "Trying to Disable Voltage CNTL when DPM is disabled",
634 return -1
635 );
636
637 PP_ASSERT_WITH_CODE(
638 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
639 PPSMC_MSG_Voltage_Cntl_Disable)),
640 "Failed to disable voltage DPM during DPM stop Function!",
641 return -1);
642
643 return 0;
644}
645
646int tonga_enable_sclk_control(struct pp_hwmgr *hwmgr)
647{
648 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, 0);
649
650 return 0;
651}
652
653/**
654 * Send a message to the SMC and return a parameter
655 *
656 * @param hwmgr: the address of the powerplay hardware manager.
657 * @param msg: the message to send.
658 * @param parameter: pointer to the received parameter
659 * @return The response that came from the SMC.
660 */
661PPSMC_Result tonga_send_msg_to_smc_return_parameter(
662 struct pp_hwmgr *hwmgr,
663 PPSMC_Msg msg,
664 uint32_t *parameter)
665{
666 int result;
667
668 result = smum_send_msg_to_smc(hwmgr->smumgr, msg);
669
670 if ((0 == result) && parameter) {
671 *parameter = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
672 }
673
674 return result;
675}
676
677/**
678 * force DPM power State
679 *
680 * @param hwmgr: the address of the powerplay hardware manager.
681 * @param n : DPM level
682 * @return The response that came from the SMC.
683 */
684int tonga_dpm_force_state(struct pp_hwmgr *hwmgr, uint32_t n)
685{
686 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
687 uint32_t level_mask = 1 << n;
688
689 /* Checking if DPM is running. If we discover hang because of this, we should skip this message. */
690 PP_ASSERT_WITH_CODE(0 == tonga_is_dpm_running(hwmgr),
691 "Trying to force SCLK when DPM is disabled", return -1;);
692 if (0 == data->sclk_dpm_key_disabled)
693 return (0 == smum_send_msg_to_smc_with_parameter(
694 hwmgr->smumgr,
695 (PPSMC_Msg)(PPSMC_MSG_SCLKDPM_SetEnabledMask),
696 level_mask) ? 0 : 1);
697
698 return 0;
699}
700
701/**
702 * force DPM power State
703 *
704 * @param hwmgr: the address of the powerplay hardware manager.
705 * @param n : DPM level
706 * @return The response that came from the SMC.
707 */
708int tonga_dpm_force_state_mclk(struct pp_hwmgr *hwmgr, uint32_t n)
709{
710 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
711 uint32_t level_mask = 1 << n;
712
713 /* Checking if DPM is running. If we discover hang because of this, we should skip this message. */
714 PP_ASSERT_WITH_CODE(0 == tonga_is_dpm_running(hwmgr),
715 "Trying to Force MCLK when DPM is disabled", return -1;);
716 if (0 == data->mclk_dpm_key_disabled)
717 return (0 == smum_send_msg_to_smc_with_parameter(
718 hwmgr->smumgr,
719 (PPSMC_Msg)(PPSMC_MSG_MCLKDPM_SetEnabledMask),
720 level_mask) ? 0 : 1);
721
722 return 0;
723}
724
725/**
726 * force DPM power State
727 *
728 * @param hwmgr: the address of the powerplay hardware manager.
729 * @param n : DPM level
730 * @return The response that came from the SMC.
731 */
732int tonga_dpm_force_state_pcie(struct pp_hwmgr *hwmgr, uint32_t n)
733{
734 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
735
736 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
737 PP_ASSERT_WITH_CODE(0 == tonga_is_dpm_running(hwmgr),
738 "Trying to Force PCIE level when DPM is disabled", return -1;);
739 if (0 == data->pcie_dpm_key_disabled)
740 return (0 == smum_send_msg_to_smc_with_parameter(
741 hwmgr->smumgr,
742 (PPSMC_Msg)(PPSMC_MSG_PCIeDPM_ForceLevel),
743 n) ? 0 : 1);
744
745 return 0;
746}
747
748/**
749 * Set the initial state by calling SMC to switch to this state directly
750 *
751 * @param hwmgr the address of the powerplay hardware manager.
752 * @return always 0
753 */
754int tonga_set_boot_state(struct pp_hwmgr *hwmgr)
755{
756 /*
757 * SMC only stores one state that SW will ask to switch too,
758 * so we switch the the just uploaded one
759 */
760 return (0 == tonga_disable_sclk_mclk_dpm(hwmgr)) ? 0 : 1;
761}
762
763/**
764 * Get the location of various tables inside the FW image.
765 *
766 * @param hwmgr the address of the powerplay hardware manager.
767 * @return always 0
768 */
769int tonga_process_firmware_header(struct pp_hwmgr *hwmgr)
770{
771 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
772 struct tonga_smumgr *tonga_smu = (struct tonga_smumgr *)(hwmgr->smumgr->backend);
773
774 uint32_t tmp;
775 int result;
776 bool error = 0;
777
778 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
779 SMU72_FIRMWARE_HEADER_LOCATION +
780 offsetof(SMU72_Firmware_Header, DpmTable),
781 &tmp, data->sram_end);
782
783 if (0 == result) {
784 data->dpm_table_start = tmp;
785 }
786
787 error |= (0 != result);
788
789 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
790 SMU72_FIRMWARE_HEADER_LOCATION +
791 offsetof(SMU72_Firmware_Header, SoftRegisters),
792 &tmp, data->sram_end);
793
794 if (0 == result) {
795 data->soft_regs_start = tmp;
796 tonga_smu->ulSoftRegsStart = tmp;
797 }
798
799 error |= (0 != result);
800
801
802 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
803 SMU72_FIRMWARE_HEADER_LOCATION +
804 offsetof(SMU72_Firmware_Header, mcRegisterTable),
805 &tmp, data->sram_end);
806
807 if (0 == result) {
808 data->mc_reg_table_start = tmp;
809 }
810
811 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
812 SMU72_FIRMWARE_HEADER_LOCATION +
813 offsetof(SMU72_Firmware_Header, FanTable),
814 &tmp, data->sram_end);
815
816 if (0 == result) {
817 data->fan_table_start = tmp;
818 }
819
820 error |= (0 != result);
821
822 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
823 SMU72_FIRMWARE_HEADER_LOCATION +
824 offsetof(SMU72_Firmware_Header, mcArbDramTimingTable),
825 &tmp, data->sram_end);
826
827 if (0 == result) {
828 data->arb_table_start = tmp;
829 }
830
831 error |= (0 != result);
832
833
834 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
835 SMU72_FIRMWARE_HEADER_LOCATION +
836 offsetof(SMU72_Firmware_Header, Version),
837 &tmp, data->sram_end);
838
839 if (0 == result) {
840 hwmgr->microcode_version_info.SMC = tmp;
841 }
842
843 error |= (0 != result);
844
845 return error ? 1 : 0;
846}
847
848/**
849 * Read clock related registers.
850 *
851 * @param hwmgr the address of the powerplay hardware manager.
852 * @return always 0
853 */
854int tonga_read_clock_registers(struct pp_hwmgr *hwmgr)
855{
856 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
857
858 data->clock_registers.vCG_SPLL_FUNC_CNTL =
859 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL);
860 data->clock_registers.vCG_SPLL_FUNC_CNTL_2 =
861 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2);
862 data->clock_registers.vCG_SPLL_FUNC_CNTL_3 =
863 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_3);
864 data->clock_registers.vCG_SPLL_FUNC_CNTL_4 =
865 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4);
866 data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM =
867 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM);
868 data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2 =
869 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM_2);
870 data->clock_registers.vDLL_CNTL =
871 cgs_read_register(hwmgr->device, mmDLL_CNTL);
872 data->clock_registers.vMCLK_PWRMGT_CNTL =
873 cgs_read_register(hwmgr->device, mmMCLK_PWRMGT_CNTL);
874 data->clock_registers.vMPLL_AD_FUNC_CNTL =
875 cgs_read_register(hwmgr->device, mmMPLL_AD_FUNC_CNTL);
876 data->clock_registers.vMPLL_DQ_FUNC_CNTL =
877 cgs_read_register(hwmgr->device, mmMPLL_DQ_FUNC_CNTL);
878 data->clock_registers.vMPLL_FUNC_CNTL =
879 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL);
880 data->clock_registers.vMPLL_FUNC_CNTL_1 =
881 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_1);
882 data->clock_registers.vMPLL_FUNC_CNTL_2 =
883 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_2);
884 data->clock_registers.vMPLL_SS1 =
885 cgs_read_register(hwmgr->device, mmMPLL_SS1);
886 data->clock_registers.vMPLL_SS2 =
887 cgs_read_register(hwmgr->device, mmMPLL_SS2);
888
889 return 0;
890}
891
892/**
893 * Find out if memory is GDDR5.
894 *
895 * @param hwmgr the address of the powerplay hardware manager.
896 * @return always 0
897 */
898int tonga_get_memory_type(struct pp_hwmgr *hwmgr)
899{
900 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
901 uint32_t temp;
902
903 temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
904
905 data->is_memory_GDDR5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
906 ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
907 MC_SEQ_MISC0_GDDR5_SHIFT));
908
909 return 0;
910}
911
912/**
913 * Enables Dynamic Power Management by SMC
914 *
915 * @param hwmgr the address of the powerplay hardware manager.
916 * @return always 0
917 */
918int tonga_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
919{
920 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, STATIC_PM_EN, 1);
921
922 return 0;
923}
924
925/**
926 * Initialize PowerGating States for different engines
927 *
928 * @param hwmgr the address of the powerplay hardware manager.
929 * @return always 0
930 */
931int tonga_init_power_gate_state(struct pp_hwmgr *hwmgr)
932{
933 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
934
935 data->uvd_power_gated = 0;
936 data->vce_power_gated = 0;
937 data->samu_power_gated = 0;
938 data->acp_power_gated = 0;
939 data->pg_acp_init = 1;
940
941 return 0;
942}
943
944/**
945 * Checks if DPM is enabled
946 *
947 * @param hwmgr the address of the powerplay hardware manager.
948 * @return always 0
949 */
950int tonga_check_for_dpm_running(struct pp_hwmgr *hwmgr)
951{
952 /*
953 * We return the status of Voltage Control instead of checking SCLK/MCLK DPM
954 * because we may have test scenarios that need us intentionly disable SCLK/MCLK DPM,
955 * whereas voltage control is a fundemental change that will not be disabled
956 */
957 return (0 == tonga_is_dpm_running(hwmgr) ? 0 : 1);
958}
959
960/**
961 * Checks if DPM is stopped
962 *
963 * @param hwmgr the address of the powerplay hardware manager.
964 * @return always 0
965 */
966int tonga_check_for_dpm_stopped(struct pp_hwmgr *hwmgr)
967{
968 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
969
970 if (0 != tonga_is_dpm_running(hwmgr)) {
971 /* If HW Virtualization is enabled, dpm_table_start will not have a valid value */
972 if (!data->dpm_table_start) {
973 return 1;
974 }
975 }
976
977 return 0;
978}
979
980/**
981 * Remove repeated voltage values and create table with unique values.
982 *
983 * @param hwmgr the address of the powerplay hardware manager.
984 * @param voltage_table the pointer to changing voltage table
985 * @return 1 in success
986 */
987
988static int tonga_trim_voltage_table(struct pp_hwmgr *hwmgr,
989 pp_atomctrl_voltage_table *voltage_table)
990{
991 uint32_t table_size, i, j;
992 uint16_t vvalue;
993 bool bVoltageFound = 0;
994 pp_atomctrl_voltage_table *table;
995
996 PP_ASSERT_WITH_CODE((NULL != voltage_table), "Voltage Table empty.", return -1;);
997 table_size = sizeof(pp_atomctrl_voltage_table);
998 table = kzalloc(table_size, GFP_KERNEL);
999
1000 if (NULL == table)
1001 return -ENOMEM;
1002
1003 memset(table, 0x00, table_size);
1004 table->mask_low = voltage_table->mask_low;
1005 table->phase_delay = voltage_table->phase_delay;
1006
1007 for (i = 0; i < voltage_table->count; i++) {
1008 vvalue = voltage_table->entries[i].value;
1009 bVoltageFound = 0;
1010
1011 for (j = 0; j < table->count; j++) {
1012 if (vvalue == table->entries[j].value) {
1013 bVoltageFound = 1;
1014 break;
1015 }
1016 }
1017
1018 if (!bVoltageFound) {
1019 table->entries[table->count].value = vvalue;
1020 table->entries[table->count].smio_low =
1021 voltage_table->entries[i].smio_low;
1022 table->count++;
1023 }
1024 }
1025
1026 memcpy(table, voltage_table, sizeof(pp_atomctrl_voltage_table));
1027
1028 kfree(table);
1029
1030 return 0;
1031}
1032
1033static int tonga_get_svi2_vdd_ci_voltage_table(
1034 struct pp_hwmgr *hwmgr,
1035 phm_ppt_v1_clock_voltage_dependency_table *voltage_dependency_table)
1036{
1037 uint32_t i;
1038 int result;
1039 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1040 pp_atomctrl_voltage_table *vddci_voltage_table = &(data->vddci_voltage_table);
1041
1042 PP_ASSERT_WITH_CODE((0 != voltage_dependency_table->count),
1043 "Voltage Dependency Table empty.", return -1;);
1044
1045 vddci_voltage_table->mask_low = 0;
1046 vddci_voltage_table->phase_delay = 0;
1047 vddci_voltage_table->count = voltage_dependency_table->count;
1048
1049 for (i = 0; i < voltage_dependency_table->count; i++) {
1050 vddci_voltage_table->entries[i].value =
1051 voltage_dependency_table->entries[i].vddci;
1052 vddci_voltage_table->entries[i].smio_low = 0;
1053 }
1054
1055 result = tonga_trim_voltage_table(hwmgr, vddci_voltage_table);
1056 PP_ASSERT_WITH_CODE((0 == result),
1057 "Failed to trim VDDCI table.", return result;);
1058
1059 return 0;
1060}
1061
1062
1063
1064static int tonga_get_svi2_vdd_voltage_table(
1065 struct pp_hwmgr *hwmgr,
1066 phm_ppt_v1_voltage_lookup_table *look_up_table,
1067 pp_atomctrl_voltage_table *voltage_table)
1068{
1069 uint8_t i = 0;
1070
1071 PP_ASSERT_WITH_CODE((0 != look_up_table->count),
1072 "Voltage Lookup Table empty.", return -1;);
1073
1074 voltage_table->mask_low = 0;
1075 voltage_table->phase_delay = 0;
1076
1077 voltage_table->count = look_up_table->count;
1078
1079 for (i = 0; i < voltage_table->count; i++) {
1080 voltage_table->entries[i].value = look_up_table->entries[i].us_vdd;
1081 voltage_table->entries[i].smio_low = 0;
1082 }
1083
1084 return 0;
1085}
1086
1087/*
1088 * -------------------------------------------------------- Voltage Tables --------------------------------------------------------------------------
1089 * If the voltage table would be bigger than what will fit into the state table on the SMC keep only the higher entries.
1090 */
1091
1092static void tonga_trim_voltage_table_to_fit_state_table(
1093 struct pp_hwmgr *hwmgr,
1094 uint32_t max_voltage_steps,
1095 pp_atomctrl_voltage_table *voltage_table)
1096{
1097 unsigned int i, diff;
1098
1099 if (voltage_table->count <= max_voltage_steps) {
1100 return;
1101 }
1102
1103 diff = voltage_table->count - max_voltage_steps;
1104
1105 for (i = 0; i < max_voltage_steps; i++) {
1106 voltage_table->entries[i] = voltage_table->entries[i + diff];
1107 }
1108
1109 voltage_table->count = max_voltage_steps;
1110
1111 return;
1112}
1113
1114/**
1115 * Create Voltage Tables.
1116 *
1117 * @param hwmgr the address of the powerplay hardware manager.
1118 * @return always 0
1119 */
1120int tonga_construct_voltage_tables(struct pp_hwmgr *hwmgr)
1121{
1122 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1123 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1124 int result;
1125
1126 /* MVDD has only GPIO voltage control */
1127 if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1128 result = atomctrl_get_voltage_table_v3(hwmgr,
1129 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT, &(data->mvdd_voltage_table));
1130 PP_ASSERT_WITH_CODE((0 == result),
1131 "Failed to retrieve MVDD table.", return result;);
1132 }
1133
1134 if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control) {
1135 /* GPIO voltage */
1136 result = atomctrl_get_voltage_table_v3(hwmgr,
1137 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT, &(data->vddci_voltage_table));
1138 PP_ASSERT_WITH_CODE((0 == result),
1139 "Failed to retrieve VDDCI table.", return result;);
1140 } else if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control) {
1141 /* SVI2 voltage */
1142 result = tonga_get_svi2_vdd_ci_voltage_table(hwmgr,
1143 pptable_info->vdd_dep_on_mclk);
1144 PP_ASSERT_WITH_CODE((0 == result),
1145 "Failed to retrieve SVI2 VDDCI table from dependancy table.", return result;);
1146 }
1147
1148 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
1149 /* VDDGFX has only SVI2 voltage control */
1150 result = tonga_get_svi2_vdd_voltage_table(hwmgr,
1151 pptable_info->vddgfx_lookup_table, &(data->vddgfx_voltage_table));
1152 PP_ASSERT_WITH_CODE((0 == result),
1153 "Failed to retrieve SVI2 VDDGFX table from lookup table.", return result;);
1154 }
1155
1156 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1157 /* VDDC has only SVI2 voltage control */
1158 result = tonga_get_svi2_vdd_voltage_table(hwmgr,
1159 pptable_info->vddc_lookup_table, &(data->vddc_voltage_table));
1160 PP_ASSERT_WITH_CODE((0 == result),
1161 "Failed to retrieve SVI2 VDDC table from lookup table.", return result;);
1162 }
1163
1164 PP_ASSERT_WITH_CODE(
1165 (data->vddc_voltage_table.count <= (SMU72_MAX_LEVELS_VDDC)),
1166 "Too many voltage values for VDDC. Trimming to fit state table.",
1167 tonga_trim_voltage_table_to_fit_state_table(hwmgr,
1168 SMU72_MAX_LEVELS_VDDC, &(data->vddc_voltage_table));
1169 );
1170
1171 PP_ASSERT_WITH_CODE(
1172 (data->vddgfx_voltage_table.count <= (SMU72_MAX_LEVELS_VDDGFX)),
1173 "Too many voltage values for VDDGFX. Trimming to fit state table.",
1174 tonga_trim_voltage_table_to_fit_state_table(hwmgr,
1175 SMU72_MAX_LEVELS_VDDGFX, &(data->vddgfx_voltage_table));
1176 );
1177
1178 PP_ASSERT_WITH_CODE(
1179 (data->vddci_voltage_table.count <= (SMU72_MAX_LEVELS_VDDCI)),
1180 "Too many voltage values for VDDCI. Trimming to fit state table.",
1181 tonga_trim_voltage_table_to_fit_state_table(hwmgr,
1182 SMU72_MAX_LEVELS_VDDCI, &(data->vddci_voltage_table));
1183 );
1184
1185 PP_ASSERT_WITH_CODE(
1186 (data->mvdd_voltage_table.count <= (SMU72_MAX_LEVELS_MVDD)),
1187 "Too many voltage values for MVDD. Trimming to fit state table.",
1188 tonga_trim_voltage_table_to_fit_state_table(hwmgr,
1189 SMU72_MAX_LEVELS_MVDD, &(data->mvdd_voltage_table));
1190 );
1191
1192 return 0;
1193}
1194
1195/**
1196 * Vddc table preparation for SMC.
1197 *
1198 * @param hwmgr the address of the hardware manager
1199 * @param table the SMC DPM table structure to be populated
1200 * @return always 0
1201 */
1202static int tonga_populate_smc_vddc_table(struct pp_hwmgr *hwmgr,
1203 SMU72_Discrete_DpmTable *table)
1204{
1205 unsigned int count;
1206 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1207
1208 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1209 table->VddcLevelCount = data->vddc_voltage_table.count;
1210 for (count = 0; count < table->VddcLevelCount; count++) {
1211 table->VddcTable[count] =
1212 PP_HOST_TO_SMC_US(data->vddc_voltage_table.entries[count].value * VOLTAGE_SCALE);
1213 }
1214 CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount);
1215 }
1216 return 0;
1217}
1218
1219/**
1220 * VddGfx table preparation for SMC.
1221 *
1222 * @param hwmgr the address of the hardware manager
1223 * @param table the SMC DPM table structure to be populated
1224 * @return always 0
1225 */
1226static int tonga_populate_smc_vdd_gfx_table(struct pp_hwmgr *hwmgr,
1227 SMU72_Discrete_DpmTable *table)
1228{
1229 unsigned int count;
1230 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1231
1232 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
1233 table->VddGfxLevelCount = data->vddgfx_voltage_table.count;
1234 for (count = 0; count < data->vddgfx_voltage_table.count; count++) {
1235 table->VddGfxTable[count] =
1236 PP_HOST_TO_SMC_US(data->vddgfx_voltage_table.entries[count].value * VOLTAGE_SCALE);
1237 }
1238 CONVERT_FROM_HOST_TO_SMC_UL(table->VddGfxLevelCount);
1239 }
1240 return 0;
1241}
1242
1243/**
1244 * Vddci table preparation for SMC.
1245 *
1246 * @param *hwmgr The address of the hardware manager.
1247 * @param *table The SMC DPM table structure to be populated.
1248 * @return 0
1249 */
1250static int tonga_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr,
1251 SMU72_Discrete_DpmTable *table)
1252{
1253 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1254 uint32_t count;
1255
1256 table->VddciLevelCount = data->vddci_voltage_table.count;
1257 for (count = 0; count < table->VddciLevelCount; count++) {
1258 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control) {
1259 table->VddciTable[count] =
1260 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
1261 } else if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control) {
1262 table->SmioTable1.Pattern[count].Voltage =
1263 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
1264 /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level. */
1265 table->SmioTable1.Pattern[count].Smio =
1266 (uint8_t) count;
1267 table->Smio[count] |=
1268 data->vddci_voltage_table.entries[count].smio_low;
1269 table->VddciTable[count] =
1270 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
1271 }
1272 }
1273
1274 table->SmioMask1 = data->vddci_voltage_table.mask_low;
1275 CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount);
1276
1277 return 0;
1278}
1279
1280/**
1281 * Mvdd table preparation for SMC.
1282 *
1283 * @param *hwmgr The address of the hardware manager.
1284 * @param *table The SMC DPM table structure to be populated.
1285 * @return 0
1286 */
1287static int tonga_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
1288 SMU72_Discrete_DpmTable *table)
1289{
1290 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1291 uint32_t count;
1292
1293 if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1294 table->MvddLevelCount = data->mvdd_voltage_table.count;
1295 for (count = 0; count < table->MvddLevelCount; count++) {
1296 table->SmioTable2.Pattern[count].Voltage =
1297 PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
1298 /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
1299 table->SmioTable2.Pattern[count].Smio =
1300 (uint8_t) count;
1301 table->Smio[count] |=
1302 data->mvdd_voltage_table.entries[count].smio_low;
1303 }
1304 table->SmioMask2 = data->vddci_voltage_table.mask_low;
1305
1306 CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount);
1307 }
1308
1309 return 0;
1310}
1311
1312/**
1313 * Convert a voltage value in mv unit to VID number required by SMU firmware
1314 */
1315static uint8_t convert_to_vid(uint16_t vddc)
1316{
1317 return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
1318}
1319
1320
1321/**
1322 * Preparation of vddc and vddgfx CAC tables for SMC.
1323 *
1324 * @param hwmgr the address of the hardware manager
1325 * @param table the SMC DPM table structure to be populated
1326 * @return always 0
1327 */
1328static int tonga_populate_cac_tables(struct pp_hwmgr *hwmgr,
1329 SMU72_Discrete_DpmTable *table)
1330{
1331 uint32_t count;
1332 uint8_t index;
1333 int result = 0;
1334 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1335 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1336 struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table = pptable_info->vddgfx_lookup_table;
1337 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table = pptable_info->vddc_lookup_table;
1338
1339 /* pTables is already swapped, so in order to use the value from it, we need to swap it back. */
1340 uint32_t vddcLevelCount = PP_SMC_TO_HOST_UL(table->VddcLevelCount);
1341 uint32_t vddgfxLevelCount = PP_SMC_TO_HOST_UL(table->VddGfxLevelCount);
1342
1343 for (count = 0; count < vddcLevelCount; count++) {
1344 /* We are populating vddc CAC data to BapmVddc table in split and merged mode */
1345 index = tonga_get_voltage_index(vddc_lookup_table,
1346 data->vddc_voltage_table.entries[count].value);
1347 table->BapmVddcVidLoSidd[count] =
1348 convert_to_vid(vddc_lookup_table->entries[index].us_cac_low);
1349 table->BapmVddcVidHiSidd[count] =
1350 convert_to_vid(vddc_lookup_table->entries[index].us_cac_mid);
1351 table->BapmVddcVidHiSidd2[count] =
1352 convert_to_vid(vddc_lookup_table->entries[index].us_cac_high);
1353 }
1354
1355 if ((data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2)) {
1356 /* We are populating vddgfx CAC data to BapmVddgfx table in split mode */
1357 for (count = 0; count < vddgfxLevelCount; count++) {
1358 index = tonga_get_voltage_index(vddgfx_lookup_table,
1359 data->vddgfx_voltage_table.entries[count].value);
1360 table->BapmVddGfxVidLoSidd[count] =
1361 convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_low);
1362 table->BapmVddGfxVidHiSidd[count] =
1363 convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_mid);
1364 table->BapmVddGfxVidHiSidd2[count] =
1365 convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_high);
1366 }
1367 } else {
1368 for (count = 0; count < vddcLevelCount; count++) {
1369 index = tonga_get_voltage_index(vddc_lookup_table,
1370 data->vddc_voltage_table.entries[count].value);
1371 table->BapmVddGfxVidLoSidd[count] =
1372 convert_to_vid(vddc_lookup_table->entries[index].us_cac_low);
1373 table->BapmVddGfxVidHiSidd[count] =
1374 convert_to_vid(vddc_lookup_table->entries[index].us_cac_mid);
1375 table->BapmVddGfxVidHiSidd2[count] =
1376 convert_to_vid(vddc_lookup_table->entries[index].us_cac_high);
1377 }
1378 }
1379
1380 return result;
1381}
1382
1383
1384/**
1385 * Preparation of voltage tables for SMC.
1386 *
1387 * @param hwmgr the address of the hardware manager
1388 * @param table the SMC DPM table structure to be populated
1389 * @return always 0
1390 */
1391
1392int tonga_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
1393 SMU72_Discrete_DpmTable *table)
1394{
1395 int result;
1396
1397 result = tonga_populate_smc_vddc_table(hwmgr, table);
1398 PP_ASSERT_WITH_CODE(0 == result,
1399 "can not populate VDDC voltage table to SMC", return -1);
1400
1401 result = tonga_populate_smc_vdd_ci_table(hwmgr, table);
1402 PP_ASSERT_WITH_CODE(0 == result,
1403 "can not populate VDDCI voltage table to SMC", return -1);
1404
1405 result = tonga_populate_smc_vdd_gfx_table(hwmgr, table);
1406 PP_ASSERT_WITH_CODE(0 == result,
1407 "can not populate VDDGFX voltage table to SMC", return -1);
1408
1409 result = tonga_populate_smc_mvdd_table(hwmgr, table);
1410 PP_ASSERT_WITH_CODE(0 == result,
1411 "can not populate MVDD voltage table to SMC", return -1);
1412
1413 result = tonga_populate_cac_tables(hwmgr, table);
1414 PP_ASSERT_WITH_CODE(0 == result,
1415 "can not populate CAC voltage tables to SMC", return -1);
1416
1417 return 0;
1418}
1419
1420/**
1421 * Populates the SMC VRConfig field in DPM table.
1422 *
1423 * @param hwmgr the address of the hardware manager
1424 * @param table the SMC DPM table structure to be populated
1425 * @return always 0
1426 */
1427static int tonga_populate_vr_config(struct pp_hwmgr *hwmgr,
1428 SMU72_Discrete_DpmTable *table)
1429{
1430 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1431 uint16_t config;
1432
1433 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
1434 /* Splitted mode */
1435 config = VR_SVI2_PLANE_1;
1436 table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);
1437
1438 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1439 config = VR_SVI2_PLANE_2;
1440 table->VRConfig |= config;
1441 } else {
1442 printk(KERN_ERR "[ powerplay ] VDDC and VDDGFX should be both on SVI2 control in splitted mode! \n");
1443 }
1444 } else {
1445 /* Merged mode */
1446 config = VR_MERGED_WITH_VDDC;
1447 table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);
1448
1449 /* Set Vddc Voltage Controller */
1450 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1451 config = VR_SVI2_PLANE_1;
1452 table->VRConfig |= config;
1453 } else {
1454 printk(KERN_ERR "[ powerplay ] VDDC should be on SVI2 control in merged mode! \n");
1455 }
1456 }
1457
1458 /* Set Vddci Voltage Controller */
1459 if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control) {
1460 config = VR_SVI2_PLANE_2; /* only in merged mode */
1461 table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);
1462 } else if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control) {
1463 config = VR_SMIO_PATTERN_1;
1464 table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);
1465 }
1466
1467 /* Set Mvdd Voltage Controller */
1468 if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1469 config = VR_SMIO_PATTERN_2;
1470 table->VRConfig |= (config<<VRCONF_MVDD_SHIFT);
1471 }
1472
1473 return 0;
1474}
1475
1476static int tonga_get_dependecy_volt_by_clk(struct pp_hwmgr *hwmgr,
1477 phm_ppt_v1_clock_voltage_dependency_table *allowed_clock_voltage_table,
1478 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
1479{
1480 uint32_t i = 0;
1481 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1482 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1483
1484 /* clock - voltage dependency table is empty table */
1485 if (allowed_clock_voltage_table->count == 0)
1486 return -1;
1487
1488 for (i = 0; i < allowed_clock_voltage_table->count; i++) {
1489 /* find first sclk bigger than request */
1490 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
1491 voltage->VddGfx = tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1492 allowed_clock_voltage_table->entries[i].vddgfx);
1493
1494 voltage->Vddc = tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1495 allowed_clock_voltage_table->entries[i].vddc);
1496
1497 if (allowed_clock_voltage_table->entries[i].vddci) {
1498 voltage->Vddci = tonga_get_voltage_id(&data->vddci_voltage_table,
1499 allowed_clock_voltage_table->entries[i].vddci);
1500 } else {
1501 voltage->Vddci = tonga_get_voltage_id(&data->vddci_voltage_table,
1502 allowed_clock_voltage_table->entries[i].vddc - data->vddc_vddci_delta);
1503 }
1504
1505 if (allowed_clock_voltage_table->entries[i].mvdd) {
1506 *mvdd = (uint32_t) allowed_clock_voltage_table->entries[i].mvdd;
1507 }
1508
1509 voltage->Phases = 1;
1510 return 0;
1511 }
1512 }
1513
1514 /* sclk is bigger than max sclk in the dependence table */
1515 voltage->VddGfx = tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1516 allowed_clock_voltage_table->entries[i-1].vddgfx);
1517 voltage->Vddc = tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1518 allowed_clock_voltage_table->entries[i-1].vddc);
1519
1520 if (allowed_clock_voltage_table->entries[i-1].vddci) {
1521 voltage->Vddci = tonga_get_voltage_id(&data->vddci_voltage_table,
1522 allowed_clock_voltage_table->entries[i-1].vddci);
1523 }
1524 if (allowed_clock_voltage_table->entries[i-1].mvdd) {
1525 *mvdd = (uint32_t) allowed_clock_voltage_table->entries[i-1].mvdd;
1526 }
1527
1528 return 0;
1529}
1530
1531/**
1532 * Call SMC to reset S0/S1 to S1 and Reset SMIO to initial value
1533 *
1534 * @param hwmgr the address of the powerplay hardware manager.
1535 * @return always 0
1536 */
1537int tonga_reset_to_default(struct pp_hwmgr *hwmgr)
1538{
1539 return (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ResetToDefaults) == 0) ? 0 : 1;
1540}
1541
1542int tonga_populate_memory_timing_parameters(
1543 struct pp_hwmgr *hwmgr,
1544 uint32_t engine_clock,
1545 uint32_t memory_clock,
1546 struct SMU72_Discrete_MCArbDramTimingTableEntry *arb_regs
1547 )
1548{
1549 uint32_t dramTiming;
1550 uint32_t dramTiming2;
1551 uint32_t burstTime;
1552 int result;
1553
1554 result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1555 engine_clock, memory_clock);
1556
1557 PP_ASSERT_WITH_CODE(result == 0,
1558 "Error calling VBIOS to set DRAM_TIMING.", return result);
1559
1560 dramTiming = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1561 dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1562 burstTime = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1563
1564 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dramTiming);
1565 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2);
1566 arb_regs->McArbBurstTime = (uint8_t)burstTime;
1567
1568 return 0;
1569}
1570
1571/**
1572 * Setup parameters for the MC ARB.
1573 *
1574 * @param hwmgr the address of the powerplay hardware manager.
1575 * @return always 0
1576 * This function is to be called from the SetPowerState table.
1577 */
1578int tonga_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1579{
1580 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1581 int result = 0;
1582 SMU72_Discrete_MCArbDramTimingTable arb_regs;
1583 uint32_t i, j;
1584
1585 memset(&arb_regs, 0x00, sizeof(SMU72_Discrete_MCArbDramTimingTable));
1586
1587 for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1588 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
1589 result = tonga_populate_memory_timing_parameters
1590 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value,
1591 data->dpm_table.mclk_table.dpm_levels[j].value,
1592 &arb_regs.entries[i][j]);
1593
1594 if (0 != result) {
1595 break;
1596 }
1597 }
1598 }
1599
1600 if (0 == result) {
1601 result = tonga_copy_bytes_to_smc(
1602 hwmgr->smumgr,
1603 data->arb_table_start,
1604 (uint8_t *)&arb_regs,
1605 sizeof(SMU72_Discrete_MCArbDramTimingTable),
1606 data->sram_end
1607 );
1608 }
1609
1610 return result;
1611}
1612
1613static int tonga_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU72_Discrete_DpmTable *table)
1614{
1615 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1616 struct tonga_dpm_table *dpm_table = &data->dpm_table;
1617 uint32_t i;
1618
1619 /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */
1620 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
1621 table->LinkLevel[i].PcieGenSpeed =
1622 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
1623 table->LinkLevel[i].PcieLaneCount =
1624 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
1625 table->LinkLevel[i].EnabledForActivity =
1626 1;
1627 table->LinkLevel[i].SPC =
1628 (uint8_t)(data->pcie_spc_cap & 0xff);
1629 table->LinkLevel[i].DownThreshold =
1630 PP_HOST_TO_SMC_UL(5);
1631 table->LinkLevel[i].UpThreshold =
1632 PP_HOST_TO_SMC_UL(30);
1633 }
1634
1635 data->smc_state_table.LinkLevelCount =
1636 (uint8_t)dpm_table->pcie_speed_table.count;
1637 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
1638 tonga_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
1639
1640 return 0;
1641}
1642
0104aa21
AD		 1643static int tonga_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1644 SMU72_Discrete_DpmTable *table)
1645{
1646 int result = 0;
1647
1648 uint8_t count;
1649 pp_atomctrl_clock_dividers_vi dividers;
1650 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1651 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1652 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
1653
1654 table->UvdLevelCount = (uint8_t) (mm_table->count);
1655 table->UvdBootLevel = 0;
1656
1657 for (count = 0; count < table->UvdLevelCount; count++) {
1658 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1659 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1660 table->UvdLevel[count].MinVoltage.Vddc =
1661 tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1662 mm_table->entries[count].vddc);
1663 table->UvdLevel[count].MinVoltage.VddGfx =
1664 (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ?
1665 tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1666 mm_table->entries[count].vddgfx) : 0;
1667 table->UvdLevel[count].MinVoltage.Vddci =
1668 tonga_get_voltage_id(&data->vddci_voltage_table,
1669 mm_table->entries[count].vddc - data->vddc_vddci_delta);
1670 table->UvdLevel[count].MinVoltage.Phases = 1;
1671
1672 /* retrieve divider value for VBIOS */
1673 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1674 table->UvdLevel[count].VclkFrequency, &dividers);
1675 PP_ASSERT_WITH_CODE((0 == result),
1676 "can not find divide id for Vclk clock", return result);
1677
1678 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1679
1680 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1681 table->UvdLevel[count].DclkFrequency, &dividers);
1682 PP_ASSERT_WITH_CODE((0 == result),
1683 "can not find divide id for Dclk clock", return result);
1684
1685 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1686
1687 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1688 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1689 //CONVERT_FROM_HOST_TO_SMC_UL((uint32_t)table->UvdLevel[count].MinVoltage);
c15c8d70 1690 }
0104aa21 1691
c15c8d70 1692 return result;
0104aa21
AD		 1693
1694}
c82baa28 1695
1696static int tonga_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1697 SMU72_Discrete_DpmTable *table)
1698{
1699 int result = 0;
1700
1701 uint8_t count;
1702 pp_atomctrl_clock_dividers_vi dividers;
1703 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1704 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1705 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
1706
1707 table->VceLevelCount = (uint8_t) (mm_table->count);
1708 table->VceBootLevel = 0;
1709
1710 for (count = 0; count < table->VceLevelCount; count++) {
1711 table->VceLevel[count].Frequency =
1712 mm_table->entries[count].eclk;
1713 table->VceLevel[count].MinVoltage.Vddc =
1714 tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1715 mm_table->entries[count].vddc);
1716 table->VceLevel[count].MinVoltage.VddGfx =
1717 (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ?
1718 tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1719 mm_table->entries[count].vddgfx) : 0;
1720 table->VceLevel[count].MinVoltage.Vddci =
1721 tonga_get_voltage_id(&data->vddci_voltage_table,
1722 mm_table->entries[count].vddc - data->vddc_vddci_delta);
1723 table->VceLevel[count].MinVoltage.Phases = 1;
1724
1725 /* retrieve divider value for VBIOS */
1726 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1727 table->VceLevel[count].Frequency, &dividers);
1728 PP_ASSERT_WITH_CODE((0 == result),
1729 "can not find divide id for VCE engine clock", return result);
1730
c15c8d70 1731 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
c82baa28 1732
1733 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1734 }
1735
1736 return result;
1737}
1738
1739static int tonga_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
1740 SMU72_Discrete_DpmTable *table)
1741{
1742 int result = 0;
1743 uint8_t count;
1744 pp_atomctrl_clock_dividers_vi dividers;
1745 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1746 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1747 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
1748
1749 table->AcpLevelCount = (uint8_t) (mm_table->count);
1750 table->AcpBootLevel = 0;
1751
1752 for (count = 0; count < table->AcpLevelCount; count++) {
1753 table->AcpLevel[count].Frequency =
1754 pptable_info->mm_dep_table->entries[count].aclk;
1755 table->AcpLevel[count].MinVoltage.Vddc =
1756 tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1757 mm_table->entries[count].vddc);
1758 table->AcpLevel[count].MinVoltage.VddGfx =
1759 (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ?
1760 tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1761 mm_table->entries[count].vddgfx) : 0;
1762 table->AcpLevel[count].MinVoltage.Vddci =
1763 tonga_get_voltage_id(&data->vddci_voltage_table,
1764 mm_table->entries[count].vddc - data->vddc_vddci_delta);
1765 table->AcpLevel[count].MinVoltage.Phases = 1;
1766
1767 /* retrieve divider value for VBIOS */
1768 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1769 table->AcpLevel[count].Frequency, &dividers);
1770 PP_ASSERT_WITH_CODE((0 == result),
1771 "can not find divide id for engine clock", return result);
1772
1773 table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1774
1775 CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);
1776 }
1777
1778 return result;
1779}
1780
1781static int tonga_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
1782 SMU72_Discrete_DpmTable *table)
1783{
1784 int result = 0;
1785 uint8_t count;
1786 pp_atomctrl_clock_dividers_vi dividers;
1787 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1788 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1789 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
1790
1791 table->SamuBootLevel = 0;
1792 table->SamuLevelCount = (uint8_t) (mm_table->count);
1793
1794 for (count = 0; count < table->SamuLevelCount; count++) {
1795 /* not sure whether we need evclk or not */
1796 table->SamuLevel[count].Frequency =
1797 pptable_info->mm_dep_table->entries[count].samclock;
1798 table->SamuLevel[count].MinVoltage.Vddc =
1799 tonga_get_voltage_index(pptable_info->vddc_lookup_table,
1800 mm_table->entries[count].vddc);
1801 table->SamuLevel[count].MinVoltage.VddGfx =
1802 (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ?
1803 tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
1804 mm_table->entries[count].vddgfx) : 0;
1805 table->SamuLevel[count].MinVoltage.Vddci =
1806 tonga_get_voltage_id(&data->vddci_voltage_table,
1807 mm_table->entries[count].vddc - data->vddc_vddci_delta);
1808 table->SamuLevel[count].MinVoltage.Phases = 1;
1809
1810 /* retrieve divider value for VBIOS */
1811 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1812 table->SamuLevel[count].Frequency, &dividers);
1813 PP_ASSERT_WITH_CODE((0 == result),
1814 "can not find divide id for samu clock", return result);
1815
c15c8d70 1816 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
c82baa28 1817
1818 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
1819 }
1820
1821 return result;
1822}
1823
1824/**
1825 * Populates the SMC MCLK structure using the provided memory clock
1826 *
1827 * @param hwmgr the address of the hardware manager
1828 * @param memory_clock the memory clock to use to populate the structure
1829 * @param sclk the SMC SCLK structure to be populated
1830 */
1831static int tonga_calculate_mclk_params(
1832 struct pp_hwmgr *hwmgr,
1833 uint32_t memory_clock,
1834 SMU72_Discrete_MemoryLevel *mclk,
1835 bool strobe_mode,
1836 bool dllStateOn
1837 )
1838{
1839 const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
1840 uint32_t dll_cntl = data->clock_registers.vDLL_CNTL;
1841 uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
1842 uint32_t mpll_ad_func_cntl = data->clock_registers.vMPLL_AD_FUNC_CNTL;
1843 uint32_t mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL;
1844 uint32_t mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL;
1845 uint32_t mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1;
1846 uint32_t mpll_func_cntl_2 = data->clock_registers.vMPLL_FUNC_CNTL_2;
1847 uint32_t mpll_ss1 = data->clock_registers.vMPLL_SS1;
1848 uint32_t mpll_ss2 = data->clock_registers.vMPLL_SS2;
1849
1850 pp_atomctrl_memory_clock_param mpll_param;
1851 int result;
1852
1853 result = atomctrl_get_memory_pll_dividers_si(hwmgr,
1854 memory_clock, &mpll_param, strobe_mode);
1855 PP_ASSERT_WITH_CODE(0 == result,
1856 "Error retrieving Memory Clock Parameters from VBIOS.", return result);
1857
1858 /* MPLL_FUNC_CNTL setup*/
c15c8d70 1859 mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL, mpll_param.bw_ctrl);
c82baa28 1860
1861 /* MPLL_FUNC_CNTL_1 setup*/
1862 mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
1863 MPLL_FUNC_CNTL_1, CLKF, mpll_param.mpll_fb_divider.cl_kf);
1864 mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
1865 MPLL_FUNC_CNTL_1, CLKFRAC, mpll_param.mpll_fb_divider.clk_frac);
1866 mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
1867 MPLL_FUNC_CNTL_1, VCO_MODE, mpll_param.vco_mode);
1868
1869 /* MPLL_AD_FUNC_CNTL setup*/
1870 mpll_ad_func_cntl = PHM_SET_FIELD(mpll_ad_func_cntl,
1871 MPLL_AD_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
1872
1873 if (data->is_memory_GDDR5) {
1874 /* MPLL_DQ_FUNC_CNTL setup*/
1875 mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl,
1876 MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel);
1877 mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl,
1878 MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
1879 }
1880
1881 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1882 PHM_PlatformCaps_MemorySpreadSpectrumSupport)) {
1883 /*
1884 ************************************
1885 Fref = Reference Frequency
1886 NF = Feedback divider ratio
1887 NR = Reference divider ratio
1888 Fnom = Nominal VCO output frequency = Fref * NF / NR
1889 Fs = Spreading Rate
1890 D = Percentage down-spread / 2
1891 Fint = Reference input frequency to PFD = Fref / NR
1892 NS = Spreading rate divider ratio = int(Fint / (2 * Fs))
1893 CLKS = NS - 1 = ISS_STEP_NUM[11:0]
1894 NV = D * Fs / Fnom * 4 * ((Fnom/Fref * NR) ^ 2)
1895 CLKV = 65536 * NV = ISS_STEP_SIZE[25:0]
1896 *************************************
1897 */
1898 pp_atomctrl_internal_ss_info ss_info;
1899 uint32_t freq_nom;
1900 uint32_t tmp;
1901 uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr);
1902
1903 /* for GDDR5 for all modes and DDR3 */
1904 if (1 == mpll_param.qdr)
1905 freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider);
1906 else
1907 freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider);
1908
1909 /* tmp = (freq_nom / reference_clock * reference_divider) ^ 2 Note: S.I. reference_divider = 1*/
1910 tmp = (freq_nom / reference_clock);
1911 tmp = tmp * tmp;
1912
1913 if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) {
1914 /* ss_info.speed_spectrum_percentage -- in unit of 0.01% */
1915 /* ss.Info.speed_spectrum_rate -- in unit of khz */
1916 /* CLKS = reference_clock / (2 * speed_spectrum_rate * reference_divider) * 10 */
1917 /* = reference_clock * 5 / speed_spectrum_rate */
1918 uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate;
1919
1920 /* CLKV = 65536 * speed_spectrum_percentage / 2 * spreadSpecrumRate / freq_nom * 4 / 100000 * ((freq_nom / reference_clock) ^ 2) */
1921 /* = 131 * speed_spectrum_percentage * speed_spectrum_rate / 100 * ((freq_nom / reference_clock) ^ 2) / freq_nom */
1922 uint32_t clkv =
1923 (uint32_t)((((131 * ss_info.speed_spectrum_percentage *
1924 ss_info.speed_spectrum_rate) / 100) * tmp) / freq_nom);
1925
1926 mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv);
1927 mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks);
1928 }
1929 }
1930
1931 /* MCLK_PWRMGT_CNTL setup */
1932 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1933 MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed);
1934 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1935 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, dllStateOn);
1936 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1937 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, dllStateOn);
1938
1939
1940 /* Save the result data to outpupt memory level structure */
1941 mclk->MclkFrequency = memory_clock;
1942 mclk->MpllFuncCntl = mpll_func_cntl;
1943 mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
1944 mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
1945 mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
1946 mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
1947 mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
1948 mclk->DllCntl = dll_cntl;
1949 mclk->MpllSs1 = mpll_ss1;
1950 mclk->MpllSs2 = mpll_ss2;
1951
1952 return 0;
1953}
1954
1955static uint8_t tonga_get_mclk_frequency_ratio(uint32_t memory_clock,
1956 bool strobe_mode)
1957{
1958 uint8_t mc_para_index;
1959
1960 if (strobe_mode) {
1961 if (memory_clock < 12500) {
1962 mc_para_index = 0x00;
1963 } else if (memory_clock > 47500) {
1964 mc_para_index = 0x0f;
1965 } else {
1966 mc_para_index = (uint8_t)((memory_clock - 10000) / 2500);
1967 }
1968 } else {
1969 if (memory_clock < 65000) {
1970 mc_para_index = 0x00;
1971 } else if (memory_clock > 135000) {
1972 mc_para_index = 0x0f;
1973 } else {
1974 mc_para_index = (uint8_t)((memory_clock - 60000) / 5000);
1975 }
1976 }
1977
1978 return mc_para_index;
1979}
1980
1981static uint8_t tonga_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock)
1982{
1983 uint8_t mc_para_index;
1984
1985 if (memory_clock < 10000) {
1986 mc_para_index = 0;
1987 } else if (memory_clock >= 80000) {
1988 mc_para_index = 0x0f;
1989 } else {
1990 mc_para_index = (uint8_t)((memory_clock - 10000) / 5000 + 1);
1991 }
1992
1993 return mc_para_index;
1994}
1995
1996static int tonga_populate_single_memory_level(
1997 struct pp_hwmgr *hwmgr,
1998 uint32_t memory_clock,
1999 SMU72_Discrete_MemoryLevel *memory_level
2000 )
2001{
2002 uint32_t minMvdd = 0;
2003 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2004 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2005 int result = 0;
2006 bool dllStateOn;
2007 struct cgs_display_info info = {0};
2008
2009
2010 if (NULL != pptable_info->vdd_dep_on_mclk) {
2011 result = tonga_get_dependecy_volt_by_clk(hwmgr,
2012 pptable_info->vdd_dep_on_mclk, memory_clock, &memory_level->MinVoltage, &minMvdd);
2013 PP_ASSERT_WITH_CODE((0 == result),
2014 "can not find MinVddc voltage value from memory VDDC voltage dependency table", return result);
2015 }
2016
2017 if (data->mvdd_control == TONGA_VOLTAGE_CONTROL_NONE) {
2018 memory_level->MinMvdd = data->vbios_boot_state.mvdd_bootup_value;
2019 } else {
2020 memory_level->MinMvdd = minMvdd;
2021 }
2022 memory_level->EnabledForThrottle = 1;
2023 memory_level->EnabledForActivity = 0;
2024 memory_level->UpHyst = 0;
2025 memory_level->DownHyst = 100;
2026 memory_level->VoltageDownHyst = 0;
2027
2028 /* Indicates maximum activity level for this performance level.*/
2029 memory_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
2030 memory_level->StutterEnable = 0;
2031 memory_level->StrobeEnable = 0;
2032 memory_level->EdcReadEnable = 0;
2033 memory_level->EdcWriteEnable = 0;
2034 memory_level->RttEnable = 0;
2035
2036 /* default set to low watermark. Highest level will be set to high later.*/
2037 memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2038
2039 cgs_get_active_displays_info(hwmgr->device, &info);
2040 data->display_timing.num_existing_displays = info.display_count;
2041
2042 if ((data->mclk_stutter_mode_threshold != 0) &&
7e8d1fbd
AD		 2043 (memory_clock <= data->mclk_stutter_mode_threshold) &&
2044 (data->is_uvd_enabled == 0)
2045 && (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE) & 0x1)
2046 && (data->display_timing.num_existing_displays <= 2)
2047 && (data->display_timing.num_existing_displays != 0))
c82baa28 2048 memory_level->StutterEnable = 1;
2049
2050 /* decide strobe mode*/
2051 memory_level->StrobeEnable = (data->mclk_strobe_mode_threshold != 0) &&
2052 (memory_clock <= data->mclk_strobe_mode_threshold);
2053
2054 /* decide EDC mode and memory clock ratio*/
2055 if (data->is_memory_GDDR5) {
2056 memory_level->StrobeRatio = tonga_get_mclk_frequency_ratio(memory_clock,
2057 memory_level->StrobeEnable);
2058
2059 if ((data->mclk_edc_enable_threshold != 0) &&
2060 (memory_clock > data->mclk_edc_enable_threshold)) {
2061 memory_level->EdcReadEnable = 1;
2062 }
2063
2064 if ((data->mclk_edc_wr_enable_threshold != 0) &&
2065 (memory_clock > data->mclk_edc_wr_enable_threshold)) {
2066 memory_level->EdcWriteEnable = 1;
2067 }
2068
2069 if (memory_level->StrobeEnable) {
2070 if (tonga_get_mclk_frequency_ratio(memory_clock, 1) >=
2071 ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf)) {
2072 dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
2073 } else {
2074 dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0;
2075 }
2076
2077 } else {
2078 dllStateOn = data->dll_defaule_on;
2079 }
2080 } else {
2081 memory_level->StrobeRatio =
2082 tonga_get_ddr3_mclk_frequency_ratio(memory_clock);
2083 dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
2084 }
2085
2086 result = tonga_calculate_mclk_params(hwmgr,
2087 memory_clock, memory_level, memory_level->StrobeEnable, dllStateOn);
2088
2089 if (0 == result) {
2090 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinMvdd);
2091 /* MCLK frequency in units of 10KHz*/
2092 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkFrequency);
2093 /* Indicates maximum activity level for this performance level.*/
2094 CONVERT_FROM_HOST_TO_SMC_US(memory_level->ActivityLevel);
2095 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl);
2096 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_1);
2097 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_2);
2098 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllAdFuncCntl);
2099 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllDqFuncCntl);
2100 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkPwrmgtCntl);
2101 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->DllCntl);
2102 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs1);
2103 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs2);
2104 }
2105
2106 return result;
2107}
2108
2109/**
2110 * Populates the SMC MVDD structure using the provided memory clock.
2111 *
2112 * @param hwmgr the address of the hardware manager
2113 * @param mclk the MCLK value to be used in the decision if MVDD should be high or low.
2114 * @param voltage the SMC VOLTAGE structure to be populated
2115 */
2116int tonga_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk, SMIO_Pattern *smio_pattern)
2117{
2118 const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2119 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2120 uint32_t i = 0;
2121
2122 if (TONGA_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
2123 /* find mvdd value which clock is more than request */
2124 for (i = 0; i < pptable_info->vdd_dep_on_mclk->count; i++) {
2125 if (mclk <= pptable_info->vdd_dep_on_mclk->entries[i].clk) {
2126 /* Always round to higher voltage. */
2127 smio_pattern->Voltage = data->mvdd_voltage_table.entries[i].value;
2128 break;
2129 }
2130 }
2131
2132 PP_ASSERT_WITH_CODE(i < pptable_info->vdd_dep_on_mclk->count,
2133 "MVDD Voltage is outside the supported range.", return -1);
2134
2135 } else {
2136 return -1;
2137 }
2138
2139 return 0;
2140}
2141
2142
2143static int tonga_populate_smv_acpi_level(struct pp_hwmgr *hwmgr,
2144 SMU72_Discrete_DpmTable *table)
2145{
2146 int result = 0;
2147 const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2148 pp_atomctrl_clock_dividers_vi dividers;
2149 SMIO_Pattern voltage_level;
2150 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
2151 uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
2152 uint32_t dll_cntl = data->clock_registers.vDLL_CNTL;
2153 uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
2154
2155 /* The ACPI state should not do DPM on DC (or ever).*/
2156 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
2157
2158 table->ACPILevel.MinVoltage = data->smc_state_table.GraphicsLevel[0].MinVoltage;
2159
2160 /* assign zero for now*/
2161 table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);
2162
2163 /* get the engine clock dividers for this clock value*/
2164 result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
2165 table->ACPILevel.SclkFrequency, &dividers);
2166
2167 PP_ASSERT_WITH_CODE(result == 0,
2168 "Error retrieving Engine Clock dividers from VBIOS.", return result);
2169
2170 /* divider ID for required SCLK*/
2171 table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
2172 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2173 table->ACPILevel.DeepSleepDivId = 0;
2174
2175 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
2176 CG_SPLL_FUNC_CNTL, SPLL_PWRON, 0);
2177 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
2178 CG_SPLL_FUNC_CNTL, SPLL_RESET, 1);
2179 spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2,
2180 CG_SPLL_FUNC_CNTL_2, SCLK_MUX_SEL, 4);
2181
2182 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
2183 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
2184 table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
2185 table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
2186 table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
2187 table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
2188 table->ACPILevel.CcPwrDynRm = 0;
2189 table->ACPILevel.CcPwrDynRm1 = 0;
2190
2191
2192 /* For various features to be enabled/disabled while this level is active.*/
2193 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
2194 /* SCLK frequency in units of 10KHz*/
2195 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
2196 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
2197 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
2198 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
2199 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
2200 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
2201 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
2202 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
2203 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
2204
2205 /* table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;*/
2206 table->MemoryACPILevel.MinVoltage = data->smc_state_table.MemoryLevel[0].MinVoltage;
2207
2208 /* CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);*/
2209
2210 if (0 == tonga_populate_mvdd_value(hwmgr, 0, &voltage_level))
2211 table->MemoryACPILevel.MinMvdd =
2212 PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE);
2213 else
2214 table->MemoryACPILevel.MinMvdd = 0;
2215
2216 /* Force reset on DLL*/
2217 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
2218 MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1);
2219 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
2220 MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1);
2221
2222 /* Disable DLL in ACPIState*/
2223 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
2224 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0);
2225 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
2226 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0);
2227
2228 /* Enable DLL bypass signal*/
2229 dll_cntl = PHM_SET_FIELD(dll_cntl,
2230 DLL_CNTL, MRDCK0_BYPASS, 0);
2231 dll_cntl = PHM_SET_FIELD(dll_cntl,
2232 DLL_CNTL, MRDCK1_BYPASS, 0);
2233
2234 table->MemoryACPILevel.DllCntl =
2235 PP_HOST_TO_SMC_UL(dll_cntl);
2236 table->MemoryACPILevel.MclkPwrmgtCntl =
2237 PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl);
2238 table->MemoryACPILevel.MpllAdFuncCntl =
2239 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_AD_FUNC_CNTL);
2240 table->MemoryACPILevel.MpllDqFuncCntl =
2241 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_DQ_FUNC_CNTL);
2242 table->MemoryACPILevel.MpllFuncCntl =
2243 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL);
2244 table->MemoryACPILevel.MpllFuncCntl_1 =
2245 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_1);
2246 table->MemoryACPILevel.MpllFuncCntl_2 =
2247 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_2);
2248 table->MemoryACPILevel.MpllSs1 =
2249 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS1);
2250 table->MemoryACPILevel.MpllSs2 =
2251 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2);
2252
2253 table->MemoryACPILevel.EnabledForThrottle = 0;
2254 table->MemoryACPILevel.EnabledForActivity = 0;
2255 table->MemoryACPILevel.UpHyst = 0;
2256 table->MemoryACPILevel.DownHyst = 100;
2257 table->MemoryACPILevel.VoltageDownHyst = 0;
2258 /* Indicates maximum activity level for this performance level.*/
2259 table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
2260
2261 table->MemoryACPILevel.StutterEnable = 0;
2262 table->MemoryACPILevel.StrobeEnable = 0;
2263 table->MemoryACPILevel.EdcReadEnable = 0;
2264 table->MemoryACPILevel.EdcWriteEnable = 0;
2265 table->MemoryACPILevel.RttEnable = 0;
2266
2267 return result;
2268}
2269
2270static int tonga_find_boot_level(struct tonga_single_dpm_table *table, uint32_t value, uint32_t *boot_level)
2271{
2272 int result = 0;
2273 uint32_t i;
2274
2275 for (i = 0; i < table->count; i++) {
2276 if (value == table->dpm_levels[i].value) {
2277 *boot_level = i;
2278 result = 0;
2279 }
2280 }
2281 return result;
2282}
2283
2284static int tonga_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
2285 SMU72_Discrete_DpmTable *table)
2286{
2287 int result = 0;
2288 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2289
2290 table->GraphicsBootLevel = 0; /* 0 == DPM[0] (low), etc. */
2291 table->MemoryBootLevel = 0; /* 0 == DPM[0] (low), etc. */
2292
2293 /* find boot level from dpm table*/
2294 result = tonga_find_boot_level(&(data->dpm_table.sclk_table),
2295 data->vbios_boot_state.sclk_bootup_value,
2296 (uint32_t *)&(data->smc_state_table.GraphicsBootLevel));
2297
2298 if (0 != result) {
2299 data->smc_state_table.GraphicsBootLevel = 0;
2300 printk(KERN_ERR "[ powerplay ] VBIOS did not find boot engine clock value \
2301 in dependency table. Using Graphics DPM level 0!");
2302 result = 0;
2303 }
2304
2305 result = tonga_find_boot_level(&(data->dpm_table.mclk_table),
2306 data->vbios_boot_state.mclk_bootup_value,
2307 (uint32_t *)&(data->smc_state_table.MemoryBootLevel));
2308
2309 if (0 != result) {
2310 data->smc_state_table.MemoryBootLevel = 0;
2311 printk(KERN_ERR "[ powerplay ] VBIOS did not find boot engine clock value \
2312 in dependency table. Using Memory DPM level 0!");
2313 result = 0;
2314 }
2315
2316 table->BootVoltage.Vddc =
2317 tonga_get_voltage_id(&(data->vddc_voltage_table),
2318 data->vbios_boot_state.vddc_bootup_value);
2319 table->BootVoltage.VddGfx =
2320 tonga_get_voltage_id(&(data->vddgfx_voltage_table),
2321 data->vbios_boot_state.vddgfx_bootup_value);
2322 table->BootVoltage.Vddci =
2323 tonga_get_voltage_id(&(data->vddci_voltage_table),
2324 data->vbios_boot_state.vddci_bootup_value);
2325 table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value;
2326
2327 CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
2328
2329 return result;
2330}
2331
2332
2333/**
2334 * Calculates the SCLK dividers using the provided engine clock
2335 *
2336 * @param hwmgr the address of the hardware manager
2337 * @param engine_clock the engine clock to use to populate the structure
2338 * @param sclk the SMC SCLK structure to be populated
2339 */
2340int tonga_calculate_sclk_params(struct pp_hwmgr *hwmgr,
2341 uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *sclk)
2342{
2343 const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2344 pp_atomctrl_clock_dividers_vi dividers;
2345 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
2346 uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
2347 uint32_t spll_func_cntl_4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
2348 uint32_t cg_spll_spread_spectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
2349 uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
2350 uint32_t reference_clock;
2351 uint32_t reference_divider;
2352 uint32_t fbdiv;
2353 int result;
2354
2355 /* get the engine clock dividers for this clock value*/
2356 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, &dividers);
2357
2358 PP_ASSERT_WITH_CODE(result == 0,
2359 "Error retrieving Engine Clock dividers from VBIOS.", return result);
2360
2361 /* To get FBDIV we need to multiply this by 16384 and divide it by Fref.*/
2362 reference_clock = atomctrl_get_reference_clock(hwmgr);
2363
2364 reference_divider = 1 + dividers.uc_pll_ref_div;
2365
2366 /* low 14 bits is fraction and high 12 bits is divider*/
2367 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
2368
2369 /* SPLL_FUNC_CNTL setup*/
2370 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
2371 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div);
2372 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
2373 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div);
2374
2375 /* SPLL_FUNC_CNTL_3 setup*/
2376 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
2377 CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv);
2378
2379 /* set to use fractional accumulation*/
2380 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
2381 CG_SPLL_FUNC_CNTL_3, SPLL_DITHEN, 1);
2382
2383 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2384 PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
2385 pp_atomctrl_internal_ss_info ss_info;
2386
2387 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;
2388 if (0 == atomctrl_get_engine_clock_spread_spectrum(hwmgr, vcoFreq, &ss_info)) {
2389 /*
2390 * ss_info.speed_spectrum_percentage -- in unit of 0.01%
2391 * ss_info.speed_spectrum_rate -- in unit of khz
2392 */
2393 /* clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2 */
2394 uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate);
2395
2396 /* clkv = 2 * D * fbdiv / NS */
2397 uint32_t clkV = 4 * ss_info.speed_spectrum_percentage * fbdiv / (clkS * 10000);
2398
2399 cg_spll_spread_spectrum =
2400 PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, CLKS, clkS);
2401 cg_spll_spread_spectrum =
2402 PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
2403 cg_spll_spread_spectrum_2 =
2404 PHM_SET_FIELD(cg_spll_spread_spectrum_2, CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clkV);
2405 }
2406 }
2407
2408 sclk->SclkFrequency = engine_clock;
2409 sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
2410 sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
2411 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
2412 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
2413 sclk->SclkDid = (uint8_t)dividers.pll_post_divider;
2414
2415 return 0;
2416}
2417
a4333b4c
EH		 2418static uint8_t tonga_get_sleep_divider_id_from_clock(struct pp_hwmgr *hwmgr,
2419 uint32_t engine_clock, uint32_t min_engine_clock_in_sr)
2420{
2421 uint32_t i, temp;
2422 uint32_t min = (min_engine_clock_in_sr > TONGA_MINIMUM_ENGINE_CLOCK) ?
2423 min_engine_clock_in_sr : TONGA_MINIMUM_ENGINE_CLOCK;
2424
2425 PP_ASSERT_WITH_CODE((engine_clock >= min),
2426 "Engine clock can't satisfy stutter requirement!", return 0);
2427
2428 for (i = TONGA_MAX_DEEPSLEEP_DIVIDER_ID;; i--) {
2429 temp = engine_clock / (1 << i);
2430
2431 if(temp >= min || i == 0)
2432 break;
2433 }
2434 return (uint8_t)i;
2435}
2436
c82baa28 2437/**
2438 * Populates single SMC SCLK structure using the provided engine clock
2439 *
2440 * @param hwmgr the address of the hardware manager
2441 * @param engine_clock the engine clock to use to populate the structure
2442 * @param sclk the SMC SCLK structure to be populated
2443 */
2444static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint16_t sclk_activity_level_threshold, SMU72_Discrete_GraphicsLevel *graphic_level)
2445{
2446 int result;
2447 uint32_t threshold;
2448 uint32_t mvdd;
2449 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2450 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2451
2452 result = tonga_calculate_sclk_params(hwmgr, engine_clock, graphic_level);
2453
2454
2455 /* populate graphics levels*/
2456 result = tonga_get_dependecy_volt_by_clk(hwmgr,
2457 pptable_info->vdd_dep_on_sclk, engine_clock,
2458 &graphic_level->MinVoltage, &mvdd);
2459 PP_ASSERT_WITH_CODE((0 == result),
2460 "can not find VDDC voltage value for VDDC \
2461 engine clock dependency table", return result);
2462
2463 /* SCLK frequency in units of 10KHz*/
2464 graphic_level->SclkFrequency = engine_clock;
2465
2466 /* Indicates maximum activity level for this performance level. 50% for now*/
2467 graphic_level->ActivityLevel = sclk_activity_level_threshold;
2468
2469 graphic_level->CcPwrDynRm = 0;
2470 graphic_level->CcPwrDynRm1 = 0;
2471 /* this level can be used if activity is high enough.*/
2472 graphic_level->EnabledForActivity = 0;
2473 /* this level can be used for throttling.*/
2474 graphic_level->EnabledForThrottle = 1;
2475 graphic_level->UpHyst = 0;
2476 graphic_level->DownHyst = 0;
2477 graphic_level->VoltageDownHyst = 0;
2478 graphic_level->PowerThrottle = 0;
2479
2480 threshold = engine_clock * data->fast_watemark_threshold / 100;
2481/*
2482 *get the DAL clock. do it in funture.
2483 PECI_GetMinClockSettings(hwmgr->peci, &minClocks);
2484 data->display_timing.min_clock_insr = minClocks.engineClockInSR;
c82baa28 2485*/
a4333b4c
EH		 2486 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2487 PHM_PlatformCaps_SclkDeepSleep))
2488 graphic_level->DeepSleepDivId =
2489 tonga_get_sleep_divider_id_from_clock(hwmgr, engine_clock,
2490 data->display_timing.min_clock_insr);
c82baa28 2491
2492 /* Default to slow, highest DPM level will be set to PPSMC_DISPLAY_WATERMARK_LOW later.*/
2493 graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2494
2495 if (0 == result) {
2496 /* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVoltage);*/
2497 /* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVddcPhases);*/
2498 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SclkFrequency);
2499 CONVERT_FROM_HOST_TO_SMC_US(graphic_level->ActivityLevel);
2500 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl3);
2501 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl4);
2502 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum);
2503 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum2);
2504 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm);
2505 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm1);
2506 }
2507
2508 return result;
2509}
2510
2511/**
2512 * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
2513 *
2514 * @param hwmgr the address of the hardware manager
2515 */
2516static int tonga_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
2517{
2518 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2519 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2520 struct tonga_dpm_table *dpm_table = &data->dpm_table;
2521 phm_ppt_v1_pcie_table *pcie_table = pptable_info->pcie_table;
2522 uint8_t pcie_entry_count = (uint8_t) data->dpm_table.pcie_speed_table.count;
2523 int result = 0;
2524 uint32_t level_array_adress = data->dpm_table_start +
2525 offsetof(SMU72_Discrete_DpmTable, GraphicsLevel);
2526 uint32_t level_array_size = sizeof(SMU72_Discrete_GraphicsLevel) *
2527 SMU72_MAX_LEVELS_GRAPHICS; /* 64 -> long; 32 -> int*/
2528 SMU72_Discrete_GraphicsLevel *levels = data->smc_state_table.GraphicsLevel;
2529 uint32_t i, maxEntry;
2530 uint8_t highest_pcie_level_enabled = 0, lowest_pcie_level_enabled = 0, mid_pcie_level_enabled = 0, count = 0;
2531 PECI_RegistryValue reg_value;
2532 memset(levels, 0x00, level_array_size);
2533
2534 for (i = 0; i < dpm_table->sclk_table.count; i++) {
2535 result = tonga_populate_single_graphic_level(hwmgr,
2536 dpm_table->sclk_table.dpm_levels[i].value,
2537 (uint16_t)data->activity_target[i],
2538 &(data->smc_state_table.GraphicsLevel[i]));
2539
2540 if (0 != result)
2541 return result;
2542
2543 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
2544 if (i > 1)
2545 data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
2546
2547 if (0 == i) {
2548 reg_value = 0;
2549 if (reg_value != 0)
2550 data->smc_state_table.GraphicsLevel[0].UpHyst = (uint8_t)reg_value;
2551 }
2552
2553 if (1 == i) {
2554 reg_value = 0;
2555 if (reg_value != 0)
2556 data->smc_state_table.GraphicsLevel[1].UpHyst = (uint8_t)reg_value;
2557 }
2558 }
2559
2560 /* Only enable level 0 for now. */
2561 data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
2562
2563 /* set highest level watermark to high */
2564 if (dpm_table->sclk_table.count > 1)
2565 data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark =
2566 PPSMC_DISPLAY_WATERMARK_HIGH;
2567
2568 data->smc_state_table.GraphicsDpmLevelCount =
2569 (uint8_t)dpm_table->sclk_table.count;
2570 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
2571 tonga_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
2572
2573 if (pcie_table != NULL) {
2574 PP_ASSERT_WITH_CODE((pcie_entry_count >= 1),
2575 "There must be 1 or more PCIE levels defined in PPTable.", return -1);
2576 maxEntry = pcie_entry_count - 1; /* for indexing, we need to decrement by 1.*/
2577 for (i = 0; i < dpm_table->sclk_table.count; i++) {
2578 data->smc_state_table.GraphicsLevel[i].pcieDpmLevel =
2579 (uint8_t) ((i < maxEntry) ? i : maxEntry);
2580 }
2581 } else {
2582 if (0 == data->dpm_level_enable_mask.pcie_dpm_enable_mask)
2583 printk(KERN_ERR "[ powerplay ] Pcie Dpm Enablemask is 0!");
2584
2585 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
2586 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2587 (1<<(highest_pcie_level_enabled+1))) != 0)) {
2588 highest_pcie_level_enabled++;
2589 }
2590
2591 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
2592 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2593 (1<<lowest_pcie_level_enabled)) == 0)) {
2594 lowest_pcie_level_enabled++;
2595 }
2596
2597 while ((count < highest_pcie_level_enabled) &&
2598 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2599 (1<<(lowest_pcie_level_enabled+1+count))) == 0)) {
2600 count++;
2601 }
2602 mid_pcie_level_enabled = (lowest_pcie_level_enabled+1+count) < highest_pcie_level_enabled ?
2603 (lowest_pcie_level_enabled+1+count) : highest_pcie_level_enabled;
2604
2605
2606 /* set pcieDpmLevel to highest_pcie_level_enabled*/
2607 for (i = 2; i < dpm_table->sclk_table.count; i++) {
2608 data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled;
2609 }
2610
2611 /* set pcieDpmLevel to lowest_pcie_level_enabled*/
2612 data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled;
2613
2614 /* set pcieDpmLevel to mid_pcie_level_enabled*/
2615 data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled;
2616 }
2617 /* level count will send to smc once at init smc table and never change*/
2618 result = tonga_copy_bytes_to_smc(hwmgr->smumgr, level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size, data->sram_end);
2619
2620 if (0 != result)
2621 return result;
2622
2623 return 0;
2624}
2625
2626/**
2627 * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
2628 *
2629 * @param hwmgr the address of the hardware manager
2630 */
2631
2632static int tonga_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
2633{
2634 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2635 struct tonga_dpm_table *dpm_table = &data->dpm_table;
2636 int result;
2637 /* populate MCLK dpm table to SMU7 */
2638 uint32_t level_array_adress = data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable, MemoryLevel);
2639 uint32_t level_array_size = sizeof(SMU72_Discrete_MemoryLevel) * SMU72_MAX_LEVELS_MEMORY;
2640 SMU72_Discrete_MemoryLevel *levels = data->smc_state_table.MemoryLevel;
2641 uint32_t i;
2642
2643 memset(levels, 0x00, level_array_size);
2644
2645 for (i = 0; i < dpm_table->mclk_table.count; i++) {
2646 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
2647 "can not populate memory level as memory clock is zero", return -1);
2648 result = tonga_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value,
2649 &(data->smc_state_table.MemoryLevel[i]));
2650 if (0 != result) {
2651 return result;
2652 }
2653 }
2654
2655 /* Only enable level 0 for now.*/
2656 data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
2657
2658 /*
2659 * in order to prevent MC activity from stutter mode to push DPM up.
2660 * the UVD change complements this by putting the MCLK in a higher state
2661 * by default such that we are not effected by up threshold or and MCLK DPM latency.
2662 */
2663 data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F;
2664 CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.MemoryLevel[0].ActivityLevel);
2665
2666 data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count;
2667 data->dpm_level_enable_mask.mclk_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
2668 /* set highest level watermark to high*/
2669 data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
2670
2671 /* level count will send to smc once at init smc table and never change*/
2672 result = tonga_copy_bytes_to_smc(hwmgr->smumgr,
2673 level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size, data->sram_end);
2674
2675 if (0 != result) {
2676 return result;
2677 }
2678
2679 return 0;
2680}
2681
2682struct TONGA_DLL_SPEED_SETTING {
2683 uint16_t Min; /* Minimum Data Rate*/
2684 uint16_t Max; /* Maximum Data Rate*/
2685 uint32_t dll_speed; /* The desired DLL_SPEED setting*/
2686};
2687
2688static int tonga_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
2689{
2690 return 0;
2691}
2692
2693/* ---------------------------------------- ULV related functions ----------------------------------------------------*/
2694
2695
2696static int tonga_reset_single_dpm_table(
2697 struct pp_hwmgr *hwmgr,
2698 struct tonga_single_dpm_table *dpm_table,
2699 uint32_t count)
2700{
2701 uint32_t i;
2702 if (!(count <= MAX_REGULAR_DPM_NUMBER))
2703 printk(KERN_ERR "[ powerplay ] Fatal error, can not set up single DPM \
2704 table entries to exceed max number! \n");
2705
2706 dpm_table->count = count;
2707 for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++) {
2708 dpm_table->dpm_levels[i].enabled = 0;
2709 }
2710
2711 return 0;
2712}
2713
2714static void tonga_setup_pcie_table_entry(
2715 struct tonga_single_dpm_table *dpm_table,
2716 uint32_t index, uint32_t pcie_gen,
2717 uint32_t pcie_lanes)
2718{
2719 dpm_table->dpm_levels[index].value = pcie_gen;
2720 dpm_table->dpm_levels[index].param1 = pcie_lanes;
2721 dpm_table->dpm_levels[index].enabled = 1;
2722}
2723
c82baa28 2724static int tonga_setup_default_pcie_tables(struct pp_hwmgr *hwmgr)
2725{
2726 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2727 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2728 phm_ppt_v1_pcie_table *pcie_table = pptable_info->pcie_table;
2729 uint32_t i, maxEntry;
2730
2731 if (data->use_pcie_performance_levels && !data->use_pcie_power_saving_levels) {
2732 data->pcie_gen_power_saving = data->pcie_gen_performance;
2733 data->pcie_lane_power_saving = data->pcie_lane_performance;
2734 } else if (!data->use_pcie_performance_levels && data->use_pcie_power_saving_levels) {
2735 data->pcie_gen_performance = data->pcie_gen_power_saving;
2736 data->pcie_lane_performance = data->pcie_lane_power_saving;
2737 }
2738
2739 tonga_reset_single_dpm_table(hwmgr, &data->dpm_table.pcie_speed_table, SMU72_MAX_LEVELS_LINK);
2740
2741 if (pcie_table != NULL) {
2742 /*
2743 * maxEntry is used to make sure we reserve one PCIE level for boot level (fix for A+A PSPP issue).
2744 * If PCIE table from PPTable have ULV entry + 8 entries, then ignore the last entry.
2745 */
2746 maxEntry = (SMU72_MAX_LEVELS_LINK < pcie_table->count) ?
2747 SMU72_MAX_LEVELS_LINK : pcie_table->count;
2748 for (i = 1; i < maxEntry; i++) {
2749 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i-1,
2750 get_pcie_gen_support(data->pcie_gen_cap, pcie_table->entries[i].gen_speed),
2751 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2752 }
2753 data->dpm_table.pcie_speed_table.count = maxEntry - 1;
2754 } else {
2755 /* Hardcode Pcie Table */
2756 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
2757 get_pcie_gen_support(data->pcie_gen_cap, PP_Min_PCIEGen),
2758 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2759 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
2760 get_pcie_gen_support(data->pcie_gen_cap, PP_Min_PCIEGen),
2761 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2762 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
2763 get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen),
2764 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2765 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
2766 get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen),
2767 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2768 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
2769 get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen),
2770 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2771 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
2772 get_pcie_gen_support(data->pcie_gen_cap, PP_Max_PCIEGen),
2773 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2774 data->dpm_table.pcie_speed_table.count = 6;
2775 }
2776 /* Populate last level for boot PCIE level, but do not increment count. */
2777 tonga_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
2778 data->dpm_table.pcie_speed_table.count,
2779 get_pcie_gen_support(data->pcie_gen_cap, PP_Min_PCIEGen),
2780 get_pcie_lane_support(data->pcie_lane_cap, PP_Max_PCIELane));
2781
2782 return 0;
2783
2784}
2785
2786/*
2787 * This function is to initalize all DPM state tables for SMU7 based on the dependency table.
2788 * Dynamic state patching function will then trim these state tables to the allowed range based
2789 * on the power policy or external client requests, such as UVD request, etc.
2790 */
2791static int tonga_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
2792{
2793 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2794 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2795 uint32_t i;
2796
2797 phm_ppt_v1_clock_voltage_dependency_table *allowed_vdd_sclk_table =
2798 pptable_info->vdd_dep_on_sclk;
2799 phm_ppt_v1_clock_voltage_dependency_table *allowed_vdd_mclk_table =
2800 pptable_info->vdd_dep_on_mclk;
2801
2802 PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL,
2803 "SCLK dependency table is missing. This table is mandatory", return -1);
2804 PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table->count >= 1,
2805 "SCLK dependency table has to have is missing. This table is mandatory", return -1);
2806
2807 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
2808 "MCLK dependency table is missing. This table is mandatory", return -1);
2809 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table->count >= 1,
2810 "VMCLK dependency table has to have is missing. This table is mandatory", return -1);
2811
2812 /* clear the state table to reset everything to default */
2813 memset(&(data->dpm_table), 0x00, sizeof(data->dpm_table));
2814 tonga_reset_single_dpm_table(hwmgr, &data->dpm_table.sclk_table, SMU72_MAX_LEVELS_GRAPHICS);
2815 tonga_reset_single_dpm_table(hwmgr, &data->dpm_table.mclk_table, SMU72_MAX_LEVELS_MEMORY);
2816 /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.VddcTable, SMU72_MAX_LEVELS_VDDC); */
2817 /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.vdd_gfx_table, SMU72_MAX_LEVELS_VDDGFX);*/
2818 /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.vdd_ci_table, SMU72_MAX_LEVELS_VDDCI);*/
2819 /* tonga_reset_single_dpm_table(hwmgr, &tonga_hwmgr->dpm_table.mvdd_table, SMU72_MAX_LEVELS_MVDD);*/
2820
2821 PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL,
2822 "SCLK dependency table is missing. This table is mandatory", return -1);
2823 /* Initialize Sclk DPM table based on allow Sclk values*/
2824 data->dpm_table.sclk_table.count = 0;
2825
2826 for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
2827 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value !=
2828 allowed_vdd_sclk_table->entries[i].clk) {
2829 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
2830 allowed_vdd_sclk_table->entries[i].clk;
2831 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = 1; /*(i==0) ? 1 : 0; to do */
2832 data->dpm_table.sclk_table.count++;
2833 }
2834 }
2835
2836 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
2837 "MCLK dependency table is missing. This table is mandatory", return -1);
2838 /* Initialize Mclk DPM table based on allow Mclk values */
2839 data->dpm_table.mclk_table.count = 0;
2840 for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
2841 if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value !=
2842 allowed_vdd_mclk_table->entries[i].clk) {
2843 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
2844 allowed_vdd_mclk_table->entries[i].clk;
2845 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = 1; /*(i==0) ? 1 : 0; */
2846 data->dpm_table.mclk_table.count++;
2847 }
2848 }
2849
2850 /* Initialize Vddc DPM table based on allow Vddc values. And populate corresponding std values. */
2851 for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
2852 data->dpm_table.vddc_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].vddc;
2853 /* tonga_hwmgr->dpm_table.VddcTable.dpm_levels[i].param1 = stdVoltageTable->entries[i].Leakage; */
2854 /* param1 is for corresponding std voltage */
2855 data->dpm_table.vddc_table.dpm_levels[i].enabled = 1;
2856 }
2857 data->dpm_table.vddc_table.count = allowed_vdd_sclk_table->count;
2858
2859 if (NULL != allowed_vdd_mclk_table) {
2860 /* Initialize Vddci DPM table based on allow Mclk values */
2861 for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
2862 data->dpm_table.vdd_ci_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].vddci;
2863 data->dpm_table.vdd_ci_table.dpm_levels[i].enabled = 1;
2864 data->dpm_table.mvdd_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].mvdd;
2865 data->dpm_table.mvdd_table.dpm_levels[i].enabled = 1;
2866 }
2867 data->dpm_table.vdd_ci_table.count = allowed_vdd_mclk_table->count;
2868 data->dpm_table.mvdd_table.count = allowed_vdd_mclk_table->count;
2869 }
2870
2871 /* setup PCIE gen speed levels*/
2872 tonga_setup_default_pcie_tables(hwmgr);
2873
2874 /* save a copy of the default DPM table*/
2875 memcpy(&(data->golden_dpm_table), &(data->dpm_table), sizeof(struct tonga_dpm_table));
2876
2877 return 0;
2878}
2879
2880int tonga_populate_smc_initial_state(struct pp_hwmgr *hwmgr,
2881 const struct tonga_power_state *bootState)
2882{
2883 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2884 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2885 uint8_t count, level;
2886
2887 count = (uint8_t) (pptable_info->vdd_dep_on_sclk->count);
2888 for (level = 0; level < count; level++) {
2889 if (pptable_info->vdd_dep_on_sclk->entries[level].clk >=
2890 bootState->performance_levels[0].engine_clock) {
2891 data->smc_state_table.GraphicsBootLevel = level;
2892 break;
2893 }
2894 }
2895
2896 count = (uint8_t) (pptable_info->vdd_dep_on_mclk->count);
2897 for (level = 0; level < count; level++) {
2898 if (pptable_info->vdd_dep_on_mclk->entries[level].clk >=
2899 bootState->performance_levels[0].memory_clock) {
2900 data->smc_state_table.MemoryBootLevel = level;
2901 break;
2902 }
2903 }
2904
2905 return 0;
2906}
2907
2908/**
2909 * Initializes the SMC table and uploads it
2910 *
2911 * @param hwmgr the address of the powerplay hardware manager.
2912 * @param pInput the pointer to input data (PowerState)
2913 * @return always 0
2914 */
2915int tonga_init_smc_table(struct pp_hwmgr *hwmgr)
2916{
2917 int result;
2918 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
2919 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
2920 SMU72_Discrete_DpmTable *table = &(data->smc_state_table);
2921 const phw_tonga_ulv_parm *ulv = &(data->ulv);
2922 uint8_t i;
2923 PECI_RegistryValue reg_value;
2924 pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
2925
2926 result = tonga_setup_default_dpm_tables(hwmgr);
2927 PP_ASSERT_WITH_CODE(0 == result,
2928 "Failed to setup default DPM tables!", return result;);
2929 memset(&(data->smc_state_table), 0x00, sizeof(data->smc_state_table));
2930 if (TONGA_VOLTAGE_CONTROL_NONE != data->voltage_control) {
2931 tonga_populate_smc_voltage_tables(hwmgr, table);
2932 }
2933
2934 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2935 PHM_PlatformCaps_AutomaticDCTransition)) {
2936 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
2937 }
2938
2939 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2940 PHM_PlatformCaps_StepVddc)) {
2941 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
2942 }
2943
2944 if (data->is_memory_GDDR5) {
2945 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
2946 }
2947
2948 i = PHM_READ_FIELD(hwmgr->device, CC_MC_MAX_CHANNEL, NOOFCHAN);
2949
2950 if (i == 1 || i == 0) {
2951 table->SystemFlags |= PPSMC_SYSTEMFLAG_12CHANNEL;
2952 }
2953
2954 if (ulv->ulv_supported && pptable_info->us_ulv_voltage_offset) {
2955 PP_ASSERT_WITH_CODE(0 == result,
2956 "Failed to initialize ULV state!", return result;);
2957
2958 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2959 ixCG_ULV_PARAMETER, ulv->ch_ulv_parameter);
2960 }
2961
2962 result = tonga_populate_smc_link_level(hwmgr, table);
2963 PP_ASSERT_WITH_CODE(0 == result,
2964 "Failed to initialize Link Level!", return result;);
2965
2966 result = tonga_populate_all_graphic_levels(hwmgr);
2967 PP_ASSERT_WITH_CODE(0 == result,
2968 "Failed to initialize Graphics Level!", return result;);
2969
2970 result = tonga_populate_all_memory_levels(hwmgr);
2971 PP_ASSERT_WITH_CODE(0 == result,
2972 "Failed to initialize Memory Level!", return result;);
2973
2974 result = tonga_populate_smv_acpi_level(hwmgr, table);
2975 PP_ASSERT_WITH_CODE(0 == result,
2976 "Failed to initialize ACPI Level!", return result;);
2977
2978 result = tonga_populate_smc_vce_level(hwmgr, table);
2979 PP_ASSERT_WITH_CODE(0 == result,
2980 "Failed to initialize VCE Level!", return result;);
2981
2982 result = tonga_populate_smc_acp_level(hwmgr, table);
2983 PP_ASSERT_WITH_CODE(0 == result,
2984 "Failed to initialize ACP Level!", return result;);
2985
2986 result = tonga_populate_smc_samu_level(hwmgr, table);
2987 PP_ASSERT_WITH_CODE(0 == result,
2988 "Failed to initialize SAMU Level!", return result;);
2989
2990 /* Since only the initial state is completely set up at this point (the other states are just copies of the boot state) we only */
2991 /* need to populate the ARB settings for the initial state. */
2992 result = tonga_program_memory_timing_parameters(hwmgr);
2993 PP_ASSERT_WITH_CODE(0 == result,
2994 "Failed to Write ARB settings for the initial state.", return result;);
2995
0104aa21
AD		 2996 result = tonga_populate_smc_uvd_level(hwmgr, table);
2997 PP_ASSERT_WITH_CODE(0 == result,
2998 "Failed to initialize UVD Level!", return result;);
2999
c82baa28 3000 result = tonga_populate_smc_boot_level(hwmgr, table);
3001 PP_ASSERT_WITH_CODE(0 == result,
3002 "Failed to initialize Boot Level!", return result;);
3003
3004 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3005 PHM_PlatformCaps_ClockStretcher)) {
3006 result = tonga_populate_clock_stretcher_data_table(hwmgr);
3007 PP_ASSERT_WITH_CODE(0 == result,
3008 "Failed to populate Clock Stretcher Data Table!", return result;);
3009 }
3010 table->GraphicsVoltageChangeEnable = 1;
3011 table->GraphicsThermThrottleEnable = 1;
3012 table->GraphicsInterval = 1;
3013 table->VoltageInterval = 1;
3014 table->ThermalInterval = 1;
3015 table->TemperatureLimitHigh =
3016 pptable_info->cac_dtp_table->usTargetOperatingTemp *
3017 TONGA_Q88_FORMAT_CONVERSION_UNIT;
3018 table->TemperatureLimitLow =
3019 (pptable_info->cac_dtp_table->usTargetOperatingTemp - 1) *
3020 TONGA_Q88_FORMAT_CONVERSION_UNIT;
3021 table->MemoryVoltageChangeEnable = 1;
3022 table->MemoryInterval = 1;
3023 table->VoltageResponseTime = 0;
3024 table->PhaseResponseTime = 0;
3025 table->MemoryThermThrottleEnable = 1;
3026
3027 /*
3028 * Cail reads current link status and reports it as cap (we cannot change this due to some previous issues we had)
3029 * SMC drops the link status to lowest level after enabling DPM by PowerPlay. After pnp or toggling CF, driver gets reloaded again
3030 * but this time Cail reads current link status which was set to low by SMC and reports it as cap to powerplay
3031 * To avoid it, we set PCIeBootLinkLevel to highest dpm level
3032 */
3033 PP_ASSERT_WITH_CODE((1 <= data->dpm_table.pcie_speed_table.count),
3034 "There must be 1 or more PCIE levels defined in PPTable.",
3035 return -1);
3036
3037 table->PCIeBootLinkLevel = (uint8_t) (data->dpm_table.pcie_speed_table.count);
3038
3039 table->PCIeGenInterval = 1;
3040
3041 result = tonga_populate_vr_config(hwmgr, table);
3042 PP_ASSERT_WITH_CODE(0 == result,
3043 "Failed to populate VRConfig setting!", return result);
3044
3045 table->ThermGpio = 17;
3046 table->SclkStepSize = 0x4000;
3047
3048 reg_value = 0;
3049 if ((0 == reg_value) &&
3050 (0 == atomctrl_get_pp_assign_pin(hwmgr,
3051 VDDC_VRHOT_GPIO_PINID, &gpio_pin_assignment))) {
3052 table->VRHotGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
3053 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3054 PHM_PlatformCaps_RegulatorHot);
3055 } else {
3056 table->VRHotGpio = TONGA_UNUSED_GPIO_PIN;
3057 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3058 PHM_PlatformCaps_RegulatorHot);
3059 }
3060
3061 /* ACDC Switch GPIO */
3062 reg_value = 0;
3063 if ((0 == reg_value) &&
3064 (0 == atomctrl_get_pp_assign_pin(hwmgr,
3065 PP_AC_DC_SWITCH_GPIO_PINID, &gpio_pin_assignment))) {
3066 table->AcDcGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
3067 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3068 PHM_PlatformCaps_AutomaticDCTransition);
3069 } else {
3070 table->AcDcGpio = TONGA_UNUSED_GPIO_PIN;
3071 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3072 PHM_PlatformCaps_AutomaticDCTransition);
3073 }
3074
3075 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3076 PHM_PlatformCaps_Falcon_QuickTransition);
3077
3078 reg_value = 0;
3079 if (1 == reg_value) {
3080 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3081 PHM_PlatformCaps_AutomaticDCTransition);
3082 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3083 PHM_PlatformCaps_Falcon_QuickTransition);
3084 }
3085
3086 reg_value = 0;
3087 if ((0 == reg_value) &&
3088 (0 == atomctrl_get_pp_assign_pin(hwmgr,
3089 THERMAL_INT_OUTPUT_GPIO_PINID, &gpio_pin_assignment))) {
3090 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3091 PHM_PlatformCaps_ThermalOutGPIO);
3092
3093 table->ThermOutGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
3094
3095 table->ThermOutPolarity =
3096 (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
3097 (1 << gpio_pin_assignment.uc_gpio_pin_bit_shift))) ? 1:0;
3098
3099 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
3100
3101 /* if required, combine VRHot/PCC with thermal out GPIO*/
3102 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3103 PHM_PlatformCaps_RegulatorHot) &&
3104 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3105 PHM_PlatformCaps_CombinePCCWithThermalSignal)){
3106 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
3107 }
3108 } else {
3109 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3110 PHM_PlatformCaps_ThermalOutGPIO);
3111
3112 table->ThermOutGpio = 17;
3113 table->ThermOutPolarity = 1;
3114 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
3115 }
3116
3117 for (i = 0; i < SMU72_MAX_ENTRIES_SMIO; i++) {
3118 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
3119 }
3120 CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
3121 CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
3122 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
3123 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
3124 CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
3125 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
3126 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
3127 CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
3128 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
3129
3130 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
3131 result = tonga_copy_bytes_to_smc(hwmgr->smumgr, data->dpm_table_start +
3132 offsetof(SMU72_Discrete_DpmTable, SystemFlags),
3133 (uint8_t *)&(table->SystemFlags),
3134 sizeof(SMU72_Discrete_DpmTable)-3 * sizeof(SMU72_PIDController),
3135 data->sram_end);
3136
3137 PP_ASSERT_WITH_CODE(0 == result,
3138 "Failed to upload dpm data to SMC memory!", return result;);
3139
3140 return result;
3141}
3142
3143/* Look up the voltaged based on DAL's requested level. and then send the requested VDDC voltage to SMC*/
3144static void tonga_apply_dal_minimum_voltage_request(struct pp_hwmgr *hwmgr)
3145{
3146 return;
3147}
3148
3149int tonga_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
3150{
3151 PPSMC_Result result;
3152 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3153
3154 /* Apply minimum voltage based on DAL's request level */
3155 tonga_apply_dal_minimum_voltage_request(hwmgr);
3156
3157 if (0 == data->sclk_dpm_key_disabled) {
3158 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
3159 if (0 != tonga_is_dpm_running(hwmgr))
3160 printk(KERN_ERR "[ powerplay ] Trying to set Enable Mask when DPM is disabled \n");
3161
3162 if (0 != data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3163 result = smum_send_msg_to_smc_with_parameter(
3164 hwmgr->smumgr,
3165 (PPSMC_Msg)PPSMC_MSG_SCLKDPM_SetEnabledMask,
3166 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3167 PP_ASSERT_WITH_CODE((0 == result),
3168 "Set Sclk Dpm enable Mask failed", return -1);
3169 }
3170 }
3171
3172 if (0 == data->mclk_dpm_key_disabled) {
3173 /* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
3174 if (0 != tonga_is_dpm_running(hwmgr))
3175 printk(KERN_ERR "[ powerplay ] Trying to set Enable Mask when DPM is disabled \n");
3176
3177 if (0 != data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3178 result = smum_send_msg_to_smc_with_parameter(
3179 hwmgr->smumgr,
3180 (PPSMC_Msg)PPSMC_MSG_MCLKDPM_SetEnabledMask,
3181 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3182 PP_ASSERT_WITH_CODE((0 == result),
3183 "Set Mclk Dpm enable Mask failed", return -1);
3184 }
3185 }
3186
3187 return 0;
3188}
3189
3190
3191int tonga_force_dpm_highest(struct pp_hwmgr *hwmgr)
3192{
3193 uint32_t level, tmp;
3194 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3195
3196 if (0 == data->pcie_dpm_key_disabled) {
3197 /* PCIE */
3198 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask != 0) {
3199 level = 0;
3200 tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
3201 while (tmp >>= 1)
3202 level++ ;
3203
3204 if (0 != level) {
3205 PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_pcie(hwmgr, level)),
3206 "force highest pcie dpm state failed!", return -1);
3207 }
3208 }
3209 }
3210
3211 if (0 == data->sclk_dpm_key_disabled) {
3212 /* SCLK */
3213 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask != 0) {
3214 level = 0;
3215 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
3216 while (tmp >>= 1)
3217 level++ ;
3218
3219 if (0 != level) {
3220 PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state(hwmgr, level)),
3221 "force highest sclk dpm state failed!", return -1);
3222 if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
3223 CGS_IND_REG__SMC, TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX) != level)
3224 printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \
3225 Curr_Sclk_Index does not match the level \n");
3226
3227 }
3228 }
3229 }
3230
3231 if (0 == data->mclk_dpm_key_disabled) {
3232 /* MCLK */
3233 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask != 0) {
3234 level = 0;
3235 tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
3236 while (tmp >>= 1)
3237 level++ ;
3238
3239 if (0 != level) {
3240 PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_mclk(hwmgr, level)),
3241 "force highest mclk dpm state failed!", return -1);
3242 if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
3243 TARGET_AND_CURRENT_PROFILE_INDEX, CURR_MCLK_INDEX) != level)
3244 printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \
9fe1837d 3245 Curr_Mclk_Index does not match the level \n");
c82baa28 3246 }
3247 }
3248 }
3249
3250 return 0;
3251}
3252
3253/**
3254 * Find the MC microcode version and store it in the HwMgr struct
3255 *
3256 * @param hwmgr the address of the powerplay hardware manager.
3257 * @return always 0
3258 */
3259int tonga_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
3260{
3261 cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
3262
3263 hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
3264
3265 return 0;
3266}
3267
3268/**
3269 * Initialize Dynamic State Adjustment Rule Settings
3270 *
3271 * @param hwmgr the address of the powerplay hardware manager.
3272 */
3273int tonga_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr)
3274{
3275 uint32_t table_size;
3276 struct phm_clock_voltage_dependency_table *table_clk_vlt;
3277 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3278
3279 hwmgr->dyn_state.mclk_sclk_ratio = 4;
3280 hwmgr->dyn_state.sclk_mclk_delta = 15000; /* 150 MHz */
3281 hwmgr->dyn_state.vddc_vddci_delta = 200; /* 200mV */
3282
3283 /* initialize vddc_dep_on_dal_pwrl table */
3284 table_size = sizeof(uint32_t) + 4 * sizeof(struct phm_clock_voltage_dependency_record);
3285 table_clk_vlt = (struct phm_clock_voltage_dependency_table *)kzalloc(table_size, GFP_KERNEL);
3286
3287 if (NULL == table_clk_vlt) {
3288 printk(KERN_ERR "[ powerplay ] Can not allocate space for vddc_dep_on_dal_pwrl! \n");
3289 return -ENOMEM;
3290 } else {
3291 table_clk_vlt->count = 4;
3292 table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_ULTRALOW;
3293 table_clk_vlt->entries[0].v = 0;
3294 table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_LOW;
3295 table_clk_vlt->entries[1].v = 720;
3296 table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_NOMINAL;
3297 table_clk_vlt->entries[2].v = 810;
3298 table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_PERFORMANCE;
3299 table_clk_vlt->entries[3].v = 900;
3300 pptable_info->vddc_dep_on_dal_pwrl = table_clk_vlt;
3301 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
3302 }
3303
3304 return 0;
3305}
3306
3307static int tonga_set_private_var_based_on_pptale(struct pp_hwmgr *hwmgr)
3308{
3309 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3310 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3311
3312 phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
3313 pptable_info->vdd_dep_on_sclk;
3314 phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
3315 pptable_info->vdd_dep_on_mclk;
3316
3317 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
3318 "VDD dependency on SCLK table is missing. \
3319 This table is mandatory", return -1);
3320 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
3321 "VDD dependency on SCLK table has to have is missing. \
3322 This table is mandatory", return -1);
3323
3324 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
3325 "VDD dependency on MCLK table is missing. \
3326 This table is mandatory", return -1);
3327 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
3328 "VDD dependency on MCLK table has to have is missing. \
3329 This table is mandatory", return -1);
3330
3331 data->min_vddc_in_pp_table = (uint16_t)allowed_sclk_vdd_table->entries[0].vddc;
3332 data->max_vddc_in_pp_table = (uint16_t)allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
3333
3334 pptable_info->max_clock_voltage_on_ac.sclk =
3335 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
3336 pptable_info->max_clock_voltage_on_ac.mclk =
3337 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
3338 pptable_info->max_clock_voltage_on_ac.vddc =
3339 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
3340 pptable_info->max_clock_voltage_on_ac.vddci =
3341 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
3342
3343 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
3344 pptable_info->max_clock_voltage_on_ac.sclk;
3345 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
3346 pptable_info->max_clock_voltage_on_ac.mclk;
3347 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
3348 pptable_info->max_clock_voltage_on_ac.vddc;
3349 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =
3350 pptable_info->max_clock_voltage_on_ac.vddci;
3351
3352 return 0;
3353}
3354
3355int tonga_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
3356{
3357 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3358 int result = 1;
3359
3360 PP_ASSERT_WITH_CODE (0 == tonga_is_dpm_running(hwmgr),
3361 "Trying to Unforce DPM when DPM is disabled. Returning without sending SMC message.",
3362 return result);
3363
3364 if (0 == data->pcie_dpm_key_disabled) {
3365 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(
3366 hwmgr->smumgr,
3367 PPSMC_MSG_PCIeDPM_UnForceLevel)),
3368 "unforce pcie level failed!",
3369 return -1);
3370 }
3371
3372 result = tonga_upload_dpm_level_enable_mask(hwmgr);
3373
3374 return result;
3375}
3376
3377static uint32_t tonga_get_lowest_enable_level(
3378 struct pp_hwmgr *hwmgr, uint32_t level_mask)
3379{
3380 uint32_t level = 0;
3381
3382 while (0 == (level_mask & (1 << level)))
3383 level++;
3384
3385 return level;
3386}
3387
3388static int tonga_force_dpm_lowest(struct pp_hwmgr *hwmgr)
3389{
9fe1837d 3390 uint32_t level;
c82baa28 3391 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3392
9fe1837d
AD		 3393 if (0 == data->pcie_dpm_key_disabled) {
3394 /* PCIE */
3395 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask != 0) {
3396 level = tonga_get_lowest_enable_level(hwmgr,
3397 data->dpm_level_enable_mask.pcie_dpm_enable_mask);
3398 PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_pcie(hwmgr, level)),
3399 "force lowest pcie dpm state failed!", return -1);
3400 }
3401 }
3402
3403 if (0 == data->sclk_dpm_key_disabled) {
3404 /* SCLK */
3405 if (0 != data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3406 level = tonga_get_lowest_enable_level(hwmgr,
3407 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
c82baa28 3408
9fe1837d
AD		 3409 PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state(hwmgr, level)),
3410 "force sclk dpm state failed!", return -1);
c82baa28 3411
9fe1837d
AD		 3412 if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
3413 CGS_IND_REG__SMC, TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX) != level)
3414 printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \
c82baa28 3415 Curr_Sclk_Index does not match the level \n");
9fe1837d
AD		 3416 }
3417 }
3418
3419 if (0 == data->mclk_dpm_key_disabled) {
3420 /* MCLK */
3421 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask != 0) {
3422 level = tonga_get_lowest_enable_level(hwmgr,
3423 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3424 PP_ASSERT_WITH_CODE((0 == tonga_dpm_force_state_mclk(hwmgr, level)),
3425 "force lowest mclk dpm state failed!", return -1);
3426 if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
3427 TARGET_AND_CURRENT_PROFILE_INDEX, CURR_MCLK_INDEX) != level)
3428 printk(KERN_ERR "[ powerplay ] Target_and_current_Profile_Index. \
3429 Curr_Mclk_Index does not match the level \n");
3430 }
c82baa28 3431 }
3432
3433 return 0;
3434}
3435
3436static int tonga_patch_voltage_dependency_tables_with_lookup_table(struct pp_hwmgr *hwmgr)
3437{
3438 uint8_t entryId;
3439 uint8_t voltageId;
3440 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3441 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3442
3443 phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk;
3444 phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk;
3445 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
3446
3447 if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
3448 for (entryId = 0; entryId < sclk_table->count; ++entryId) {
3449 voltageId = sclk_table->entries[entryId].vddInd;
3450 sclk_table->entries[entryId].vddgfx =
3451 pptable_info->vddgfx_lookup_table->entries[voltageId].us_vdd;
3452 }
3453 } else {
3454 for (entryId = 0; entryId < sclk_table->count; ++entryId) {
3455 voltageId = sclk_table->entries[entryId].vddInd;
3456 sclk_table->entries[entryId].vddc =
3457 pptable_info->vddc_lookup_table->entries[voltageId].us_vdd;
3458 }
3459 }
3460
3461 for (entryId = 0; entryId < mclk_table->count; ++entryId) {
3462 voltageId = mclk_table->entries[entryId].vddInd;
3463 mclk_table->entries[entryId].vddc =
3464 pptable_info->vddc_lookup_table->entries[voltageId].us_vdd;
3465 }
3466
3467 for (entryId = 0; entryId < mm_table->count; ++entryId) {
3468 voltageId = mm_table->entries[entryId].vddcInd;
3469 mm_table->entries[entryId].vddc =
3470 pptable_info->vddc_lookup_table->entries[voltageId].us_vdd;
3471 }
3472
3473 return 0;
3474
3475}
3476
3477static int tonga_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
3478{
3479 uint8_t entryId;
3480 phm_ppt_v1_voltage_lookup_record v_record;
3481 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3482 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3483
3484 phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk;
3485 phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk;
3486
3487 if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
3488 for (entryId = 0; entryId < sclk_table->count; ++entryId) {
3489 if (sclk_table->entries[entryId].vdd_offset & (1 << 15))
3490 v_record.us_vdd = sclk_table->entries[entryId].vddgfx +
3491 sclk_table->entries[entryId].vdd_offset - 0xFFFF;
3492 else
3493 v_record.us_vdd = sclk_table->entries[entryId].vddgfx +
3494 sclk_table->entries[entryId].vdd_offset;
3495
3496 sclk_table->entries[entryId].vddc =
3497 v_record.us_cac_low = v_record.us_cac_mid =
3498 v_record.us_cac_high = v_record.us_vdd;
3499
3500 tonga_add_voltage(hwmgr, pptable_info->vddc_lookup_table, &v_record);
3501 }
3502
3503 for (entryId = 0; entryId < mclk_table->count; ++entryId) {
3504 if (mclk_table->entries[entryId].vdd_offset & (1 << 15))
3505 v_record.us_vdd = mclk_table->entries[entryId].vddc +
3506 mclk_table->entries[entryId].vdd_offset - 0xFFFF;
3507 else
3508 v_record.us_vdd = mclk_table->entries[entryId].vddc +
3509 mclk_table->entries[entryId].vdd_offset;
3510
3511 mclk_table->entries[entryId].vddgfx = v_record.us_cac_low =
3512 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd;
3513 tonga_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record);
3514 }
3515 }
3516
3517 return 0;
3518
3519}
3520
3521static int tonga_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
3522{
3523 uint32_t entryId;
3524 phm_ppt_v1_voltage_lookup_record v_record;
3525 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3526 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3527 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
3528
3529 if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
3530 for (entryId = 0; entryId < mm_table->count; entryId++) {
3531 if (mm_table->entries[entryId].vddgfx_offset & (1 << 15))
3532 v_record.us_vdd = mm_table->entries[entryId].vddc +
3533 mm_table->entries[entryId].vddgfx_offset - 0xFFFF;
3534 else
3535 v_record.us_vdd = mm_table->entries[entryId].vddc +
3536 mm_table->entries[entryId].vddgfx_offset;
3537
3538 /* Add the calculated VDDGFX to the VDDGFX lookup table */
3539 mm_table->entries[entryId].vddgfx = v_record.us_cac_low =
3540 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd;
3541 tonga_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record);
3542 }
3543 }
3544 return 0;
3545}
3546
3547
3548/**
3549 * Change virtual leakage voltage to actual value.
3550 *
3551 * @param hwmgr the address of the powerplay hardware manager.
3552 * @param pointer to changing voltage
3553 * @param pointer to leakage table
3554 */
3555static void tonga_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
3556 uint16_t *voltage, phw_tonga_leakage_voltage *pLeakageTable)
3557{
3558 uint32_t leakage_index;
3559
3560 /* search for leakage voltage ID 0xff01 ~ 0xff08 */
3561 for (leakage_index = 0; leakage_index < pLeakageTable->count; leakage_index++) {
3562 /* if this voltage matches a leakage voltage ID */
3563 /* patch with actual leakage voltage */
3564 if (pLeakageTable->leakage_id[leakage_index] == *voltage) {
3565 *voltage = pLeakageTable->actual_voltage[leakage_index];
3566 break;
3567 }
3568 }
3569
3570 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
3571 printk(KERN_ERR "[ powerplay ] Voltage value looks like a Leakage ID but it's not patched \n");
3572}
3573
3574/**
3575 * Patch voltage lookup table by EVV leakages.
3576 *
3577 * @param hwmgr the address of the powerplay hardware manager.
3578 * @param pointer to voltage lookup table
3579 * @param pointer to leakage table
3580 * @return always 0
3581 */
3582static int tonga_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
3583 phm_ppt_v1_voltage_lookup_table *lookup_table,
3584 phw_tonga_leakage_voltage *pLeakageTable)
3585{
3586 uint32_t i;
3587
3588 for (i = 0; i < lookup_table->count; i++) {
3589 tonga_patch_with_vdd_leakage(hwmgr,
3590 &lookup_table->entries[i].us_vdd, pLeakageTable);
3591 }
3592
3593 return 0;
3594}
3595
3596static int tonga_patch_clock_voltage_lomits_with_vddc_leakage(struct pp_hwmgr *hwmgr,
3597 phw_tonga_leakage_voltage *pLeakageTable, uint16_t *Vddc)
3598{
3599 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3600
3601 tonga_patch_with_vdd_leakage(hwmgr, (uint16_t *)Vddc, pLeakageTable);
3602 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
3603 pptable_info->max_clock_voltage_on_dc.vddc;
3604
3605 return 0;
3606}
3607
3608static int tonga_patch_clock_voltage_limits_with_vddgfx_leakage(
3609 struct pp_hwmgr *hwmgr, phw_tonga_leakage_voltage *pLeakageTable,
3610 uint16_t *Vddgfx)
3611{
3612 tonga_patch_with_vdd_leakage(hwmgr, (uint16_t *)Vddgfx, pLeakageTable);
3613 return 0;
3614}
3615
3616int tonga_sort_lookup_table(struct pp_hwmgr *hwmgr,
3617 phm_ppt_v1_voltage_lookup_table *lookup_table)
3618{
3619 uint32_t table_size, i, j;
3620 phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
3621 table_size = lookup_table->count;
3622
3623 PP_ASSERT_WITH_CODE(0 != lookup_table->count,
3624 "Lookup table is empty", return -1);
3625
3626 /* Sorting voltages */
3627 for (i = 0; i < table_size - 1; i++) {
3628 for (j = i + 1; j > 0; j--) {
3629 if (lookup_table->entries[j].us_vdd < lookup_table->entries[j-1].us_vdd) {
3630 tmp_voltage_lookup_record = lookup_table->entries[j-1];
3631 lookup_table->entries[j-1] = lookup_table->entries[j];
3632 lookup_table->entries[j] = tmp_voltage_lookup_record;
3633 }
3634 }
3635 }
3636
3637 return 0;
3638}
3639
3640static int tonga_complete_dependency_tables(struct pp_hwmgr *hwmgr)
3641{
3642 int result = 0;
3643 int tmp_result;
3644 tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
3645 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
3646
3647 if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
3648 tmp_result = tonga_patch_lookup_table_with_leakage(hwmgr,
3649 pptable_info->vddgfx_lookup_table, &(data->vddcgfx_leakage));
3650 if (tmp_result != 0)
3651 result = tmp_result;
3652
3653 tmp_result = tonga_patch_clock_voltage_limits_with_vddgfx_leakage(hwmgr,
3654 &(data->vddcgfx_leakage), &pptable_info->max_clock_voltage_on_dc.vddgfx);
3655 if (tmp_result != 0)
3656 result = tmp_result;
3657 } else {
3658 tmp_result = tonga_patch_lookup_table_with_leakage(hwmgr,
3659 pptable_info->vddc_lookup_table, &(data->vddc_leakage));
3660 if (tmp_result != 0)
3661 result = tmp_result;
3662
3663 tmp_result = tonga_patch_clock_voltage_lomits_with_vddc_leakage(hwmgr,
3664 &(data->vddc_leakage), &pptable_info->max_clock_voltage_on_dc.vddc);
3665 if (tmp_result != 0)
3666 result = tmp_result;
3667 }
3668
3669 tmp_result = tonga_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
3670 if (tmp_result != 0)
3671 result = tmp_result;
3672
3673 tmp_result = tonga_calc_voltage_dependency_tables(hwmgr);
3674 if (tmp_result != 0)
3675 result = tmp_result;
3676
3677 tmp_result = tonga_calc_mm_voltage_dependency_table(hwmgr);
3678 if (tmp_result != 0)
3679 result = tmp_result;
3680
3681 tmp_result = tonga_sort_lookup_table(hwmgr, pptable_info->vddgfx_lookup_table);
3682 if (tmp_result != 0)
3683 result = tmp_result;
3684
3685 tmp_result = tonga_sort_lookup_table(hwmgr, pptable_info->vddc_lookup_table);
3686 if (tmp_result != 0)
3687 result = tmp_result;
3688
3689 return result;
3690}
3691
3692int tonga_init_sclk_threshold(struct pp_hwmgr *hwmgr)
3693{
3694 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
3695 data->low_sclk_interrupt_threshold = 0;
3696
3697 return 0;
3698}
3699
3700int tonga_setup_asic_task(struct pp_hwmgr *hwmgr)
3701{
3702 int tmp_result, result = 0;
3703
3704 tmp_result = tonga_read_clock_registers(hwmgr);
3705 PP_ASSERT_WITH_CODE((0 == tmp_result),
3706 "Failed to read clock registers!", result = tmp_result);
3707
3708 tmp_result = tonga_get_memory_type(hwmgr);
3709 PP_ASSERT_WITH_CODE((0 == tmp_result),
3710 "Failed to get memory type!", result = tmp_result);
3711
3712 tmp_result = tonga_enable_acpi_power_management(hwmgr);
3713 PP_ASSERT_WITH_CODE((0 == tmp_result),
3714 "Failed to enable ACPI power management!", result = tmp_result);
3715
3716 tmp_result = tonga_init_power_gate_state(hwmgr);
3717 PP_ASSERT_WITH_CODE((0 == tmp_result),
3718 "Failed to init power gate state!", result = tmp_result);
3719
3720 tmp_result = tonga_get_mc_microcode_version(hwmgr);
3721 PP_ASSERT_WITH_CODE((0 == tmp_result),
3722 "Failed to get MC microcode version!", result = tmp_result);
3723
3724 tmp_result = tonga_init_sclk_threshold(hwmgr);
3725 PP_ASSERT_WITH_CODE((0 == tmp_result),
3726 "Failed to init sclk threshold!", result = tmp_result);
3727
3728 return result;
3729}
3730
3731/**
3732 * Enable voltage control
3733 *
3734 * @param hwmgr the address of the powerplay hardware manager.
3735 * @return always 0
3736 */
3737int tonga_enable_voltage_control(struct pp_hwmgr *hwmgr)
3738{
3739 /* enable voltage control */
3740 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
3741
3742 return 0;
3743}
3744
3745/**
3746 * Checks if we want to support voltage control
3747 *
3748 * @param hwmgr the address of the powerplay hardware manager.
3749 */
3750bool cf_tonga_voltage_control(const struct pp_hwmgr *hwmgr)
3751{
3752 const struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
3753
3754 return(TONGA_VOLTAGE_CONTROL_NONE != data->voltage_control);
3755}
3756
3757/*---------------------------MC----------------------------*/
3758
3759uint8_t tonga_get_memory_modile_index(struct pp_hwmgr *hwmgr)
3760{
3761 return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
3762}
3763
3764bool tonga_check_s0_mc_reg_index(uint16_t inReg, uint16_t *outReg)
3765{
3766 bool result = 1;
3767
3768 switch (inReg) {
3769 case mmMC_SEQ_RAS_TIMING:
3770 *outReg = mmMC_SEQ_RAS_TIMING_LP;
3771 break;
3772
3773 case mmMC_SEQ_DLL_STBY:
3774 *outReg = mmMC_SEQ_DLL_STBY_LP;
3775 break;
3776
3777 case mmMC_SEQ_G5PDX_CMD0:
3778 *outReg = mmMC_SEQ_G5PDX_CMD0_LP;
3779 break;
3780
3781 case mmMC_SEQ_G5PDX_CMD1:
3782 *outReg = mmMC_SEQ_G5PDX_CMD1_LP;
3783 break;
3784
3785 case mmMC_SEQ_G5PDX_CTRL:
3786 *outReg = mmMC_SEQ_G5PDX_CTRL_LP;
3787 break;
3788
3789 case mmMC_SEQ_CAS_TIMING:
3790 *outReg = mmMC_SEQ_CAS_TIMING_LP;
3791 break;
3792
3793 case mmMC_SEQ_MISC_TIMING:
3794 *outReg = mmMC_SEQ_MISC_TIMING_LP;
3795 break;
3796
3797 case mmMC_SEQ_MISC_TIMING2:
3798 *outReg = mmMC_SEQ_MISC_TIMING2_LP;
3799 break;
3800
3801 case mmMC_SEQ_PMG_DVS_CMD:
3802 *outReg = mmMC_SEQ_PMG_DVS_CMD_LP;
3803 break;
3804
3805 case mmMC_SEQ_PMG_DVS_CTL:
3806 *outReg = mmMC_SEQ_PMG_DVS_CTL_LP;
3807 break;
3808
3809 case mmMC_SEQ_RD_CTL_D0:
3810 *outReg = mmMC_SEQ_RD_CTL_D0_LP;
3811 break;
3812
3813 case mmMC_SEQ_RD_CTL_D1:
3814 *outReg = mmMC_SEQ_RD_CTL_D1_LP;
3815 break;
3816
3817 case mmMC_SEQ_WR_CTL_D0:
3818 *outReg = mmMC_SEQ_WR_CTL_D0_LP;
3819 break;
3820
3821 case mmMC_SEQ_WR_CTL_D1:
3822 *outReg = mmMC_SEQ_WR_CTL_D1_LP;
3823 break;
3824
3825 case mmMC_PMG_CMD_EMRS:
3826 *outReg = mmMC_SEQ_PMG_CMD_EMRS_LP;
3827 break;
3828
3829 case mmMC_PMG_CMD_MRS:
3830 *outReg = mmMC_SEQ_PMG_CMD_MRS_LP;
3831 break;
3832
3833 case mmMC_PMG_CMD_MRS1:
3834 *outReg = mmMC_SEQ_PMG_CMD_MRS1_LP;
3835 break;
3836
3837 case mmMC_SEQ_PMG_TIMING:
3838 *outReg = mmMC_SEQ_PMG_TIMING_LP;
3839 break;
3840
3841 case mmMC_PMG_CMD_MRS2:
3842 *outReg = mmMC_SEQ_PMG_CMD_MRS2_LP;
3843 break;
3844
3845 case mmMC_SEQ_WR_CTL_2:
3846 *outReg = mmMC_SEQ_WR_CTL_2_LP;
3847 break;
3848
3849 default:
3850 result = 0;
3851 break;
3852 }
3853
3854 return result;
3855}
3856
3857int tonga_set_s0_mc_reg_index(phw_tonga_mc_reg_table *table)
3858{
3859 uint32_t i;
3860 uint16_t address;
3861
3862 for (i = 0; i < table->last; i++) {
3863 table->mc_reg_address[i].s0 =
3864 tonga_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address)
3865 ? address : table->mc_reg_address[i].s1;
3866 }
3867 return 0;
3868}
3869
3870int tonga_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table, phw_tonga_mc_reg_table *ni_table)
3871{
3872 uint8_t i, j;
3873
3874 PP_ASSERT_WITH_CODE((table->last <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3875 "Invalid VramInfo table.", return -1);
3876 PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES),
3877 "Invalid VramInfo table.", return -1);
3878
3879 for (i = 0; i < table->last; i++) {
3880 ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
3881 }
3882 ni_table->last = table->last;
3883
3884 for (i = 0; i < table->num_entries; i++) {
3885 ni_table->mc_reg_table_entry[i].mclk_max =
3886 table->mc_reg_table_entry[i].mclk_max;
3887 for (j = 0; j < table->last; j++) {
3888 ni_table->mc_reg_table_entry[i].mc_data[j] =
3889 table->mc_reg_table_entry[i].mc_data[j];
3890 }
3891 }
c15c8d70 3892
c82baa28 3893 ni_table->num_entries = table->num_entries;
3894
3895 return 0;
3896}
3897
3898/**
3899 * VBIOS omits some information to reduce size, we need to recover them here.
3900 * 1. when we see mmMC_SEQ_MISC1, bit[31:16] EMRS1, need to be write to mmMC_PMG_CMD_EMRS /_LP[15:0].
3901 * Bit[15:0] MRS, need to be update mmMC_PMG_CMD_MRS/_LP[15:0]
3902 * 2. when we see mmMC_SEQ_RESERVE_M, bit[15:0] EMRS2, need to be write to mmMC_PMG_CMD_MRS1/_LP[15:0].
3903 * 3. need to set these data for each clock range
3904 *
3905 * @param hwmgr the address of the powerplay hardware manager.
3906 * @param table the address of MCRegTable
3907 * @return always 0
3908 */
3909int tonga_set_mc_special_registers(struct pp_hwmgr *hwmgr, phw_tonga_mc_reg_table *table)
3910{
3911 uint8_t i, j, k;
3912 uint32_t temp_reg;
3913 const tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
3914
3915 for (i = 0, j = table->last; i < table->last; i++) {
3916 PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3917 "Invalid VramInfo table.", return -1);
3918 switch (table->mc_reg_address[i].s1) {
3919 /*
3920 * mmMC_SEQ_MISC1, bit[31:16] EMRS1, need to be write to mmMC_PMG_CMD_EMRS /_LP[15:0].
3921 * Bit[15:0] MRS, need to be update mmMC_PMG_CMD_MRS/_LP[15:0]
3922 */
3923 case mmMC_SEQ_MISC1:
3924 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS);
3925 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
3926 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;
3927 for (k = 0; k < table->num_entries; k++) {
3928 table->mc_reg_table_entry[k].mc_data[j] =
3929 ((temp_reg & 0xffff0000)) |
3930 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
3931 }
3932 j++;
3933 PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3934 "Invalid VramInfo table.", return -1);
3935
3936 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS);
3937 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
3938 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
3939 for (k = 0; k < table->num_entries; k++) {
3940 table->mc_reg_table_entry[k].mc_data[j] =
3941 (temp_reg & 0xffff0000) |
3942 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3943
3944 if (!data->is_memory_GDDR5) {
3945 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
3946 }
3947 }
3948 j++;
3949 PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3950 "Invalid VramInfo table.", return -1);
3951
3952 if (!data->is_memory_GDDR5) {
3953 table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
3954 table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
3955 for (k = 0; k < table->num_entries; k++) {
3956 table->mc_reg_table_entry[k].mc_data[j] =
3957 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
3958 }
3959 j++;
3960 PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3961 "Invalid VramInfo table.", return -1);
3962 }
3963
3964 break;
3965
3966 case mmMC_SEQ_RESERVE_M:
3967 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1);
3968 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;
3969 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;
3970 for (k = 0; k < table->num_entries; k++) {
3971 table->mc_reg_table_entry[k].mc_data[j] =
3972 (temp_reg & 0xffff0000) |
3973 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3974 }
3975 j++;
3976 PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
3977 "Invalid VramInfo table.", return -1);
3978 break;
3979
3980 default:
3981 break;
3982 }
3983
3984 }
3985
3986 table->last = j;
3987
3988 return 0;
3989}
3990
3991int tonga_set_valid_flag(phw_tonga_mc_reg_table *table)
3992{
3993 uint8_t i, j;
3994 for (i = 0; i < table->last; i++) {
3995 for (j = 1; j < table->num_entries; j++) {
3996 if (table->mc_reg_table_entry[j-1].mc_data[i] !=
3997 table->mc_reg_table_entry[j].mc_data[i]) {
3998 table->validflag |= (1<<i);
3999 break;
4000 }
4001 }
4002 }
4003
4004 return 0;
4005}
4006
4007int tonga_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
4008{
4009 int result;
4010 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
4011 pp_atomctrl_mc_reg_table *table;
4012 phw_tonga_mc_reg_table *ni_table = &data->tonga_mc_reg_table;
4013 uint8_t module_index = tonga_get_memory_modile_index(hwmgr);
4014
4015 table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL);
4016
4017 if (NULL == table)
c15c8d70 4018 return -ENOMEM;
c82baa28 4019
4020 /* Program additional LP registers that are no longer programmed by VBIOS */
4021 cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
4022 cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
4023 cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY));
4024 cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0));
4025 cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1));
4026 cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL));
4027 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD));
4028 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL));
4029 cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING));
4030 cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
4031 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_EMRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS));
4032 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS));
4033 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS1_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1));
4034 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0));
4035 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
4036 cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
4037 cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
4038 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
4039 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2));
4040 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2));
4041
4042 memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table));
4043
4044 result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table);
4045
4046 if (0 == result)
4047 result = tonga_copy_vbios_smc_reg_table(table, ni_table);
4048
4049 if (0 == result) {
4050 tonga_set_s0_mc_reg_index(ni_table);
4051 result = tonga_set_mc_special_registers(hwmgr, ni_table);
4052 }
4053
4054 if (0 == result)
4055 tonga_set_valid_flag(ni_table);
4056
4057 kfree(table);
4058 return result;
4059}
4060
4061/*
4062* Copy one arb setting to another and then switch the active set.
4063* arbFreqSrc and arbFreqDest is one of the MC_CG_ARB_FREQ_Fx constants.
4064*/
4065int tonga_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
4066 uint32_t arbFreqSrc, uint32_t arbFreqDest)
4067{
4068 uint32_t mc_arb_dram_timing;
4069 uint32_t mc_arb_dram_timing2;
4070 uint32_t burst_time;
4071 uint32_t mc_cg_config;
4072
4073 switch (arbFreqSrc) {
4074 case MC_CG_ARB_FREQ_F0:
4075 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
4076 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
4077 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
4078 break;
4079
4080 case MC_CG_ARB_FREQ_F1:
4081 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
4082 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
4083 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
4084 break;
4085
4086 default:
4087 return -1;
4088 }
4089
4090 switch (arbFreqDest) {
4091 case MC_CG_ARB_FREQ_F0:
4092 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
4093 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
4094 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
4095 break;
4096
4097 case MC_CG_ARB_FREQ_F1:
4098 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
4099 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
4100 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
4101 break;
4102
4103 default:
4104 return -1;
4105 }
4106
4107 mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
4108 mc_cg_config |= 0x0000000F;
4109 cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
4110 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arbFreqDest);
4111
4112 return 0;
4113}
4114
4115/**
4116 * Initial switch from ARB F0->F1
4117 *
4118 * @param hwmgr the address of the powerplay hardware manager.
4119 * @return always 0
4120 * This function is to be called from the SetPowerState table.
4121 */
4122int tonga_initial_switch_from_arb_f0_to_f1(struct pp_hwmgr *hwmgr)
4123{
4124 return tonga_copy_and_switch_arb_sets(hwmgr, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4125}
4126
4127/**
4128 * Initialize the ARB DRAM timing table's index field.
4129 *
4130 * @param hwmgr the address of the powerplay hardware manager.
4131 * @return always 0
4132 */
4133int tonga_init_arb_table_index(struct pp_hwmgr *hwmgr)
4134{
4135 const tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4136 uint32_t tmp;
4137 int result;
4138
4139 /*
4140 * This is a read-modify-write on the first byte of the ARB table.
4141 * The first byte in the SMU72_Discrete_MCArbDramTimingTable structure is the field 'current'.
4142 * This solution is ugly, but we never write the whole table only individual fields in it.
4143 * In reality this field should not be in that structure but in a soft register.
4144 */
4145 result = tonga_read_smc_sram_dword(hwmgr->smumgr,
4146 data->arb_table_start, &tmp, data->sram_end);
4147
4148 if (0 != result)
4149 return result;
4150
4151 tmp &= 0x00FFFFFF;
4152 tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
4153
4154 return tonga_write_smc_sram_dword(hwmgr->smumgr,
4155 data->arb_table_start, tmp, data->sram_end);
4156}
4157
4158int tonga_populate_mc_reg_address(struct pp_hwmgr *hwmgr, SMU72_Discrete_MCRegisters *mc_reg_table)
4159{
4160 const struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4161
4162 uint32_t i, j;
4163
4164 for (i = 0, j = 0; j < data->tonga_mc_reg_table.last; j++) {
4165 if (data->tonga_mc_reg_table.validflag & 1<<j) {
4166 PP_ASSERT_WITH_CODE(i < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE,
4167 "Index of mc_reg_table->address[] array out of boundary", return -1);
4168 mc_reg_table->address[i].s0 =
4169 PP_HOST_TO_SMC_US(data->tonga_mc_reg_table.mc_reg_address[j].s0);
4170 mc_reg_table->address[i].s1 =
4171 PP_HOST_TO_SMC_US(data->tonga_mc_reg_table.mc_reg_address[j].s1);
4172 i++;
4173 }
4174 }
4175
4176 mc_reg_table->last = (uint8_t)i;
4177
4178 return 0;
4179}
4180
4181/*convert register values from driver to SMC format */
4182void tonga_convert_mc_registers(
4183 const phw_tonga_mc_reg_entry * pEntry,
4184 SMU72_Discrete_MCRegisterSet *pData,
4185 uint32_t numEntries, uint32_t validflag)
4186{
4187 uint32_t i, j;
4188
4189 for (i = 0, j = 0; j < numEntries; j++) {
4190 if (validflag & 1<<j) {
4191 pData->value[i] = PP_HOST_TO_SMC_UL(pEntry->mc_data[j]);
4192 i++;
4193 }
4194 }
4195}
4196
4197/* find the entry in the memory range table, then populate the value to SMC's tonga_mc_reg_table */
4198int tonga_convert_mc_reg_table_entry_to_smc(
4199 struct pp_hwmgr *hwmgr,
4200 const uint32_t memory_clock,
4201 SMU72_Discrete_MCRegisterSet *mc_reg_table_data
4202 )
4203{
4204 const tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4205 uint32_t i = 0;
4206
4207 for (i = 0; i < data->tonga_mc_reg_table.num_entries; i++) {
4208 if (memory_clock <=
4209 data->tonga_mc_reg_table.mc_reg_table_entry[i].mclk_max) {
4210 break;
4211 }
4212 }
4213
4214 if ((i == data->tonga_mc_reg_table.num_entries) && (i > 0))
4215 --i;
4216
4217 tonga_convert_mc_registers(&data->tonga_mc_reg_table.mc_reg_table_entry[i],
4218 mc_reg_table_data, data->tonga_mc_reg_table.last, data->tonga_mc_reg_table.validflag);
4219
4220 return 0;
4221}
4222
4223int tonga_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
4224 SMU72_Discrete_MCRegisters *mc_reg_table)
4225{
4226 int result = 0;
4227 tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4228 int res;
4229 uint32_t i;
4230
4231 for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
4232 res = tonga_convert_mc_reg_table_entry_to_smc(
4233 hwmgr,
4234 data->dpm_table.mclk_table.dpm_levels[i].value,
4235 &mc_reg_table->data[i]
4236 );
4237
4238 if (0 != res)
4239 result = res;
4240 }
4241
4242 return result;
4243}
4244
4245int tonga_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
4246{
4247 int result;
4248 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4249
4250 memset(&data->mc_reg_table, 0x00, sizeof(SMU72_Discrete_MCRegisters));
4251 result = tonga_populate_mc_reg_address(hwmgr, &(data->mc_reg_table));
4252 PP_ASSERT_WITH_CODE(0 == result,
4253 "Failed to initialize MCRegTable for the MC register addresses!", return result;);
4254
4255 result = tonga_convert_mc_reg_table_to_smc(hwmgr, &data->mc_reg_table);
4256 PP_ASSERT_WITH_CODE(0 == result,
4257 "Failed to initialize MCRegTable for driver state!", return result;);
4258
4259 return tonga_copy_bytes_to_smc(hwmgr->smumgr, data->mc_reg_table_start,
4260 (uint8_t *)&data->mc_reg_table, sizeof(SMU72_Discrete_MCRegisters), data->sram_end);
4261}
4262
4263/**
4264 * Programs static screed detection parameters
4265 *
4266 * @param hwmgr the address of the powerplay hardware manager.
4267 * @return always 0
4268 */
4269int tonga_program_static_screen_threshold_parameters(struct pp_hwmgr *hwmgr)
4270{
4271 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
4272
4273 /* Set static screen threshold unit*/
4274 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
4275 CGS_IND_REG__SMC, CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
4276 data->static_screen_threshold_unit);
4277 /* Set static screen threshold*/
4278 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
4279 CGS_IND_REG__SMC, CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
4280 data->static_screen_threshold);
4281
4282 return 0;
4283}
4284
4285/**
4286 * Setup display gap for glitch free memory clock switching.
4287 *
4288 * @param hwmgr the address of the powerplay hardware manager.
4289 * @return always 0
4290 */
4291int tonga_enable_display_gap(struct pp_hwmgr *hwmgr)
4292{
4293 uint32_t display_gap = cgs_read_ind_register(hwmgr->device,
4294 CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
4295
4296 display_gap = PHM_SET_FIELD(display_gap,
4297 CG_DISPLAY_GAP_CNTL, DISP_GAP, DISPLAY_GAP_IGNORE);
4298
4299 display_gap = PHM_SET_FIELD(display_gap,
4300 CG_DISPLAY_GAP_CNTL, DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
4301
4302 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4303 ixCG_DISPLAY_GAP_CNTL, display_gap);
4304
4305 return 0;
4306}
4307
4308/**
4309 * Programs activity state transition voting clients
4310 *
4311 * @param hwmgr the address of the powerplay hardware manager.
4312 * @return always 0
4313 */
4314int tonga_program_voting_clients(struct pp_hwmgr *hwmgr)
4315{
4316 tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
4317
4318 /* Clear reset for voting clients before enabling DPM */
4319 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4320 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
4321 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4322 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
4323
4324 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4325 ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
4326 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4327 ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
4328 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4329 ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
4330 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4331 ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
4332 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4333 ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
4334 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4335 ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
4336 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4337 ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
4338 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4339 ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
4340
4341 return 0;
4342}
4343
4344
4345int tonga_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
4346{
4347 int tmp_result, result = 0;
4348
4349 tmp_result = tonga_check_for_dpm_stopped(hwmgr);
4350
4351 if (cf_tonga_voltage_control(hwmgr)) {
4352 tmp_result = tonga_enable_voltage_control(hwmgr);
4353 PP_ASSERT_WITH_CODE((0 == tmp_result),
4354 "Failed to enable voltage control!", result = tmp_result);
4355
4356 tmp_result = tonga_construct_voltage_tables(hwmgr);
4357 PP_ASSERT_WITH_CODE((0 == tmp_result),
4358 "Failed to contruct voltage tables!", result = tmp_result);
4359 }
4360
4361 tmp_result = tonga_initialize_mc_reg_table(hwmgr);
4362 PP_ASSERT_WITH_CODE((0 == tmp_result),
4363 "Failed to initialize MC reg table!", result = tmp_result);
4364
4365 tmp_result = tonga_program_static_screen_threshold_parameters(hwmgr);
4366 PP_ASSERT_WITH_CODE((0 == tmp_result),
4367 "Failed to program static screen threshold parameters!", result = tmp_result);
4368
4369 tmp_result = tonga_enable_display_gap(hwmgr);
4370 PP_ASSERT_WITH_CODE((0 == tmp_result),
4371 "Failed to enable display gap!", result = tmp_result);
4372
4373 tmp_result = tonga_program_voting_clients(hwmgr);
4374 PP_ASSERT_WITH_CODE((0 == tmp_result),
4375 "Failed to program voting clients!", result = tmp_result);
4376
4377 tmp_result = tonga_process_firmware_header(hwmgr);
4378 PP_ASSERT_WITH_CODE((0 == tmp_result),
4379 "Failed to process firmware header!", result = tmp_result);
4380
4381 tmp_result = tonga_initial_switch_from_arb_f0_to_f1(hwmgr);
4382 PP_ASSERT_WITH_CODE((0 == tmp_result),
4383 "Failed to initialize switch from ArbF0 to F1!", result = tmp_result);
4384
4385 tmp_result = tonga_init_smc_table(hwmgr);
4386 PP_ASSERT_WITH_CODE((0 == tmp_result),
4387 "Failed to initialize SMC table!", result = tmp_result);
4388
4389 tmp_result = tonga_init_arb_table_index(hwmgr);
4390 PP_ASSERT_WITH_CODE((0 == tmp_result),
4391 "Failed to initialize ARB table index!", result = tmp_result);
4392
4393 tmp_result = tonga_populate_initial_mc_reg_table(hwmgr);
4394 PP_ASSERT_WITH_CODE((0 == tmp_result),
4395 "Failed to populate initialize MC Reg table!", result = tmp_result);
4396
bbb207f3
RZ		 4397 tmp_result = tonga_notify_smc_display_change(hwmgr, false);
4398 PP_ASSERT_WITH_CODE((0 == tmp_result),
4399 "Failed to notify no display!", result = tmp_result);
4400
c82baa28 4401 /* enable SCLK control */
4402 tmp_result = tonga_enable_sclk_control(hwmgr);
4403 PP_ASSERT_WITH_CODE((0 == tmp_result),
4404 "Failed to enable SCLK control!", result = tmp_result);
4405
4406 /* enable DPM */
4407 tmp_result = tonga_start_dpm(hwmgr);
4408 PP_ASSERT_WITH_CODE((0 == tmp_result),
4409 "Failed to start DPM!", result = tmp_result);
4410
4411 return result;
4412}
4413
4414int tonga_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
4415{
4416 int tmp_result, result = 0;
4417
4418 tmp_result = tonga_check_for_dpm_running(hwmgr);
4419 PP_ASSERT_WITH_CODE((0 == tmp_result),
4420 "SMC is still running!", return 0);
4421
4422 tmp_result = tonga_stop_dpm(hwmgr);
4423 PP_ASSERT_WITH_CODE((0 == tmp_result),
4424 "Failed to stop DPM!", result = tmp_result);
4425
4426 tmp_result = tonga_reset_to_default(hwmgr);
4427 PP_ASSERT_WITH_CODE((0 == tmp_result),
4428 "Failed to reset to default!", result = tmp_result);
4429
4430 return result;
4431}
4432
4433int tonga_reset_asic_tasks(struct pp_hwmgr *hwmgr)
4434{
4435 int result;
4436
4437 result = tonga_set_boot_state(hwmgr);
4438 if (0 != result)
4439 printk(KERN_ERR "[ powerplay ] Failed to reset asic via set boot state! \n");
4440
4441 return result;
4442}
4443
4444int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
4445{
4446 if (NULL != hwmgr->dyn_state.vddc_dep_on_dal_pwrl) {
4447 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
4448 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
4449 }
4450
4451 if (NULL != hwmgr->backend) {
4452 kfree(hwmgr->backend);
4453 hwmgr->backend = NULL;
4454 }
4455
4456 return 0;
4457}
4458
4459/**
4460 * Initializes the Volcanic Islands Hardware Manager
4461 *
4462 * @param hwmgr the address of the powerplay hardware manager.
4463 * @return 1 if success; otherwise appropriate error code.
4464 */
4465int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
4466{
4467 int result = 0;
4468 SMU72_Discrete_DpmTable *table = NULL;
4469 tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4470 pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
4471 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
4472 phw_tonga_ulv_parm *ulv;
52b52a87 4473 struct cgs_system_info sys_info = {0};
c82baa28 4474
4475 PP_ASSERT_WITH_CODE((NULL != hwmgr),
4476 "Invalid Parameter!", return -1;);
4477
4478 data->dll_defaule_on = 0;
4479 data->sram_end = SMC_RAM_END;
4480
4481 data->activity_target[0] = PPTONGA_TARGETACTIVITY_DFLT;
4482 data->activity_target[1] = PPTONGA_TARGETACTIVITY_DFLT;
4483 data->activity_target[2] = PPTONGA_TARGETACTIVITY_DFLT;
4484 data->activity_target[3] = PPTONGA_TARGETACTIVITY_DFLT;
4485 data->activity_target[4] = PPTONGA_TARGETACTIVITY_DFLT;
4486 data->activity_target[5] = PPTONGA_TARGETACTIVITY_DFLT;
4487 data->activity_target[6] = PPTONGA_TARGETACTIVITY_DFLT;
4488 data->activity_target[7] = PPTONGA_TARGETACTIVITY_DFLT;
4489
4490 data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
4491 data->vddc_vddgfx_delta = VDDC_VDDGFX_DELTA;
4492 data->mclk_activity_target = PPTONGA_MCLK_TARGETACTIVITY_DFLT;
4493
4494 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4495 PHM_PlatformCaps_DisableVoltageIsland);
4496
4497 data->sclk_dpm_key_disabled = 0;
4498 data->mclk_dpm_key_disabled = 0;
4499 data->pcie_dpm_key_disabled = 0;
4500 data->pcc_monitor_enabled = 0;
4501
4502 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4503 PHM_PlatformCaps_UnTabledHardwareInterface);
4504
4505 data->gpio_debug = 0;
4506 data->engine_clock_data = 0;
4507 data->memory_clock_data = 0;
4508 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4509 PHM_PlatformCaps_DynamicPatchPowerState);
4510
4511 /* need to set voltage control types before EVV patching*/
4512 data->voltage_control = TONGA_VOLTAGE_CONTROL_NONE;
4513 data->vdd_ci_control = TONGA_VOLTAGE_CONTROL_NONE;
4514 data->vdd_gfx_control = TONGA_VOLTAGE_CONTROL_NONE;
4515 data->mvdd_control = TONGA_VOLTAGE_CONTROL_NONE;
4516
3ec2cdb8 4517 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
c82baa28 4518 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) {
4519 data->voltage_control = TONGA_VOLTAGE_CONTROL_BY_SVID2;
4520 }
4521
4522 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4523 PHM_PlatformCaps_ControlVDDGFX)) {
3ec2cdb8 4524 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
c82baa28 4525 VOLTAGE_TYPE_VDDGFX, VOLTAGE_OBJ_SVID2)) {
4526 data->vdd_gfx_control = TONGA_VOLTAGE_CONTROL_BY_SVID2;
4527 }
4528 }
4529
4530 if (TONGA_VOLTAGE_CONTROL_NONE == data->vdd_gfx_control) {
4531 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
4532 PHM_PlatformCaps_ControlVDDGFX);
4533 }
4534
4535 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4536 PHM_PlatformCaps_EnableMVDDControl)) {
3ec2cdb8 4537 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
c82baa28 4538 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT)) {
4539 data->mvdd_control = TONGA_VOLTAGE_CONTROL_BY_GPIO;
4540 }
4541 }
4542
4543 if (TONGA_VOLTAGE_CONTROL_NONE == data->mvdd_control) {
4544 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
4545 PHM_PlatformCaps_EnableMVDDControl);
4546 }
4547
4548 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4549 PHM_PlatformCaps_ControlVDDCI)) {
3ec2cdb8 4550 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
c82baa28 4551 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
4552 data->vdd_ci_control = TONGA_VOLTAGE_CONTROL_BY_GPIO;
3ec2cdb8 4553 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
c82baa28 4554 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
4555 data->vdd_ci_control = TONGA_VOLTAGE_CONTROL_BY_SVID2;
4556 }
4557
4558 if (TONGA_VOLTAGE_CONTROL_NONE == data->vdd_ci_control)
4559 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
4560 PHM_PlatformCaps_ControlVDDCI);
4561
4562 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4563 PHM_PlatformCaps_TablelessHardwareInterface);
4564
4565 if (pptable_info->cac_dtp_table->usClockStretchAmount != 0)
4566 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4567 PHM_PlatformCaps_ClockStretcher);
4568
4569 /* Initializes DPM default values*/
4570 tonga_initialize_dpm_defaults(hwmgr);
4571
4572 /* Get leakage voltage based on leakage ID.*/
4573 PP_ASSERT_WITH_CODE((0 == tonga_get_evv_voltage(hwmgr)),
4574 "Get EVV Voltage Failed. Abort Driver loading!", return -1);
4575
4576 tonga_complete_dependency_tables(hwmgr);
4577
4578 /* Parse pptable data read from VBIOS*/
4579 tonga_set_private_var_based_on_pptale(hwmgr);
4580
4581 /* ULV Support*/
4582 ulv = &(data->ulv);
4583 ulv->ulv_supported = 0;
4584
4585 /* Initalize Dynamic State Adjustment Rule Settings*/
4586 result = tonga_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
aa22ae4b
AD		 4587 if (result)
4588 printk(KERN_ERR "[ powerplay ] tonga_initializa_dynamic_state_adjustment_rule_settings failed!\n");
c82baa28 4589 data->uvd_enabled = 0;
4590
4591 table = &(data->smc_state_table);
4592
4593 /*
4594 * if ucGPIO_ID=VDDC_PCC_GPIO_PINID in GPIO_LUTable,
4595 * Peak Current Control feature is enabled and we should program PCC HW register
4596 */
4597 if (0 == atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
4598 uint32_t temp_reg = cgs_read_ind_register(hwmgr->device,
4599 CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
4600
4601 switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
4602 case 0:
4603 temp_reg = PHM_SET_FIELD(temp_reg,
4604 CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
4605 break;
4606 case 1:
4607 temp_reg = PHM_SET_FIELD(temp_reg,
4608 CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
4609 break;
4610 case 2:
4611 temp_reg = PHM_SET_FIELD(temp_reg,
4612 CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
4613 break;
4614 case 3:
4615 temp_reg = PHM_SET_FIELD(temp_reg,
4616 CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
4617 break;
4618 case 4:
4619 temp_reg = PHM_SET_FIELD(temp_reg,
4620 CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
4621 break;
4622 default:
4623 printk(KERN_ERR "[ powerplay ] Failed to setup PCC HW register! \
4624 Wrong GPIO assigned for VDDC_PCC_GPIO_PINID! \n");
4625 break;
4626 }
4627 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4628 ixCNB_PWRMGT_CNTL, temp_reg);
4629 }
4630
4631 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4632 PHM_PlatformCaps_EnableSMU7ThermalManagement);
4633 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4634 PHM_PlatformCaps_SMU7);
4635
4636 data->vddc_phase_shed_control = 0;
4637
3d5afb41
AD		 4638 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
4639 PHM_PlatformCaps_UVDPowerGating);
f997e6f2
AD		 4640 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
4641 PHM_PlatformCaps_VCEPowerGating);
52b52a87
AD		 4642 sys_info.size = sizeof(struct cgs_system_info);
4643 sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS;
4644 result = cgs_query_system_info(hwmgr->device, &sys_info);
4645 if (!result) {
4646 if (sys_info.value & AMD_PG_SUPPORT_UVD)
4647 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4648 PHM_PlatformCaps_UVDPowerGating);
4649 if (sys_info.value & AMD_PG_SUPPORT_VCE)
4650 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
4651 PHM_PlatformCaps_VCEPowerGating);
4652 }
834b694c 4653
c82baa28 4654 if (0 == result) {
4655 data->is_tlu_enabled = 0;
4656 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
4657 TONGA_MAX_HARDWARE_POWERLEVELS;
4658 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
4659 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
4660
834b694c
AD		 4661 sys_info.size = sizeof(struct cgs_system_info);
4662 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
4663 result = cgs_query_system_info(hwmgr->device, &sys_info);
4664 if (result)
4665 data->pcie_gen_cap = 0x30007;
4666 else
4667 data->pcie_gen_cap = (uint32_t)sys_info.value;
4668 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
4669 data->pcie_spc_cap = 20;
4670 sys_info.size = sizeof(struct cgs_system_info);
4671 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
4672 result = cgs_query_system_info(hwmgr->device, &sys_info);
4673 if (result)
4674 data->pcie_lane_cap = 0x2f0000;
4675 else
4676 data->pcie_lane_cap = (uint32_t)sys_info.value;
c82baa28 4677 } else {
4678 /* Ignore return value in here, we are cleaning up a mess. */
4679 tonga_hwmgr_backend_fini(hwmgr);
4680 }
4681
4682 return result;
4683}
4684
4685static int tonga_force_dpm_level(struct pp_hwmgr *hwmgr,
4686 enum amd_dpm_forced_level level)
4687{
4688 int ret = 0;
4689
4690 switch (level) {
4691 case AMD_DPM_FORCED_LEVEL_HIGH:
4692 ret = tonga_force_dpm_highest(hwmgr);
4693 if (ret)
4694 return ret;
4695 break;
4696 case AMD_DPM_FORCED_LEVEL_LOW:
4697 ret = tonga_force_dpm_lowest(hwmgr);
4698 if (ret)
4699 return ret;
4700 break;
4701 case AMD_DPM_FORCED_LEVEL_AUTO:
4702 ret = tonga_unforce_dpm_levels(hwmgr);
4703 if (ret)
4704 return ret;
4705 break;
4706 default:
4707 break;
4708 }
4709
4710 hwmgr->dpm_level = level;
4711 return ret;
4712}
4713
4714static int tonga_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
4715 struct pp_power_state *prequest_ps,
4716 const struct pp_power_state *pcurrent_ps)
4717{
4718 struct tonga_power_state *tonga_ps =
4719 cast_phw_tonga_power_state(&prequest_ps->hardware);
4720
4721 uint32_t sclk;
4722 uint32_t mclk;
4723 struct PP_Clocks minimum_clocks = {0};
4724 bool disable_mclk_switching;
4725 bool disable_mclk_switching_for_frame_lock;
4726 struct cgs_display_info info = {0};
4727 const struct phm_clock_and_voltage_limits *max_limits;
4728 uint32_t i;
4729 tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4730 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
4731
4732 int32_t count;
4733 int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
4734
4735 data->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label);
4736
4737 PP_ASSERT_WITH_CODE(tonga_ps->performance_level_count == 2,
4738 "VI should always have 2 performance levels",
4739 );
4740
4741 max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
4742 &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
4743 &(hwmgr->dyn_state.max_clock_voltage_on_dc);
4744
4745 if (PP_PowerSource_DC == hwmgr->power_source) {
4746 for (i = 0; i < tonga_ps->performance_level_count; i++) {
4747 if (tonga_ps->performance_levels[i].memory_clock > max_limits->mclk)
4748 tonga_ps->performance_levels[i].memory_clock = max_limits->mclk;
4749 if (tonga_ps->performance_levels[i].engine_clock > max_limits->sclk)
4750 tonga_ps->performance_levels[i].engine_clock = max_limits->sclk;
4751 }
4752 }
4753
4754 tonga_ps->vce_clocks.EVCLK = hwmgr->vce_arbiter.evclk;
4755 tonga_ps->vce_clocks.ECCLK = hwmgr->vce_arbiter.ecclk;
4756
4757 tonga_ps->acp_clk = hwmgr->acp_arbiter.acpclk;
4758
4759 cgs_get_active_displays_info(hwmgr->device, &info);
4760
4761 /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
4762
4763 /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
4764
4765 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
4766
4767 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
4768 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
4769
4770 for (count = pptable_info->vdd_dep_on_sclk->count-1; count >= 0; count--) {
4771 if (stable_pstate_sclk >= pptable_info->vdd_dep_on_sclk->entries[count].clk) {
4772 stable_pstate_sclk = pptable_info->vdd_dep_on_sclk->entries[count].clk;
4773 break;
4774 }
4775 }
4776
4777 if (count < 0)
4778 stable_pstate_sclk = pptable_info->vdd_dep_on_sclk->entries[0].clk;
4779
4780 stable_pstate_mclk = max_limits->mclk;
4781
4782 minimum_clocks.engineClock = stable_pstate_sclk;
4783 minimum_clocks.memoryClock = stable_pstate_mclk;
4784 }
4785
4786 if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
4787 minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
4788
4789 if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
4790 minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
4791
4792 tonga_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
4793
4794 if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
4795 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <= hwmgr->platform_descriptor.overdriveLimit.engineClock),
4796 "Overdrive sclk exceeds limit",
4797 hwmgr->gfx_arbiter.sclk_over_drive = hwmgr->platform_descriptor.overdriveLimit.engineClock);
4798
4799 if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
4800 tonga_ps->performance_levels[1].engine_clock = hwmgr->gfx_arbiter.sclk_over_drive;
4801 }
4802
4803 if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
4804 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <= hwmgr->platform_descriptor.overdriveLimit.memoryClock),
4805 "Overdrive mclk exceeds limit",
4806 hwmgr->gfx_arbiter.mclk_over_drive = hwmgr->platform_descriptor.overdriveLimit.memoryClock);
4807
4808 if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
4809 tonga_ps->performance_levels[1].memory_clock = hwmgr->gfx_arbiter.mclk_over_drive;
4810 }
4811
4812 disable_mclk_switching_for_frame_lock = phm_cap_enabled(
4813 hwmgr->platform_descriptor.platformCaps,
4814 PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
4815
4816 disable_mclk_switching = (1 < info.display_count) ||
4817 disable_mclk_switching_for_frame_lock;
4818
4819 sclk = tonga_ps->performance_levels[0].engine_clock;
4820 mclk = tonga_ps->performance_levels[0].memory_clock;
4821
4822 if (disable_mclk_switching)
4823 mclk = tonga_ps->performance_levels[tonga_ps->performance_level_count - 1].memory_clock;
4824
4825 if (sclk < minimum_clocks.engineClock)
4826 sclk = (minimum_clocks.engineClock > max_limits->sclk) ? max_limits->sclk : minimum_clocks.engineClock;
4827
4828 if (mclk < minimum_clocks.memoryClock)
4829 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ? max_limits->mclk : minimum_clocks.memoryClock;
4830
4831 tonga_ps->performance_levels[0].engine_clock = sclk;
4832 tonga_ps->performance_levels[0].memory_clock = mclk;
4833
4834 tonga_ps->performance_levels[1].engine_clock =
4835 (tonga_ps->performance_levels[1].engine_clock >= tonga_ps->performance_levels[0].engine_clock) ?
4836 tonga_ps->performance_levels[1].engine_clock :
4837 tonga_ps->performance_levels[0].engine_clock;
4838
4839 if (disable_mclk_switching) {
4840 if (mclk < tonga_ps->performance_levels[1].memory_clock)
4841 mclk = tonga_ps->performance_levels[1].memory_clock;
4842
4843 tonga_ps->performance_levels[0].memory_clock = mclk;
4844 tonga_ps->performance_levels[1].memory_clock = mclk;
4845 } else {
4846 if (tonga_ps->performance_levels[1].memory_clock < tonga_ps->performance_levels[0].memory_clock)
4847 tonga_ps->performance_levels[1].memory_clock = tonga_ps->performance_levels[0].memory_clock;
4848 }
4849
4850 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
4851 for (i=0; i < tonga_ps->performance_level_count; i++) {
4852 tonga_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
4853 tonga_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
4854 tonga_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
4855 tonga_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
4856 }
4857 }
4858
4859 return 0;
4860}
4861
4862int tonga_get_power_state_size(struct pp_hwmgr *hwmgr)
4863{
4864 return sizeof(struct tonga_power_state);
4865}
4866
4867static int tonga_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
4868{
4869 struct pp_power_state *ps;
4870 struct tonga_power_state *tonga_ps;
4871
4872 if (hwmgr == NULL)
4873 return -EINVAL;
4874
4875 ps = hwmgr->request_ps;
4876
4877 if (ps == NULL)
4878 return -EINVAL;
4879
4880 tonga_ps = cast_phw_tonga_power_state(&ps->hardware);
4881
4882 if (low)
4883 return tonga_ps->performance_levels[0].memory_clock;
4884 else
4885 return tonga_ps->performance_levels[tonga_ps->performance_level_count-1].memory_clock;
4886}
4887
4888static int tonga_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
4889{
4890 struct pp_power_state *ps;
4891 struct tonga_power_state *tonga_ps;
4892
4893 if (hwmgr == NULL)
4894 return -EINVAL;
4895
4896 ps = hwmgr->request_ps;
4897
4898 if (ps == NULL)
4899 return -EINVAL;
4900
4901 tonga_ps = cast_phw_tonga_power_state(&ps->hardware);
4902
4903 if (low)
4904 return tonga_ps->performance_levels[0].engine_clock;
4905 else
4906 return tonga_ps->performance_levels[tonga_ps->performance_level_count-1].engine_clock;
4907}
4908
4909static uint16_t tonga_get_current_pcie_speed(
4910 struct pp_hwmgr *hwmgr)
4911{
4912 uint32_t speed_cntl = 0;
4913
4914 speed_cntl = cgs_read_ind_register(hwmgr->device,
4915 CGS_IND_REG__PCIE,
4916 ixPCIE_LC_SPEED_CNTL);
4917 return((uint16_t)PHM_GET_FIELD(speed_cntl,
4918 PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
4919}
4920
4921static int tonga_get_current_pcie_lane_number(
4922 struct pp_hwmgr *hwmgr)
4923{
4924 uint32_t link_width;
4925
4926 link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device,
4927 CGS_IND_REG__PCIE,
4928 PCIE_LC_LINK_WIDTH_CNTL,
4929 LC_LINK_WIDTH_RD);
4930
4931 PP_ASSERT_WITH_CODE((7 >= link_width),
4932 "Invalid PCIe lane width!", return 0);
4933
4934 return decode_pcie_lane_width(link_width);
4935}
4936
4937static int tonga_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
4938 struct pp_hw_power_state *hw_ps)
4939{
4940 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4941 struct tonga_power_state *ps = (struct tonga_power_state *)hw_ps;
4942 ATOM_FIRMWARE_INFO_V2_2 *fw_info;
4943 uint16_t size;
4944 uint8_t frev, crev;
4945 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
4946
4947 /* First retrieve the Boot clocks and VDDC from the firmware info table.
4948 * We assume here that fw_info is unchanged if this call fails.
4949 */
4950 fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
4951 hwmgr->device, index,
4952 &size, &frev, &crev);
4953 if (!fw_info)
4954 /* During a test, there is no firmware info table. */
4955 return 0;
4956
4957 /* Patch the state. */
4958 data->vbios_boot_state.sclk_bootup_value = le32_to_cpu(fw_info->ulDefaultEngineClock);
4959 data->vbios_boot_state.mclk_bootup_value = le32_to_cpu(fw_info->ulDefaultMemoryClock);
4960 data->vbios_boot_state.mvdd_bootup_value = le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
4961 data->vbios_boot_state.vddc_bootup_value = le16_to_cpu(fw_info->usBootUpVDDCVoltage);
4962 data->vbios_boot_state.vddci_bootup_value = le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
4963 data->vbios_boot_state.pcie_gen_bootup_value = tonga_get_current_pcie_speed(hwmgr);
4964 data->vbios_boot_state.pcie_lane_bootup_value =
4965 (uint16_t)tonga_get_current_pcie_lane_number(hwmgr);
4966
4967 /* set boot power state */
4968 ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
4969 ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
4970 ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
4971 ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
4972
4973 return 0;
4974}
4975
4976static int tonga_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
4977 void *state, struct pp_power_state *power_state,
4978 void *pp_table, uint32_t classification_flag)
4979{
4980 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
4981
4982 struct tonga_power_state *tonga_ps =
4983 (struct tonga_power_state *)(&(power_state->hardware));
4984
4985 struct tonga_performance_level *performance_level;
4986
4987 ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
4988
4989 ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
4990 (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
4991
4992 ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table =
4993 (ATOM_Tonga_SCLK_Dependency_Table *)
c9fe74e6 4994 (((unsigned long)powerplay_table) +
c82baa28 4995 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
4996
4997 ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
4998 (ATOM_Tonga_MCLK_Dependency_Table *)
c9fe74e6 4999 (((unsigned long)powerplay_table) +
c82baa28 5000 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
5001
5002 /* The following fields are not initialized here: id orderedList allStatesList */
5003 power_state->classification.ui_label =
5004 (le16_to_cpu(state_entry->usClassification) &
5005 ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
5006 ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
5007 power_state->classification.flags = classification_flag;
5008 /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
5009
5010 power_state->classification.temporary_state = false;
5011 power_state->classification.to_be_deleted = false;
5012
5013 power_state->validation.disallowOnDC =
5014 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & ATOM_Tonga_DISALLOW_ON_DC));
5015
5016 power_state->pcie.lanes = 0;
5017
5018 power_state->display.disableFrameModulation = false;
5019 power_state->display.limitRefreshrate = false;
5020 power_state->display.enableVariBright =
5021 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & ATOM_Tonga_ENABLE_VARIBRIGHT));
5022
5023 power_state->validation.supportedPowerLevels = 0;
5024 power_state->uvd_clocks.VCLK = 0;
5025 power_state->uvd_clocks.DCLK = 0;
5026 power_state->temperatures.min = 0;
5027 power_state->temperatures.max = 0;
5028
5029 performance_level = &(tonga_ps->performance_levels
5030 [tonga_ps->performance_level_count++]);
5031
5032 PP_ASSERT_WITH_CODE(
5033 (tonga_ps->performance_level_count < SMU72_MAX_LEVELS_GRAPHICS),
5034 "Performance levels exceeds SMC limit!",
5035 return -1);
5036
5037 PP_ASSERT_WITH_CODE(
5038 (tonga_ps->performance_level_count <=
5039 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
5040 "Performance levels exceeds Driver limit!",
5041 return -1);
5042
5043 /* Performance levels are arranged from low to high. */
5044 performance_level->memory_clock =
5045 le32_to_cpu(mclk_dep_table->entries[state_entry->ucMemoryClockIndexLow].ulMclk);
5046
5047 performance_level->engine_clock =
5048 le32_to_cpu(sclk_dep_table->entries[state_entry->ucEngineClockIndexLow].ulSclk);
5049
5050 performance_level->pcie_gen = get_pcie_gen_support(
5051 data->pcie_gen_cap,
5052 state_entry->ucPCIEGenLow);
5053
5054 performance_level->pcie_lane = get_pcie_lane_support(
5055 data->pcie_lane_cap,
5056 state_entry->ucPCIELaneHigh);
5057
5058 performance_level =
5059 &(tonga_ps->performance_levels[tonga_ps->performance_level_count++]);
5060
5061 performance_level->memory_clock =
5062 le32_to_cpu(mclk_dep_table->entries[state_entry->ucMemoryClockIndexHigh].ulMclk);
5063
5064 performance_level->engine_clock =
5065 le32_to_cpu(sclk_dep_table->entries[state_entry->ucEngineClockIndexHigh].ulSclk);
5066
5067 performance_level->pcie_gen = get_pcie_gen_support(
5068 data->pcie_gen_cap,
5069 state_entry->ucPCIEGenHigh);
5070
5071 performance_level->pcie_lane = get_pcie_lane_support(
5072 data->pcie_lane_cap,
5073 state_entry->ucPCIELaneHigh);
5074
5075 return 0;
5076}
5077
5078static int tonga_get_pp_table_entry(struct pp_hwmgr *hwmgr,
5079 unsigned long entry_index, struct pp_power_state *ps)
5080{
5081 int result;
5082 struct tonga_power_state *tonga_ps;
5083 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5084
5085 struct phm_ppt_v1_information *table_info =
5086 (struct phm_ppt_v1_information *)(hwmgr->pptable);
5087
5088 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
5089 table_info->vdd_dep_on_mclk;
5090
5091 ps->hardware.magic = PhwTonga_Magic;
5092
5093 tonga_ps = cast_phw_tonga_power_state(&(ps->hardware));
5094
5095 result = tonga_get_powerplay_table_entry(hwmgr, entry_index, ps,
5096 tonga_get_pp_table_entry_callback_func);
5097
5098 /* This is the earliest time we have all the dependency table and the VBIOS boot state
5099 * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
5100 * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
5101 */
5102 if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
5103 if (dep_mclk_table->entries[0].clk !=
5104 data->vbios_boot_state.mclk_bootup_value)
5105 printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
5106 "does not match VBIOS boot MCLK level");
5107 if (dep_mclk_table->entries[0].vddci !=
5108 data->vbios_boot_state.vddci_bootup_value)
5109 printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
5110 "does not match VBIOS boot VDDCI level");
5111 }
5112
5113 /* set DC compatible flag if this state supports DC */
5114 if (!ps->validation.disallowOnDC)
5115 tonga_ps->dc_compatible = true;
5116
5117 if (ps->classification.flags & PP_StateClassificationFlag_ACPI)
5118 data->acpi_pcie_gen = tonga_ps->performance_levels[0].pcie_gen;
5119 else if (ps->classification.flags & PP_StateClassificationFlag_Boot) {
5120 if (data->bacos.best_match == 0xffff) {
5121 /* For V.I. use boot state as base BACO state */
5122 data->bacos.best_match = PP_StateClassificationFlag_Boot;
5123 data->bacos.performance_level = tonga_ps->performance_levels[0];
5124 }
5125 }
5126
5127 tonga_ps->uvd_clocks.VCLK = ps->uvd_clocks.VCLK;
5128 tonga_ps->uvd_clocks.DCLK = ps->uvd_clocks.DCLK;
5129
5130 if (!result) {
5131 uint32_t i;
5132
5133 switch (ps->classification.ui_label) {
5134 case PP_StateUILabel_Performance:
5135 data->use_pcie_performance_levels = true;
5136
5137 for (i = 0; i < tonga_ps->performance_level_count; i++) {
5138 if (data->pcie_gen_performance.max <
5139 tonga_ps->performance_levels[i].pcie_gen)
5140 data->pcie_gen_performance.max =
5141 tonga_ps->performance_levels[i].pcie_gen;
5142
5143 if (data->pcie_gen_performance.min >
5144 tonga_ps->performance_levels[i].pcie_gen)
5145 data->pcie_gen_performance.min =
5146 tonga_ps->performance_levels[i].pcie_gen;
5147
5148 if (data->pcie_lane_performance.max <
5149 tonga_ps->performance_levels[i].pcie_lane)
5150 data->pcie_lane_performance.max =
5151 tonga_ps->performance_levels[i].pcie_lane;
5152
5153 if (data->pcie_lane_performance.min >
5154 tonga_ps->performance_levels[i].pcie_lane)
5155 data->pcie_lane_performance.min =
5156 tonga_ps->performance_levels[i].pcie_lane;
5157 }
5158 break;
5159 case PP_StateUILabel_Battery:
5160 data->use_pcie_power_saving_levels = true;
5161
5162 for (i = 0; i < tonga_ps->performance_level_count; i++) {
5163 if (data->pcie_gen_power_saving.max <
5164 tonga_ps->performance_levels[i].pcie_gen)
5165 data->pcie_gen_power_saving.max =
5166 tonga_ps->performance_levels[i].pcie_gen;
5167
5168 if (data->pcie_gen_power_saving.min >
5169 tonga_ps->performance_levels[i].pcie_gen)
5170 data->pcie_gen_power_saving.min =
5171 tonga_ps->performance_levels[i].pcie_gen;
5172
5173 if (data->pcie_lane_power_saving.max <
5174 tonga_ps->performance_levels[i].pcie_lane)
5175 data->pcie_lane_power_saving.max =
5176 tonga_ps->performance_levels[i].pcie_lane;
5177
5178 if (data->pcie_lane_power_saving.min >
5179 tonga_ps->performance_levels[i].pcie_lane)
5180 data->pcie_lane_power_saving.min =
5181 tonga_ps->performance_levels[i].pcie_lane;
5182 }
5183 break;
5184 default:
5185 break;
5186 }
5187 }
5188 return 0;
5189}
5190
5191static void
5192tonga_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
5193{
ab4f4b14 5194 uint32_t sclk, mclk, activity_percent;
9c5f8de6
RZ		 5195 uint32_t offset;
5196 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
c82baa28 5197
5198 smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)(PPSMC_MSG_API_GetSclkFrequency));
5199
5200 sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5201
5202 smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)(PPSMC_MSG_API_GetMclkFrequency));
5203
5204 mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5205 seq_printf(m, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n", mclk/100, sclk/100);
9c5f8de6 5206
9c5f8de6 5207 offset = data->soft_regs_start + offsetof(SMU72_SoftRegisters, AverageGraphicsActivity);
ab4f4b14
RZ		 5208 activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
5209 activity_percent += 0x80;
5210 activity_percent >>= 8;
9c5f8de6 5211
ab4f4b14 5212 seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
9c5f8de6 5213
d27d4941
RZ		 5214 seq_printf(m, "uvd %sabled\n", data->uvd_power_gated ? "dis" : "en");
5215
5216 seq_printf(m, "vce %sabled\n", data->vce_power_gated ? "dis" : "en");
c82baa28 5217}
5218
5219static int tonga_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
5220{
5221 const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5222 const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state);
5223 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5224 struct tonga_single_dpm_table *psclk_table = &(data->dpm_table.sclk_table);
5225 uint32_t sclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].engine_clock;
5226 struct tonga_single_dpm_table *pmclk_table = &(data->dpm_table.mclk_table);
5227 uint32_t mclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].memory_clock;
5228 struct PP_Clocks min_clocks = {0};
5229 uint32_t i;
5230 struct cgs_display_info info = {0};
5231
5232 data->need_update_smu7_dpm_table = 0;
5233
5234 for (i = 0; i < psclk_table->count; i++) {
5235 if (sclk == psclk_table->dpm_levels[i].value)
5236 break;
5237 }
5238
5239 if (i >= psclk_table->count)
5240 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
5241 else {
5242 /* TODO: Check SCLK in DAL's minimum clocks in case DeepSleep divider update is required.*/
5243 if(data->display_timing.min_clock_insr != min_clocks.engineClockInSR)
5244 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
5245 }
5246
5247 for (i=0; i < pmclk_table->count; i++) {
5248 if (mclk == pmclk_table->dpm_levels[i].value)
5249 break;
5250 }
5251
5252 if (i >= pmclk_table->count)
5253 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
5254
5255 cgs_get_active_displays_info(hwmgr->device, &info);
5256
5257 if (data->display_timing.num_existing_displays != info.display_count)
5258 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
5259
5260 return 0;
5261}
5262
5263static uint16_t tonga_get_maximum_link_speed(struct pp_hwmgr *hwmgr, const struct tonga_power_state *hw_ps)
5264{
5265 uint32_t i;
5266 uint32_t sclk, max_sclk = 0;
5267 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5268 struct tonga_dpm_table *pdpm_table = &data->dpm_table;
5269
5270 for (i = 0; i < hw_ps->performance_level_count; i++) {
5271 sclk = hw_ps->performance_levels[i].engine_clock;
5272 if (max_sclk < sclk)
5273 max_sclk = sclk;
5274 }
5275
5276 for (i = 0; i < pdpm_table->sclk_table.count; i++) {
5277 if (pdpm_table->sclk_table.dpm_levels[i].value == max_sclk)
5278 return (uint16_t) ((i >= pdpm_table->pcie_speed_table.count) ?
5279 pdpm_table->pcie_speed_table.dpm_levels[pdpm_table->pcie_speed_table.count-1].value :
5280 pdpm_table->pcie_speed_table.dpm_levels[i].value);
5281 }
5282
5283 return 0;
5284}
5285
5286static int tonga_request_link_speed_change_before_state_change(struct pp_hwmgr *hwmgr, const void *input)
5287{
5288 const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5289 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5290 const struct tonga_power_state *tonga_nps = cast_const_phw_tonga_power_state(states->pnew_state);
5291 const struct tonga_power_state *tonga_cps = cast_const_phw_tonga_power_state(states->pcurrent_state);
5292
5293 uint16_t target_link_speed = tonga_get_maximum_link_speed(hwmgr, tonga_nps);
5294 uint16_t current_link_speed;
5295
5296 if (data->force_pcie_gen == PP_PCIEGenInvalid)
5297 current_link_speed = tonga_get_maximum_link_speed(hwmgr, tonga_cps);
5298 else
5299 current_link_speed = data->force_pcie_gen;
5300
5301 data->force_pcie_gen = PP_PCIEGenInvalid;
5302 data->pspp_notify_required = false;
5303 if (target_link_speed > current_link_speed) {
5304 switch(target_link_speed) {
5305 case PP_PCIEGen3:
5306 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
5307 break;
5308 data->force_pcie_gen = PP_PCIEGen2;
5309 if (current_link_speed == PP_PCIEGen2)
5310 break;
5311 case PP_PCIEGen2:
5312 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
5313 break;
5314 default:
5315 data->force_pcie_gen = tonga_get_current_pcie_speed(hwmgr);
5316 break;
5317 }
5318 } else {
5319 if (target_link_speed < current_link_speed)
5320 data->pspp_notify_required = true;
5321 }
5322
5323 return 0;
5324}
5325
5326static int tonga_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
5327{
5328 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5329
5330 if (0 == data->need_update_smu7_dpm_table)
5331 return 0;
5332
5333 if ((0 == data->sclk_dpm_key_disabled) &&
5334 (data->need_update_smu7_dpm_table &
5335 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
5336 PP_ASSERT_WITH_CODE(
5337 true == tonga_is_dpm_running(hwmgr),
5338 "Trying to freeze SCLK DPM when DPM is disabled",
5339 );
5340 PP_ASSERT_WITH_CODE(
5341 0 == smum_send_msg_to_smc(hwmgr->smumgr,
5342 PPSMC_MSG_SCLKDPM_FreezeLevel),
5343 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
5344 return -1);
5345 }
5346
5347 if ((0 == data->mclk_dpm_key_disabled) &&
5348 (data->need_update_smu7_dpm_table &
5349 DPMTABLE_OD_UPDATE_MCLK)) {
5350 PP_ASSERT_WITH_CODE(true == tonga_is_dpm_running(hwmgr),
5351 "Trying to freeze MCLK DPM when DPM is disabled",
5352 );
5353 PP_ASSERT_WITH_CODE(
5354 0 == smum_send_msg_to_smc(hwmgr->smumgr,
5355 PPSMC_MSG_MCLKDPM_FreezeLevel),
5356 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
5357 return -1);
5358 }
5359
5360 return 0;
5361}
5362
5363static int tonga_populate_and_upload_sclk_mclk_dpm_levels(struct pp_hwmgr *hwmgr, const void *input)
5364{
5365 int result = 0;
5366
5367 const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5368 const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state);
5369 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5370 uint32_t sclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].engine_clock;
5371 uint32_t mclk = tonga_ps->performance_levels[tonga_ps->performance_level_count-1].memory_clock;
5372 struct tonga_dpm_table *pdpm_table = &data->dpm_table;
5373
5374 struct tonga_dpm_table *pgolden_dpm_table = &data->golden_dpm_table;
5375 uint32_t dpm_count, clock_percent;
5376 uint32_t i;
5377
5378 if (0 == data->need_update_smu7_dpm_table)
5379 return 0;
5380
5381 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
5382 pdpm_table->sclk_table.dpm_levels[pdpm_table->sclk_table.count-1].value = sclk;
5383
5384 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
5385 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
5386 /* Need to do calculation based on the golden DPM table
5387 * as the Heatmap GPU Clock axis is also based on the default values
5388 */
5389 PP_ASSERT_WITH_CODE(
5390 (pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value != 0),
5391 "Divide by 0!",
5392 return -1);
5393 dpm_count = pdpm_table->sclk_table.count < 2 ? 0 : pdpm_table->sclk_table.count-2;
5394 for (i = dpm_count; i > 1; i--) {
5395 if (sclk > pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value) {
5396 clock_percent = ((sclk - pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value)*100) /
5397 pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value;
5398
5399 pdpm_table->sclk_table.dpm_levels[i].value =
5400 pgolden_dpm_table->sclk_table.dpm_levels[i].value +
5401 (pgolden_dpm_table->sclk_table.dpm_levels[i].value * clock_percent)/100;
5402
5403 } else if (pgolden_dpm_table->sclk_table.dpm_levels[pdpm_table->sclk_table.count-1].value > sclk) {
5404 clock_percent = ((pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value - sclk)*100) /
5405 pgolden_dpm_table->sclk_table.dpm_levels[pgolden_dpm_table->sclk_table.count-1].value;
5406
5407 pdpm_table->sclk_table.dpm_levels[i].value =
5408 pgolden_dpm_table->sclk_table.dpm_levels[i].value -
5409 (pgolden_dpm_table->sclk_table.dpm_levels[i].value * clock_percent)/100;
5410 } else
5411 pdpm_table->sclk_table.dpm_levels[i].value =
5412 pgolden_dpm_table->sclk_table.dpm_levels[i].value;
5413 }
5414 }
5415 }
5416
5417 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
5418 pdpm_table->mclk_table.dpm_levels[pdpm_table->mclk_table.count-1].value = mclk;
5419
5420 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
5421 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
5422
5423 PP_ASSERT_WITH_CODE(
5424 (pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value != 0),
5425 "Divide by 0!",
5426 return -1);
5427 dpm_count = pdpm_table->mclk_table.count < 2? 0 : pdpm_table->mclk_table.count-2;
5428 for (i = dpm_count; i > 1; i--) {
5429 if (mclk > pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value) {
5430 clock_percent = ((mclk - pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value)*100) /
5431 pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value;
5432
5433 pdpm_table->mclk_table.dpm_levels[i].value =
5434 pgolden_dpm_table->mclk_table.dpm_levels[i].value +
5435 (pgolden_dpm_table->mclk_table.dpm_levels[i].value * clock_percent)/100;
5436
5437 } else if (pgolden_dpm_table->mclk_table.dpm_levels[pdpm_table->mclk_table.count-1].value > mclk) {
5438 clock_percent = ((pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value - mclk)*100) /
5439 pgolden_dpm_table->mclk_table.dpm_levels[pgolden_dpm_table->mclk_table.count-1].value;
5440
5441 pdpm_table->mclk_table.dpm_levels[i].value =
5442 pgolden_dpm_table->mclk_table.dpm_levels[i].value -
5443 (pgolden_dpm_table->mclk_table.dpm_levels[i].value * clock_percent)/100;
5444 } else
5445 pdpm_table->mclk_table.dpm_levels[i].value = pgolden_dpm_table->mclk_table.dpm_levels[i].value;
5446 }
5447 }
5448 }
5449
5450 if (data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
5451 result = tonga_populate_all_memory_levels(hwmgr);
5452 PP_ASSERT_WITH_CODE((0 == result),
5453 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
5454 return result);
5455 }
5456
5457 if (data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
5458 /*populate MCLK dpm table to SMU7 */
5459 result = tonga_populate_all_memory_levels(hwmgr);
5460 PP_ASSERT_WITH_CODE((0 == result),
5461 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
5462 return result);
5463 }
5464
5465 return result;
5466}
5467
5468static int tonga_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
5469 struct tonga_single_dpm_table * pdpm_table,
5470 uint32_t low_limit, uint32_t high_limit)
5471{
5472 uint32_t i;
5473
5474 for (i = 0; i < pdpm_table->count; i++) {
5475 if ((pdpm_table->dpm_levels[i].value < low_limit) ||
5476 (pdpm_table->dpm_levels[i].value > high_limit))
5477 pdpm_table->dpm_levels[i].enabled = false;
5478 else
5479 pdpm_table->dpm_levels[i].enabled = true;
5480 }
5481 return 0;
5482}
5483
5484static int tonga_trim_dpm_states(struct pp_hwmgr *hwmgr, const struct tonga_power_state *hw_state)
5485{
5486 int result = 0;
5487 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5488 uint32_t high_limit_count;
5489
5490 PP_ASSERT_WITH_CODE((hw_state->performance_level_count >= 1),
5491 "power state did not have any performance level",
5492 return -1);
5493
5494 high_limit_count = (1 == hw_state->performance_level_count) ? 0: 1;
5495
5496 tonga_trim_single_dpm_states(hwmgr,
5497 &(data->dpm_table.sclk_table),
5498 hw_state->performance_levels[0].engine_clock,
5499 hw_state->performance_levels[high_limit_count].engine_clock);
5500
5501 tonga_trim_single_dpm_states(hwmgr,
5502 &(data->dpm_table.mclk_table),
5503 hw_state->performance_levels[0].memory_clock,
5504 hw_state->performance_levels[high_limit_count].memory_clock);
5505
5506 return result;
5507}
5508
5509static int tonga_generate_dpm_level_enable_mask(struct pp_hwmgr *hwmgr, const void *input)
5510{
5511 int result;
5512 const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5513 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5514 const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state);
5515
c82baa28 5516 result = tonga_trim_dpm_states(hwmgr, tonga_ps);
5517 if (0 != result)
5518 return result;
5519
5520 data->dpm_level_enable_mask.sclk_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
5521 data->dpm_level_enable_mask.mclk_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
5522 data->last_mclk_dpm_enable_mask = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
5523 if (data->uvd_enabled)
5524 data->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
5525
5526 data->dpm_level_enable_mask.pcie_dpm_enable_mask = tonga_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
5527
5528 return 0;
5529}
5530
0859ed3d 5531int tonga_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
c82baa28 5532{
0859ed3d 5533 return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
c82baa28 5534 (PPSMC_Msg)PPSMC_MSG_VCEDPM_Enable :
5535 (PPSMC_Msg)PPSMC_MSG_VCEDPM_Disable);
5536}
5537
0859ed3d
RZ		 5538int tonga_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
5539{
5540 return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
5541 (PPSMC_Msg)PPSMC_MSG_UVDDPM_Enable :
5542 (PPSMC_Msg)PPSMC_MSG_UVDDPM_Disable);
5543}
5544
5545int tonga_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
5546{
5547 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5548 uint32_t mm_boot_level_offset, mm_boot_level_value;
5549 struct phm_ppt_v1_information *ptable_information = (struct phm_ppt_v1_information *)(hwmgr->pptable);
5550
5551 if (!bgate) {
5552 data->smc_state_table.UvdBootLevel = (uint8_t) (ptable_information->mm_dep_table->count - 1);
5553 mm_boot_level_offset = data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable, UvdBootLevel);
5554 mm_boot_level_offset /= 4;
5555 mm_boot_level_offset *= 4;
5556 mm_boot_level_value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset);
5557 mm_boot_level_value &= 0x00FFFFFF;
5558 mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24;
5559 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
5560
5561 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM) ||
5562 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
5563 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5564 PPSMC_MSG_UVDDPM_SetEnabledMask,
5565 (uint32_t)(1 << data->smc_state_table.UvdBootLevel));
5566 }
5567
5568 return tonga_enable_disable_uvd_dpm(hwmgr, !bgate);
5569}
5570
5571int tonga_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
c82baa28 5572{
5573 const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5574 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5575 const struct tonga_power_state *tonga_nps = cast_const_phw_tonga_power_state(states->pnew_state);
5576 const struct tonga_power_state *tonga_cps = cast_const_phw_tonga_power_state(states->pcurrent_state);
5577
5578 uint32_t mm_boot_level_offset, mm_boot_level_value;
5579 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
5580
0859ed3d 5581 if (tonga_nps->vce_clocks.EVCLK > 0 && (tonga_cps == NULL || tonga_cps->vce_clocks.EVCLK == 0)) {
c82baa28 5582 data->smc_state_table.VceBootLevel = (uint8_t) (pptable_info->mm_dep_table->count - 1);
5583
5584 mm_boot_level_offset = data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable, VceBootLevel);
5585 mm_boot_level_offset /= 4;
5586 mm_boot_level_offset *= 4;
5587 mm_boot_level_value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset);
5588 mm_boot_level_value &= 0xFF00FFFF;
5589 mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
5590 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
5591
0859ed3d
RZ		 5592 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
5593 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5594 PPSMC_MSG_VCEDPM_SetEnabledMask,
5595 (uint32_t)(1 << data->smc_state_table.VceBootLevel));
c82baa28 5596
0859ed3d
RZ		 5597 tonga_enable_disable_vce_dpm(hwmgr, true);
5598 } else if (tonga_nps->vce_clocks.EVCLK == 0 && tonga_cps != NULL && tonga_cps->vce_clocks.EVCLK > 0)
5599 tonga_enable_disable_vce_dpm(hwmgr, false);
c82baa28 5600
5601 return 0;
5602}
5603
5604static int tonga_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
5605{
5606 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5607
5608 uint32_t address;
5609 int32_t result;
5610
5611 if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
5612 return 0;
5613
5614
5615 memset(&data->mc_reg_table, 0, sizeof(SMU72_Discrete_MCRegisters));
5616
5617 result = tonga_convert_mc_reg_table_to_smc(hwmgr, &(data->mc_reg_table));
5618
5619 if(result != 0)
5620 return result;
5621
5622
5623 address = data->mc_reg_table_start + (uint32_t)offsetof(SMU72_Discrete_MCRegisters, data[0]);
5624
5625 return tonga_copy_bytes_to_smc(hwmgr->smumgr, address,
5626 (uint8_t *)&data->mc_reg_table.data[0],
5627 sizeof(SMU72_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count,
5628 data->sram_end);
5629}
5630
5631static int tonga_program_memory_timing_parameters_conditionally(struct pp_hwmgr *hwmgr)
5632{
5633 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5634
5635 if (data->need_update_smu7_dpm_table &
5636 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
5637 return tonga_program_memory_timing_parameters(hwmgr);
5638
5639 return 0;
5640}
5641
5642static int tonga_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
5643{
5644 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5645
5646 if (0 == data->need_update_smu7_dpm_table)
5647 return 0;
5648
5649 if ((0 == data->sclk_dpm_key_disabled) &&
5650 (data->need_update_smu7_dpm_table &
5651 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
5652
5653 PP_ASSERT_WITH_CODE(true == tonga_is_dpm_running(hwmgr),
5654 "Trying to Unfreeze SCLK DPM when DPM is disabled",
5655 );
5656 PP_ASSERT_WITH_CODE(
5657 0 == smum_send_msg_to_smc(hwmgr->smumgr,
5658 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
5659 "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
5660 return -1);
5661 }
5662
5663 if ((0 == data->mclk_dpm_key_disabled) &&
5664 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
5665
5666 PP_ASSERT_WITH_CODE(
5667 true == tonga_is_dpm_running(hwmgr),
5668 "Trying to Unfreeze MCLK DPM when DPM is disabled",
5669 );
5670 PP_ASSERT_WITH_CODE(
5671 0 == smum_send_msg_to_smc(hwmgr->smumgr,
5672 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
5673 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
5674 return -1);
5675 }
5676
5677 data->need_update_smu7_dpm_table = 0;
5678
5679 return 0;
5680}
5681
5682static int tonga_notify_link_speed_change_after_state_change(struct pp_hwmgr *hwmgr, const void *input)
5683{
5684 const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input;
5685 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5686 const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state);
5687 uint16_t target_link_speed = tonga_get_maximum_link_speed(hwmgr, tonga_ps);
5688 uint8_t request;
5689
5690 if (data->pspp_notify_required ||
5691 data->pcie_performance_request) {
5692 if (target_link_speed == PP_PCIEGen3)
5693 request = PCIE_PERF_REQ_GEN3;
5694 else if (target_link_speed == PP_PCIEGen2)
5695 request = PCIE_PERF_REQ_GEN2;
5696 else
5697 request = PCIE_PERF_REQ_GEN1;
5698
5699 if(request == PCIE_PERF_REQ_GEN1 && tonga_get_current_pcie_speed(hwmgr) > 0) {
5700 data->pcie_performance_request = false;
5701 return 0;
5702 }
5703
5704 if (0 != acpi_pcie_perf_request(hwmgr->device, request, false)) {
5705 if (PP_PCIEGen2 == target_link_speed)
5706 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
5707 else
5708 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
5709 }
5710 }
5711
5712 data->pcie_performance_request = false;
5713 return 0;
5714}
5715
5716static int tonga_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
5717{
5718 int tmp_result, result = 0;
5719
5720 tmp_result = tonga_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
5721 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to find DPM states clocks in DPM table!", result = tmp_result);
5722
5723 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest)) {
5724 tmp_result = tonga_request_link_speed_change_before_state_change(hwmgr, input);
5725 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to request link speed change before state change!", result = tmp_result);
5726 }
5727
5728 tmp_result = tonga_freeze_sclk_mclk_dpm(hwmgr);
5729 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
5730
5731 tmp_result = tonga_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
5732 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to populate and upload SCLK MCLK DPM levels!", result = tmp_result);
5733
5734 tmp_result = tonga_generate_dpm_level_enable_mask(hwmgr, input);
5735 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to generate DPM level enabled mask!", result = tmp_result);
5736
5737 tmp_result = tonga_update_vce_dpm(hwmgr, input);
5738 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to update VCE DPM!", result = tmp_result);
5739
5740 tmp_result = tonga_update_sclk_threshold(hwmgr);
5741 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to update SCLK threshold!", result = tmp_result);
5742
5743 tmp_result = tonga_update_and_upload_mc_reg_table(hwmgr);
5744 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to upload MC reg table!", result = tmp_result);
5745
5746 tmp_result = tonga_program_memory_timing_parameters_conditionally(hwmgr);
5747 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to program memory timing parameters!", result = tmp_result);
5748
5749 tmp_result = tonga_unfreeze_sclk_mclk_dpm(hwmgr);
5750 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to unfreeze SCLK MCLK DPM!", result = tmp_result);
5751
5752 tmp_result = tonga_upload_dpm_level_enable_mask(hwmgr);
5753 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to upload DPM level enabled mask!", result = tmp_result);
5754
5755 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest)) {
5756 tmp_result = tonga_notify_link_speed_change_after_state_change(hwmgr, input);
5757 PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to notify link speed change after state change!", result = tmp_result);
5758 }
5759
5760 return result;
5761}
5762
1e4854e9
RZ		 5763/**
5764* Set maximum target operating fan output PWM
5765*
5766* @param pHwMgr: the address of the powerplay hardware manager.
5767* @param usMaxFanPwm: max operating fan PWM in percents
5768* @return The response that came from the SMC.
5769*/
5770static int tonga_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
5771{
5772 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
5773
5774 if (phm_is_hw_access_blocked(hwmgr))
5775 return 0;
5776
c15c8d70 5777 return (0 == smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm) ? 0 : -1);
1e4854e9 5778}
bbb207f3
RZ		 5779
5780int tonga_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
5781{
5782 uint32_t num_active_displays = 0;
5783 struct cgs_display_info info = {0};
5784 info.mode_info = NULL;
5785
5786 cgs_get_active_displays_info(hwmgr->device, &info);
5787
5788 num_active_displays = info.display_count;
5789
5790 if (num_active_displays > 1) /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */
5791 tonga_notify_smc_display_change(hwmgr, false);
5792 else
5793 tonga_notify_smc_display_change(hwmgr, true);
5794
5795 return 0;
5796}
5797
5798/**
5799* Programs the display gap
5800*
5801* @param hwmgr the address of the powerplay hardware manager.
5802* @return always OK
5803*/
5804int tonga_program_display_gap(struct pp_hwmgr *hwmgr)
5805{
5806 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5807 uint32_t num_active_displays = 0;
5808 uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
5809 uint32_t display_gap2;
5810 uint32_t pre_vbi_time_in_us;
5811 uint32_t frame_time_in_us;
5812 uint32_t ref_clock;
5813 uint32_t refresh_rate = 0;
5814 struct cgs_display_info info = {0};
5815 struct cgs_mode_info mode_info;
5816
5817 info.mode_info = &mode_info;
5818
5819 cgs_get_active_displays_info(hwmgr->device, &info);
5820 num_active_displays = info.display_count;
5821
5822 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0)? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
5823 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
5824
5825 ref_clock = mode_info.ref_clock;
5826 refresh_rate = mode_info.refresh_rate;
5827
5828 if(0 == refresh_rate)
5829 refresh_rate = 60;
5830
5831 frame_time_in_us = 1000000 / refresh_rate;
5832
5833 pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
5834 display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
5835
5836 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
5837
5838 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU72_SoftRegisters, PreVBlankGap), 0x64);
5839
5840 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU72_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
5841
5842 if (num_active_displays == 1)
5843 tonga_notify_smc_display_change(hwmgr, true);
5844
5845 return 0;
5846}
5847
5848int tonga_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
5849{
5850
5851 tonga_program_display_gap(hwmgr);
5852
5853 /* to do PhwTonga_CacUpdateDisplayConfiguration(pHwMgr); */
5854 return 0;
5855}
5856
1e4854e9
RZ		 5857/**
5858* Set maximum target operating fan output RPM
5859*
5860* @param pHwMgr: the address of the powerplay hardware manager.
5861* @param usMaxFanRpm: max operating fan RPM value.
5862* @return The response that came from the SMC.
5863*/
5864static int tonga_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
5865{
5866 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM = us_max_fan_pwm;
5867
5868 if (phm_is_hw_access_blocked(hwmgr))
5869 return 0;
5870
c15c8d70 5871 return (0 == smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanRpmMax, us_max_fan_pwm) ? 0 : -1);
1e4854e9
RZ		 5872}
5873
5874uint32_t tonga_get_xclk(struct pp_hwmgr *hwmgr)
5875{
5876 uint32_t reference_clock;
5877 uint32_t tc;
5878 uint32_t divide;
5879
5880 ATOM_FIRMWARE_INFO *fw_info;
5881 uint16_t size;
5882 uint8_t frev, crev;
5883 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
5884
5885 tc = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK);
5886
5887 if (tc)
5888 return TCLK;
5889
5890 fw_info = (ATOM_FIRMWARE_INFO *)cgs_atom_get_data_table(hwmgr->device, index,
5891 &size, &frev, &crev);
5892
5893 if (!fw_info)
5894 return 0;
5895
dcf799e5 5896 reference_clock = le16_to_cpu(fw_info->usReferenceClock);
1e4854e9
RZ		 5897
5898 divide = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE);
5899
5900 if (0 != divide)
5901 return reference_clock / 4;
5902
5903 return reference_clock;
5904}
5905
5906int tonga_dpm_set_interrupt_state(void *private_data,
5907 unsigned src_id, unsigned type,
5908 int enabled)
5909{
5910 uint32_t cg_thermal_int;
5911 struct pp_hwmgr *hwmgr = ((struct pp_eventmgr *)private_data)->hwmgr;
5912
5913 if (hwmgr == NULL)
5914 return -EINVAL;
5915
5916 switch (type) {
5917 case AMD_THERMAL_IRQ_LOW_TO_HIGH:
5918 if (enabled) {
5919 cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5920 cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
5921 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5922 } else {
5923 cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5924 cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
5925 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5926 }
5927 break;
5928
5929 case AMD_THERMAL_IRQ_HIGH_TO_LOW:
5930 if (enabled) {
5931 cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5932 cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
5933 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5934 } else {
5935 cg_thermal_int = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5936 cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
5937 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5938 }
5939 break;
5940 default:
5941 break;
5942 }
5943 return 0;
5944}
5945
5946int tonga_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
5947 const void *thermal_interrupt_info)
5948{
5949 int result;
5950 const struct pp_interrupt_registration_info *info =
5951 (const struct pp_interrupt_registration_info *)thermal_interrupt_info;
5952
5953 if (info == NULL)
5954 return -EINVAL;
5955
5956 result = cgs_add_irq_source(hwmgr->device, 230, AMD_THERMAL_IRQ_LAST,
5957 tonga_dpm_set_interrupt_state,
5958 info->call_back, info->context);
5959
5960 if (result)
5961 return -EINVAL;
5962
5963 result = cgs_add_irq_source(hwmgr->device, 231, AMD_THERMAL_IRQ_LAST,
5964 tonga_dpm_set_interrupt_state,
5965 info->call_back, info->context);
5966
5967 if (result)
5968 return -EINVAL;
5969
5970 return 0;
5971}
5972
e829ecdb
RZ		 5973bool tonga_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
5974{
5975 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
5976 bool is_update_required = false;
5977 struct cgs_display_info info = {0,0,NULL};
5978
5979 cgs_get_active_displays_info(hwmgr->device, &info);
5980
5981 if (data->display_timing.num_existing_displays != info.display_count)
5982 is_update_required = true;
5983/* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
5984 if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
5985 cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
5986 if(min_clocks.engineClockInSR != data->display_timing.minClockInSR)
5987 is_update_required = true;
5988*/
5989 return is_update_required;
5990}
5991
5992static inline bool tonga_are_power_levels_equal(const struct tonga_performance_level *pl1,
5993 const struct tonga_performance_level *pl2)
5994{
5995 return ((pl1->memory_clock == pl2->memory_clock) &&
5996 (pl1->engine_clock == pl2->engine_clock) &&
5997 (pl1->pcie_gen == pl2->pcie_gen) &&
5998 (pl1->pcie_lane == pl2->pcie_lane));
5999}
6000
6001int tonga_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
6002{
6003 const struct tonga_power_state *psa = cast_const_phw_tonga_power_state(pstate1);
6004 const struct tonga_power_state *psb = cast_const_phw_tonga_power_state(pstate2);
6005 int i;
6006
c15c8d70 6007 if (equal == NULL || psa == NULL || psb == NULL)
e829ecdb
RZ		 6008 return -EINVAL;
6009
6010 /* If the two states don't even have the same number of performance levels they cannot be the same state. */
6011 if (psa->performance_level_count != psb->performance_level_count) {
6012 *equal = false;
6013 return 0;
6014 }
6015
6016 for (i = 0; i < psa->performance_level_count; i++) {
6017 if (!tonga_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
6018 /* If we have found even one performance level pair that is different the states are different. */
6019 *equal = false;
6020 return 0;
6021 }
6022 }
6023
6024 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
6025 *equal = ((psa->uvd_clocks.VCLK == psb->uvd_clocks.VCLK) && (psa->uvd_clocks.DCLK == psb->uvd_clocks.DCLK));
6026 *equal &= ((psa->vce_clocks.EVCLK == psb->vce_clocks.EVCLK) && (psa->vce_clocks.ECCLK == psb->vce_clocks.ECCLK));
6027 *equal &= (psa->sclk_threshold == psb->sclk_threshold);
6028 *equal &= (psa->acp_clk == psb->acp_clk);
6029
6030 return 0;
6031}
6032
9dcfc193
EH		 6033static int tonga_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
6034{
6035 if (mode) {
6036 /* stop auto-manage */
6037 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
6038 PHM_PlatformCaps_MicrocodeFanControl))
6039 tonga_fan_ctrl_stop_smc_fan_control(hwmgr);
6040 tonga_fan_ctrl_set_static_mode(hwmgr, mode);
6041 } else
6042 /* restart auto-manage */
6043 tonga_fan_ctrl_reset_fan_speed_to_default(hwmgr);
6044
6045 return 0;
6046}
6047
6048static int tonga_get_fan_control_mode(struct pp_hwmgr *hwmgr)
6049{
6050 if (hwmgr->fan_ctrl_is_in_default_mode)
6051 return hwmgr->fan_ctrl_default_mode;
6052 else
6053 return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
6054 CG_FDO_CTRL2, FDO_PWM_MODE);
6055}
6056
5d37a63d
EH		 6057static int tonga_get_pp_table(struct pp_hwmgr *hwmgr, char **table)
6058{
6059 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
6060
6061 *table = (char *)&data->smc_state_table;
6062
6063 return sizeof(struct SMU72_Discrete_DpmTable);
6064}
6065
6066static int tonga_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t size)
6067{
6068 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
6069
6070 void *table = (void *)&data->smc_state_table;
6071
6072 memcpy(table, buf, size);
6073
6074 return 0;
6075}
6076
6077static int tonga_force_clock_level(struct pp_hwmgr *hwmgr,
6078 enum pp_clock_type type, int level)
6079{
6080 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
6081
6082 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
6083 return -EINVAL;
6084
6085 switch (type) {
6086 case PP_SCLK:
6087 if (!data->sclk_dpm_key_disabled)
6088 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
6089 PPSMC_MSG_SCLKDPM_SetEnabledMask,
6090 (1 << level));
6091 break;
6092 case PP_MCLK:
6093 if (!data->mclk_dpm_key_disabled)
6094 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
6095 PPSMC_MSG_MCLKDPM_SetEnabledMask,
6096 (1 << level));
6097 break;
6098 case PP_PCIE:
6099 if (!data->pcie_dpm_key_disabled)
6100 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
6101 PPSMC_MSG_PCIeDPM_ForceLevel,
6102 (1 << level));
6103 break;
6104 default:
6105 break;
6106 }
6107
6108 return 0;
6109}
6110
6111static int tonga_print_clock_levels(struct pp_hwmgr *hwmgr,
6112 enum pp_clock_type type, char *buf)
6113{
6114 struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
6115 struct tonga_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
6116 struct tonga_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
6117 struct tonga_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
6118 int i, now, size = 0;
6119 uint32_t clock, pcie_speed;
6120
6121 switch (type) {
6122 case PP_SCLK:
6123 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
6124 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
6125
6126 for (i = 0; i < sclk_table->count; i++) {
6127 if (clock > sclk_table->dpm_levels[i].value)
6128 continue;
6129 break;
6130 }
6131 now = i;
6132
6133 for (i = 0; i < sclk_table->count; i++)
6134 size += sprintf(buf + size, "%d: %uMhz %s\n",
6135 i, sclk_table->dpm_levels[i].value / 100,
6136 (i == now) ? "*" : "");
6137 break;
6138 case PP_MCLK:
6139 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
6140 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
6141
6142 for (i = 0; i < mclk_table->count; i++) {
6143 if (clock > mclk_table->dpm_levels[i].value)
6144 continue;
6145 break;
6146 }
6147 now = i;
6148
6149 for (i = 0; i < mclk_table->count; i++)
6150 size += sprintf(buf + size, "%d: %uMhz %s\n",
6151 i, mclk_table->dpm_levels[i].value / 100,
6152 (i == now) ? "*" : "");
6153 break;
6154 case PP_PCIE:
6155 pcie_speed = tonga_get_current_pcie_speed(hwmgr);
6156 for (i = 0; i < pcie_table->count; i++) {
6157 if (pcie_speed != pcie_table->dpm_levels[i].value)
6158 continue;
6159 break;
6160 }
6161 now = i;
6162
6163 for (i = 0; i < pcie_table->count; i++)
6164 size += sprintf(buf + size, "%d: %s %s\n", i,
6165 (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" :
6166 (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
6167 (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
6168 (i == now) ? "*" : "");
6169 break;
6170 default:
6171 break;
6172 }
6173 return size;
6174}
6175
c82baa28 6176static const struct pp_hwmgr_func tonga_hwmgr_funcs = {
6177 .backend_init = &tonga_hwmgr_backend_init,
6178 .backend_fini = &tonga_hwmgr_backend_fini,
6179 .asic_setup = &tonga_setup_asic_task,
6180 .dynamic_state_management_enable = &tonga_enable_dpm_tasks,
6181 .apply_state_adjust_rules = tonga_apply_state_adjust_rules,
6182 .force_dpm_level = &tonga_force_dpm_level,
6183 .power_state_set = tonga_set_power_state_tasks,
6184 .get_power_state_size = tonga_get_power_state_size,
6185 .get_mclk = tonga_dpm_get_mclk,
6186 .get_sclk = tonga_dpm_get_sclk,
6187 .patch_boot_state = tonga_dpm_patch_boot_state,
6188 .get_pp_table_entry = tonga_get_pp_table_entry,
6189 .get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries,
6190 .print_current_perforce_level = tonga_print_current_perforce_level,
0859ed3d
RZ		 6191 .powerdown_uvd = tonga_phm_powerdown_uvd,
6192 .powergate_uvd = tonga_phm_powergate_uvd,
6193 .powergate_vce = tonga_phm_powergate_vce,
6194 .disable_clock_power_gating = tonga_phm_disable_clock_power_gating,
bbb207f3
RZ		 6195 .notify_smc_display_config_after_ps_adjustment = tonga_notify_smc_display_config_after_ps_adjustment,
6196 .display_config_changed = tonga_display_configuration_changed_task,
1e4854e9
RZ		 6197 .set_max_fan_pwm_output = tonga_set_max_fan_pwm_output,
6198 .set_max_fan_rpm_output = tonga_set_max_fan_rpm_output,
6199 .get_temperature = tonga_thermal_get_temperature,
6200 .stop_thermal_controller = tonga_thermal_stop_thermal_controller,
6201 .get_fan_speed_info = tonga_fan_ctrl_get_fan_speed_info,
6202 .get_fan_speed_percent = tonga_fan_ctrl_get_fan_speed_percent,
6203 .set_fan_speed_percent = tonga_fan_ctrl_set_fan_speed_percent,
6204 .reset_fan_speed_to_default = tonga_fan_ctrl_reset_fan_speed_to_default,
6205 .get_fan_speed_rpm = tonga_fan_ctrl_get_fan_speed_rpm,
6206 .set_fan_speed_rpm = tonga_fan_ctrl_set_fan_speed_rpm,
6207 .uninitialize_thermal_controller = tonga_thermal_ctrl_uninitialize_thermal_controller,
6208 .register_internal_thermal_interrupt = tonga_register_internal_thermal_interrupt,
e829ecdb
RZ		 6209 .check_smc_update_required_for_display_configuration = tonga_check_smc_update_required_for_display_configuration,
6210 .check_states_equal = tonga_check_states_equal,
9dcfc193
EH		 6211 .set_fan_control_mode = tonga_set_fan_control_mode,
6212 .get_fan_control_mode = tonga_get_fan_control_mode,
5d37a63d
EH		 6213 .get_pp_table = tonga_get_pp_table,
6214 .set_pp_table = tonga_set_pp_table,
6215 .force_clock_level = tonga_force_clock_level,
6216 .print_clock_levels = tonga_print_clock_levels,
c82baa28 6217};
6218
6219int tonga_hwmgr_init(struct pp_hwmgr *hwmgr)
6220{
6221 tonga_hwmgr *data;
6222
6223 data = kzalloc (sizeof(tonga_hwmgr), GFP_KERNEL);
6224 if (data == NULL)
6225 return -ENOMEM;
6226 memset(data, 0x00, sizeof(tonga_hwmgr));
6227
6228 hwmgr->backend = data;
6229 hwmgr->hwmgr_func = &tonga_hwmgr_funcs;
6230 hwmgr->pptable_func = &tonga_pptable_funcs;
1e4854e9 6231 pp_tonga_thermal_initialize(hwmgr);
c82baa28 6232 return 0;
6233}
6234
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