[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / powerplay / inc / amd_powerplay.h

/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#ifndef _AMD_POWERPLAY_H_
#define _AMD_POWERPLAY_H_

#include <linux/seq_file.h>
#include <linux/types.h>
#include "amd_shared.h"
#include "cgs_common.h"

enum amd_pp_event {
	AMD_PP_EVENT_INITIALIZE = 0,
	AMD_PP_EVENT_UNINITIALIZE,
	AMD_PP_EVENT_POWER_SOURCE_CHANGE,
	AMD_PP_EVENT_SUSPEND,
	AMD_PP_EVENT_RESUME,
	AMD_PP_EVENT_ENTER_REST_STATE,
	AMD_PP_EVENT_EXIT_REST_STATE,
	AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE,
	AMD_PP_EVENT_THERMAL_NOTIFICATION,
	AMD_PP_EVENT_VBIOS_NOTIFICATION,
	AMD_PP_EVENT_ENTER_THERMAL_STATE,
	AMD_PP_EVENT_EXIT_THERMAL_STATE,
	AMD_PP_EVENT_ENTER_FORCED_STATE,
	AMD_PP_EVENT_EXIT_FORCED_STATE,
	AMD_PP_EVENT_ENTER_EXCLUSIVE_MODE,
	AMD_PP_EVENT_EXIT_EXCLUSIVE_MODE,
	AMD_PP_EVENT_ENTER_SCREEN_SAVER,
	AMD_PP_EVENT_EXIT_SCREEN_SAVER,
	AMD_PP_EVENT_VPU_RECOVERY_BEGIN,
	AMD_PP_EVENT_VPU_RECOVERY_END,
	AMD_PP_EVENT_ENABLE_POWER_PLAY,
	AMD_PP_EVENT_DISABLE_POWER_PLAY,
	AMD_PP_EVENT_CHANGE_POWER_SOURCE_UI_LABEL,
	AMD_PP_EVENT_ENABLE_USER2D_PERFORMANCE,
	AMD_PP_EVENT_DISABLE_USER2D_PERFORMANCE,
	AMD_PP_EVENT_ENABLE_USER3D_PERFORMANCE,
	AMD_PP_EVENT_DISABLE_USER3D_PERFORMANCE,
	AMD_PP_EVENT_ENABLE_OVER_DRIVE_TEST,
	AMD_PP_EVENT_DISABLE_OVER_DRIVE_TEST,
	AMD_PP_EVENT_ENABLE_REDUCED_REFRESH_RATE,
	AMD_PP_EVENT_DISABLE_REDUCED_REFRESH_RATE,
	AMD_PP_EVENT_ENABLE_GFX_CLOCK_GATING,
	AMD_PP_EVENT_DISABLE_GFX_CLOCK_GATING,
	AMD_PP_EVENT_ENABLE_CGPG,
	AMD_PP_EVENT_DISABLE_CGPG,
	AMD_PP_EVENT_ENTER_TEXT_MODE,
	AMD_PP_EVENT_EXIT_TEXT_MODE,
	AMD_PP_EVENT_VIDEO_START,
	AMD_PP_EVENT_VIDEO_STOP,
	AMD_PP_EVENT_ENABLE_USER_STATE,
	AMD_PP_EVENT_DISABLE_USER_STATE,
	AMD_PP_EVENT_READJUST_POWER_STATE,
	AMD_PP_EVENT_START_INACTIVITY,
	AMD_PP_EVENT_STOP_INACTIVITY,
	AMD_PP_EVENT_LINKED_ADAPTERS_READY,
	AMD_PP_EVENT_ADAPTER_SAFE_TO_DISABLE,
	AMD_PP_EVENT_COMPLETE_INIT,
	AMD_PP_EVENT_CRITICAL_THERMAL_FAULT,
	AMD_PP_EVENT_BACKLIGHT_CHANGED,
	AMD_PP_EVENT_ENABLE_VARI_BRIGHT,
	AMD_PP_EVENT_DISABLE_VARI_BRIGHT,
	AMD_PP_EVENT_ENABLE_VARI_BRIGHT_ON_POWER_XPRESS,
	AMD_PP_EVENT_DISABLE_VARI_BRIGHT_ON_POWER_XPRESS,
	AMD_PP_EVENT_SET_VARI_BRIGHT_LEVEL,
	AMD_PP_EVENT_VARI_BRIGHT_MONITOR_MEASUREMENT,
	AMD_PP_EVENT_SCREEN_ON,
	AMD_PP_EVENT_SCREEN_OFF,
	AMD_PP_EVENT_PRE_DISPLAY_CONFIG_CHANGE,
	AMD_PP_EVENT_ENTER_ULP_STATE,
	AMD_PP_EVENT_EXIT_ULP_STATE,
	AMD_PP_EVENT_REGISTER_IP_STATE,
	AMD_PP_EVENT_UNREGISTER_IP_STATE,
	AMD_PP_EVENT_ENTER_MGPU_MODE,
	AMD_PP_EVENT_EXIT_MGPU_MODE,
	AMD_PP_EVENT_ENTER_MULTI_GPU_MODE,
	AMD_PP_EVENT_PRE_SUSPEND,
	AMD_PP_EVENT_PRE_RESUME,
	AMD_PP_EVENT_ENTER_BACOS,
	AMD_PP_EVENT_EXIT_BACOS,
	AMD_PP_EVENT_RESUME_BACO,
	AMD_PP_EVENT_RESET_BACO,
	AMD_PP_EVENT_PRE_DISPLAY_PHY_ACCESS,
	AMD_PP_EVENT_POST_DISPLAY_PHY_CCESS,
	AMD_PP_EVENT_START_COMPUTE_APPLICATION,
	AMD_PP_EVENT_STOP_COMPUTE_APPLICATION,
	AMD_PP_EVENT_REDUCE_POWER_LIMIT,
	AMD_PP_EVENT_ENTER_FRAME_LOCK,
	AMD_PP_EVENT_EXIT_FRAME_LOOCK,
	AMD_PP_EVENT_LONG_IDLE_REQUEST_BACO,
	AMD_PP_EVENT_LONG_IDLE_ENTER_BACO,
	AMD_PP_EVENT_LONG_IDLE_EXIT_BACO,
	AMD_PP_EVENT_HIBERNATE,
	AMD_PP_EVENT_CONNECTED_STANDBY,
	AMD_PP_EVENT_ENTER_SELF_REFRESH,
	AMD_PP_EVENT_EXIT_SELF_REFRESH,
	AMD_PP_EVENT_START_AVFS_BTC,
	AMD_PP_EVENT_MAX
};

enum amd_dpm_forced_level {
	AMD_DPM_FORCED_LEVEL_AUTO = 0,
	AMD_DPM_FORCED_LEVEL_LOW = 1,
	AMD_DPM_FORCED_LEVEL_HIGH = 2,
};

struct amd_pp_init {
	struct cgs_device *device;
	uint32_t chip_family;
	uint32_t chip_id;
	uint32_t rev_id;
};
enum amd_pp_display_config_type{
	AMD_PP_DisplayConfigType_None = 0,
	AMD_PP_DisplayConfigType_DP54 ,
	AMD_PP_DisplayConfigType_DP432 ,
	AMD_PP_DisplayConfigType_DP324 ,
	AMD_PP_DisplayConfigType_DP27,
	AMD_PP_DisplayConfigType_DP243,
	AMD_PP_DisplayConfigType_DP216,
	AMD_PP_DisplayConfigType_DP162,
	AMD_PP_DisplayConfigType_HDMI6G ,
	AMD_PP_DisplayConfigType_HDMI297 ,
	AMD_PP_DisplayConfigType_HDMI162,
	AMD_PP_DisplayConfigType_LVDS,
	AMD_PP_DisplayConfigType_DVI,
	AMD_PP_DisplayConfigType_WIRELESS,
	AMD_PP_DisplayConfigType_VGA
};

struct single_display_configuration
{
	uint32_t controller_index;
	uint32_t controller_id;
	uint32_t signal_type;
	uint32_t display_state;
	/* phy id for the primary internal transmitter */
	uint8_t primary_transmitter_phyi_d;
	/* bitmap with the active lanes */
	uint8_t primary_transmitter_active_lanemap;
	/* phy id for the secondary internal transmitter (for dual-link dvi) */
	uint8_t secondary_transmitter_phy_id;
	/* bitmap with the active lanes */
	uint8_t secondary_transmitter_active_lanemap;
	/* misc phy settings for SMU. */
	uint32_t config_flags;
	uint32_t display_type;
	uint32_t view_resolution_cx;
	uint32_t view_resolution_cy;
	enum amd_pp_display_config_type displayconfigtype;
	uint32_t vertical_refresh; /* for active display */
};

#define MAX_NUM_DISPLAY 32

struct amd_pp_display_configuration {
	bool nb_pstate_switch_disable;/* controls NB PState switch */
	bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
	bool cpu_pstate_disable;
	uint32_t cpu_pstate_separation_time;

	uint32_t num_display;  /* total number of display*/
	uint32_t num_path_including_non_display;
	uint32_t crossfire_display_index;
	uint32_t min_mem_set_clock;
	uint32_t min_core_set_clock;
	/* unit 10KHz x bit*/
	uint32_t min_bus_bandwidth;
	/* minimum required stutter sclk, in 10khz uint32_t ulMinCoreSetClk;*/
	uint32_t min_core_set_clock_in_sr;

	struct single_display_configuration displays[MAX_NUM_DISPLAY];

	uint32_t vrefresh; /* for active display*/

	uint32_t min_vblank_time; /* for active display*/
	bool multi_monitor_in_sync;
	/* Controller Index of primary display - used in MCLK SMC switching hang
	 * SW Workaround*/
	uint32_t crtc_index;
	/* htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/
	uint32_t line_time_in_us;
	bool invalid_vblank_time;

	uint32_t display_clk;
	/*
	 * for given display configuration if multimonitormnsync == false then
	 * Memory clock DPMS with this latency or below is allowed, DPMS with
	 * higher latency not allowed.
	 */
	uint32_t dce_tolerable_mclk_in_active_latency;
};

struct amd_pp_dal_clock_info {
	uint32_t	engine_max_clock;
	uint32_t	memory_max_clock;
	uint32_t	level;
};

enum {
	PP_GROUP_UNKNOWN = 0,
	PP_GROUP_GFX = 1,
	PP_GROUP_SYS,
	PP_GROUP_MAX
};

#define PP_GROUP_MASK        0xF0000000
#define PP_GROUP_SHIFT       28

#define PP_BLOCK_MASK        0x0FFFFF00
#define PP_BLOCK_SHIFT       8

#define PP_BLOCK_GFX_CG         0x01
#define PP_BLOCK_GFX_MG         0x02
#define PP_BLOCK_SYS_BIF        0x01
#define PP_BLOCK_SYS_MC         0x02
#define PP_BLOCK_SYS_ROM        0x04
#define PP_BLOCK_SYS_DRM        0x08
#define PP_BLOCK_SYS_HDP        0x10
#define PP_BLOCK_SYS_SDMA       0x20

#define PP_STATE_MASK           0x0000000F
#define PP_STATE_SHIFT          0
#define PP_STATE_SUPPORT_MASK   0x000000F0
#define PP_STATE_SUPPORT_SHIFT  0

#define PP_STATE_CG             0x01
#define PP_STATE_LS             0x02
#define PP_STATE_DS             0x04
#define PP_STATE_SD             0x08
#define PP_STATE_SUPPORT_CG     0x10
#define PP_STATE_SUPPORT_LS     0x20
#define PP_STATE_SUPPORT_DS     0x40
#define PP_STATE_SUPPORT_SD     0x80

#define PP_CG_MSG_ID(group, block, support, state) (group << PP_GROUP_SHIFT |\
								block << PP_BLOCK_SHIFT |\
								support << PP_STATE_SUPPORT_SHIFT |\
								state << PP_STATE_SHIFT)

struct amd_powerplay_funcs {
	int (*get_temperature)(void *handle);
	int (*load_firmware)(void *handle);
	int (*wait_for_fw_loading_complete)(void *handle);
	int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
	enum amd_dpm_forced_level (*get_performance_level)(void *handle);
	enum amd_pm_state_type (*get_current_power_state)(void *handle);
	int (*get_sclk)(void *handle, bool low);
	int (*get_mclk)(void *handle, bool low);
	int (*powergate_vce)(void *handle, bool gate);
	int (*powergate_uvd)(void *handle, bool gate);
	int (*dispatch_tasks)(void *handle, enum amd_pp_event event_id,
				   void *input, void *output);
	void (*print_current_performance_level)(void *handle,
						      struct seq_file *m);
	int (*set_fan_control_mode)(void *handle, uint32_t mode);
	int (*get_fan_control_mode)(void *handle);
	int (*set_fan_speed_percent)(void *handle, uint32_t percent);
	int (*get_fan_speed_percent)(void *handle, uint32_t *speed);
};

struct amd_powerplay {
	void *pp_handle;
	const struct amd_ip_funcs *ip_funcs;
	const struct amd_powerplay_funcs *pp_funcs;
};

int amd_powerplay_init(struct amd_pp_init *pp_init,
		       struct amd_powerplay *amd_pp);
int amd_powerplay_fini(void *handle);

int amd_powerplay_display_configuration_change(void *handle, const void *input);

int amd_powerplay_get_display_power_level(void *handle,
		struct amd_pp_dal_clock_info *output);


#endif /* _AMD_POWERPLAY_H_ */
Commit	Line	Data
1f7371b2 AD	1	/*
	2	* Copyright 2015 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#ifndef _AMD_POWERPLAY_H_
	24	#define _AMD_POWERPLAY_H_
	25
	26	#include <linux/seq_file.h>
	27	#include <linux/types.h>
	28	#include "amd_shared.h"
	29	#include "cgs_common.h"
	30
1f7371b2 AD	31	enum amd_pp_event {
	32	AMD_PP_EVENT_INITIALIZE = 0,
	33	AMD_PP_EVENT_UNINITIALIZE,
	34	AMD_PP_EVENT_POWER_SOURCE_CHANGE,
	35	AMD_PP_EVENT_SUSPEND,
	36	AMD_PP_EVENT_RESUME,
	37	AMD_PP_EVENT_ENTER_REST_STATE,
	38	AMD_PP_EVENT_EXIT_REST_STATE,
	39	AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE,
	40	AMD_PP_EVENT_THERMAL_NOTIFICATION,
	41	AMD_PP_EVENT_VBIOS_NOTIFICATION,
	42	AMD_PP_EVENT_ENTER_THERMAL_STATE,
	43	AMD_PP_EVENT_EXIT_THERMAL_STATE,
	44	AMD_PP_EVENT_ENTER_FORCED_STATE,
	45	AMD_PP_EVENT_EXIT_FORCED_STATE,
	46	AMD_PP_EVENT_ENTER_EXCLUSIVE_MODE,
	47	AMD_PP_EVENT_EXIT_EXCLUSIVE_MODE,
	48	AMD_PP_EVENT_ENTER_SCREEN_SAVER,
	49	AMD_PP_EVENT_EXIT_SCREEN_SAVER,
	50	AMD_PP_EVENT_VPU_RECOVERY_BEGIN,
	51	AMD_PP_EVENT_VPU_RECOVERY_END,
	52	AMD_PP_EVENT_ENABLE_POWER_PLAY,
	53	AMD_PP_EVENT_DISABLE_POWER_PLAY,
	54	AMD_PP_EVENT_CHANGE_POWER_SOURCE_UI_LABEL,
	55	AMD_PP_EVENT_ENABLE_USER2D_PERFORMANCE,
	56	AMD_PP_EVENT_DISABLE_USER2D_PERFORMANCE,
	57	AMD_PP_EVENT_ENABLE_USER3D_PERFORMANCE,
	58	AMD_PP_EVENT_DISABLE_USER3D_PERFORMANCE,
	59	AMD_PP_EVENT_ENABLE_OVER_DRIVE_TEST,
	60	AMD_PP_EVENT_DISABLE_OVER_DRIVE_TEST,
	61	AMD_PP_EVENT_ENABLE_REDUCED_REFRESH_RATE,
	62	AMD_PP_EVENT_DISABLE_REDUCED_REFRESH_RATE,
	63	AMD_PP_EVENT_ENABLE_GFX_CLOCK_GATING,
	64	AMD_PP_EVENT_DISABLE_GFX_CLOCK_GATING,
	65	AMD_PP_EVENT_ENABLE_CGPG,
	66	AMD_PP_EVENT_DISABLE_CGPG,
	67	AMD_PP_EVENT_ENTER_TEXT_MODE,
	68	AMD_PP_EVENT_EXIT_TEXT_MODE,
	69	AMD_PP_EVENT_VIDEO_START,
	70	AMD_PP_EVENT_VIDEO_STOP,
	71	AMD_PP_EVENT_ENABLE_USER_STATE,
	72	AMD_PP_EVENT_DISABLE_USER_STATE,
	73	AMD_PP_EVENT_READJUST_POWER_STATE,
	74	AMD_PP_EVENT_START_INACTIVITY,
	75	AMD_PP_EVENT_STOP_INACTIVITY,
	76	AMD_PP_EVENT_LINKED_ADAPTERS_READY,
	77	AMD_PP_EVENT_ADAPTER_SAFE_TO_DISABLE,
	78	AMD_PP_EVENT_COMPLETE_INIT,
	79	AMD_PP_EVENT_CRITICAL_THERMAL_FAULT,
	80	AMD_PP_EVENT_BACKLIGHT_CHANGED,
	81	AMD_PP_EVENT_ENABLE_VARI_BRIGHT,
	82	AMD_PP_EVENT_DISABLE_VARI_BRIGHT,
	83	AMD_PP_EVENT_ENABLE_VARI_BRIGHT_ON_POWER_XPRESS,
	84	AMD_PP_EVENT_DISABLE_VARI_BRIGHT_ON_POWER_XPRESS,
	85	AMD_PP_EVENT_SET_VARI_BRIGHT_LEVEL,
	86	AMD_PP_EVENT_VARI_BRIGHT_MONITOR_MEASUREMENT,
	87	AMD_PP_EVENT_SCREEN_ON,
	88	AMD_PP_EVENT_SCREEN_OFF,
	89	AMD_PP_EVENT_PRE_DISPLAY_CONFIG_CHANGE,
	90	AMD_PP_EVENT_ENTER_ULP_STATE,
	91	AMD_PP_EVENT_EXIT_ULP_STATE,
	92	AMD_PP_EVENT_REGISTER_IP_STATE,
	93	AMD_PP_EVENT_UNREGISTER_IP_STATE,
	94	AMD_PP_EVENT_ENTER_MGPU_MODE,
95	AMD_PP_EVENT_EXIT_MGPU_MODE,
96	AMD_PP_EVENT_ENTER_MULTI_GPU_MODE,
97	AMD_PP_EVENT_PRE_SUSPEND,
98	AMD_PP_EVENT_PRE_RESUME,
99	AMD_PP_EVENT_ENTER_BACOS,
100	AMD_PP_EVENT_EXIT_BACOS,
101	AMD_PP_EVENT_RESUME_BACO,
102	AMD_PP_EVENT_RESET_BACO,
103	AMD_PP_EVENT_PRE_DISPLAY_PHY_ACCESS,
104	AMD_PP_EVENT_POST_DISPLAY_PHY_CCESS,
105	AMD_PP_EVENT_START_COMPUTE_APPLICATION,
106	AMD_PP_EVENT_STOP_COMPUTE_APPLICATION,
107	AMD_PP_EVENT_REDUCE_POWER_LIMIT,
108	AMD_PP_EVENT_ENTER_FRAME_LOCK,
109	AMD_PP_EVENT_EXIT_FRAME_LOOCK,
110	AMD_PP_EVENT_LONG_IDLE_REQUEST_BACO,
111	AMD_PP_EVENT_LONG_IDLE_ENTER_BACO,
112	AMD_PP_EVENT_LONG_IDLE_EXIT_BACO,
113	AMD_PP_EVENT_HIBERNATE,
114	AMD_PP_EVENT_CONNECTED_STANDBY,
115	AMD_PP_EVENT_ENTER_SELF_REFRESH,
116	AMD_PP_EVENT_EXIT_SELF_REFRESH,
117	AMD_PP_EVENT_START_AVFS_BTC,
118	AMD_PP_EVENT_MAX
119	};
120
121	enum amd_dpm_forced_level {
122	AMD_DPM_FORCED_LEVEL_AUTO = 0,
123	AMD_DPM_FORCED_LEVEL_LOW = 1,
124	AMD_DPM_FORCED_LEVEL_HIGH = 2,
125	};
126
127	struct amd_pp_init {
128	struct cgs_device *device;
129	uint32_t chip_family;
130	uint32_t chip_id;
131	uint32_t rev_id;
132	};
14f63411 EY	133	enum amd_pp_display_config_type{
	134	AMD_PP_DisplayConfigType_None = 0,
	135	AMD_PP_DisplayConfigType_DP54 ,
	136	AMD_PP_DisplayConfigType_DP432 ,
	137	AMD_PP_DisplayConfigType_DP324 ,
	138	AMD_PP_DisplayConfigType_DP27,
	139	AMD_PP_DisplayConfigType_DP243,
	140	AMD_PP_DisplayConfigType_DP216,
	141	AMD_PP_DisplayConfigType_DP162,
	142	AMD_PP_DisplayConfigType_HDMI6G ,
	143	AMD_PP_DisplayConfigType_HDMI297 ,
	144	AMD_PP_DisplayConfigType_HDMI162,
	145	AMD_PP_DisplayConfigType_LVDS,
	146	AMD_PP_DisplayConfigType_DVI,
	147	AMD_PP_DisplayConfigType_WIRELESS,
	148	AMD_PP_DisplayConfigType_VGA
	149	};
	150
	151	struct single_display_configuration
	152	{
	153	uint32_t controller_index;
	154	uint32_t controller_id;
	155	uint32_t signal_type;
	156	uint32_t display_state;
	157	/* phy id for the primary internal transmitter */
	158	uint8_t primary_transmitter_phyi_d;
	159	/* bitmap with the active lanes */
	160	uint8_t primary_transmitter_active_lanemap;
	161	/* phy id for the secondary internal transmitter (for dual-link dvi) */
	162	uint8_t secondary_transmitter_phy_id;
	163	/* bitmap with the active lanes */
	164	uint8_t secondary_transmitter_active_lanemap;
	165	/* misc phy settings for SMU. */
	166	uint32_t config_flags;
	167	uint32_t display_type;
	168	uint32_t view_resolution_cx;
	169	uint32_t view_resolution_cy;
	170	enum amd_pp_display_config_type displayconfigtype;
	171	uint32_t vertical_refresh; /* for active display */
	172	};
	173
	174	#define MAX_NUM_DISPLAY 32
1f7371b2	175
7fb72a1f RZ	176	struct amd_pp_display_configuration {
	177	bool nb_pstate_switch_disable;/* controls NB PState switch */
	178	bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
	179	bool cpu_pstate_disable;
	180	uint32_t cpu_pstate_separation_time;
14f63411 EY	181
	182	uint32_t num_display; /* total number of display*/
	183	uint32_t num_path_including_non_display;
	184	uint32_t crossfire_display_index;
	185	uint32_t min_mem_set_clock;
	186	uint32_t min_core_set_clock;
	187	/* unit 10KHz x bit*/
	188	uint32_t min_bus_bandwidth;
	189	/* minimum required stutter sclk, in 10khz uint32_t ulMinCoreSetClk;*/
	190	uint32_t min_core_set_clock_in_sr;
	191
	192	struct single_display_configuration displays[MAX_NUM_DISPLAY];
	193
	194	uint32_t vrefresh; /* for active display*/
	195
	196	uint32_t min_vblank_time; /* for active display*/
	197	bool multi_monitor_in_sync;
	198	/* Controller Index of primary display - used in MCLK SMC switching hang
	199	* SW Workaround*/
	200	uint32_t crtc_index;
	201	/* htotal1000/pixelclk - used in MCLK SMC switching hang SW Workaround/
	202	uint32_t line_time_in_us;
	203	bool invalid_vblank_time;
	204
	205	uint32_t display_clk;
	206	/*
	207	* for given display configuration if multimonitormnsync == false then
	208	* Memory clock DPMS with this latency or below is allowed, DPMS with
	209	* higher latency not allowed.
	210	*/
	211	uint32_t dce_tolerable_mclk_in_active_latency;
7fb72a1f RZ	212	};
7fb72a1f RZ	213
c4dd206b VP	214	struct amd_pp_dal_clock_info {
	215	uint32_t engine_max_clock;
	216	uint32_t memory_max_clock;
	217	uint32_t level;
	218	};
	219
3cec76f9 RZ	220	enum {
	221	PP_GROUP_UNKNOWN = 0,
	222	PP_GROUP_GFX = 1,
	223	PP_GROUP_SYS,
	224	PP_GROUP_MAX
	225	};
	226
	227	#define PP_GROUP_MASK 0xF0000000
	228	#define PP_GROUP_SHIFT 28
	229
	230	#define PP_BLOCK_MASK 0x0FFFFF00
	231	#define PP_BLOCK_SHIFT 8
	232
	233	#define PP_BLOCK_GFX_CG 0x01
	234	#define PP_BLOCK_GFX_MG 0x02
	235	#define PP_BLOCK_SYS_BIF 0x01
	236	#define PP_BLOCK_SYS_MC 0x02
	237	#define PP_BLOCK_SYS_ROM 0x04
	238	#define PP_BLOCK_SYS_DRM 0x08
	239	#define PP_BLOCK_SYS_HDP 0x10
	240	#define PP_BLOCK_SYS_SDMA 0x20
	241
	242	#define PP_STATE_MASK 0x0000000F
	243	#define PP_STATE_SHIFT 0
	244	#define PP_STATE_SUPPORT_MASK 0x000000F0
	245	#define PP_STATE_SUPPORT_SHIFT 0
	246
	247	#define PP_STATE_CG 0x01
	248	#define PP_STATE_LS 0x02
	249	#define PP_STATE_DS 0x04
	250	#define PP_STATE_SD 0x08
	251	#define PP_STATE_SUPPORT_CG 0x10
	252	#define PP_STATE_SUPPORT_LS 0x20
	253	#define PP_STATE_SUPPORT_DS 0x40
	254	#define PP_STATE_SUPPORT_SD 0x80
	255
	256	#define PP_CG_MSG_ID(group, block, support, state) (group << PP_GROUP_SHIFT \|\
	257	block << PP_BLOCK_SHIFT \|\
	258	support << PP_STATE_SUPPORT_SHIFT \|\
	259	state << PP_STATE_SHIFT)
	260
1f7371b2 AD	261	struct amd_powerplay_funcs {
	262	int (get_temperature)(void handle);
	263	int (load_firmware)(void handle);
	264	int (wait_for_fw_loading_complete)(void handle);
	265	int (force_performance_level)(void handle, enum amd_dpm_forced_level level);
	266	enum amd_dpm_forced_level (get_performance_level)(void handle);
	267	enum amd_pm_state_type (get_current_power_state)(void handle);
	268	int (get_sclk)(void handle, bool low);
	269	int (get_mclk)(void handle, bool low);
	270	int (powergate_vce)(void handle, bool gate);
	271	int (powergate_uvd)(void handle, bool gate);
	272	int (dispatch_tasks)(void handle, enum amd_pp_event event_id,
	273	void input, void output);
	274	void (print_current_performance_level)(void handle,
	275	struct seq_file *m);
cac9a199 RZ	276	int (set_fan_control_mode)(void handle, uint32_t mode);
	277	int (get_fan_control_mode)(void handle);
	278	int (set_fan_speed_percent)(void handle, uint32_t percent);
	279	int (get_fan_speed_percent)(void handle, uint32_t *speed);
1f7371b2 AD	280	};
	281
	282	struct amd_powerplay {
	283	void *pp_handle;
	284	const struct amd_ip_funcs *ip_funcs;
	285	const struct amd_powerplay_funcs *pp_funcs;
	286	};
	287
	288	int amd_powerplay_init(struct amd_pp_init *pp_init,
	289	struct amd_powerplay *amd_pp);
	290	int amd_powerplay_fini(void *handle);
	291
7fb72a1f RZ	292	int amd_powerplay_display_configuration_change(void handle, const void input);
7fb72a1f RZ	293
1c9a9082 VP	294	int amd_powerplay_get_display_power_level(void *handle,
1c9a9082 VP	295	struct amd_pp_dal_clock_info *output);
c4dd206b VP	296
c4dd206b VP	297
1f7371b2	298	#endif /* _AMD_POWERPLAY_H_ */