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drm/amd/powerplay: add new function point in hwmgr_func for CG/PG.
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / amd / powerplay / inc / hwmgr.h
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3bace359
JZ		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef _HWMGR_H_
24#define _HWMGR_H_
25
28a18bab 26#include <linux/seq_file.h>
3bace359
JZ		 27#include "amd_powerplay.h"
28#include "pp_instance.h"
29#include "hardwaremanager.h"
30#include "pp_power_source.h"
c82baa28 31#include "hwmgr_ppt.h"
3bace359
JZ		 32
33struct pp_instance;
34struct pp_hwmgr;
35struct pp_hw_power_state;
36struct pp_power_state;
37struct PP_VCEState;
38
39enum PP_Result {
40 PP_Result_TableImmediateExit = 0x13,
41};
42
43#define PCIE_PERF_REQ_REMOVE_REGISTRY 0
44#define PCIE_PERF_REQ_FORCE_LOWPOWER 1
45#define PCIE_PERF_REQ_GEN1 2
46#define PCIE_PERF_REQ_GEN2 3
47#define PCIE_PERF_REQ_GEN3 4
48
49enum PHM_BackEnd_Magic {
50 PHM_Dummy_Magic = 0xAA5555AA,
51 PHM_RV770_Magic = 0xDCBAABCD,
52 PHM_Kong_Magic = 0x239478DF,
53 PHM_NIslands_Magic = 0x736C494E,
54 PHM_Sumo_Magic = 0x8339FA11,
55 PHM_SIslands_Magic = 0x369431AC,
56 PHM_Trinity_Magic = 0x96751873,
57 PHM_CIslands_Magic = 0x38AC78B0,
58 PHM_Kv_Magic = 0xDCBBABC0,
59 PHM_VIslands_Magic = 0x20130307,
60 PHM_Cz_Magic = 0x67DCBA25
61};
62
63enum PP_DAL_POWERLEVEL {
64 PP_DAL_POWERLEVEL_INVALID = 0,
65 PP_DAL_POWERLEVEL_ULTRALOW,
66 PP_DAL_POWERLEVEL_LOW,
67 PP_DAL_POWERLEVEL_NOMINAL,
68 PP_DAL_POWERLEVEL_PERFORMANCE,
69
70 PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW,
71 PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW,
72 PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL,
73 PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE,
74 PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1,
75 PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1,
76 PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1,
77 PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1,
78};
79
80#define PHM_PCIE_POWERGATING_TARGET_GFX 0
81#define PHM_PCIE_POWERGATING_TARGET_DDI 1
82#define PHM_PCIE_POWERGATING_TARGET_PLLCASCADE 2
83#define PHM_PCIE_POWERGATING_TARGET_PHY 3
84
85typedef int (*phm_table_function)(struct pp_hwmgr *hwmgr, void *input,
86 void *output, void *storage, int result);
87
88typedef bool (*phm_check_function)(struct pp_hwmgr *hwmgr);
89
28a18bab
RZ		 90struct phm_set_power_state_input {
91 const struct pp_hw_power_state *pcurrent_state;
92 const struct pp_hw_power_state *pnew_state;
93};
94
3bace359
JZ		 95struct phm_acp_arbiter {
96 uint32_t acpclk;
97};
98
99struct phm_uvd_arbiter {
100 uint32_t vclk;
101 uint32_t dclk;
102 uint32_t vclk_ceiling;
103 uint32_t dclk_ceiling;
104};
105
106struct phm_vce_arbiter {
107 uint32_t evclk;
108 uint32_t ecclk;
109};
110
111struct phm_gfx_arbiter {
112 uint32_t sclk;
113 uint32_t mclk;
114 uint32_t sclk_over_drive;
115 uint32_t mclk_over_drive;
116 uint32_t sclk_threshold;
117 uint32_t num_cus;
118};
119
120/* Entries in the master tables */
121struct phm_master_table_item {
122 phm_check_function isFunctionNeededInRuntimeTable;
123 phm_table_function tableFunction;
124};
125
126enum phm_master_table_flag {
127 PHM_MasterTableFlag_None = 0,
128 PHM_MasterTableFlag_ExitOnError = 1,
129};
130
131/* The header of the master tables */
132struct phm_master_table_header {
133 uint32_t storage_size;
134 uint32_t flags;
135 struct phm_master_table_item *master_list;
136};
137
138struct phm_runtime_table_header {
139 uint32_t storage_size;
140 bool exit_error;
141 phm_table_function *function_list;
142};
143
144struct phm_clock_array {
145 uint32_t count;
146 uint32_t values[1];
147};
148
149struct phm_clock_voltage_dependency_record {
150 uint32_t clk;
151 uint32_t v;
152};
153
154struct phm_vceclock_voltage_dependency_record {
155 uint32_t ecclk;
156 uint32_t evclk;
157 uint32_t v;
158};
159
160struct phm_uvdclock_voltage_dependency_record {
161 uint32_t vclk;
162 uint32_t dclk;
163 uint32_t v;
164};
165
166struct phm_samuclock_voltage_dependency_record {
167 uint32_t samclk;
168 uint32_t v;
169};
170
171struct phm_acpclock_voltage_dependency_record {
172 uint32_t acpclk;
173 uint32_t v;
174};
175
176struct phm_clock_voltage_dependency_table {
177 uint32_t count; /* Number of entries. */
178 struct phm_clock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
179};
180
181struct phm_phase_shedding_limits_record {
182 uint32_t Voltage;
183 uint32_t Sclk;
184 uint32_t Mclk;
185};
186
187
188extern int phm_dispatch_table(struct pp_hwmgr *hwmgr,
189 struct phm_runtime_table_header *rt_table,
190 void *input, void *output);
191
192extern int phm_construct_table(struct pp_hwmgr *hwmgr,
193 struct phm_master_table_header *master_table,
194 struct phm_runtime_table_header *rt_table);
195
196extern int phm_destroy_table(struct pp_hwmgr *hwmgr,
197 struct phm_runtime_table_header *rt_table);
198
199
200struct phm_uvd_clock_voltage_dependency_record {
201 uint32_t vclk;
202 uint32_t dclk;
203 uint32_t v;
204};
205
206struct phm_uvd_clock_voltage_dependency_table {
207 uint8_t count;
208 struct phm_uvd_clock_voltage_dependency_record entries[1];
209};
210
211struct phm_acp_clock_voltage_dependency_record {
212 uint32_t acpclk;
213 uint32_t v;
214};
215
216struct phm_acp_clock_voltage_dependency_table {
217 uint32_t count;
218 struct phm_acp_clock_voltage_dependency_record entries[1];
219};
220
221struct phm_vce_clock_voltage_dependency_record {
222 uint32_t ecclk;
223 uint32_t evclk;
224 uint32_t v;
225};
226
227struct phm_phase_shedding_limits_table {
228 uint32_t count;
229 struct phm_phase_shedding_limits_record entries[1];
230};
231
232struct phm_vceclock_voltage_dependency_table {
233 uint8_t count; /* Number of entries. */
234 struct phm_vceclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
235};
236
237struct phm_uvdclock_voltage_dependency_table {
238 uint8_t count; /* Number of entries. */
239 struct phm_uvdclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
240};
241
242struct phm_samuclock_voltage_dependency_table {
243 uint8_t count; /* Number of entries. */
244 struct phm_samuclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
245};
246
247struct phm_acpclock_voltage_dependency_table {
248 uint32_t count; /* Number of entries. */
249 struct phm_acpclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
250};
251
252struct phm_vce_clock_voltage_dependency_table {
253 uint8_t count;
254 struct phm_vce_clock_voltage_dependency_record entries[1];
255};
256
257struct pp_hwmgr_func {
258 int (*backend_init)(struct pp_hwmgr *hw_mgr);
259 int (*backend_fini)(struct pp_hwmgr *hw_mgr);
260 int (*asic_setup)(struct pp_hwmgr *hw_mgr);
261 int (*get_power_state_size)(struct pp_hwmgr *hw_mgr);
28a18bab
RZ		 262
263 int (*apply_state_adjust_rules)(struct pp_hwmgr *hwmgr,
264 struct pp_power_state *prequest_ps,
265 const struct pp_power_state *pcurrent_ps);
266
267 int (*force_dpm_level)(struct pp_hwmgr *hw_mgr,
268 enum amd_dpm_forced_level level);
269
270 int (*dynamic_state_management_enable)(
271 struct pp_hwmgr *hw_mgr);
272
273 int (*patch_boot_state)(struct pp_hwmgr *hwmgr,
274 struct pp_hw_power_state *hw_ps);
275
276 int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr,
277 unsigned long, struct pp_power_state *);
3bace359 278 int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr);
28a18bab
RZ		 279 int (*powerdown_uvd)(struct pp_hwmgr *hwmgr);
280 int (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate);
281 int (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate);
282 int (*get_mclk)(struct pp_hwmgr *hwmgr, bool low);
283 int (*get_sclk)(struct pp_hwmgr *hwmgr, bool low);
284 int (*power_state_set)(struct pp_hwmgr *hwmgr,
285 const void *state);
286 void (*print_current_perforce_level)(struct pp_hwmgr *hwmgr,
287 struct seq_file *m);
288 int (*enable_clock_power_gating)(struct pp_hwmgr *hwmgr);
e8c7de5b
RZ		 289 int (*notify_smc_display_config_after_ps_adjustment)(struct pp_hwmgr *hwmgr);
290 int (*display_config_changed)(struct pp_hwmgr *hwmgr);
b1132013
RZ		 291 int (*disable_clock_power_gating)(struct pp_hwmgr *hwmgr);
292 int (*update_clock_gatings)(struct pp_hwmgr *hwmgr,
293 const uint32_t *msg_id);
3bace359
JZ		 294};
295
296struct pp_table_func {
297 int (*pptable_init)(struct pp_hwmgr *hw_mgr);
298 int (*pptable_fini)(struct pp_hwmgr *hw_mgr);
299 int (*pptable_get_number_of_vce_state_table_entries)(struct pp_hwmgr *hw_mgr);
300 int (*pptable_get_vce_state_table_entry)(
301 struct pp_hwmgr *hwmgr,
302 unsigned long i,
303 struct PP_VCEState *vce_state,
304 void **clock_info,
305 unsigned long *flag);
306};
307
308union phm_cac_leakage_record {
309 struct {
310 uint16_t Vddc; /* in CI, we use it for StdVoltageHiSidd */
311 uint32_t Leakage; /* in CI, we use it for StdVoltageLoSidd */
312 };
313 struct {
314 uint16_t Vddc1;
315 uint16_t Vddc2;
316 uint16_t Vddc3;
317 };
318};
319
320struct phm_cac_leakage_table {
321 uint32_t count;
322 union phm_cac_leakage_record entries[1];
323};
324
325struct phm_samu_clock_voltage_dependency_record {
326 uint32_t samclk;
327 uint32_t v;
328};
329
330
331struct phm_samu_clock_voltage_dependency_table {
332 uint8_t count;
333 struct phm_samu_clock_voltage_dependency_record entries[1];
334};
335
336struct phm_cac_tdp_table {
337 uint16_t usTDP;
338 uint16_t usConfigurableTDP;
339 uint16_t usTDC;
340 uint16_t usBatteryPowerLimit;
341 uint16_t usSmallPowerLimit;
342 uint16_t usLowCACLeakage;
343 uint16_t usHighCACLeakage;
344 uint16_t usMaximumPowerDeliveryLimit;
345 uint16_t usOperatingTempMinLimit;
346 uint16_t usOperatingTempMaxLimit;
347 uint16_t usOperatingTempStep;
348 uint16_t usOperatingTempHyst;
349 uint16_t usDefaultTargetOperatingTemp;
350 uint16_t usTargetOperatingTemp;
351 uint16_t usPowerTuneDataSetID;
352 uint16_t usSoftwareShutdownTemp;
353 uint16_t usClockStretchAmount;
354 uint16_t usTemperatureLimitHotspot;
355 uint16_t usTemperatureLimitLiquid1;
356 uint16_t usTemperatureLimitLiquid2;
357 uint16_t usTemperatureLimitVrVddc;
358 uint16_t usTemperatureLimitVrMvdd;
359 uint16_t usTemperatureLimitPlx;
360 uint8_t ucLiquid1_I2C_address;
361 uint8_t ucLiquid2_I2C_address;
362 uint8_t ucLiquid_I2C_Line;
363 uint8_t ucVr_I2C_address;
364 uint8_t ucVr_I2C_Line;
365 uint8_t ucPlx_I2C_address;
366 uint8_t ucPlx_I2C_Line;
367};
368
369struct phm_ppm_table {
370 uint8_t ppm_design;
371 uint16_t cpu_core_number;
372 uint32_t platform_tdp;
373 uint32_t small_ac_platform_tdp;
374 uint32_t platform_tdc;
375 uint32_t small_ac_platform_tdc;
376 uint32_t apu_tdp;
377 uint32_t dgpu_tdp;
378 uint32_t dgpu_ulv_power;
379 uint32_t tj_max;
380};
381
382struct phm_vq_budgeting_record {
383 uint32_t ulCUs;
384 uint32_t ulSustainableSOCPowerLimitLow;
385 uint32_t ulSustainableSOCPowerLimitHigh;
386 uint32_t ulMinSclkLow;
387 uint32_t ulMinSclkHigh;
388 uint8_t ucDispConfig;
389 uint32_t ulDClk;
390 uint32_t ulEClk;
391 uint32_t ulSustainableSclk;
392 uint32_t ulSustainableCUs;
393};
394
395struct phm_vq_budgeting_table {
396 uint8_t numEntries;
397 struct phm_vq_budgeting_record entries[1];
398};
399
400struct phm_clock_and_voltage_limits {
401 uint32_t sclk;
402 uint32_t mclk;
403 uint16_t vddc;
404 uint16_t vddci;
405 uint16_t vddgfx;
406};
407
c82baa28 408/* Structure to hold PPTable information */
3bace359 409
c82baa28 410struct phm_ppt_v1_information {
411 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
412 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
413 struct phm_clock_array *valid_sclk_values;
414 struct phm_clock_array *valid_mclk_values;
415 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
416 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
417 struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
418 struct phm_ppm_table *ppm_parameter_table;
419 struct phm_cac_tdp_table *cac_dtp_table;
420 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
421 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
422 struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
423 struct phm_ppt_v1_pcie_table *pcie_table;
424 uint16_t us_ulv_voltage_offset;
425};
3bace359
JZ		 426
427struct phm_dynamic_state_info {
428 struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk;
429 struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk;
430 struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk;
431 struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk;
432 struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
433 struct phm_clock_array *valid_sclk_values;
434 struct phm_clock_array *valid_mclk_values;
435 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
436 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
437 uint32_t mclk_sclk_ratio;
438 uint32_t sclk_mclk_delta;
439 uint32_t vddc_vddci_delta;
440 uint32_t min_vddc_for_pcie_gen2;
441 struct phm_cac_leakage_table *cac_leakage_table;
442 struct phm_phase_shedding_limits_table *vddc_phase_shed_limits_table;
443
444 struct phm_vce_clock_voltage_dependency_table
445 *vce_clocl_voltage_dependency_table;
446 struct phm_uvd_clock_voltage_dependency_table
447 *uvd_clocl_voltage_dependency_table;
448 struct phm_acp_clock_voltage_dependency_table
449 *acp_clock_voltage_dependency_table;
450 struct phm_samu_clock_voltage_dependency_table
451 *samu_clock_voltage_dependency_table;
452
453 struct phm_ppm_table *ppm_parameter_table;
454 struct phm_cac_tdp_table *cac_dtp_table;
455 struct phm_clock_voltage_dependency_table *vdd_gfx_dependency_on_sclk;
456 struct phm_vq_budgeting_table *vq_budgeting_table;
457};
458
c82baa28 459struct pp_fan_info {
460 bool bNoFan;
461 uint8_t ucTachometerPulsesPerRevolution;
462 uint32_t ulMinRPM;
463 uint32_t ulMaxRPM;
464};
465
466struct pp_advance_fan_control_parameters {
467 uint16_t usTMin; /* The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. */
468 uint16_t usTMed; /* The middle temperature where we change slopes. */
469 uint16_t usTHigh; /* The high temperature for setting the second slope. */
470 uint16_t usPWMMin; /* The minimum PWM value in percent (0.01% increments). */
471 uint16_t usPWMMed; /* The PWM value (in percent) at TMed. */
472 uint16_t usPWMHigh; /* The PWM value at THigh. */
473 uint8_t ucTHyst; /* Temperature hysteresis. Integer. */
474 uint32_t ulCycleDelay; /* The time between two invocations of the fan control routine in microseconds. */
475 uint16_t usTMax; /* The max temperature */
476 uint8_t ucFanControlMode;
477 uint16_t usFanPWMMinLimit;
478 uint16_t usFanPWMMaxLimit;
479 uint16_t usFanPWMStep;
480 uint16_t usDefaultMaxFanPWM;
481 uint16_t usFanOutputSensitivity;
482 uint16_t usDefaultFanOutputSensitivity;
483 uint16_t usMaxFanPWM; /* The max Fan PWM value for Fuzzy Fan Control feature */
484 uint16_t usFanRPMMinLimit; /* Minimum limit range in percentage, need to calculate based on minRPM/MaxRpm */
485 uint16_t usFanRPMMaxLimit; /* Maximum limit range in percentage, usually set to 100% by default */
486 uint16_t usFanRPMStep; /* Step increments/decerements, in percent */
487 uint16_t usDefaultMaxFanRPM; /* The max Fan RPM value for Fuzzy Fan Control feature, default from PPTable */
488 uint16_t usMaxFanRPM; /* The max Fan RPM value for Fuzzy Fan Control feature, user defined */
489 uint16_t usFanCurrentLow; /* Low current */
490 uint16_t usFanCurrentHigh; /* High current */
491 uint16_t usFanRPMLow; /* Low RPM */
492 uint16_t usFanRPMHigh; /* High RPM */
493 uint32_t ulMinFanSCLKAcousticLimit; /* Minimum Fan Controller SCLK Frequency Acoustic Limit. */
494 uint8_t ucTargetTemperature; /* Advanced fan controller target temperature. */
495 uint8_t ucMinimumPWMLimit; /* The minimum PWM that the advanced fan controller can set. This should be set to the highest PWM that will run the fan at its lowest RPM. */
496 uint16_t usFanGainEdge; /* The following is added for Fiji */
497 uint16_t usFanGainHotspot;
498 uint16_t usFanGainLiquid;
499 uint16_t usFanGainVrVddc;
500 uint16_t usFanGainVrMvdd;
501 uint16_t usFanGainPlx;
502 uint16_t usFanGainHbm;
503};
504
505struct pp_thermal_controller_info {
506 uint8_t ucType;
507 uint8_t ucI2cLine;
508 uint8_t ucI2cAddress;
509 struct pp_fan_info fanInfo;
510 struct pp_advance_fan_control_parameters advanceFanControlParameters;
511};
512
513struct phm_microcode_version_info {
514 uint32_t SMC;
515 uint32_t DMCU;
516 uint32_t MC;
517 uint32_t NB;
518};
519
520/**
521 * The main hardware manager structure.
522 */
3bace359
JZ		 523struct pp_hwmgr {
524 uint32_t chip_family;
525 uint32_t chip_id;
526 uint32_t hw_revision;
527 uint32_t sub_sys_id;
528 uint32_t sub_vendor_id;
529
530 void *device;
531 struct pp_smumgr *smumgr;
532 const void *soft_pp_table;
533 enum amd_dpm_forced_level dpm_level;
28a18bab 534 bool block_hw_access;
3bace359
JZ		 535 struct phm_gfx_arbiter gfx_arbiter;
536 struct phm_acp_arbiter acp_arbiter;
537 struct phm_uvd_arbiter uvd_arbiter;
538 struct phm_vce_arbiter vce_arbiter;
539 uint32_t usec_timeout;
540 void *pptable;
541 struct phm_platform_descriptor platform_descriptor;
542 void *backend;
543 enum PP_DAL_POWERLEVEL dal_power_level;
544 struct phm_dynamic_state_info dyn_state;
545 struct phm_runtime_table_header setup_asic;
546 struct phm_runtime_table_header disable_dynamic_state_management;
547 struct phm_runtime_table_header enable_dynamic_state_management;
28a18bab
RZ		 548 struct phm_runtime_table_header set_power_state;
549 struct phm_runtime_table_header enable_clock_power_gatings;
e8c7de5b 550 struct phm_runtime_table_header display_configuration_changed;
3bace359
JZ		 551 const struct pp_hwmgr_func *hwmgr_func;
552 const struct pp_table_func *pptable_func;
553 struct pp_power_state *ps;
554 enum pp_power_source power_source;
555 uint32_t num_ps;
c82baa28 556 struct pp_thermal_controller_info thermal_controller;
557 struct phm_microcode_version_info microcode_version_info;
3bace359
JZ		 558 uint32_t ps_size;
559 struct pp_power_state *current_ps;
560 struct pp_power_state *request_ps;
561 struct pp_power_state *boot_ps;
562 struct pp_power_state *uvd_ps;
563};
564
565
566extern int hwmgr_init(struct amd_pp_init *pp_init,
567 struct pp_instance *handle);
568
569extern int hwmgr_fini(struct pp_hwmgr *hwmgr);
570
571extern int hw_init_power_state_table(struct pp_hwmgr *hwmgr);
572
573extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
574 uint32_t value, uint32_t mask);
575
576extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
577 uint32_t index, uint32_t value, uint32_t mask);
578
c82baa28 579extern uint32_t phm_read_indirect_register(struct pp_hwmgr *hwmgr,
580 uint32_t indirect_port, uint32_t index);
3bace359 581
c82baa28 582extern void phm_write_indirect_register(struct pp_hwmgr *hwmgr,
583 uint32_t indirect_port,
584 uint32_t index,
585 uint32_t value);
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JZ		 586
587extern void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
588 uint32_t indirect_port,
589 uint32_t index,
590 uint32_t value,
591 uint32_t mask);
592
593extern void phm_wait_for_indirect_register_unequal(
594 struct pp_hwmgr *hwmgr,
595 uint32_t indirect_port,
596 uint32_t index,
597 uint32_t value,
598 uint32_t mask);
599
28a18bab
RZ		 600bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr);
601bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr);
602
603#define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU
604
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JZ		 605#define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
606#define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK
607
608#define PHM_SET_FIELD(origval, reg, field, fieldval) \
609 (((origval) & ~PHM_FIELD_MASK(reg, field)) | \
610 (PHM_FIELD_MASK(reg, field) & ((fieldval) << PHM_FIELD_SHIFT(reg, field))))
611
612#define PHM_GET_FIELD(value, reg, field) \
613 (((value) & PHM_FIELD_MASK(reg, field)) >> \
614 PHM_FIELD_SHIFT(reg, field))
615
616
617#define PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, index, value, mask) \
618 phm_wait_on_register(hwmgr, index, value, mask)
619
620#define PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, index, value, mask) \
621 phm_wait_for_register_unequal(hwmgr, index, value, mask)
622
623#define PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask) \
624 phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX, index, value, mask)
625
626#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask) \
627 phm_wait_for_indirect_register_unequal(hwmgr, mm##port##_INDEX, index, value, mask)
628
629#define PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask) \
630 phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX_0, index, value, mask)
631
632#define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask) \
633 phm_wait_for_indirect_register_unequal(hwmgr, mm##port##_INDEX_0, index, value, mask)
634
635/* Operations on named registers. */
636
637#define PHM_WAIT_REGISTER(hwmgr, reg, value, mask) \
638 PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, mm##reg, value, mask)
639
640#define PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask) \
641 PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, mm##reg, value, mask)
642
643#define PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
644 PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
645
646#define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \
647 PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
648
649#define PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
650 PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
651
652#define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \
653 PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
654
655/* Operations on named fields. */
656
657#define PHM_READ_FIELD(device, reg, field) \
658 PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)
659
660#define PHM_READ_INDIRECT_FIELD(device, port, reg, field) \
661 PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
662 reg, field)
663
664#define PHM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field) \
665 PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
666 reg, field)
667
668#define PHM_WRITE_FIELD(device, reg, field, fieldval) \
669 cgs_write_register(device, mm##reg, PHM_SET_FIELD( \
670 cgs_read_register(device, mm##reg), reg, field, fieldval))
671
672#define PHM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval) \
673 cgs_write_ind_register(device, port, ix##reg, \
674 PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
675 reg, field, fieldval))
676
677#define PHM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval) \
678 cgs_write_ind_register(device, port, ix##reg, \
679 PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
680 reg, field, fieldval))
681
682#define PHM_WAIT_FIELD(hwmgr, reg, field, fieldval) \
683 PHM_WAIT_REGISTER(hwmgr, reg, (fieldval) \
684 << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
685
686#define PHM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
687 PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \
688 << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
689
690#define PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
691 PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \
692 << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
693
694#define PHM_WAIT_FIELD_UNEQUAL(hwmgr, reg, field, fieldval) \
695 PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, (fieldval) \
696 << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
697
698#define PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
699 PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, (fieldval) \
700 << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
701
702#define PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
703 PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, (fieldval) \
704 << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
705
706/* Operations on arrays of registers & fields. */
707
708#define PHM_READ_ARRAY_REGISTER(device, reg, offset) \
709 cgs_read_register(device, mm##reg + (offset))
710
711#define PHM_WRITE_ARRAY_REGISTER(device, reg, offset, value) \
712 cgs_write_register(device, mm##reg + (offset), value)
713
714#define PHM_WAIT_ARRAY_REGISTER(hwmgr, reg, offset, value, mask) \
715 PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, mm##reg + (offset), value, mask)
716
717#define PHM_WAIT_ARRAY_REGISTER_UNEQUAL(hwmgr, reg, offset, value, mask) \
718 PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, mm##reg + (offset), value, mask)
719
720#define PHM_READ_ARRAY_FIELD(hwmgr, reg, offset, field) \
721 PHM_GET_FIELD(PHM_READ_ARRAY_REGISTER(hwmgr->device, reg, offset), reg, field)
722
723#define PHM_WRITE_ARRAY_FIELD(hwmgr, reg, offset, field, fieldvalue) \
724 PHM_WRITE_ARRAY_REGISTER(hwmgr->device, reg, offset, \
725 PHM_SET_FIELD(PHM_READ_ARRAY_REGISTER(hwmgr->device, reg, offset), \
726 reg, field, fieldvalue))
727
728#define PHM_WAIT_ARRAY_FIELD(hwmgr, reg, offset, field, fieldvalue) \
729 PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, mm##reg + (offset), \
730 (fieldvalue) << PHM_FIELD_SHIFT(reg, field), \
731 PHM_FIELD_MASK(reg, field))
732
733#define PHM_WAIT_ARRAY_FIELD_UNEQUAL(hwmgr, reg, offset, field, fieldvalue) \
734 PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, mm##reg + (offset), \
735 (fieldvalue) << PHM_FIELD_SHIFT(reg, field), \
736 PHM_FIELD_MASK(reg, field))
737
738#endif /* _HWMGR_H_ */
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