| b2441318 |
1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 306d8db3 |
2 | #ifndef SMU72_H |
| 3 | #define SMU72_H |
| 4 | |
| 5 | #if !defined(SMC_MICROCODE) |
| 6 | #pragma pack(push, 1) |
| 7 | #endif |
| 8 | |
| 9 | #define SMU__NUM_SCLK_DPM_STATE 8 |
| 10 | #define SMU__NUM_MCLK_DPM_LEVELS 4 |
| 11 | #define SMU__NUM_LCLK_DPM_LEVELS 8 |
| 12 | #define SMU__NUM_PCIE_DPM_LEVELS 8 |
| 13 | |
| 14 | enum SID_OPTION { |
| 15 | SID_OPTION_HI, |
| 16 | SID_OPTION_LO, |
| 17 | SID_OPTION_COUNT |
| 18 | }; |
| 19 | |
| 20 | enum Poly3rdOrderCoeff { |
| 21 | LEAKAGE_TEMPERATURE_SCALAR, |
| 22 | LEAKAGE_VOLTAGE_SCALAR, |
| 23 | DYNAMIC_VOLTAGE_SCALAR, |
| 24 | POLY_3RD_ORDER_COUNT |
| 25 | }; |
| 26 | |
| 27 | struct SMU7_Poly3rdOrder_Data { |
| 28 | int32_t a; |
| 29 | int32_t b; |
| 30 | int32_t c; |
| 31 | int32_t d; |
| 32 | uint8_t a_shift; |
| 33 | uint8_t b_shift; |
| 34 | uint8_t c_shift; |
| 35 | uint8_t x_shift; |
| 36 | }; |
| 37 | |
| 38 | typedef struct SMU7_Poly3rdOrder_Data SMU7_Poly3rdOrder_Data; |
| 39 | |
| 40 | struct Power_Calculator_Data { |
| 41 | uint16_t NoLoadVoltage; |
| 42 | uint16_t LoadVoltage; |
| 43 | uint16_t Resistance; |
| 44 | uint16_t Temperature; |
| 45 | uint16_t BaseLeakage; |
| 46 | uint16_t LkgTempScalar; |
| 47 | uint16_t LkgVoltScalar; |
| 48 | uint16_t LkgAreaScalar; |
| 49 | uint16_t LkgPower; |
| 50 | uint16_t DynVoltScalar; |
| 51 | uint32_t Cac; |
| 52 | uint32_t DynPower; |
| 53 | uint32_t TotalCurrent; |
| 54 | uint32_t TotalPower; |
| 55 | }; |
| 56 | |
| 57 | typedef struct Power_Calculator_Data PowerCalculatorData_t; |
| 58 | |
| 59 | struct Gc_Cac_Weight_Data { |
| 60 | uint8_t index; |
| 61 | uint32_t value; |
| 62 | }; |
| 63 | |
| 64 | typedef struct Gc_Cac_Weight_Data GcCacWeight_Data; |
| 65 | |
| 66 | |
| 67 | typedef struct { |
| 68 | uint32_t high; |
| 69 | uint32_t low; |
| 70 | } data_64_t; |
| 71 | |
| 72 | typedef struct { |
| 73 | data_64_t high; |
| 74 | data_64_t low; |
| 75 | } data_128_t; |
| 76 | |
| 77 | #define SMU7_CONTEXT_ID_SMC 1 |
| 78 | #define SMU7_CONTEXT_ID_VBIOS 2 |
| 79 | |
| 80 | #define SMU72_MAX_LEVELS_VDDC 16 |
| 81 | #define SMU72_MAX_LEVELS_VDDGFX 16 |
| 82 | #define SMU72_MAX_LEVELS_VDDCI 8 |
| 83 | #define SMU72_MAX_LEVELS_MVDD 4 |
| 84 | |
| 85 | #define SMU_MAX_SMIO_LEVELS 4 |
| 86 | |
| 87 | #define SMU72_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE /* SCLK + SQ DPM + ULV */ |
| 88 | #define SMU72_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS /* MCLK Levels DPM */ |
| 89 | #define SMU72_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS /* LCLK Levels */ |
| 90 | #define SMU72_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS /* PCIe speed and number of lanes. */ |
| 91 | #define SMU72_MAX_LEVELS_UVD 8 /* VCLK/DCLK levels for UVD. */ |
| 92 | #define SMU72_MAX_LEVELS_VCE 8 /* ECLK levels for VCE. */ |
| 93 | #define SMU72_MAX_LEVELS_ACP 8 /* ACLK levels for ACP. */ |
| 94 | #define SMU72_MAX_LEVELS_SAMU 8 /* SAMCLK levels for SAMU. */ |
| 95 | #define SMU72_MAX_ENTRIES_SMIO 32 /* Number of entries in SMIO table. */ |
| 96 | |
| 97 | #define DPM_NO_LIMIT 0 |
| 98 | #define DPM_NO_UP 1 |
| 99 | #define DPM_GO_DOWN 2 |
| 100 | #define DPM_GO_UP 3 |
| 101 | |
| 102 | #define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0 |
| 103 | #define SMU7_FIRST_DPM_MEMORY_LEVEL 0 |
| 104 | |
| 105 | #define GPIO_CLAMP_MODE_VRHOT 1 |
| 106 | #define GPIO_CLAMP_MODE_THERM 2 |
| 107 | #define GPIO_CLAMP_MODE_DC 4 |
| 108 | |
| 109 | #define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0 |
| 110 | #define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT) |
| 111 | #define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3 |
| 112 | #define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT) |
| 113 | #define SCRATCH_B_TARG_UVD_INDEX_SHIFT 6 |
| 114 | #define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT) |
| 115 | #define SCRATCH_B_CURR_UVD_INDEX_SHIFT 9 |
| 116 | #define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT) |
| 117 | #define SCRATCH_B_TARG_VCE_INDEX_SHIFT 12 |
| 118 | #define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT) |
| 119 | #define SCRATCH_B_CURR_VCE_INDEX_SHIFT 15 |
| 120 | #define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT) |
| 121 | #define SCRATCH_B_TARG_ACP_INDEX_SHIFT 18 |
| 122 | #define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT) |
| 123 | #define SCRATCH_B_CURR_ACP_INDEX_SHIFT 21 |
| 124 | #define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT) |
| 125 | #define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24 |
| 126 | #define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT) |
| 127 | #define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27 |
| 128 | #define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT) |
| 129 | |
| 130 | /* Virtualization Defines */ |
| 131 | #define CG_XDMA_MASK 0x1 |
| 132 | #define CG_XDMA_SHIFT 0 |
| 133 | #define CG_UVD_MASK 0x2 |
| 134 | #define CG_UVD_SHIFT 1 |
| 135 | #define CG_VCE_MASK 0x4 |
| 136 | #define CG_VCE_SHIFT 2 |
| 137 | #define CG_SAMU_MASK 0x8 |
| 138 | #define CG_SAMU_SHIFT 3 |
| 139 | #define CG_GFX_MASK 0x10 |
| 140 | #define CG_GFX_SHIFT 4 |
| 141 | #define CG_SDMA_MASK 0x20 |
| 142 | #define CG_SDMA_SHIFT 5 |
| 143 | #define CG_HDP_MASK 0x40 |
| 144 | #define CG_HDP_SHIFT 6 |
| 145 | #define CG_MC_MASK 0x80 |
| 146 | #define CG_MC_SHIFT 7 |
| 147 | #define CG_DRM_MASK 0x100 |
| 148 | #define CG_DRM_SHIFT 8 |
| 149 | #define CG_ROM_MASK 0x200 |
| 150 | #define CG_ROM_SHIFT 9 |
| 151 | #define CG_BIF_MASK 0x400 |
| 152 | #define CG_BIF_SHIFT 10 |
| 153 | |
| 154 | #define SMU72_DTE_ITERATIONS 5 |
| 155 | #define SMU72_DTE_SOURCES 3 |
| 156 | #define SMU72_DTE_SINKS 1 |
| 157 | #define SMU72_NUM_CPU_TES 0 |
| 158 | #define SMU72_NUM_GPU_TES 1 |
| 159 | #define SMU72_NUM_NON_TES 2 |
| 160 | #define SMU72_DTE_FAN_SCALAR_MIN 0x100 |
| 161 | #define SMU72_DTE_FAN_SCALAR_MAX 0x166 |
| 162 | #define SMU72_DTE_FAN_TEMP_MAX 93 |
| 163 | #define SMU72_DTE_FAN_TEMP_MIN 83 |
| 164 | |
| 165 | #if defined SMU__FUSION_ONLY |
| 166 | #define SMU7_DTE_ITERATIONS 5 |
| 167 | #define SMU7_DTE_SOURCES 5 |
| 168 | #define SMU7_DTE_SINKS 3 |
| 169 | #define SMU7_NUM_CPU_TES 2 |
| 170 | #define SMU7_NUM_GPU_TES 1 |
| 171 | #define SMU7_NUM_NON_TES 2 |
| 172 | #endif |
| 173 | |
| 174 | struct SMU7_HystController_Data { |
| 175 | uint8_t waterfall_up; |
| 176 | uint8_t waterfall_down; |
| 177 | uint8_t waterfall_limit; |
| 178 | uint8_t spare; |
| 179 | uint16_t release_cnt; |
| 180 | uint16_t release_limit; |
| 181 | }; |
| 182 | |
| 183 | typedef struct SMU7_HystController_Data SMU7_HystController_Data; |
| 184 | |
| 185 | struct SMU72_PIDController { |
| 186 | uint32_t Ki; |
| 187 | int32_t LFWindupUpperLim; |
| 188 | int32_t LFWindupLowerLim; |
| 189 | uint32_t StatePrecision; |
| 190 | uint32_t LfPrecision; |
| 191 | uint32_t LfOffset; |
| 192 | uint32_t MaxState; |
| 193 | uint32_t MaxLfFraction; |
| 194 | uint32_t StateShift; |
| 195 | }; |
| 196 | |
| 197 | typedef struct SMU72_PIDController SMU72_PIDController; |
| 198 | |
| 199 | struct SMU7_LocalDpmScoreboard { |
| 200 | uint32_t PercentageBusy; |
| 201 | |
| 202 | int32_t PIDError; |
| 203 | int32_t PIDIntegral; |
| 204 | int32_t PIDOutput; |
| 205 | |
| 206 | uint32_t SigmaDeltaAccum; |
| 207 | uint32_t SigmaDeltaOutput; |
| 208 | uint32_t SigmaDeltaLevel; |
| 209 | |
| 210 | uint32_t UtilizationSetpoint; |
| 211 | |
| 212 | uint8_t TdpClampMode; |
| 213 | uint8_t TdcClampMode; |
| 214 | uint8_t ThermClampMode; |
| 215 | uint8_t VoltageBusy; |
| 216 | |
| 217 | int8_t CurrLevel; |
| 218 | int8_t TargLevel; |
| 219 | uint8_t LevelChangeInProgress; |
| 220 | uint8_t UpHyst; |
| 221 | |
| 222 | uint8_t DownHyst; |
| 223 | uint8_t VoltageDownHyst; |
| 224 | uint8_t DpmEnable; |
| 225 | uint8_t DpmRunning; |
| 226 | |
| 227 | uint8_t DpmForce; |
| 228 | uint8_t DpmForceLevel; |
| 229 | uint8_t DisplayWatermark; |
| 230 | uint8_t McArbIndex; |
| 231 | |
| 232 | uint32_t MinimumPerfSclk; |
| 233 | |
| 234 | uint8_t AcpiReq; |
| 235 | uint8_t AcpiAck; |
| 236 | uint8_t GfxClkSlow; |
| 237 | uint8_t GpioClampMode; /* bit0 = VRHOT: bit1 = THERM: bit2 = DC */ |
| 238 | |
| 239 | uint8_t FpsFilterWeight; |
| 240 | uint8_t EnabledLevelsChange; |
| 241 | uint8_t DteClampMode; |
| 242 | uint8_t FpsClampMode; |
| 243 | |
| 244 | uint16_t LevelResidencyCounters[SMU72_MAX_LEVELS_GRAPHICS]; |
| 245 | uint16_t LevelSwitchCounters[SMU72_MAX_LEVELS_GRAPHICS]; |
| 246 | |
| 247 | void (*TargetStateCalculator)(uint8_t); |
| 248 | void (*SavedTargetStateCalculator)(uint8_t); |
| 249 | |
| 250 | uint16_t AutoDpmInterval; |
| 251 | uint16_t AutoDpmRange; |
| 252 | |
| 253 | uint8_t FpsEnabled; |
| 254 | uint8_t MaxPerfLevel; |
| 255 | uint8_t AllowLowClkInterruptToHost; |
| 256 | uint8_t FpsRunning; |
| 257 | |
| 258 | uint32_t MaxAllowedFrequency; |
| 259 | |
| 260 | uint32_t FilteredSclkFrequency; |
| 261 | uint32_t LastSclkFrequency; |
| 262 | uint32_t FilteredSclkFrequencyCnt; |
| 263 | }; |
| 264 | |
| 265 | typedef struct SMU7_LocalDpmScoreboard SMU7_LocalDpmScoreboard; |
| 266 | |
| 267 | #define SMU7_MAX_VOLTAGE_CLIENTS 12 |
| 268 | |
| 269 | typedef uint8_t (*VoltageChangeHandler_t)(uint16_t, uint8_t); |
| 270 | |
| 271 | struct SMU_VoltageLevel { |
| 272 | uint8_t Vddc; |
| 273 | uint8_t Vddci; |
| 274 | uint8_t VddGfx; |
| 275 | uint8_t Phases; |
| 276 | }; |
| 277 | |
| 278 | typedef struct SMU_VoltageLevel SMU_VoltageLevel; |
| 279 | |
| 280 | struct SMU7_VoltageScoreboard { |
| 281 | SMU_VoltageLevel CurrentVoltage; |
| 282 | SMU_VoltageLevel TargetVoltage; |
| 283 | uint16_t MaxVid; |
| 284 | uint8_t HighestVidOffset; |
| 285 | uint8_t CurrentVidOffset; |
| 286 | |
| 287 | uint8_t ControllerBusy; |
| 288 | uint8_t CurrentVid; |
| 289 | uint8_t CurrentVddciVid; |
| 290 | uint8_t VddGfxShutdown; /* 0 = normal mode, 1 = shut down */ |
| 291 | |
| 292 | SMU_VoltageLevel RequestedVoltage[SMU7_MAX_VOLTAGE_CLIENTS]; |
| 293 | uint8_t EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS]; |
| 294 | |
| 295 | uint8_t TargetIndex; |
| 296 | uint8_t Delay; |
| 297 | uint8_t ControllerEnable; |
| 298 | uint8_t ControllerRunning; |
| 299 | uint16_t CurrentStdVoltageHiSidd; |
| 300 | uint16_t CurrentStdVoltageLoSidd; |
| 301 | uint8_t OverrideVoltage; |
| 302 | uint8_t VddcUseUlvOffset; |
| 303 | uint8_t VddGfxUseUlvOffset; |
| 304 | uint8_t padding; |
| 305 | |
| 306 | VoltageChangeHandler_t ChangeVddc; |
| 307 | VoltageChangeHandler_t ChangeVddGfx; |
| 308 | VoltageChangeHandler_t ChangeVddci; |
| 309 | VoltageChangeHandler_t ChangePhase; |
| 310 | VoltageChangeHandler_t ChangeMvdd; |
| 311 | |
| 312 | VoltageChangeHandler_t functionLinks[6]; |
| 313 | |
| 314 | uint8_t *VddcFollower1; |
| 315 | uint8_t *VddcFollower2; |
| 316 | int16_t Driver_OD_RequestedVidOffset1; |
| 317 | int16_t Driver_OD_RequestedVidOffset2; |
| 318 | |
| 319 | }; |
| 320 | |
| 321 | typedef struct SMU7_VoltageScoreboard SMU7_VoltageScoreboard; |
| 322 | |
| 323 | #define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */ |
| 324 | |
| 325 | struct SMU7_PCIeLinkSpeedScoreboard { |
| 326 | uint8_t DpmEnable; |
| 327 | uint8_t DpmRunning; |
| 328 | uint8_t DpmForce; |
| 329 | uint8_t DpmForceLevel; |
| 330 | |
| 331 | uint8_t CurrentLinkSpeed; |
| 332 | uint8_t EnabledLevelsChange; |
| 333 | uint16_t AutoDpmInterval; |
| 334 | |
| 335 | uint16_t AutoDpmRange; |
| 336 | uint16_t AutoDpmCount; |
| 337 | |
| 338 | uint8_t DpmMode; |
| 339 | uint8_t AcpiReq; |
| 340 | uint8_t AcpiAck; |
| 341 | uint8_t CurrentLinkLevel; |
| 342 | |
| 343 | }; |
| 344 | |
| 345 | typedef struct SMU7_PCIeLinkSpeedScoreboard SMU7_PCIeLinkSpeedScoreboard; |
| 346 | |
| 347 | /* -------------------------------------------------------- CAC table ------------------------------------------------------ */ |
| 348 | #define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16 |
| 349 | #define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16 |
| 350 | #define SMU7_SCALE_I 7 |
| 351 | #define SMU7_SCALE_R 12 |
| 352 | |
| 353 | struct SMU7_PowerScoreboard { |
| 354 | PowerCalculatorData_t VddGfxPowerData[SID_OPTION_COUNT]; |
| 355 | PowerCalculatorData_t VddcPowerData[SID_OPTION_COUNT]; |
| 356 | |
| 357 | uint32_t TotalGpuPower; |
| 358 | uint32_t TdcCurrent; |
| 359 | |
| 360 | uint16_t VddciTotalPower; |
| 361 | uint16_t sparesasfsdfd; |
| 362 | uint16_t Vddr1Power; |
| 363 | uint16_t RocPower; |
| 364 | |
| 365 | uint16_t CalcMeasPowerBlend; |
| 366 | uint8_t SidOptionPower; |
| 367 | uint8_t SidOptionCurrent; |
| 368 | |
| 369 | uint32_t WinTime; |
| 370 | |
| 371 | uint16_t Telemetry_1_slope; |
| 372 | uint16_t Telemetry_2_slope; |
| 373 | int32_t Telemetry_1_offset; |
| 374 | int32_t Telemetry_2_offset; |
| 375 | |
| 376 | uint32_t VddcCurrentTelemetry; |
| 377 | uint32_t VddGfxCurrentTelemetry; |
| 378 | uint32_t VddcPowerTelemetry; |
| 379 | uint32_t VddGfxPowerTelemetry; |
| 380 | uint32_t VddciPowerTelemetry; |
| 381 | |
| 382 | uint32_t VddcPower; |
| 383 | uint32_t VddGfxPower; |
| 384 | uint32_t VddciPower; |
| 385 | |
| 386 | uint32_t TelemetryCurrent[2]; |
| 387 | uint32_t TelemetryVoltage[2]; |
| 388 | uint32_t TelemetryPower[2]; |
| 389 | }; |
| 390 | |
| 391 | typedef struct SMU7_PowerScoreboard SMU7_PowerScoreboard; |
| 392 | |
| 393 | struct SMU7_ThermalScoreboard { |
| 394 | int16_t GpuLimit; |
| 395 | int16_t GpuHyst; |
| 396 | uint16_t CurrGnbTemp; |
| 397 | uint16_t FilteredGnbTemp; |
| 398 | |
| 399 | uint8_t ControllerEnable; |
| 400 | uint8_t ControllerRunning; |
| 401 | uint8_t AutoTmonCalInterval; |
| 402 | uint8_t AutoTmonCalEnable; |
| 403 | |
| 404 | uint8_t ThermalDpmEnabled; |
| 405 | uint8_t SclkEnabledMask; |
| 406 | uint8_t spare[2]; |
| 407 | int32_t temperature_gradient; |
| 408 | |
| 409 | SMU7_HystController_Data HystControllerData; |
| 410 | int32_t WeightedSensorTemperature; |
| 411 | uint16_t TemperatureLimit[SMU72_MAX_LEVELS_GRAPHICS]; |
| 412 | uint32_t Alpha; |
| 413 | }; |
| 414 | |
| 415 | typedef struct SMU7_ThermalScoreboard SMU7_ThermalScoreboard; |
| 416 | |
| 417 | /* For FeatureEnables: */ |
| 418 | #define SMU7_SCLK_DPM_CONFIG_MASK 0x01 |
| 419 | #define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK 0x02 |
| 420 | #define SMU7_THERMAL_CONTROLLER_CONFIG_MASK 0x04 |
| 421 | #define SMU7_MCLK_DPM_CONFIG_MASK 0x08 |
| 422 | #define SMU7_UVD_DPM_CONFIG_MASK 0x10 |
| 423 | #define SMU7_VCE_DPM_CONFIG_MASK 0x20 |
| 424 | #define SMU7_ACP_DPM_CONFIG_MASK 0x40 |
| 425 | #define SMU7_SAMU_DPM_CONFIG_MASK 0x80 |
| 426 | #define SMU7_PCIEGEN_DPM_CONFIG_MASK 0x100 |
| 427 | |
| 428 | #define SMU7_ACP_MCLK_HANDSHAKE_DISABLE 0x00000001 |
| 429 | #define SMU7_ACP_SCLK_HANDSHAKE_DISABLE 0x00000002 |
| 430 | #define SMU7_UVD_MCLK_HANDSHAKE_DISABLE 0x00000100 |
| 431 | #define SMU7_UVD_SCLK_HANDSHAKE_DISABLE 0x00000200 |
| 432 | #define SMU7_VCE_MCLK_HANDSHAKE_DISABLE 0x00010000 |
| 433 | #define SMU7_VCE_SCLK_HANDSHAKE_DISABLE 0x00020000 |
| 434 | |
| 435 | /* All 'soft registers' should be uint32_t. */ |
| 436 | struct SMU72_SoftRegisters { |
| 437 | uint32_t RefClockFrequency; |
| 438 | uint32_t PmTimerPeriod; |
| 439 | uint32_t FeatureEnables; |
| 440 | |
| 441 | uint32_t PreVBlankGap; |
| 442 | uint32_t VBlankTimeout; |
| 443 | uint32_t TrainTimeGap; |
| 444 | |
| 445 | uint32_t MvddSwitchTime; |
| 446 | uint32_t LongestAcpiTrainTime; |
| 447 | uint32_t AcpiDelay; |
| 448 | uint32_t G5TrainTime; |
| 449 | uint32_t DelayMpllPwron; |
| 450 | uint32_t VoltageChangeTimeout; |
| 451 | |
| 452 | uint32_t HandshakeDisables; |
| 453 | |
| 454 | uint8_t DisplayPhy1Config; |
| 455 | uint8_t DisplayPhy2Config; |
| 456 | uint8_t DisplayPhy3Config; |
| 457 | uint8_t DisplayPhy4Config; |
| 458 | |
| 459 | uint8_t DisplayPhy5Config; |
| 460 | uint8_t DisplayPhy6Config; |
| 461 | uint8_t DisplayPhy7Config; |
| 462 | uint8_t DisplayPhy8Config; |
| 463 | |
| 464 | uint32_t AverageGraphicsActivity; |
| 465 | uint32_t AverageMemoryActivity; |
| 466 | uint32_t AverageGioActivity; |
| 467 | |
| 468 | uint8_t SClkDpmEnabledLevels; |
| 469 | uint8_t MClkDpmEnabledLevels; |
| 470 | uint8_t LClkDpmEnabledLevels; |
| 471 | uint8_t PCIeDpmEnabledLevels; |
| 472 | |
| 473 | uint8_t UVDDpmEnabledLevels; |
| 474 | uint8_t SAMUDpmEnabledLevels; |
| 475 | uint8_t ACPDpmEnabledLevels; |
| 476 | uint8_t VCEDpmEnabledLevels; |
| 477 | |
| 478 | uint32_t DRAM_LOG_ADDR_H; |
| 479 | uint32_t DRAM_LOG_ADDR_L; |
| 480 | uint32_t DRAM_LOG_PHY_ADDR_H; |
| 481 | uint32_t DRAM_LOG_PHY_ADDR_L; |
| 482 | uint32_t DRAM_LOG_BUFF_SIZE; |
| 483 | uint32_t UlvEnterCount; |
| 484 | uint32_t UlvTime; |
| 485 | uint32_t UcodeLoadStatus; |
| 486 | uint32_t Reserved[2]; |
| 487 | |
| 488 | }; |
| 489 | |
| 490 | typedef struct SMU72_SoftRegisters SMU72_SoftRegisters; |
| 491 | |
| 492 | struct SMU72_Firmware_Header { |
| 493 | uint32_t Digest[5]; |
| 494 | uint32_t Version; |
| 495 | uint32_t HeaderSize; |
| 496 | uint32_t Flags; |
| 497 | uint32_t EntryPoint; |
| 498 | uint32_t CodeSize; |
| 499 | uint32_t ImageSize; |
| 500 | |
| 501 | uint32_t Rtos; |
| 502 | uint32_t SoftRegisters; |
| 503 | uint32_t DpmTable; |
| 504 | uint32_t FanTable; |
| 505 | uint32_t CacConfigTable; |
| 506 | uint32_t CacStatusTable; |
| 507 | uint32_t mcRegisterTable; |
| 508 | uint32_t mcArbDramTimingTable; |
| 509 | uint32_t PmFuseTable; |
| 510 | uint32_t Globals; |
| 511 | uint32_t ClockStretcherTable; |
| 512 | uint32_t Reserved[41]; |
| 513 | uint32_t Signature; |
| 514 | }; |
| 515 | |
| 516 | typedef struct SMU72_Firmware_Header SMU72_Firmware_Header; |
| 517 | |
| 518 | #define SMU72_FIRMWARE_HEADER_LOCATION 0x20000 |
| 519 | |
| 520 | enum DisplayConfig { |
| 521 | PowerDown = 1, |
| 522 | DP54x4, |
| 523 | DP54x2, |
| 524 | DP54x1, |
| 525 | DP27x4, |
| 526 | DP27x2, |
| 527 | DP27x1, |
| 528 | HDMI297, |
| 529 | HDMI162, |
| 530 | LVDS, |
| 531 | DP324x4, |
| 532 | DP324x2, |
| 533 | DP324x1 |
| 534 | }; |
| 535 | |
| 536 | #define MC_BLOCK_COUNT 1 |
| 537 | #define CPL_BLOCK_COUNT 5 |
| 538 | #define SE_BLOCK_COUNT 15 |
| 539 | #define GC_BLOCK_COUNT 24 |
| 540 | |
| 541 | struct SMU7_Local_Cac { |
| 542 | uint8_t BlockId; |
| 543 | uint8_t SignalId; |
| 544 | uint8_t Threshold; |
| 545 | uint8_t Padding; |
| 546 | }; |
| 547 | |
| 548 | typedef struct SMU7_Local_Cac SMU7_Local_Cac; |
| 549 | |
| 550 | struct SMU7_Local_Cac_Table { |
| 551 | SMU7_Local_Cac CplLocalCac[CPL_BLOCK_COUNT]; |
| 552 | SMU7_Local_Cac McLocalCac[MC_BLOCK_COUNT]; |
| 553 | SMU7_Local_Cac SeLocalCac[SE_BLOCK_COUNT]; |
| 554 | SMU7_Local_Cac GcLocalCac[GC_BLOCK_COUNT]; |
| 555 | }; |
| 556 | |
| 557 | typedef struct SMU7_Local_Cac_Table SMU7_Local_Cac_Table; |
| 558 | |
| 559 | #if !defined(SMC_MICROCODE) |
| 560 | #pragma pack(pop) |
| 561 | #endif |
| 562 | |
| 563 | /* Description of Clock Gating bitmask for Tonga: */ |
| 564 | /* System Clock Gating */ |
| 565 | #define CG_SYS_BITMASK_FIRST_BIT 0 /* First bit of Sys CG bitmask */ |
| 566 | #define CG_SYS_BITMASK_LAST_BIT 9 /* Last bit of Sys CG bitmask */ |
| 567 | #define CG_SYS_BIF_MGLS_SHIFT 0 |
| 568 | #define CG_SYS_ROM_SHIFT 1 |
| 569 | #define CG_SYS_MC_MGCG_SHIFT 2 |
| 570 | #define CG_SYS_MC_MGLS_SHIFT 3 |
| 571 | #define CG_SYS_SDMA_MGCG_SHIFT 4 |
| 572 | #define CG_SYS_SDMA_MGLS_SHIFT 5 |
| 573 | #define CG_SYS_DRM_MGCG_SHIFT 6 |
| 574 | #define CG_SYS_HDP_MGCG_SHIFT 7 |
| 575 | #define CG_SYS_HDP_MGLS_SHIFT 8 |
| 576 | #define CG_SYS_DRM_MGLS_SHIFT 9 |
| 577 | |
| 578 | #define CG_SYS_BIF_MGLS_MASK 0x1 |
| 579 | #define CG_SYS_ROM_MASK 0x2 |
| 580 | #define CG_SYS_MC_MGCG_MASK 0x4 |
| 581 | #define CG_SYS_MC_MGLS_MASK 0x8 |
| 582 | #define CG_SYS_SDMA_MGCG_MASK 0x10 |
| 583 | #define CG_SYS_SDMA_MGLS_MASK 0x20 |
| 584 | #define CG_SYS_DRM_MGCG_MASK 0x40 |
| 585 | #define CG_SYS_HDP_MGCG_MASK 0x80 |
| 586 | #define CG_SYS_HDP_MGLS_MASK 0x100 |
| 587 | #define CG_SYS_DRM_MGLS_MASK 0x200 |
| 588 | |
| 589 | /* Graphics Clock Gating */ |
| 590 | #define CG_GFX_BITMASK_FIRST_BIT 16 /* First bit of Gfx CG bitmask */ |
| 591 | #define CG_GFX_BITMASK_LAST_BIT 20 /* Last bit of Gfx CG bitmask */ |
| 592 | #define CG_GFX_CGCG_SHIFT 16 |
| 593 | #define CG_GFX_CGLS_SHIFT 17 |
| 594 | #define CG_CPF_MGCG_SHIFT 18 |
| 595 | #define CG_RLC_MGCG_SHIFT 19 |
| 596 | #define CG_GFX_OTHERS_MGCG_SHIFT 20 |
| 597 | |
| 598 | #define CG_GFX_CGCG_MASK 0x00010000 |
| 599 | #define CG_GFX_CGLS_MASK 0x00020000 |
| 600 | #define CG_CPF_MGCG_MASK 0x00040000 |
| 601 | #define CG_RLC_MGCG_MASK 0x00080000 |
| 602 | #define CG_GFX_OTHERS_MGCG_MASK 0x00100000 |
| 603 | |
| 604 | /* Voltage Regulator Configuration */ |
| 605 | /* VR Config info is contained in dpmTable.VRConfig */ |
| 606 | |
| 607 | #define VRCONF_VDDC_MASK 0x000000FF |
| 608 | #define VRCONF_VDDC_SHIFT 0 |
| 609 | #define VRCONF_VDDGFX_MASK 0x0000FF00 |
| 610 | #define VRCONF_VDDGFX_SHIFT 8 |
| 611 | #define VRCONF_VDDCI_MASK 0x00FF0000 |
| 612 | #define VRCONF_VDDCI_SHIFT 16 |
| 613 | #define VRCONF_MVDD_MASK 0xFF000000 |
| 614 | #define VRCONF_MVDD_SHIFT 24 |
| 615 | |
| 616 | #define VR_MERGED_WITH_VDDC 0 |
| 617 | #define VR_SVI2_PLANE_1 1 |
| 618 | #define VR_SVI2_PLANE_2 2 |
| 619 | #define VR_SMIO_PATTERN_1 3 |
| 620 | #define VR_SMIO_PATTERN_2 4 |
| 621 | #define VR_STATIC_VOLTAGE 5 |
| 622 | |
| 623 | /* Clock Stretcher Configuration */ |
| 624 | |
| 625 | #define CLOCK_STRETCHER_MAX_ENTRIES 0x4 |
| 626 | #define CKS_LOOKUPTable_MAX_ENTRIES 0x4 |
| 627 | |
| 628 | /* The 'settings' field is subdivided in the following way: */ |
| 629 | #define CLOCK_STRETCHER_SETTING_DDT_MASK 0x01 |
| 630 | #define CLOCK_STRETCHER_SETTING_DDT_SHIFT 0x0 |
| 631 | #define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_MASK 0x1E |
| 632 | #define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_SHIFT 0x1 |
| 633 | #define CLOCK_STRETCHER_SETTING_ENABLE_MASK 0x80 |
| 634 | #define CLOCK_STRETCHER_SETTING_ENABLE_SHIFT 0x7 |
| 635 | |
| 636 | struct SMU_ClockStretcherDataTableEntry { |
| 637 | uint8_t minVID; |
| 638 | uint8_t maxVID; |
| 639 | |
| 640 | uint16_t setting; |
| 641 | }; |
| 642 | typedef struct SMU_ClockStretcherDataTableEntry SMU_ClockStretcherDataTableEntry; |
| 643 | |
| 644 | struct SMU_ClockStretcherDataTable { |
| 645 | SMU_ClockStretcherDataTableEntry ClockStretcherDataTableEntry[CLOCK_STRETCHER_MAX_ENTRIES]; |
| 646 | }; |
| 647 | typedef struct SMU_ClockStretcherDataTable SMU_ClockStretcherDataTable; |
| 648 | |
| 649 | struct SMU_CKS_LOOKUPTableEntry { |
| 650 | uint16_t minFreq; |
| 651 | uint16_t maxFreq; |
| 652 | |
| 653 | uint8_t setting; |
| 654 | uint8_t padding[3]; |
| 655 | }; |
| 656 | typedef struct SMU_CKS_LOOKUPTableEntry SMU_CKS_LOOKUPTableEntry; |
| 657 | |
| 658 | struct SMU_CKS_LOOKUPTable { |
| 659 | SMU_CKS_LOOKUPTableEntry CKS_LOOKUPTableEntry[CKS_LOOKUPTable_MAX_ENTRIES]; |
| 660 | }; |
| 661 | typedef struct SMU_CKS_LOOKUPTable SMU_CKS_LOOKUPTable; |
| 662 | |
| 663 | #endif |
| 664 | |
| 665 | |
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