[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / amd / powerplay / smumgr / tonga_smumgr.c

/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/gfp.h>

#include "smumgr.h"
#include "tonga_smumgr.h"
#include "pp_debug.h"
#include "smu_ucode_xfer_vi.h"
#include "tonga_ppsmc.h"
#include "smu/smu_7_1_2_d.h"
#include "smu/smu_7_1_2_sh_mask.h"
#include "cgs_common.h"
#include "tonga_smc.h"
#include "smu7_smumgr.h"


static int tonga_start_in_protection_mode(struct pp_smumgr *smumgr)
{
	int result;

	/* Assert reset */
	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
		SMC_SYSCON_RESET_CNTL, rst_reg, 1);

	result = smu7_upload_smu_firmware_image(smumgr);
	if (result)
		return result;

	/* Clear status */
	cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
		ixSMU_STATUS, 0);

	/* Enable clock */
	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
		SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);

	/* De-assert reset */
	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
		SMC_SYSCON_RESET_CNTL, rst_reg, 0);

	/* Set SMU Auto Start */
	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
		SMU_INPUT_DATA, AUTO_START, 1);

	/* Clear firmware interrupt enable flag */
	cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
		ixFIRMWARE_FLAGS, 0);

	SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
		RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);

	/**
	 * Call Test SMU message with 0x20000 offset to trigger SMU start
	 */
	smu7_send_msg_to_smc_offset(smumgr);

	/* Wait for done bit to be set */
	SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
		SMU_STATUS, SMU_DONE, 0);

	/* Check pass/failed indicator */
	if (1 != SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device,
				CGS_IND_REG__SMC, SMU_STATUS, SMU_PASS)) {
		printk(KERN_ERR "[ powerplay ] SMU Firmware start failed\n");
		return -EINVAL;
	}

	/* Wait for firmware to initialize */
	SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
		FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);

	return 0;
}


static int tonga_start_in_non_protection_mode(struct pp_smumgr *smumgr)
{
	int result = 0;

	/* wait for smc boot up */
	SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
		RCU_UC_EVENTS, boot_seq_done, 0);

	/*Clear firmware interrupt enable flag*/
	cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
		ixFIRMWARE_FLAGS, 0);


	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
		SMC_SYSCON_RESET_CNTL, rst_reg, 1);

	result = smu7_upload_smu_firmware_image(smumgr);

	if (result != 0)
		return result;

	/* Set smc instruct start point at 0x0 */
	smu7_program_jump_on_start(smumgr);


	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
		SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);

	/*De-assert reset*/
	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
		SMC_SYSCON_RESET_CNTL, rst_reg, 0);

	/* Wait for firmware to initialize */
	SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
		FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);

	return result;
}

static int tonga_start_smu(struct pp_smumgr *smumgr)
{
	int result;

	/* Only start SMC if SMC RAM is not running */
	if (!smu7_is_smc_ram_running(smumgr)) {
		/*Check if SMU is running in protected mode*/
		if (0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
					SMU_FIRMWARE, SMU_MODE)) {
			result = tonga_start_in_non_protection_mode(smumgr);
			if (result)
				return result;
		} else {
			result = tonga_start_in_protection_mode(smumgr);
			if (result)
				return result;
		}
	}

	result = smu7_request_smu_load_fw(smumgr);

	return result;
}

/**
 * Write a 32bit value to the SMC SRAM space.
 * ALL PARAMETERS ARE IN HOST BYTE ORDER.
 * @param    smumgr  the address of the powerplay hardware manager.
 * @param    smcAddress the address in the SMC RAM to access.
 * @param    value to write to the SMC SRAM.
 */
static int tonga_smu_init(struct pp_smumgr *smumgr)
{
	struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(smumgr->backend);

	int i;

	if (smu7_init(smumgr))
		return -EINVAL;

	for (i = 0; i < SMU72_MAX_LEVELS_GRAPHICS; i++)
		smu_data->activity_target[i] = 30;

	return 0;
}

static const struct pp_smumgr_func tonga_smu_funcs = {
	.smu_init = &tonga_smu_init,
	.smu_fini = &smu7_smu_fini,
	.start_smu = &tonga_start_smu,
	.check_fw_load_finish = &smu7_check_fw_load_finish,
	.request_smu_load_fw = &smu7_request_smu_load_fw,
	.request_smu_load_specific_fw = NULL,
	.send_msg_to_smc = &smu7_send_msg_to_smc,
	.send_msg_to_smc_with_parameter = &smu7_send_msg_to_smc_with_parameter,
	.download_pptable_settings = NULL,
	.upload_pptable_settings = NULL,
	.update_smc_table = tonga_update_smc_table,
	.get_offsetof = tonga_get_offsetof,
	.process_firmware_header = tonga_process_firmware_header,
	.init_smc_table = tonga_init_smc_table,
	.update_sclk_threshold = tonga_update_sclk_threshold,
	.thermal_setup_fan_table = tonga_thermal_setup_fan_table,
	.populate_all_graphic_levels = tonga_populate_all_graphic_levels,
	.populate_all_memory_levels = tonga_populate_all_memory_levels,
	.get_mac_definition = tonga_get_mac_definition,
	.initialize_mc_reg_table = tonga_initialize_mc_reg_table,
	.is_dpm_running = tonga_is_dpm_running,
};

int tonga_smum_init(struct pp_smumgr *smumgr)
{
	struct tonga_smumgr *tonga_smu = NULL;

	tonga_smu = kzalloc(sizeof(struct tonga_smumgr), GFP_KERNEL);

	if (tonga_smu == NULL)
		return -ENOMEM;

	smumgr->backend = tonga_smu;
	smumgr->smumgr_funcs = &tonga_smu_funcs;

	return 0;
}
Commit	Line	Data
1060029f JZ	1	/*
	2	* Copyright 2015 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#include <linux/types.h>
	24	#include <linux/kernel.h>
	25	#include <linux/slab.h>
	26	#include <linux/gfp.h>
	27
	28	#include "smumgr.h"
	29	#include "tonga_smumgr.h"
	30	#include "pp_debug.h"
	31	#include "smu_ucode_xfer_vi.h"
	32	#include "tonga_ppsmc.h"
	33	#include "smu/smu_7_1_2_d.h"
	34	#include "smu/smu_7_1_2_sh_mask.h"
	35	#include "cgs_common.h"
14860220	36	#include "tonga_smc.h"
ac43f080	37	#include "smu7_smumgr.h"
1060029f	38
1060029f JZ	39
	40	static int tonga_start_in_protection_mode(struct pp_smumgr *smumgr)
	41	{
	42	int result;
	43
	44	/* Assert reset */
	45	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
	46	SMC_SYSCON_RESET_CNTL, rst_reg, 1);
	47
ac43f080	48	result = smu7_upload_smu_firmware_image(smumgr);
1060029f JZ	49	if (result)
	50	return result;
	51
	52	/* Clear status */
	53	cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
	54	ixSMU_STATUS, 0);
	55
	56	/* Enable clock */
	57	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
	58	SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
	59
	60	/* De-assert reset */
	61	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
	62	SMC_SYSCON_RESET_CNTL, rst_reg, 0);
	63
	64	/* Set SMU Auto Start */
	65	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
	66	SMU_INPUT_DATA, AUTO_START, 1);
	67
	68	/* Clear firmware interrupt enable flag */
	69	cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
	70	ixFIRMWARE_FLAGS, 0);
	71
	72	SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
	73	RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
	74
	75	/**
	76	* Call Test SMU message with 0x20000 offset to trigger SMU start
	77	*/
ac43f080	78	smu7_send_msg_to_smc_offset(smumgr);
1060029f JZ	79
	80	/* Wait for done bit to be set */
	81	SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
	82	SMU_STATUS, SMU_DONE, 0);
	83
	84	/* Check pass/failed indicator */
	85	if (1 != SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device,
	86	CGS_IND_REG__SMC, SMU_STATUS, SMU_PASS)) {
	87	printk(KERN_ERR "[ powerplay ] SMU Firmware start failed\n");
	88	return -EINVAL;
	89	}
	90
	91	/* Wait for firmware to initialize */
	92	SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
	93	FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
	94
	95	return 0;
	96	}
	97
	98
	99	static int tonga_start_in_non_protection_mode(struct pp_smumgr *smumgr)
	100	{
	101	int result = 0;
	102
	103	/* wait for smc boot up */
	104	SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
	105	RCU_UC_EVENTS, boot_seq_done, 0);
	106
	107	/Clear firmware interrupt enable flag/
	108	cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
	109	ixFIRMWARE_FLAGS, 0);
	110
	111
	112	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
	113	SMC_SYSCON_RESET_CNTL, rst_reg, 1);
	114
ac43f080	115	result = smu7_upload_smu_firmware_image(smumgr);
1060029f JZ	116
	117	if (result != 0)
	118	return result;
	119
	120	/* Set smc instruct start point at 0x0 */
ac43f080	121	smu7_program_jump_on_start(smumgr);
1060029f JZ	122
	123
	124	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
	125	SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
	126
	127	/De-assert reset/
	128	SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
	129	SMC_SYSCON_RESET_CNTL, rst_reg, 0);
	130
	131	/* Wait for firmware to initialize */
	132	SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
	133	FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
	134
	135	return result;
	136	}
	137
	138	static int tonga_start_smu(struct pp_smumgr *smumgr)
	139	{
	140	int result;
	141
	142	/* Only start SMC if SMC RAM is not running */
ac43f080	143	if (!smu7_is_smc_ram_running(smumgr)) {
1060029f JZ	144	/Check if SMU is running in protected mode/
	145	if (0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
	146	SMU_FIRMWARE, SMU_MODE)) {
	147	result = tonga_start_in_non_protection_mode(smumgr);
	148	if (result)
	149	return result;
	150	} else {
	151	result = tonga_start_in_protection_mode(smumgr);
	152	if (result)
	153	return result;
	154	}
	155	}
	156
ac43f080	157	result = smu7_request_smu_load_fw(smumgr);
1060029f JZ	158
	159	return result;
	160	}
	161
	162	/**
	163	* Write a 32bit value to the SMC SRAM space.
	164	* ALL PARAMETERS ARE IN HOST BYTE ORDER.
	165	* @param smumgr the address of the powerplay hardware manager.
	166	* @param smcAddress the address in the SMC RAM to access.
	167	* @param value to write to the SMC SRAM.
	168	*/
	169	static int tonga_smu_init(struct pp_smumgr *smumgr)
	170	{
ac43f080 RZ	171	struct tonga_smumgr smu_data = (struct tonga_smumgr )(smumgr->backend);
ac43f080 RZ	172
14860220 RZ	173	int i;
14860220 RZ	174
ac43f080 RZ	175	if (smu7_init(smumgr))
ac43f080 RZ	176	return -EINVAL;
1060029f	177
14860220	178	for (i = 0; i < SMU72_MAX_LEVELS_GRAPHICS; i++)
ac43f080	179	smu_data->activity_target[i] = 30;
14860220	180
1060029f JZ	181	return 0;
	182	}
	183
	184	static const struct pp_smumgr_func tonga_smu_funcs = {
	185	.smu_init = &tonga_smu_init,
ac43f080	186	.smu_fini = &smu7_smu_fini,
1060029f	187	.start_smu = &tonga_start_smu,
ac43f080 RZ	188	.check_fw_load_finish = &smu7_check_fw_load_finish,
	189	.request_smu_load_fw = &smu7_request_smu_load_fw,
	190	.request_smu_load_specific_fw = NULL,
	191	.send_msg_to_smc = &smu7_send_msg_to_smc,
	192	.send_msg_to_smc_with_parameter = &smu7_send_msg_to_smc_with_parameter,
1060029f JZ	193	.download_pptable_settings = NULL,
1060029f JZ	194	.upload_pptable_settings = NULL,
14860220 RZ	195	.update_smc_table = tonga_update_smc_table,
	196	.get_offsetof = tonga_get_offsetof,
	197	.process_firmware_header = tonga_process_firmware_header,
	198	.init_smc_table = tonga_init_smc_table,
	199	.update_sclk_threshold = tonga_update_sclk_threshold,
	200	.thermal_setup_fan_table = tonga_thermal_setup_fan_table,
	201	.populate_all_graphic_levels = tonga_populate_all_graphic_levels,
	202	.populate_all_memory_levels = tonga_populate_all_memory_levels,
	203	.get_mac_definition = tonga_get_mac_definition,
	204	.initialize_mc_reg_table = tonga_initialize_mc_reg_table,
	205	.is_dpm_running = tonga_is_dpm_running,
1060029f JZ	206	};
	207
	208	int tonga_smum_init(struct pp_smumgr *smumgr)
	209	{
	210	struct tonga_smumgr *tonga_smu = NULL;
	211
	212	tonga_smu = kzalloc(sizeof(struct tonga_smumgr), GFP_KERNEL);
	213
	214	if (tonga_smu == NULL)
c15c8d70	215	return -ENOMEM;
1060029f JZ	216
	217	smumgr->backend = tonga_smu;
	218	smumgr->smumgr_funcs = &tonga_smu_funcs;
	219
	220	return 0;
	221	}