[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / powerplay / smumgr / tonga_smumgr.h

/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#ifndef _TONGA_SMUMGR_H_
#define _TONGA_SMUMGR_H_

#include "smu72_discrete.h"
#include "smu7_smumgr.h"
#include "smu72.h"


#define ASICID_IS_TONGA_P(wDID, bRID)	 \
	(((wDID == 0x6930) && ((bRID == 0xF0) || (bRID == 0xF1) || (bRID == 0xFF))) \
	|| ((wDID == 0x6920) && ((bRID == 0) || (bRID == 1))))

struct tonga_pt_defaults {
	uint8_t   svi_load_line_en;
	uint8_t   svi_load_line_vddC;
	uint8_t   tdc_vddc_throttle_release_limit_perc;
	uint8_t   tdc_mawt;
	uint8_t   tdc_waterfall_ctl;
	uint8_t   dte_ambient_temp_base;
	uint32_t  display_cac;
	uint32_t  bapm_temp_gradient;
	uint16_t  bapmti_r[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS];
	uint16_t  bapmti_rc[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS];
};

struct tonga_mc_reg_entry {
	uint32_t mclk_max;
	uint32_t mc_data[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE];
};

struct tonga_mc_reg_table {
	uint8_t   last;               /* number of registers*/
	uint8_t   num_entries;        /* number of entries in mc_reg_table_entry used*/
	uint16_t  validflag;          /* indicate the corresponding register is valid or not. 1: valid, 0: invalid. bit0->address[0], bit1->address[1], etc.*/
	struct tonga_mc_reg_entry    mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
	SMU72_Discrete_MCRegisterAddress mc_reg_address[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE];
};


struct tonga_smumgr {

	struct smu7_smumgr                   smu7_data;
	struct SMU72_Discrete_DpmTable       smc_state_table;
	struct SMU72_Discrete_Ulv            ulv_setting;
	struct SMU72_Discrete_PmFuses  power_tune_table;
	const struct tonga_pt_defaults  *power_tune_defaults;
	SMU72_Discrete_MCRegisters      mc_regs;
	struct tonga_mc_reg_table mc_reg_table;

	uint32_t        activity_target[SMU72_MAX_LEVELS_GRAPHICS];

};

#endif
Commit	Line	Data
1060029f JZ	1	/*
	2	* Copyright 2015 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23
	24	#ifndef _TONGA_SMUMGR_H_
	25	#define _TONGA_SMUMGR_H_
	26
14860220	27	#include "smu72_discrete.h"
ac43f080	28	#include "smu7_smumgr.h"
4dddc212 RZ	29	#include "smu72.h"
	30
	31
	32	#define ASICID_IS_TONGA_P(wDID, bRID) \
	33	(((wDID == 0x6930) && ((bRID == 0xF0) \|\| (bRID == 0xF1) \|\| (bRID == 0xFF))) \
	34	\|\| ((wDID == 0x6920) && ((bRID == 0) \|\| (bRID == 1))))
	35
	36	struct tonga_pt_defaults {
	37	uint8_t svi_load_line_en;
	38	uint8_t svi_load_line_vddC;
	39	uint8_t tdc_vddc_throttle_release_limit_perc;
	40	uint8_t tdc_mawt;
	41	uint8_t tdc_waterfall_ctl;
	42	uint8_t dte_ambient_temp_base;
	43	uint32_t display_cac;
	44	uint32_t bapm_temp_gradient;
	45	uint16_t bapmti_r[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS];
	46	uint16_t bapmti_rc[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS];
	47	};
14860220 RZ	48
	49	struct tonga_mc_reg_entry {
	50	uint32_t mclk_max;
	51	uint32_t mc_data[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE];
	52	};
	53
	54	struct tonga_mc_reg_table {
	55	uint8_t last; /* number of registers*/
	56	uint8_t num_entries; /* number of entries in mc_reg_table_entry used*/
	57	uint16_t validflag; /* indicate the corresponding register is valid or not. 1: valid, 0: invalid. bit0->address[0], bit1->address[1], etc.*/
	58	struct tonga_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
	59	SMU72_Discrete_MCRegisterAddress mc_reg_address[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE];
	60	};
	61
	62
1060029f	63	struct tonga_smumgr {
14860220	64
ac43f080	65	struct smu7_smumgr smu7_data;
14860220 RZ	66	struct SMU72_Discrete_DpmTable smc_state_table;
	67	struct SMU72_Discrete_Ulv ulv_setting;
	68	struct SMU72_Discrete_PmFuses power_tune_table;
a1c1a1de	69	const struct tonga_pt_defaults *power_tune_defaults;
14860220 RZ	70	SMU72_Discrete_MCRegisters mc_regs;
	71	struct tonga_mc_reg_table mc_reg_table;
	72
	73	uint32_t activity_target[SMU72_MAX_LEVELS_GRAPHICS];
	74
1060029f JZ	75	};
1060029f JZ	76
1060029f	77	#endif