[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / arc / arcpgu_crtc.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * ARC PGU DRM driver.
 *
 * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com)
 */

#include <drm/drm_atomic_helper.h>
#include <drm/drm_device.h>
#include <drm/drm_fb_cma_helper.h>
#include <drm/drm_gem_cma_helper.h>
#include <drm/drm_vblank.h>
#include <drm/drm_plane_helper.h>
#include <drm/drm_probe_helper.h>
#include <linux/clk.h>
#include <linux/platform_data/simplefb.h>

#include "arcpgu.h"
#include "arcpgu_regs.h"

#define ENCODE_PGU_XY(x, y)	((((x) - 1) << 16) | ((y) - 1))

static struct simplefb_format supported_formats[] = {
	{ "r5g6b5", 16, {11, 5}, {5, 6}, {0, 5}, {0, 0}, DRM_FORMAT_RGB565 },
	{ "r8g8b8", 24, {16, 8}, {8, 8}, {0, 8}, {0, 0}, DRM_FORMAT_RGB888 },
};

static void arc_pgu_set_pxl_fmt(struct drm_crtc *crtc)
{
	struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
	const struct drm_framebuffer *fb = crtc->primary->state->fb;
	uint32_t pixel_format = fb->format->format;
	struct simplefb_format *format = NULL;
	int i;

	for (i = 0; i < ARRAY_SIZE(supported_formats); i++) {
		if (supported_formats[i].fourcc == pixel_format)
			format = &supported_formats[i];
	}

	if (WARN_ON(!format))
		return;

	if (format->fourcc == DRM_FORMAT_RGB888)
		arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
			      arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) |
					   ARCPGU_MODE_RGB888_MASK);

}

static const struct drm_crtc_funcs arc_pgu_crtc_funcs = {
	.destroy = drm_crtc_cleanup,
	.set_config = drm_atomic_helper_set_config,
	.page_flip = drm_atomic_helper_page_flip,
	.reset = drm_atomic_helper_crtc_reset,
	.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
	.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
};

static enum drm_mode_status arc_pgu_crtc_mode_valid(struct drm_crtc *crtc,
						    const struct drm_display_mode *mode)
{
	struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
	long rate, clk_rate = mode->clock * 1000;
	long diff = clk_rate / 200; /* +-0.5% allowed by HDMI spec */

	rate = clk_round_rate(arcpgu->clk, clk_rate);
	if ((max(rate, clk_rate) - min(rate, clk_rate) < diff) && (rate > 0))
		return MODE_OK;

	return MODE_NOCLOCK;
}

static void arc_pgu_crtc_mode_set_nofb(struct drm_crtc *crtc)
{
	struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
	struct drm_display_mode *m = &crtc->state->adjusted_mode;
	u32 val;

	arc_pgu_write(arcpgu, ARCPGU_REG_FMT,
		      ENCODE_PGU_XY(m->crtc_htotal, m->crtc_vtotal));

	arc_pgu_write(arcpgu, ARCPGU_REG_HSYNC,
		      ENCODE_PGU_XY(m->crtc_hsync_start - m->crtc_hdisplay,
				    m->crtc_hsync_end - m->crtc_hdisplay));

	arc_pgu_write(arcpgu, ARCPGU_REG_VSYNC,
		      ENCODE_PGU_XY(m->crtc_vsync_start - m->crtc_vdisplay,
				    m->crtc_vsync_end - m->crtc_vdisplay));

	arc_pgu_write(arcpgu, ARCPGU_REG_ACTIVE,
		      ENCODE_PGU_XY(m->crtc_hblank_end - m->crtc_hblank_start,
				    m->crtc_vblank_end - m->crtc_vblank_start));

	val = arc_pgu_read(arcpgu, ARCPGU_REG_CTRL);

	if (m->flags & DRM_MODE_FLAG_PVSYNC)
		val |= ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST;
	else
		val &= ~(ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST);

	if (m->flags & DRM_MODE_FLAG_PHSYNC)
		val |= ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST;
	else
		val &= ~(ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST);

	arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, val);
	arc_pgu_write(arcpgu, ARCPGU_REG_STRIDE, 0);
	arc_pgu_write(arcpgu, ARCPGU_REG_START_SET, 1);

	arc_pgu_set_pxl_fmt(crtc);

	clk_set_rate(arcpgu->clk, m->crtc_clock * 1000);
}

static void arc_pgu_crtc_atomic_enable(struct drm_crtc *crtc,
				       struct drm_crtc_state *old_state)
{
	struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);

	clk_prepare_enable(arcpgu->clk);
	arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
		      arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) |
		      ARCPGU_CTRL_ENABLE_MASK);
}

static void arc_pgu_crtc_atomic_disable(struct drm_crtc *crtc,
					struct drm_crtc_state *old_state)
{
	struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);

	clk_disable_unprepare(arcpgu->clk);
	arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
			      arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) &
			      ~ARCPGU_CTRL_ENABLE_MASK);
}

static void arc_pgu_crtc_atomic_begin(struct drm_crtc *crtc,
				      struct drm_crtc_state *state)
{
	struct drm_pending_vblank_event *event = crtc->state->event;

	if (event) {
		crtc->state->event = NULL;

		spin_lock_irq(&crtc->dev->event_lock);
		drm_crtc_send_vblank_event(crtc, event);
		spin_unlock_irq(&crtc->dev->event_lock);
	}
}

static const struct drm_crtc_helper_funcs arc_pgu_crtc_helper_funcs = {
	.mode_valid	= arc_pgu_crtc_mode_valid,
	.mode_set_nofb	= arc_pgu_crtc_mode_set_nofb,
	.atomic_begin	= arc_pgu_crtc_atomic_begin,
	.atomic_enable	= arc_pgu_crtc_atomic_enable,
	.atomic_disable	= arc_pgu_crtc_atomic_disable,
};

static void arc_pgu_plane_atomic_update(struct drm_plane *plane,
					struct drm_plane_state *state)
{
	struct arcpgu_drm_private *arcpgu;
	struct drm_gem_cma_object *gem;

	if (!plane->state->crtc || !plane->state->fb)
		return;

	arcpgu = crtc_to_arcpgu_priv(plane->state->crtc);
	gem = drm_fb_cma_get_gem_obj(plane->state->fb, 0);
	arc_pgu_write(arcpgu, ARCPGU_REG_BUF0_ADDR, gem->paddr);
}

static const struct drm_plane_helper_funcs arc_pgu_plane_helper_funcs = {
	.atomic_update = arc_pgu_plane_atomic_update,
};

static void arc_pgu_plane_destroy(struct drm_plane *plane)
{
	drm_plane_cleanup(plane);
}

static const struct drm_plane_funcs arc_pgu_plane_funcs = {
	.update_plane		= drm_atomic_helper_update_plane,
	.disable_plane		= drm_atomic_helper_disable_plane,
	.destroy		= arc_pgu_plane_destroy,
	.reset			= drm_atomic_helper_plane_reset,
	.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
	.atomic_destroy_state	= drm_atomic_helper_plane_destroy_state,
};

static struct drm_plane *arc_pgu_plane_init(struct drm_device *drm)
{
	struct arcpgu_drm_private *arcpgu = drm->dev_private;
	struct drm_plane *plane = NULL;
	u32 formats[ARRAY_SIZE(supported_formats)], i;
	int ret;

	plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL);
	if (!plane)
		return ERR_PTR(-ENOMEM);

	for (i = 0; i < ARRAY_SIZE(supported_formats); i++)
		formats[i] = supported_formats[i].fourcc;

	ret = drm_universal_plane_init(drm, plane, 0xff, &arc_pgu_plane_funcs,
				       formats, ARRAY_SIZE(formats),
				       NULL,
				       DRM_PLANE_TYPE_PRIMARY, NULL);
	if (ret)
		return ERR_PTR(ret);

	drm_plane_helper_add(plane, &arc_pgu_plane_helper_funcs);
	arcpgu->plane = plane;

	return plane;
}

int arc_pgu_setup_crtc(struct drm_device *drm)
{
	struct arcpgu_drm_private *arcpgu = drm->dev_private;
	struct drm_plane *primary;
	int ret;

	primary = arc_pgu_plane_init(drm);
	if (IS_ERR(primary))
		return PTR_ERR(primary);

	ret = drm_crtc_init_with_planes(drm, &arcpgu->crtc, primary, NULL,
					&arc_pgu_crtc_funcs, NULL);
	if (ret) {
		arc_pgu_plane_destroy(primary);
		return ret;
	}

	drm_crtc_helper_add(&arcpgu->crtc, &arc_pgu_crtc_helper_funcs);
	return 0;
}
Commit	Line	Data
1802d0be	1	// SPDX-License-Identifier: GPL-2.0-only
51dacf20 CP	2	/*
	3	* ARC PGU DRM driver.
	4	*
	5	* Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com)
51dacf20 CP	6	*/
	7
	8	#include <drm/drm_atomic_helper.h>
fe1f664a	9	#include <drm/drm_device.h>
51dacf20 CP	10	#include <drm/drm_fb_cma_helper.h>
51dacf20 CP	11	#include <drm/drm_gem_cma_helper.h>
fe1f664a	12	#include <drm/drm_vblank.h>
51dacf20	13	#include <drm/drm_plane_helper.h>
fcd70cd3	14	#include <drm/drm_probe_helper.h>
51dacf20 CP	15	#include <linux/clk.h>
	16	#include <linux/platform_data/simplefb.h>
	17
	18	#include "arcpgu.h"
	19	#include "arcpgu_regs.h"
	20
	21	#define ENCODE_PGU_XY(x, y) ((((x) - 1) << 16) \| ((y) - 1))
	22
	23	static struct simplefb_format supported_formats[] = {
	24	{ "r5g6b5", 16, {11, 5}, {5, 6}, {0, 5}, {0, 0}, DRM_FORMAT_RGB565 },
	25	{ "r8g8b8", 24, {16, 8}, {8, 8}, {0, 8}, {0, 0}, DRM_FORMAT_RGB888 },
	26	};
	27
	28	static void arc_pgu_set_pxl_fmt(struct drm_crtc *crtc)
	29	{
	30	struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
81852b6a	31	const struct drm_framebuffer *fb = crtc->primary->state->fb;
438b74a5	32	uint32_t pixel_format = fb->format->format;
51dacf20 CP	33	struct simplefb_format *format = NULL;
	34	int i;
	35
	36	for (i = 0; i < ARRAY_SIZE(supported_formats); i++) {
	37	if (supported_formats[i].fourcc == pixel_format)
	38	format = &supported_formats[i];
	39	}
	40
	41	if (WARN_ON(!format))
	42	return;
	43
	44	if (format->fourcc == DRM_FORMAT_RGB888)
	45	arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
	46	arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) \|
	47	ARCPGU_MODE_RGB888_MASK);
	48
	49	}
	50
	51	static const struct drm_crtc_funcs arc_pgu_crtc_funcs = {
	52	.destroy = drm_crtc_cleanup,
	53	.set_config = drm_atomic_helper_set_config,
	54	.page_flip = drm_atomic_helper_page_flip,
	55	.reset = drm_atomic_helper_crtc_reset,
	56	.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
	57	.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
	58	};
	59
2bf5ccc2	60	static enum drm_mode_status arc_pgu_crtc_mode_valid(struct drm_crtc *crtc,
2bf5ccc2	61	const struct drm_display_mode *mode)
2b3d860e JA	62	{
	63	struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
	64	long rate, clk_rate = mode->clock * 1000;
22d0be2a	65	long diff = clk_rate / 200; /* +-0.5% allowed by HDMI spec */
2b3d860e JA	66
2b3d860e JA	67	rate = clk_round_rate(arcpgu->clk, clk_rate);
22d0be2a JA	68	if ((max(rate, clk_rate) - min(rate, clk_rate) < diff) && (rate > 0))
22d0be2a JA	69	return MODE_OK;
2b3d860e	70
22d0be2a	71	return MODE_NOCLOCK;
2b3d860e JA	72	}
2b3d860e JA	73
51dacf20 CP	74	static void arc_pgu_crtc_mode_set_nofb(struct drm_crtc *crtc)
	75	{
	76	struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
	77	struct drm_display_mode *m = &crtc->state->adjusted_mode;
	78	u32 val;
	79
	80	arc_pgu_write(arcpgu, ARCPGU_REG_FMT,
	81	ENCODE_PGU_XY(m->crtc_htotal, m->crtc_vtotal));
	82
	83	arc_pgu_write(arcpgu, ARCPGU_REG_HSYNC,
	84	ENCODE_PGU_XY(m->crtc_hsync_start - m->crtc_hdisplay,
	85	m->crtc_hsync_end - m->crtc_hdisplay));
	86
	87	arc_pgu_write(arcpgu, ARCPGU_REG_VSYNC,
	88	ENCODE_PGU_XY(m->crtc_vsync_start - m->crtc_vdisplay,
	89	m->crtc_vsync_end - m->crtc_vdisplay));
	90
	91	arc_pgu_write(arcpgu, ARCPGU_REG_ACTIVE,
	92	ENCODE_PGU_XY(m->crtc_hblank_end - m->crtc_hblank_start,
	93	m->crtc_vblank_end - m->crtc_vblank_start));
	94
	95	val = arc_pgu_read(arcpgu, ARCPGU_REG_CTRL);
	96
	97	if (m->flags & DRM_MODE_FLAG_PVSYNC)
	98	val \|= ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST;
	99	else
	100	val &= ~(ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST);
	101
	102	if (m->flags & DRM_MODE_FLAG_PHSYNC)
	103	val \|= ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST;
	104	else
	105	val &= ~(ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST);
	106
	107	arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, val);
	108	arc_pgu_write(arcpgu, ARCPGU_REG_STRIDE, 0);
	109	arc_pgu_write(arcpgu, ARCPGU_REG_START_SET, 1);
	110
	111	arc_pgu_set_pxl_fmt(crtc);
	112
	113	clk_set_rate(arcpgu->clk, m->crtc_clock * 1000);
	114	}
	115
0b20a0f8 LP	116	static void arc_pgu_crtc_atomic_enable(struct drm_crtc *crtc,
0b20a0f8 LP	117	struct drm_crtc_state *old_state)
51dacf20 CP	118	{
	119	struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
	120
	121	clk_prepare_enable(arcpgu->clk);
	122	arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
	123	arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) \|
	124	ARCPGU_CTRL_ENABLE_MASK);
	125	}
	126
64581714 LP	127	static void arc_pgu_crtc_atomic_disable(struct drm_crtc *crtc,
64581714 LP	128	struct drm_crtc_state *old_state)
51dacf20 CP	129	{
	130	struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
	131
51dacf20 CP	132	clk_disable_unprepare(arcpgu->clk);
	133	arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
	134	arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) &
	135	~ARCPGU_CTRL_ENABLE_MASK);
	136	}
	137
51dacf20 CP	138	static void arc_pgu_crtc_atomic_begin(struct drm_crtc *crtc,
	139	struct drm_crtc_state *state)
	140	{
84d9a4a2	141	struct drm_pending_vblank_event *event = crtc->state->event;
51dacf20	142
84d9a4a2	143	if (event) {
51dacf20	144	crtc->state->event = NULL;
51dacf20	145
84d9a4a2 DV	146	spin_lock_irq(&crtc->dev->event_lock);
	147	drm_crtc_send_vblank_event(crtc, event);
	148	spin_unlock_irq(&crtc->dev->event_lock);
51dacf20 CP	149	}
	150	}
	151
	152	static const struct drm_crtc_helper_funcs arc_pgu_crtc_helper_funcs = {
2b3d860e	153	.mode_valid = arc_pgu_crtc_mode_valid,
51dacf20	154	.mode_set_nofb = arc_pgu_crtc_mode_set_nofb,
51dacf20	155	.atomic_begin = arc_pgu_crtc_atomic_begin,
0b20a0f8	156	.atomic_enable = arc_pgu_crtc_atomic_enable,
64581714	157	.atomic_disable = arc_pgu_crtc_atomic_disable,
51dacf20 CP	158	};
	159
	160	static void arc_pgu_plane_atomic_update(struct drm_plane *plane,
	161	struct drm_plane_state *state)
	162	{
	163	struct arcpgu_drm_private *arcpgu;
	164	struct drm_gem_cma_object *gem;
	165
	166	if (!plane->state->crtc \|\| !plane->state->fb)
	167	return;
	168
	169	arcpgu = crtc_to_arcpgu_priv(plane->state->crtc);
	170	gem = drm_fb_cma_get_gem_obj(plane->state->fb, 0);
	171	arc_pgu_write(arcpgu, ARCPGU_REG_BUF0_ADDR, gem->paddr);
	172	}
	173
	174	static const struct drm_plane_helper_funcs arc_pgu_plane_helper_funcs = {
51dacf20 CP	175	.atomic_update = arc_pgu_plane_atomic_update,
	176	};
	177
	178	static void arc_pgu_plane_destroy(struct drm_plane *plane)
	179	{
51dacf20 CP	180	drm_plane_cleanup(plane);
	181	}
	182
	183	static const struct drm_plane_funcs arc_pgu_plane_funcs = {
	184	.update_plane = drm_atomic_helper_update_plane,
	185	.disable_plane = drm_atomic_helper_disable_plane,
	186	.destroy = arc_pgu_plane_destroy,
	187	.reset = drm_atomic_helper_plane_reset,
	188	.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
	189	.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
	190	};
	191
	192	static struct drm_plane arc_pgu_plane_init(struct drm_device drm)
	193	{
	194	struct arcpgu_drm_private *arcpgu = drm->dev_private;
	195	struct drm_plane *plane = NULL;
	196	u32 formats[ARRAY_SIZE(supported_formats)], i;
	197	int ret;
	198
	199	plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL);
	200	if (!plane)
	201	return ERR_PTR(-ENOMEM);
	202
	203	for (i = 0; i < ARRAY_SIZE(supported_formats); i++)
	204	formats[i] = supported_formats[i].fourcc;
	205
	206	ret = drm_universal_plane_init(drm, plane, 0xff, &arc_pgu_plane_funcs,
	207	formats, ARRAY_SIZE(formats),
e6fc3b68	208	NULL,
51dacf20 CP	209	DRM_PLANE_TYPE_PRIMARY, NULL);
	210	if (ret)
	211	return ERR_PTR(ret);
	212
	213	drm_plane_helper_add(plane, &arc_pgu_plane_helper_funcs);
	214	arcpgu->plane = plane;
	215
	216	return plane;
	217	}
	218
	219	int arc_pgu_setup_crtc(struct drm_device *drm)
	220	{
	221	struct arcpgu_drm_private *arcpgu = drm->dev_private;
	222	struct drm_plane *primary;
	223	int ret;
	224
	225	primary = arc_pgu_plane_init(drm);
	226	if (IS_ERR(primary))
	227	return PTR_ERR(primary);
	228
	229	ret = drm_crtc_init_with_planes(drm, &arcpgu->crtc, primary, NULL,
	230	&arc_pgu_crtc_funcs, NULL);
	231	if (ret) {
	232	arc_pgu_plane_destroy(primary);
	233	return ret;
	234	}
	235
	236	drm_crtc_helper_add(&arcpgu->crtc, &arc_pgu_crtc_helper_funcs);
	237	return 0;
	238	}