[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / arm / malidp_planes.c

/*
 * (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
 * Author: Liviu Dudau <Liviu.Dudau@arm.com>
 *
 * This program is free software and is provided to you under the terms of the
 * GNU General Public License version 2 as published by the Free Software
 * Foundation, and any use by you of this program is subject to the terms
 * of such GNU licence.
 *
 * ARM Mali DP plane manipulation routines.
 */

#include <drm/drmP.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_fb_cma_helper.h>
#include <drm/drm_gem_cma_helper.h>
#include <drm/drm_plane_helper.h>
#include <drm/drm_print.h>

#include "malidp_hw.h"
#include "malidp_drv.h"

/* Layer specific register offsets */
#define MALIDP_LAYER_FORMAT		0x000
#define MALIDP_LAYER_CONTROL		0x004
#define   LAYER_ENABLE			(1 << 0)
#define   LAYER_FLOWCFG_MASK		7
#define   LAYER_FLOWCFG(x)		(((x) & LAYER_FLOWCFG_MASK) << 1)
#define     LAYER_FLOWCFG_SCALE_SE	3
#define   LAYER_ROT_OFFSET		8
#define   LAYER_H_FLIP			(1 << 10)
#define   LAYER_V_FLIP			(1 << 11)
#define   LAYER_ROT_MASK		(0xf << 8)
#define   LAYER_COMP_MASK		(0x3 << 12)
#define   LAYER_COMP_PIXEL		(0x3 << 12)
#define   LAYER_COMP_PLANE		(0x2 << 12)
#define MALIDP_LAYER_COMPOSE		0x008
#define MALIDP_LAYER_SIZE		0x00c
#define   LAYER_H_VAL(x)		(((x) & 0x1fff) << 0)
#define   LAYER_V_VAL(x)		(((x) & 0x1fff) << 16)
#define MALIDP_LAYER_COMP_SIZE		0x010
#define MALIDP_LAYER_OFFSET		0x014
#define MALIDP550_LS_ENABLE		0x01c
#define MALIDP550_LS_R1_IN_SIZE		0x020

/*
 * This 4-entry look-up-table is used to determine the full 8-bit alpha value
 * for formats with 1- or 2-bit alpha channels.
 * We set it to give 100%/0% opacity for 1-bit formats and 100%/66%/33%/0%
 * opacity for 2-bit formats.
 */
#define MALIDP_ALPHA_LUT 0xffaa5500

static void malidp_de_plane_destroy(struct drm_plane *plane)
{
	struct malidp_plane *mp = to_malidp_plane(plane);

	if (mp->base.fb)
		drm_framebuffer_put(mp->base.fb);

	drm_plane_helper_disable(plane);
	drm_plane_cleanup(plane);
	devm_kfree(plane->dev->dev, mp);
}

/*
 * Replicate what the default ->reset hook does: free the state pointer and
 * allocate a new empty object. We just need enough space to store
 * a malidp_plane_state instead of a drm_plane_state.
 */
static void malidp_plane_reset(struct drm_plane *plane)
{
	struct malidp_plane_state *state = to_malidp_plane_state(plane->state);

	if (state)
		__drm_atomic_helper_plane_destroy_state(&state->base);
	kfree(state);
	plane->state = NULL;
	state = kzalloc(sizeof(*state), GFP_KERNEL);
	if (state) {
		state->base.plane = plane;
		state->base.rotation = DRM_MODE_ROTATE_0;
		plane->state = &state->base;
	}
}

static struct
drm_plane_state *malidp_duplicate_plane_state(struct drm_plane *plane)
{
	struct malidp_plane_state *state, *m_state;

	if (!plane->state)
		return NULL;

	state = kmalloc(sizeof(*state), GFP_KERNEL);
	if (!state)
		return NULL;

	m_state = to_malidp_plane_state(plane->state);
	__drm_atomic_helper_plane_duplicate_state(plane, &state->base);
	state->rotmem_size = m_state->rotmem_size;
	state->format = m_state->format;
	state->n_planes = m_state->n_planes;

	return &state->base;
}

static void malidp_destroy_plane_state(struct drm_plane *plane,
				       struct drm_plane_state *state)
{
	struct malidp_plane_state *m_state = to_malidp_plane_state(state);

	__drm_atomic_helper_plane_destroy_state(state);
	kfree(m_state);
}

static void malidp_plane_atomic_print_state(struct drm_printer *p,
					    const struct drm_plane_state *state)
{
	struct malidp_plane_state *ms = to_malidp_plane_state(state);

	drm_printf(p, "\trotmem_size=%u\n", ms->rotmem_size);
	drm_printf(p, "\tformat_id=%u\n", ms->format);
	drm_printf(p, "\tn_planes=%u\n", ms->n_planes);
}

static const struct drm_plane_funcs malidp_de_plane_funcs = {
	.update_plane = drm_atomic_helper_update_plane,
	.disable_plane = drm_atomic_helper_disable_plane,
	.destroy = malidp_de_plane_destroy,
	.reset = malidp_plane_reset,
	.atomic_duplicate_state = malidp_duplicate_plane_state,
	.atomic_destroy_state = malidp_destroy_plane_state,
	.atomic_print_state = malidp_plane_atomic_print_state,
};

static int malidp_se_check_scaling(struct malidp_plane *mp,
				   struct drm_plane_state *state)
{
	struct drm_crtc_state *crtc_state =
		drm_atomic_get_existing_crtc_state(state->state, state->crtc);
	struct malidp_crtc_state *mc;
	struct drm_rect clip = { 0 };
	u32 src_w, src_h;
	int ret;

	if (!crtc_state)
		return -EINVAL;

	clip.x2 = crtc_state->adjusted_mode.hdisplay;
	clip.y2 = crtc_state->adjusted_mode.vdisplay;
	ret = drm_plane_helper_check_state(state, &clip, 0, INT_MAX, true, true);
	if (ret)
		return ret;

	src_w = state->src_w >> 16;
	src_h = state->src_h >> 16;
	if ((state->crtc_w == src_w) && (state->crtc_h == src_h)) {
		/* Scaling not necessary for this plane. */
		mc->scaled_planes_mask &= ~(mp->layer->id);
		return 0;
	}

	if (mp->layer->id & (DE_SMART | DE_GRAPHICS2))
		return -EINVAL;

	mc = to_malidp_crtc_state(crtc_state);

	mc->scaled_planes_mask |= mp->layer->id;
	/* Defer scaling requirements calculation to the crtc check. */
	return 0;
}

static int malidp_de_plane_check(struct drm_plane *plane,
				 struct drm_plane_state *state)
{
	struct malidp_plane *mp = to_malidp_plane(plane);
	struct malidp_plane_state *ms = to_malidp_plane_state(state);
	struct drm_framebuffer *fb;
	int i, ret;

	if (!state->crtc || !state->fb)
		return 0;

	fb = state->fb;

	ms->format = malidp_hw_get_format_id(&mp->hwdev->hw->map,
					     mp->layer->id,
					     fb->format->format);
	if (ms->format == MALIDP_INVALID_FORMAT_ID)
		return -EINVAL;

	ms->n_planes = fb->format->num_planes;
	for (i = 0; i < ms->n_planes; i++) {
		if (!malidp_hw_pitch_valid(mp->hwdev, fb->pitches[i])) {
			DRM_DEBUG_KMS("Invalid pitch %u for plane %d\n",
				      fb->pitches[i], i);
			return -EINVAL;
		}
	}

	if ((state->crtc_w > mp->hwdev->max_line_size) ||
	    (state->crtc_h > mp->hwdev->max_line_size) ||
	    (state->crtc_w < mp->hwdev->min_line_size) ||
	    (state->crtc_h < mp->hwdev->min_line_size))
		return -EINVAL;

	/*
	 * DP550/650 video layers can accept 3 plane formats only if
	 * fb->pitches[1] == fb->pitches[2] since they don't have a
	 * third plane stride register.
	 */
	if (ms->n_planes == 3 &&
	    !(mp->hwdev->hw->features & MALIDP_DEVICE_LV_HAS_3_STRIDES) &&
	    (state->fb->pitches[1] != state->fb->pitches[2]))
		return -EINVAL;

	ret = malidp_se_check_scaling(mp, state);
	if (ret)
		return ret;

	/* packed RGB888 / BGR888 can't be rotated or flipped */
	if (state->rotation != DRM_MODE_ROTATE_0 &&
	    (fb->format->format == DRM_FORMAT_RGB888 ||
	     fb->format->format == DRM_FORMAT_BGR888))
		return -EINVAL;

	ms->rotmem_size = 0;
	if (state->rotation & MALIDP_ROTATED_MASK) {
		int val;

		val = mp->hwdev->hw->rotmem_required(mp->hwdev, state->crtc_h,
						     state->crtc_w,
						     fb->format->format);
		if (val < 0)
			return val;

		ms->rotmem_size = val;
	}

	return 0;
}

static void malidp_de_set_plane_pitches(struct malidp_plane *mp,
					int num_planes, unsigned int pitches[3])
{
	int i;
	int num_strides = num_planes;

	if (!mp->layer->stride_offset)
		return;

	if (num_planes == 3)
		num_strides = (mp->hwdev->hw->features &
			       MALIDP_DEVICE_LV_HAS_3_STRIDES) ? 3 : 2;

	for (i = 0; i < num_strides; ++i)
		malidp_hw_write(mp->hwdev, pitches[i],
				mp->layer->base +
				mp->layer->stride_offset + i * 4);
}

static void malidp_de_plane_update(struct drm_plane *plane,
				   struct drm_plane_state *old_state)
{
	struct malidp_plane *mp;
	struct malidp_plane_state *ms = to_malidp_plane_state(plane->state);
	u32 src_w, src_h, dest_w, dest_h, val;
	int i;

	mp = to_malidp_plane(plane);

	/* convert src values from Q16 fixed point to integer */
	src_w = plane->state->src_w >> 16;
	src_h = plane->state->src_h >> 16;
	dest_w = plane->state->crtc_w;
	dest_h = plane->state->crtc_h;

	malidp_hw_write(mp->hwdev, ms->format, mp->layer->base);

	for (i = 0; i < ms->n_planes; i++) {
		/* calculate the offset for the layer's plane registers */
		u16 ptr = mp->layer->ptr + (i << 4);
		dma_addr_t fb_addr = drm_fb_cma_get_gem_addr(plane->state->fb,
							     plane->state, i);

		malidp_hw_write(mp->hwdev, lower_32_bits(fb_addr), ptr);
		malidp_hw_write(mp->hwdev, upper_32_bits(fb_addr), ptr + 4);
	}
	malidp_de_set_plane_pitches(mp, ms->n_planes,
				    plane->state->fb->pitches);

	malidp_hw_write(mp->hwdev, LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h),
			mp->layer->base + MALIDP_LAYER_SIZE);

	malidp_hw_write(mp->hwdev, LAYER_H_VAL(dest_w) | LAYER_V_VAL(dest_h),
			mp->layer->base + MALIDP_LAYER_COMP_SIZE);

	malidp_hw_write(mp->hwdev, LAYER_H_VAL(plane->state->crtc_x) |
			LAYER_V_VAL(plane->state->crtc_y),
			mp->layer->base + MALIDP_LAYER_OFFSET);

	if (mp->layer->id == DE_SMART)
		malidp_hw_write(mp->hwdev,
				LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h),
				mp->layer->base + MALIDP550_LS_R1_IN_SIZE);

	/* first clear the rotation bits */
	val = malidp_hw_read(mp->hwdev, mp->layer->base + MALIDP_LAYER_CONTROL);
	val &= ~LAYER_ROT_MASK;

	/* setup the rotation and axis flip bits */
	if (plane->state->rotation & DRM_MODE_ROTATE_MASK)
		val |= ilog2(plane->state->rotation & DRM_MODE_ROTATE_MASK) <<
		       LAYER_ROT_OFFSET;
	if (plane->state->rotation & DRM_MODE_REFLECT_X)
		val |= LAYER_H_FLIP;
	if (plane->state->rotation & DRM_MODE_REFLECT_Y)
		val |= LAYER_V_FLIP;

	/*
	 * always enable pixel alpha blending until we have a way to change
	 * blend modes
	 */
	val &= ~LAYER_COMP_MASK;
	val |= LAYER_COMP_PIXEL;

	val &= ~LAYER_FLOWCFG(LAYER_FLOWCFG_MASK);
	if (plane->state->crtc) {
		struct malidp_crtc_state *m =
			to_malidp_crtc_state(plane->state->crtc->state);

		if (m->scaler_config.scale_enable &&
		    m->scaler_config.plane_src_id == mp->layer->id)
			val |= LAYER_FLOWCFG(LAYER_FLOWCFG_SCALE_SE);
	}

	/* set the 'enable layer' bit */
	val |= LAYER_ENABLE;

	malidp_hw_write(mp->hwdev, val,
			mp->layer->base + MALIDP_LAYER_CONTROL);
}

static void malidp_de_plane_disable(struct drm_plane *plane,
				    struct drm_plane_state *state)
{
	struct malidp_plane *mp = to_malidp_plane(plane);

	malidp_hw_clearbits(mp->hwdev,
			    LAYER_ENABLE | LAYER_FLOWCFG(LAYER_FLOWCFG_MASK),
			    mp->layer->base + MALIDP_LAYER_CONTROL);
}

static const struct drm_plane_helper_funcs malidp_de_plane_helper_funcs = {
	.atomic_check = malidp_de_plane_check,
	.atomic_update = malidp_de_plane_update,
	.atomic_disable = malidp_de_plane_disable,
};

int malidp_de_planes_init(struct drm_device *drm)
{
	struct malidp_drm *malidp = drm->dev_private;
	const struct malidp_hw_regmap *map = &malidp->dev->hw->map;
	struct malidp_plane *plane = NULL;
	enum drm_plane_type plane_type;
	unsigned long crtcs = 1 << drm->mode_config.num_crtc;
	unsigned long flags = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_180 |
			      DRM_MODE_ROTATE_270 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y;
	u32 *formats;
	int ret, i, j, n;

	formats = kcalloc(map->n_pixel_formats, sizeof(*formats), GFP_KERNEL);
	if (!formats) {
		ret = -ENOMEM;
		goto cleanup;
	}

	for (i = 0; i < map->n_layers; i++) {
		u8 id = map->layers[i].id;

		plane = kzalloc(sizeof(*plane), GFP_KERNEL);
		if (!plane) {
			ret = -ENOMEM;
			goto cleanup;
		}

		/* build the list of DRM supported formats based on the map */
		for (n = 0, j = 0;  j < map->n_pixel_formats; j++) {
			if ((map->pixel_formats[j].layer & id) == id)
				formats[n++] = map->pixel_formats[j].format;
		}

		plane_type = (i == 0) ? DRM_PLANE_TYPE_PRIMARY :
					DRM_PLANE_TYPE_OVERLAY;
		ret = drm_universal_plane_init(drm, &plane->base, crtcs,
					       &malidp_de_plane_funcs, formats,
					       n, NULL, plane_type, NULL);
		if (ret < 0)
			goto cleanup;

		drm_plane_helper_add(&plane->base,
				     &malidp_de_plane_helper_funcs);
		plane->hwdev = malidp->dev;
		plane->layer = &map->layers[i];

		if (id == DE_SMART) {
			/*
			 * Enable the first rectangle in the SMART layer to be
			 * able to use it as a drm plane.
			 */
			malidp_hw_write(malidp->dev, 1,
					plane->layer->base + MALIDP550_LS_ENABLE);
			/* Skip the features which the SMART layer doesn't have. */
			continue;
		}

		drm_plane_create_rotation_property(&plane->base, DRM_MODE_ROTATE_0, flags);
		malidp_hw_write(malidp->dev, MALIDP_ALPHA_LUT,
				plane->layer->base + MALIDP_LAYER_COMPOSE);
	}

	kfree(formats);

	return 0;

cleanup:
	malidp_de_planes_destroy(drm);
	kfree(formats);

	return ret;
}

void malidp_de_planes_destroy(struct drm_device *drm)
{
	struct drm_plane *p, *pt;

	list_for_each_entry_safe(p, pt, &drm->mode_config.plane_list, head) {
		drm_plane_cleanup(p);
		kfree(p);
	}
}
Commit	Line	Data
ad49f860 LD	1	/*
	2	* (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
	3	* Author: Liviu Dudau <Liviu.Dudau@arm.com>
	4	*
	5	* This program is free software and is provided to you under the terms of the
	6	* GNU General Public License version 2 as published by the Free Software
	7	* Foundation, and any use by you of this program is subject to the terms
	8	* of such GNU licence.
	9	*
	10	* ARM Mali DP plane manipulation routines.
	11	*/
	12
	13	#include <drm/drmP.h>
b9c3315c	14	#include <drm/drm_atomic.h>
ad49f860 LD	15	#include <drm/drm_atomic_helper.h>
	16	#include <drm/drm_fb_cma_helper.h>
	17	#include <drm/drm_gem_cma_helper.h>
	18	#include <drm/drm_plane_helper.h>
88d4d90f	19	#include <drm/drm_print.h>
ad49f860 LD	20
	21	#include "malidp_hw.h"
	22	#include "malidp_drv.h"
	23
	24	/* Layer specific register offsets */
	25	#define MALIDP_LAYER_FORMAT 0x000
	26	#define MALIDP_LAYER_CONTROL 0x004
	27	#define LAYER_ENABLE (1 << 0)
28ce675b MA	28	#define LAYER_FLOWCFG_MASK 7
	29	#define LAYER_FLOWCFG(x) (((x) & LAYER_FLOWCFG_MASK) << 1)
	30	#define LAYER_FLOWCFG_SCALE_SE 3
ad49f860 LD	31	#define LAYER_ROT_OFFSET 8
	32	#define LAYER_H_FLIP (1 << 10)
	33	#define LAYER_V_FLIP (1 << 11)
	34	#define LAYER_ROT_MASK (0xf << 8)
c57eb710 BS	35	#define LAYER_COMP_MASK (0x3 << 12)
	36	#define LAYER_COMP_PIXEL (0x3 << 12)
	37	#define LAYER_COMP_PLANE (0x2 << 12)
	38	#define MALIDP_LAYER_COMPOSE 0x008
ad49f860 LD	39	#define MALIDP_LAYER_SIZE 0x00c
	40	#define LAYER_H_VAL(x) (((x) & 0x1fff) << 0)
	41	#define LAYER_V_VAL(x) (((x) & 0x1fff) << 16)
	42	#define MALIDP_LAYER_COMP_SIZE 0x010
	43	#define MALIDP_LAYER_OFFSET 0x014
d1479f61 MA	44	#define MALIDP550_LS_ENABLE 0x01c
d1479f61 MA	45	#define MALIDP550_LS_R1_IN_SIZE 0x020
ad49f860	46
c57eb710 BS	47	/*
	48	* This 4-entry look-up-table is used to determine the full 8-bit alpha value
	49	* for formats with 1- or 2-bit alpha channels.
	50	* We set it to give 100%/0% opacity for 1-bit formats and 100%/66%/33%/0%
	51	* opacity for 2-bit formats.
	52	*/
	53	#define MALIDP_ALPHA_LUT 0xffaa5500
	54
ad49f860 LD	55	static void malidp_de_plane_destroy(struct drm_plane *plane)
	56	{
	57	struct malidp_plane *mp = to_malidp_plane(plane);
	58
	59	if (mp->base.fb)
c2cc215c	60	drm_framebuffer_put(mp->base.fb);
ad49f860 LD	61
	62	drm_plane_helper_disable(plane);
	63	drm_plane_cleanup(plane);
	64	devm_kfree(plane->dev->dev, mp);
	65	}
	66
fe10cd67 MA	67	/*
	68	* Replicate what the default ->reset hook does: free the state pointer and
	69	* allocate a new empty object. We just need enough space to store
	70	* a malidp_plane_state instead of a drm_plane_state.
	71	*/
	72	static void malidp_plane_reset(struct drm_plane *plane)
	73	{
	74	struct malidp_plane_state *state = to_malidp_plane_state(plane->state);
	75
	76	if (state)
	77	__drm_atomic_helper_plane_destroy_state(&state->base);
	78	kfree(state);
	79	plane->state = NULL;
	80	state = kzalloc(sizeof(*state), GFP_KERNEL);
	81	if (state) {
	82	state->base.plane = plane;
c2c446ad	83	state->base.rotation = DRM_MODE_ROTATE_0;
fe10cd67 MA	84	plane->state = &state->base;
	85	}
	86	}
	87
ed8b0c0f BX	88	static struct
ed8b0c0f BX	89	drm_plane_state malidp_duplicate_plane_state(struct drm_plane plane)
ad49f860 LD	90	{
	91	struct malidp_plane_state state, m_state;
	92
	93	if (!plane->state)
	94	return NULL;
	95
	96	state = kmalloc(sizeof(*state), GFP_KERNEL);
94d8b9b7 SV	97	if (!state)
	98	return NULL;
	99
	100	m_state = to_malidp_plane_state(plane->state);
	101	__drm_atomic_helper_plane_duplicate_state(plane, &state->base);
	102	state->rotmem_size = m_state->rotmem_size;
	103	state->format = m_state->format;
	104	state->n_planes = m_state->n_planes;
ad49f860 LD	105
	106	return &state->base;
	107	}
	108
ed8b0c0f BX	109	static void malidp_destroy_plane_state(struct drm_plane *plane,
ed8b0c0f BX	110	struct drm_plane_state *state)
ad49f860 LD	111	{
	112	struct malidp_plane_state *m_state = to_malidp_plane_state(state);
	113
	114	__drm_atomic_helper_plane_destroy_state(state);
	115	kfree(m_state);
	116	}
	117
88d4d90f MA	118	static void malidp_plane_atomic_print_state(struct drm_printer *p,
	119	const struct drm_plane_state *state)
	120	{
	121	struct malidp_plane_state *ms = to_malidp_plane_state(state);
88d4d90f MA	122
	123	drm_printf(p, "\trotmem_size=%u\n", ms->rotmem_size);
	124	drm_printf(p, "\tformat_id=%u\n", ms->format);
	125	drm_printf(p, "\tn_planes=%u\n", ms->n_planes);
	126	}
	127
ad49f860 LD	128	static const struct drm_plane_funcs malidp_de_plane_funcs = {
	129	.update_plane = drm_atomic_helper_update_plane,
	130	.disable_plane = drm_atomic_helper_disable_plane,
	131	.destroy = malidp_de_plane_destroy,
fe10cd67	132	.reset = malidp_plane_reset,
ad49f860 LD	133	.atomic_duplicate_state = malidp_duplicate_plane_state,
ad49f860 LD	134	.atomic_destroy_state = malidp_destroy_plane_state,
88d4d90f	135	.atomic_print_state = malidp_plane_atomic_print_state,
ad49f860 LD	136	};
ad49f860 LD	137
28ce675b MA	138	static int malidp_se_check_scaling(struct malidp_plane *mp,
	139	struct drm_plane_state *state)
	140	{
	141	struct drm_crtc_state *crtc_state =
	142	drm_atomic_get_existing_crtc_state(state->state, state->crtc);
	143	struct malidp_crtc_state *mc;
	144	struct drm_rect clip = { 0 };
	145	u32 src_w, src_h;
	146	int ret;
	147
	148	if (!crtc_state)
	149	return -EINVAL;
	150
	151	clip.x2 = crtc_state->adjusted_mode.hdisplay;
	152	clip.y2 = crtc_state->adjusted_mode.vdisplay;
	153	ret = drm_plane_helper_check_state(state, &clip, 0, INT_MAX, true, true);
	154	if (ret)
	155	return ret;
	156
	157	src_w = state->src_w >> 16;
	158	src_h = state->src_h >> 16;
	159	if ((state->crtc_w == src_w) && (state->crtc_h == src_h)) {
	160	/* Scaling not necessary for this plane. */
	161	mc->scaled_planes_mask &= ~(mp->layer->id);
	162	return 0;
	163	}
	164
	165	if (mp->layer->id & (DE_SMART \| DE_GRAPHICS2))
	166	return -EINVAL;
	167
	168	mc = to_malidp_crtc_state(crtc_state);
	169
	170	mc->scaled_planes_mask \|= mp->layer->id;
	171	/* Defer scaling requirements calculation to the crtc check. */
	172	return 0;
	173	}
	174
ad49f860 LD	175	static int malidp_de_plane_check(struct drm_plane *plane,
	176	struct drm_plane_state *state)
	177	{
	178	struct malidp_plane *mp = to_malidp_plane(plane);
	179	struct malidp_plane_state *ms = to_malidp_plane_state(state);
a46a096a	180	struct drm_framebuffer *fb;
b9c3315c	181	int i, ret;
ad49f860 LD	182
	183	if (!state->crtc \|\| !state->fb)
	184	return 0;
	185
a46a096a BS	186	fb = state->fb;
a46a096a BS	187
a6993b21 LD	188	ms->format = malidp_hw_get_format_id(&mp->hwdev->hw->map,
	189	mp->layer->id,
	190	fb->format->format);
70c94a3c	191	if (ms->format == MALIDP_INVALID_FORMAT_ID)
ad49f860 LD	192	return -EINVAL;
ad49f860 LD	193
bcb0b461	194	ms->n_planes = fb->format->num_planes;
70c94a3c	195	for (i = 0; i < ms->n_planes; i++) {
a46a096a BS	196	if (!malidp_hw_pitch_valid(mp->hwdev, fb->pitches[i])) {
	197	DRM_DEBUG_KMS("Invalid pitch %u for plane %d\n",
	198	fb->pitches[i], i);
	199	return -EINVAL;
	200	}
	201	}
	202
ad49f860 LD	203	if ((state->crtc_w > mp->hwdev->max_line_size) \|\|
	204	(state->crtc_h > mp->hwdev->max_line_size) \|\|
	205	(state->crtc_w < mp->hwdev->min_line_size) \|\|
b2a2ddb0	206	(state->crtc_h < mp->hwdev->min_line_size))
ad49f860 LD	207	return -EINVAL;
ad49f860 LD	208
83d642ee MA	209	/*
	210	* DP550/650 video layers can accept 3 plane formats only if
	211	* fb->pitches[1] == fb->pitches[2] since they don't have a
	212	* third plane stride register.
	213	*/
	214	if (ms->n_planes == 3 &&
a6993b21	215	!(mp->hwdev->hw->features & MALIDP_DEVICE_LV_HAS_3_STRIDES) &&
83d642ee MA	216	(state->fb->pitches[1] != state->fb->pitches[2]))
	217	return -EINVAL;
	218
28ce675b MA	219	ret = malidp_se_check_scaling(mp, state);
	220	if (ret)
	221	return ret;
	222
ad49f860	223	/* packed RGB888 / BGR888 can't be rotated or flipped */
c2c446ad	224	if (state->rotation != DRM_MODE_ROTATE_0 &&
438b74a5 VS	225	(fb->format->format == DRM_FORMAT_RGB888 \|\|
438b74a5 VS	226	fb->format->format == DRM_FORMAT_BGR888))
ad49f860 LD	227	return -EINVAL;
	228
	229	ms->rotmem_size = 0;
	230	if (state->rotation & MALIDP_ROTATED_MASK) {
	231	int val;
	232
a6993b21 LD	233	val = mp->hwdev->hw->rotmem_required(mp->hwdev, state->crtc_h,
	234	state->crtc_w,
	235	fb->format->format);
ad49f860 LD	236	if (val < 0)
	237	return val;
	238
	239	ms->rotmem_size = val;
	240	}
	241
	242	return 0;
	243	}
	244
83d642ee MA	245	static void malidp_de_set_plane_pitches(struct malidp_plane *mp,
	246	int num_planes, unsigned int pitches[3])
	247	{
	248	int i;
	249	int num_strides = num_planes;
	250
	251	if (!mp->layer->stride_offset)
	252	return;
	253
	254	if (num_planes == 3)
a6993b21	255	num_strides = (mp->hwdev->hw->features &
83d642ee MA	256	MALIDP_DEVICE_LV_HAS_3_STRIDES) ? 3 : 2;
	257
	258	for (i = 0; i < num_strides; ++i)
	259	malidp_hw_write(mp->hwdev, pitches[i],
	260	mp->layer->base +
	261	mp->layer->stride_offset + i * 4);
	262	}
	263
ad49f860 LD	264	static void malidp_de_plane_update(struct drm_plane *plane,
	265	struct drm_plane_state *old_state)
	266	{
ad49f860	267	struct malidp_plane *mp;
70c94a3c	268	struct malidp_plane_state *ms = to_malidp_plane_state(plane->state);
70c94a3c BS	269	u32 src_w, src_h, dest_w, dest_h, val;
70c94a3c BS	270	int i;
ad49f860 LD	271
ad49f860 LD	272	mp = to_malidp_plane(plane);
ad49f860 LD	273
	274	/* convert src values from Q16 fixed point to integer */
	275	src_w = plane->state->src_w >> 16;
	276	src_h = plane->state->src_h >> 16;
edabb3c4 BS	277	dest_w = plane->state->crtc_w;
edabb3c4 BS	278	dest_h = plane->state->crtc_h;
ad49f860	279
70c94a3c	280	malidp_hw_write(mp->hwdev, ms->format, mp->layer->base);
ad49f860	281
70c94a3c	282	for (i = 0; i < ms->n_planes; i++) {
ad49f860	283	/* calculate the offset for the layer's plane registers */
e40eda3d LD	284	u16 ptr = mp->layer->ptr + (i << 4);
	285	dma_addr_t fb_addr = drm_fb_cma_get_gem_addr(plane->state->fb,
	286	plane->state, i);
ad49f860	287
e40eda3d LD	288	malidp_hw_write(mp->hwdev, lower_32_bits(fb_addr), ptr);
e40eda3d LD	289	malidp_hw_write(mp->hwdev, upper_32_bits(fb_addr), ptr + 4);
ad49f860	290	}
83d642ee MA	291	malidp_de_set_plane_pitches(mp, ms->n_planes,
83d642ee MA	292	plane->state->fb->pitches);
ad49f860 LD	293
	294	malidp_hw_write(mp->hwdev, LAYER_H_VAL(src_w) \| LAYER_V_VAL(src_h),
	295	mp->layer->base + MALIDP_LAYER_SIZE);
	296
	297	malidp_hw_write(mp->hwdev, LAYER_H_VAL(dest_w) \| LAYER_V_VAL(dest_h),
	298	mp->layer->base + MALIDP_LAYER_COMP_SIZE);
	299
	300	malidp_hw_write(mp->hwdev, LAYER_H_VAL(plane->state->crtc_x) \|
	301	LAYER_V_VAL(plane->state->crtc_y),
	302	mp->layer->base + MALIDP_LAYER_OFFSET);
	303
d1479f61 MA	304	if (mp->layer->id == DE_SMART)
	305	malidp_hw_write(mp->hwdev,
	306	LAYER_H_VAL(src_w) \| LAYER_V_VAL(src_h),
	307	mp->layer->base + MALIDP550_LS_R1_IN_SIZE);
	308
c57eb710 BS	309	/* first clear the rotation bits */
	310	val = malidp_hw_read(mp->hwdev, mp->layer->base + MALIDP_LAYER_CONTROL);
	311	val &= ~LAYER_ROT_MASK;
ad49f860 LD	312
ad49f860 LD	313	/* setup the rotation and axis flip bits */
c2c446ad RF	314	if (plane->state->rotation & DRM_MODE_ROTATE_MASK)
c2c446ad RF	315	val \|= ilog2(plane->state->rotation & DRM_MODE_ROTATE_MASK) <<
c7ffa59c	316	LAYER_ROT_OFFSET;
c2c446ad	317	if (plane->state->rotation & DRM_MODE_REFLECT_X)
ad49f860	318	val \|= LAYER_H_FLIP;
c2c446ad	319	if (plane->state->rotation & DRM_MODE_REFLECT_Y)
7916efe5	320	val \|= LAYER_V_FLIP;
ad49f860	321
c57eb710 BS	322	/*
	323	* always enable pixel alpha blending until we have a way to change
	324	* blend modes
	325	*/
	326	val &= ~LAYER_COMP_MASK;
	327	val \|= LAYER_COMP_PIXEL;
	328
28ce675b MA	329	val &= ~LAYER_FLOWCFG(LAYER_FLOWCFG_MASK);
	330	if (plane->state->crtc) {
	331	struct malidp_crtc_state *m =
	332	to_malidp_crtc_state(plane->state->crtc->state);
	333
	334	if (m->scaler_config.scale_enable &&
	335	m->scaler_config.plane_src_id == mp->layer->id)
	336	val \|= LAYER_FLOWCFG(LAYER_FLOWCFG_SCALE_SE);
	337	}
	338
ad49f860 LD	339	/* set the 'enable layer' bit */
	340	val \|= LAYER_ENABLE;
	341
c57eb710 BS	342	malidp_hw_write(mp->hwdev, val,
c57eb710 BS	343	mp->layer->base + MALIDP_LAYER_CONTROL);
ad49f860 LD	344	}
	345
	346	static void malidp_de_plane_disable(struct drm_plane *plane,
	347	struct drm_plane_state *state)
	348	{
	349	struct malidp_plane *mp = to_malidp_plane(plane);
	350
28ce675b MA	351	malidp_hw_clearbits(mp->hwdev,
28ce675b MA	352	LAYER_ENABLE \| LAYER_FLOWCFG(LAYER_FLOWCFG_MASK),
ad49f860 LD	353	mp->layer->base + MALIDP_LAYER_CONTROL);
	354	}
	355
	356	static const struct drm_plane_helper_funcs malidp_de_plane_helper_funcs = {
	357	.atomic_check = malidp_de_plane_check,
	358	.atomic_update = malidp_de_plane_update,
	359	.atomic_disable = malidp_de_plane_disable,
	360	};
	361
	362	int malidp_de_planes_init(struct drm_device *drm)
	363	{
	364	struct malidp_drm *malidp = drm->dev_private;
a6993b21	365	const struct malidp_hw_regmap *map = &malidp->dev->hw->map;
ad49f860 LD	366	struct malidp_plane *plane = NULL;
	367	enum drm_plane_type plane_type;
	368	unsigned long crtcs = 1 << drm->mode_config.num_crtc;
c2c446ad RF	369	unsigned long flags = DRM_MODE_ROTATE_0 \| DRM_MODE_ROTATE_90 \| DRM_MODE_ROTATE_180 \|
c2c446ad RF	370	DRM_MODE_ROTATE_270 \| DRM_MODE_REFLECT_X \| DRM_MODE_REFLECT_Y;
ad49f860 LD	371	u32 *formats;
	372	int ret, i, j, n;
	373
6211b486	374	formats = kcalloc(map->n_pixel_formats, sizeof(*formats), GFP_KERNEL);
ad49f860 LD	375	if (!formats) {
	376	ret = -ENOMEM;
	377	goto cleanup;
	378	}
	379
	380	for (i = 0; i < map->n_layers; i++) {
	381	u8 id = map->layers[i].id;
	382
	383	plane = kzalloc(sizeof(*plane), GFP_KERNEL);
	384	if (!plane) {
	385	ret = -ENOMEM;
	386	goto cleanup;
	387	}
	388
	389	/* build the list of DRM supported formats based on the map */
6211b486 BS	390	for (n = 0, j = 0; j < map->n_pixel_formats; j++) {
	391	if ((map->pixel_formats[j].layer & id) == id)
	392	formats[n++] = map->pixel_formats[j].format;
ad49f860 LD	393	}
	394
	395	plane_type = (i == 0) ? DRM_PLANE_TYPE_PRIMARY :
	396	DRM_PLANE_TYPE_OVERLAY;
	397	ret = drm_universal_plane_init(drm, &plane->base, crtcs,
	398	&malidp_de_plane_funcs, formats,
e6fc3b68	399	n, NULL, plane_type, NULL);
ad49f860 LD	400	if (ret < 0)
	401	goto cleanup;
	402
ad49f860 LD	403	drm_plane_helper_add(&plane->base,
	404	&malidp_de_plane_helper_funcs);
	405	plane->hwdev = malidp->dev;
	406	plane->layer = &map->layers[i];
15807780	407
d1479f61 MA	408	if (id == DE_SMART) {
	409	/*
	410	* Enable the first rectangle in the SMART layer to be
	411	* able to use it as a drm plane.
	412	*/
	413	malidp_hw_write(malidp->dev, 1,
	414	plane->layer->base + MALIDP550_LS_ENABLE);
	415	/* Skip the features which the SMART layer doesn't have. */
15807780	416	continue;
d1479f61	417	}
15807780	418
c2c446ad	419	drm_plane_create_rotation_property(&plane->base, DRM_MODE_ROTATE_0, flags);
c57eb710 BS	420	malidp_hw_write(malidp->dev, MALIDP_ALPHA_LUT,
c57eb710 BS	421	plane->layer->base + MALIDP_LAYER_COMPOSE);
ad49f860 LD	422	}
	423
	424	kfree(formats);
	425
	426	return 0;
	427
	428	cleanup:
	429	malidp_de_planes_destroy(drm);
	430	kfree(formats);
	431
	432	return ret;
	433	}
	434
	435	void malidp_de_planes_destroy(struct drm_device *drm)
	436	{
	437	struct drm_plane p, pt;
	438
	439	list_for_each_entry_safe(p, pt, &drm->mode_config.plane_list, head) {
	440	drm_plane_cleanup(p);
	441	kfree(p);
	442	}
	443	}