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96f60e37 RK |
1 | /* |
2 | * Copyright (C) 2012 Russell King | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * Armada 510 (aka Dove) variant support | |
9 | */ | |
10 | #include <linux/clk.h> | |
11 | #include <linux/io.h> | |
12 | #include <drm/drmP.h> | |
13 | #include <drm/drm_crtc_helper.h> | |
14 | #include "armada_crtc.h" | |
15 | #include "armada_drm.h" | |
16 | #include "armada_hw.h" | |
17 | ||
18 | static int armada510_init(struct armada_private *priv, struct device *dev) | |
19 | { | |
20 | priv->extclk[0] = devm_clk_get(dev, "ext_ref_clk_1"); | |
21 | ||
22 | if (IS_ERR(priv->extclk[0]) && PTR_ERR(priv->extclk[0]) == -ENOENT) | |
23 | priv->extclk[0] = ERR_PTR(-EPROBE_DEFER); | |
24 | ||
25 | return PTR_RET(priv->extclk[0]); | |
26 | } | |
27 | ||
28 | static int armada510_crtc_init(struct armada_crtc *dcrtc) | |
29 | { | |
30 | /* Lower the watermark so to eliminate jitter at higher bandwidths */ | |
31 | armada_updatel(0x20, (1 << 11) | 0xff, dcrtc->base + LCD_CFG_RDREG4F); | |
32 | return 0; | |
33 | } | |
34 | ||
35 | /* | |
36 | * Armada510 specific SCLK register selection. | |
37 | * This gets called with sclk = NULL to test whether the mode is | |
38 | * supportable, and again with sclk != NULL to set the clocks up for | |
39 | * that. The former can return an error, but the latter is expected | |
40 | * not to. | |
41 | * | |
42 | * We currently are pretty rudimentary here, always selecting | |
43 | * EXT_REF_CLK_1 for LCD0 and erroring LCD1. This needs improvement! | |
44 | */ | |
45 | static int armada510_crtc_compute_clock(struct armada_crtc *dcrtc, | |
46 | const struct drm_display_mode *mode, uint32_t *sclk) | |
47 | { | |
48 | struct armada_private *priv = dcrtc->crtc.dev->dev_private; | |
49 | struct clk *clk = priv->extclk[0]; | |
50 | int ret; | |
51 | ||
52 | if (dcrtc->num == 1) | |
53 | return -EINVAL; | |
54 | ||
55 | if (IS_ERR(clk)) | |
56 | return PTR_ERR(clk); | |
57 | ||
58 | if (dcrtc->clk != clk) { | |
59 | ret = clk_prepare_enable(clk); | |
60 | if (ret) | |
61 | return ret; | |
62 | dcrtc->clk = clk; | |
63 | } | |
64 | ||
65 | if (sclk) { | |
66 | uint32_t rate, ref, div; | |
67 | ||
68 | rate = mode->clock * 1000; | |
69 | ref = clk_round_rate(clk, rate); | |
70 | div = DIV_ROUND_UP(ref, rate); | |
71 | if (div < 1) | |
72 | div = 1; | |
73 | ||
74 | clk_set_rate(clk, ref); | |
75 | *sclk = div | SCLK_510_EXTCLK1; | |
76 | } | |
77 | ||
78 | return 0; | |
79 | } | |
80 | ||
81 | const struct armada_variant armada510_ops = { | |
82 | .has_spu_adv_reg = true, | |
662af0d8 | 83 | .spu_adv_reg = ADV_HWC32ENABLE | ADV_HWC32ARGB | ADV_HWC32BLEND, |
96f60e37 RK |
84 | .init = armada510_init, |
85 | .crtc_init = armada510_crtc_init, | |
86 | .crtc_compute_clock = armada510_crtc_compute_clock, | |
87 | }; |