[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / armada / armada_510.c

/*
 * Copyright (C) 2012 Russell King
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Armada 510 (aka Dove) variant support
 */
#include <linux/clk.h>
#include <linux/io.h>
#include <drm/drm_crtc_helper.h>
#include "armada_crtc.h"
#include "armada_drm.h"
#include "armada_hw.h"

static int armada510_crtc_init(struct armada_crtc *dcrtc, struct device *dev)
{
	struct clk *clk;

	clk = devm_clk_get(dev, "ext_ref_clk1");
	if (IS_ERR(clk))
		return PTR_ERR(clk) == -ENOENT ? -EPROBE_DEFER : PTR_ERR(clk);

	dcrtc->extclk[0] = clk;

	/* Lower the watermark so to eliminate jitter at higher bandwidths */
	armada_updatel(0x20, (1 << 11) | 0xff, dcrtc->base + LCD_CFG_RDREG4F);

	/* Initialise SPU register */
	writel_relaxed(ADV_HWC32ENABLE | ADV_HWC32ARGB | ADV_HWC32BLEND,
		       dcrtc->base + LCD_SPU_ADV_REG);

	return 0;
}

/*
 * Armada510 specific SCLK register selection.
 * This gets called with sclk = NULL to test whether the mode is
 * supportable, and again with sclk != NULL to set the clocks up for
 * that.  The former can return an error, but the latter is expected
 * not to.
 *
 * We currently are pretty rudimentary here, always selecting
 * EXT_REF_CLK_1 for LCD0 and erroring LCD1.  This needs improvement!
 */
static int armada510_crtc_compute_clock(struct armada_crtc *dcrtc,
	const struct drm_display_mode *mode, uint32_t *sclk)
{
	struct clk *clk = dcrtc->extclk[0];
	int ret;

	if (dcrtc->num == 1)
		return -EINVAL;

	if (IS_ERR(clk))
		return PTR_ERR(clk);

	if (dcrtc->clk != clk) {
		ret = clk_prepare_enable(clk);
		if (ret)
			return ret;
		dcrtc->clk = clk;
	}

	if (sclk) {
		uint32_t rate, ref, div;

		rate = mode->clock * 1000;
		ref = clk_round_rate(clk, rate);
		div = DIV_ROUND_UP(ref, rate);
		if (div < 1)
			div = 1;

		clk_set_rate(clk, ref);
		*sclk = div | SCLK_510_EXTCLK1;
	}

	return 0;
}

const struct armada_variant armada510_ops = {
	.has_spu_adv_reg = true,
	.init = armada510_crtc_init,
	.compute_clock = armada510_crtc_compute_clock,
};
Commit	Line	Data
96f60e37 RK	1	/*
	2	* Copyright (C) 2012 Russell King
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* Armada 510 (aka Dove) variant support
	9	*/
	10	#include <linux/clk.h>
	11	#include <linux/io.h>
96f60e37 RK	12	#include <drm/drm_crtc_helper.h>
	13	#include "armada_crtc.h"
	14	#include "armada_drm.h"
	15	#include "armada_hw.h"
	16
3ecea269	17	static int armada510_crtc_init(struct armada_crtc dcrtc, struct device dev)
96f60e37	18	{
3ecea269	19	struct clk *clk;
96f60e37	20
fe424872	21	clk = devm_clk_get(dev, "ext_ref_clk1");
3ecea269 RK	22	if (IS_ERR(clk))
3ecea269 RK	23	return PTR_ERR(clk) == -ENOENT ? -EPROBE_DEFER : PTR_ERR(clk);
96f60e37	24
3ecea269	25	dcrtc->extclk[0] = clk;
96f60e37	26
96f60e37 RK	27	/* Lower the watermark so to eliminate jitter at higher bandwidths */
96f60e37 RK	28	armada_updatel(0x20, (1 << 11) \| 0xff, dcrtc->base + LCD_CFG_RDREG4F);
3ecea269	29
4e4b3563 RK	30	/* Initialise SPU register */
	31	writel_relaxed(ADV_HWC32ENABLE \| ADV_HWC32ARGB \| ADV_HWC32BLEND,
	32	dcrtc->base + LCD_SPU_ADV_REG);
	33
96f60e37 RK	34	return 0;
	35	}
	36
	37	/*
	38	* Armada510 specific SCLK register selection.
	39	* This gets called with sclk = NULL to test whether the mode is
	40	* supportable, and again with sclk != NULL to set the clocks up for
	41	* that. The former can return an error, but the latter is expected
	42	* not to.
	43	*
	44	* We currently are pretty rudimentary here, always selecting
	45	* EXT_REF_CLK_1 for LCD0 and erroring LCD1. This needs improvement!
	46	*/
	47	static int armada510_crtc_compute_clock(struct armada_crtc *dcrtc,
	48	const struct drm_display_mode mode, uint32_t sclk)
	49	{
3ecea269	50	struct clk *clk = dcrtc->extclk[0];
96f60e37 RK	51	int ret;
	52
	53	if (dcrtc->num == 1)
	54	return -EINVAL;
	55
	56	if (IS_ERR(clk))
	57	return PTR_ERR(clk);
	58
	59	if (dcrtc->clk != clk) {
	60	ret = clk_prepare_enable(clk);
	61	if (ret)
	62	return ret;
	63	dcrtc->clk = clk;
	64	}
	65
	66	if (sclk) {
	67	uint32_t rate, ref, div;
	68
	69	rate = mode->clock * 1000;
	70	ref = clk_round_rate(clk, rate);
	71	div = DIV_ROUND_UP(ref, rate);
	72	if (div < 1)
	73	div = 1;
	74
	75	clk_set_rate(clk, ref);
	76	*sclk = div \| SCLK_510_EXTCLK1;
	77	}
	78
	79	return 0;
	80	}
	81
	82	const struct armada_variant armada510_ops = {
	83	.has_spu_adv_reg = true,
42e62ba7 RK	84	.init = armada510_crtc_init,
42e62ba7 RK	85	.compute_clock = armada510_crtc_compute_clock,
96f60e37	86	};