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drm: Move drm_crtc_init from drm_crtc.h to drm_plane_helper.h
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / armada / armada_crtc.c
CommitLineData
96f60e37
RK		 1/*
2 * Copyright (C) 2012 Russell King
3 * Rewritten from the dovefb driver, and Armada510 manuals.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9#include <linux/clk.h>
d8c96083
RK		 10#include <linux/component.h>
11#include <linux/of_device.h>
12#include <linux/platform_device.h>
96f60e37
RK		 13#include <drm/drmP.h>
14#include <drm/drm_crtc_helper.h>
3cb9ae4f 15#include <drm/drm_plane_helper.h>
96f60e37
RK		 16#include "armada_crtc.h"
17#include "armada_drm.h"
18#include "armada_fb.h"
19#include "armada_gem.h"
20#include "armada_hw.h"
21
22struct armada_frame_work {
23 struct drm_pending_vblank_event *event;
24 struct armada_regs regs[4];
25 struct drm_framebuffer *old_fb;
26};
27
28enum csc_mode {
29 CSC_AUTO = 0,
30 CSC_YUV_CCIR601 = 1,
31 CSC_YUV_CCIR709 = 2,
32 CSC_RGB_COMPUTER = 1,
33 CSC_RGB_STUDIO = 2,
34};
35
36/*
37 * A note about interlacing. Let's consider HDMI 1920x1080i.
38 * The timing parameters we have from X are:
39 * Hact HsyA HsyI Htot Vact VsyA VsyI Vtot
40 * 1920 2448 2492 2640 1080 1084 1094 1125
41 * Which get translated to:
42 * Hact HsyA HsyI Htot Vact VsyA VsyI Vtot
43 * 1920 2448 2492 2640 540 542 547 562
44 *
45 * This is how it is defined by CEA-861-D - line and pixel numbers are
46 * referenced to the rising edge of VSYNC and HSYNC. Total clocks per
47 * line: 2640. The odd frame, the first active line is at line 21, and
48 * the even frame, the first active line is 584.
49 *
50 * LN: 560 561 562 563 567 568 569
51 * DE: ~~~|____________________________//__________________________
52 * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
53 * VSYNC: _________________________|~~~~~~//~~~~~~~~~~~~~~~|__________
54 * 22 blanking lines. VSYNC at 1320 (referenced to the HSYNC rising edge).
55 *
56 * LN: 1123 1124 1125 1 5 6 7
57 * DE: ~~~|____________________________//__________________________
58 * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
59 * VSYNC: ____________________|~~~~~~~~~~~//~~~~~~~~~~|_______________
60 * 23 blanking lines
61 *
62 * The Armada LCD Controller line and pixel numbers are, like X timings,
63 * referenced to the top left of the active frame.
64 *
65 * So, translating these to our LCD controller:
66 * Odd frame, 563 total lines, VSYNC at line 543-548, pixel 1128.
67 * Even frame, 562 total lines, VSYNC at line 542-547, pixel 2448.
68 * Note: Vsync front porch remains constant!
69 *
70 * if (odd_frame) {
71 * vtotal = mode->crtc_vtotal + 1;
72 * vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay + 1;
73 * vhorizpos = mode->crtc_hsync_start - mode->crtc_htotal / 2
74 * } else {
75 * vtotal = mode->crtc_vtotal;
76 * vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay;
77 * vhorizpos = mode->crtc_hsync_start;
78 * }
79 * vfrontporch = mode->crtc_vtotal - mode->crtc_vsync_end;
80 *
81 * So, we need to reprogram these registers on each vsync event:
82 * LCD_SPU_V_PORCH, LCD_SPU_ADV_REG, LCD_SPUT_V_H_TOTAL
83 *
84 * Note: we do not use the frame done interrupts because these appear
85 * to happen too early, and lead to jitter on the display (presumably
86 * they occur at the end of the last active line, before the vsync back
87 * porch, which we're reprogramming.)
88 */
89
90void
91armada_drm_crtc_update_regs(struct armada_crtc *dcrtc, struct armada_regs *regs)
92{
93 while (regs->offset != ~0) {
94 void __iomem *reg = dcrtc->base + regs->offset;
95 uint32_t val;
96
97 val = regs->mask;
98 if (val != 0)
99 val &= readl_relaxed(reg);
100 writel_relaxed(val | regs->val, reg);
101 ++regs;
102 }
103}
104
105#define dpms_blanked(dpms) ((dpms) != DRM_MODE_DPMS_ON)
106
107static void armada_drm_crtc_update(struct armada_crtc *dcrtc)
108{
109 uint32_t dumb_ctrl;
110
111 dumb_ctrl = dcrtc->cfg_dumb_ctrl;
112
113 if (!dpms_blanked(dcrtc->dpms))
114 dumb_ctrl |= CFG_DUMB_ENA;
115
116 /*
117 * When the dumb interface isn't in DUMB24_RGB888_0 mode, it might
118 * be using SPI or GPIO. If we set this to DUMB_BLANK, we will
119 * force LCD_D[23:0] to output blank color, overriding the GPIO or
120 * SPI usage. So leave it as-is unless in DUMB24_RGB888_0 mode.
121 */
122 if (dpms_blanked(dcrtc->dpms) &&
123 (dumb_ctrl & DUMB_MASK) == DUMB24_RGB888_0) {
124 dumb_ctrl &= ~DUMB_MASK;
125 dumb_ctrl |= DUMB_BLANK;
126 }
127
128 /*
129 * The documentation doesn't indicate what the normal state of
130 * the sync signals are. Sebastian Hesselbart kindly probed
131 * these signals on his board to determine their state.
132 *
133 * The non-inverted state of the sync signals is active high.
134 * Setting these bits makes the appropriate signal active low.
135 */
136 if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NCSYNC)
137 dumb_ctrl |= CFG_INV_CSYNC;
138 if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NHSYNC)
139 dumb_ctrl |= CFG_INV_HSYNC;
140 if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NVSYNC)
141 dumb_ctrl |= CFG_INV_VSYNC;
142
143 if (dcrtc->dumb_ctrl != dumb_ctrl) {
144 dcrtc->dumb_ctrl = dumb_ctrl;
145 writel_relaxed(dumb_ctrl, dcrtc->base + LCD_SPU_DUMB_CTRL);
146 }
147}
148
149static unsigned armada_drm_crtc_calc_fb(struct drm_framebuffer *fb,
150 int x, int y, struct armada_regs *regs, bool interlaced)
151{
152 struct armada_gem_object *obj = drm_fb_obj(fb);
153 unsigned pitch = fb->pitches[0];
154 unsigned offset = y * pitch + x * fb->bits_per_pixel / 8;
155 uint32_t addr_odd, addr_even;
156 unsigned i = 0;
157
158 DRM_DEBUG_DRIVER("pitch %u x %d y %d bpp %d\n",
159 pitch, x, y, fb->bits_per_pixel);
160
161 addr_odd = addr_even = obj->dev_addr + offset;
162
163 if (interlaced) {
164 addr_even += pitch;
165 pitch *= 2;
166 }
167
168 /* write offset, base, and pitch */
169 armada_reg_queue_set(regs, i, addr_odd, LCD_CFG_GRA_START_ADDR0);
170 armada_reg_queue_set(regs, i, addr_even, LCD_CFG_GRA_START_ADDR1);
171 armada_reg_queue_mod(regs, i, pitch, 0xffff, LCD_CFG_GRA_PITCH);
172
173 return i;
174}
175
176static int armada_drm_crtc_queue_frame_work(struct armada_crtc *dcrtc,
177 struct armada_frame_work *work)
178{
179 struct drm_device *dev = dcrtc->crtc.dev;
180 unsigned long flags;
181 int ret;
182
183 ret = drm_vblank_get(dev, dcrtc->num);
184 if (ret) {
185 DRM_ERROR("failed to acquire vblank counter\n");
186 return ret;
187 }
188
189 spin_lock_irqsave(&dev->event_lock, flags);
190 if (!dcrtc->frame_work)
191 dcrtc->frame_work = work;
192 else
193 ret = -EBUSY;
194 spin_unlock_irqrestore(&dev->event_lock, flags);
195
196 if (ret)
197 drm_vblank_put(dev, dcrtc->num);
198
199 return ret;
200}
201
202static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc)
203{
204 struct drm_device *dev = dcrtc->crtc.dev;
205 struct armada_frame_work *work = dcrtc->frame_work;
206
207 dcrtc->frame_work = NULL;
208
209 armada_drm_crtc_update_regs(dcrtc, work->regs);
210
211 if (work->event)
212 drm_send_vblank_event(dev, dcrtc->num, work->event);
213
214 drm_vblank_put(dev, dcrtc->num);
215
216 /* Finally, queue the process-half of the cleanup. */
217 __armada_drm_queue_unref_work(dcrtc->crtc.dev, work->old_fb);
218 kfree(work);
219}
220
221static void armada_drm_crtc_finish_fb(struct armada_crtc *dcrtc,
222 struct drm_framebuffer *fb, bool force)
223{
224 struct armada_frame_work *work;
225
226 if (!fb)
227 return;
228
229 if (force) {
230 /* Display is disabled, so just drop the old fb */
231 drm_framebuffer_unreference(fb);
232 return;
233 }
234
235 work = kmalloc(sizeof(*work), GFP_KERNEL);
236 if (work) {
237 int i = 0;
238 work->event = NULL;
239 work->old_fb = fb;
240 armada_reg_queue_end(work->regs, i);
241
242 if (armada_drm_crtc_queue_frame_work(dcrtc, work) == 0)
243 return;
244
245 kfree(work);
246 }
247
248 /*
249 * Oops - just drop the reference immediately and hope for
250 * the best. The worst that will happen is the buffer gets
251 * reused before it has finished being displayed.
252 */
253 drm_framebuffer_unreference(fb);
254}
255
256static void armada_drm_vblank_off(struct armada_crtc *dcrtc)
257{
258 struct drm_device *dev = dcrtc->crtc.dev;
259
260 /*
261 * Tell the DRM core that vblank IRQs aren't going to happen for
262 * a while. This cleans up any pending vblank events for us.
263 */
264 drm_vblank_off(dev, dcrtc->num);
265
266 /* Handle any pending flip event. */
267 spin_lock_irq(&dev->event_lock);
268 if (dcrtc->frame_work)
269 armada_drm_crtc_complete_frame_work(dcrtc);
270 spin_unlock_irq(&dev->event_lock);
271}
272
273void armada_drm_crtc_gamma_set(struct drm_crtc *crtc, u16 r, u16 g, u16 b,
274 int idx)
275{
276}
277
278void armada_drm_crtc_gamma_get(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
279 int idx)
280{
281}
282
283/* The mode_config.mutex will be held for this call */
284static void armada_drm_crtc_dpms(struct drm_crtc *crtc, int dpms)
285{
286 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
287
288 if (dcrtc->dpms != dpms) {
289 dcrtc->dpms = dpms;
290 armada_drm_crtc_update(dcrtc);
291 if (dpms_blanked(dpms))
292 armada_drm_vblank_off(dcrtc);
293 }
294}
295
296/*
297 * Prepare for a mode set. Turn off overlay to ensure that we don't end
298 * up with the overlay size being bigger than the active screen size.
299 * We rely upon X refreshing this state after the mode set has completed.
300 *
301 * The mode_config.mutex will be held for this call
302 */
303static void armada_drm_crtc_prepare(struct drm_crtc *crtc)
304{
305 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
306 struct drm_plane *plane;
307
308 /*
309 * If we have an overlay plane associated with this CRTC, disable
310 * it before the modeset to avoid its coordinates being outside
311 * the new mode parameters. DRM doesn't provide help with this.
312 */
313 plane = dcrtc->plane;
314 if (plane) {
315 struct drm_framebuffer *fb = plane->fb;
316
317 plane->funcs->disable_plane(plane);
318 plane->fb = NULL;
319 plane->crtc = NULL;
320 drm_framebuffer_unreference(fb);
321 }
322}
323
324/* The mode_config.mutex will be held for this call */
325static void armada_drm_crtc_commit(struct drm_crtc *crtc)
326{
327 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
328
329 if (dcrtc->dpms != DRM_MODE_DPMS_ON) {
330 dcrtc->dpms = DRM_MODE_DPMS_ON;
331 armada_drm_crtc_update(dcrtc);
332 }
333}
334
335/* The mode_config.mutex will be held for this call */
336static bool armada_drm_crtc_mode_fixup(struct drm_crtc *crtc,
337 const struct drm_display_mode *mode, struct drm_display_mode *adj)
338{
96f60e37
RK		 339 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
340 int ret;
341
342 /* We can't do interlaced modes if we don't have the SPU_ADV_REG */
42e62ba7 343 if (!dcrtc->variant->has_spu_adv_reg &&
96f60e37
RK		 344 adj->flags & DRM_MODE_FLAG_INTERLACE)
345 return false;
346
347 /* Check whether the display mode is possible */
42e62ba7 348 ret = dcrtc->variant->compute_clock(dcrtc, adj, NULL);
96f60e37
RK		 349 if (ret)
350 return false;
351
352 return true;
353}
354
e5d9ddfb 355static void armada_drm_crtc_irq(struct armada_crtc *dcrtc, u32 stat)
96f60e37
RK		 356{
357 struct armada_vbl_event *e, *n;
358 void __iomem *base = dcrtc->base;
359
360 if (stat & DMA_FF_UNDERFLOW)
361 DRM_ERROR("video underflow on crtc %u\n", dcrtc->num);
362 if (stat & GRA_FF_UNDERFLOW)
363 DRM_ERROR("graphics underflow on crtc %u\n", dcrtc->num);
364
365 if (stat & VSYNC_IRQ)
366 drm_handle_vblank(dcrtc->crtc.dev, dcrtc->num);
367
368 spin_lock(&dcrtc->irq_lock);
369
370 list_for_each_entry_safe(e, n, &dcrtc->vbl_list, node) {
371 list_del_init(&e->node);
372 drm_vblank_put(dcrtc->crtc.dev, dcrtc->num);
373 e->fn(dcrtc, e->data);
374 }
375
376 if (stat & GRA_FRAME_IRQ && dcrtc->interlaced) {
377 int i = stat & GRA_FRAME_IRQ0 ? 0 : 1;
378 uint32_t val;
379
380 writel_relaxed(dcrtc->v[i].spu_v_porch, base + LCD_SPU_V_PORCH);
381 writel_relaxed(dcrtc->v[i].spu_v_h_total,
382 base + LCD_SPUT_V_H_TOTAL);
383
384 val = readl_relaxed(base + LCD_SPU_ADV_REG);
385 val &= ~(ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF | ADV_VSYNCOFFEN);
386 val |= dcrtc->v[i].spu_adv_reg;
662af0d8 387 writel_relaxed(val, base + LCD_SPU_ADV_REG);
96f60e37 388 }
662af0d8
RK		 389
390 if (stat & DUMB_FRAMEDONE && dcrtc->cursor_update) {
391 writel_relaxed(dcrtc->cursor_hw_pos,
392 base + LCD_SPU_HWC_OVSA_HPXL_VLN);
393 writel_relaxed(dcrtc->cursor_hw_sz,
394 base + LCD_SPU_HWC_HPXL_VLN);
395 armada_updatel(CFG_HWC_ENA,
396 CFG_HWC_ENA | CFG_HWC_1BITMOD | CFG_HWC_1BITENA,
397 base + LCD_SPU_DMA_CTRL0);
398 dcrtc->cursor_update = false;
399 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
400 }
401
96f60e37
RK		 402 spin_unlock(&dcrtc->irq_lock);
403
404 if (stat & GRA_FRAME_IRQ) {
405 struct drm_device *dev = dcrtc->crtc.dev;
406
407 spin_lock(&dev->event_lock);
408 if (dcrtc->frame_work)
409 armada_drm_crtc_complete_frame_work(dcrtc);
410 spin_unlock(&dev->event_lock);
411
412 wake_up(&dcrtc->frame_wait);
413 }
414}
415
e5d9ddfb
RK		 416static irqreturn_t armada_drm_irq(int irq, void *arg)
417{
418 struct armada_crtc *dcrtc = arg;
419 u32 v, stat = readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR);
420
421 /*
422 * This is rediculous - rather than writing bits to clear, we
423 * have to set the actual status register value. This is racy.
424 */
425 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
426
427 /* Mask out those interrupts we haven't enabled */
428 v = stat & dcrtc->irq_ena;
429
430 if (v & (VSYNC_IRQ|GRA_FRAME_IRQ|DUMB_FRAMEDONE)) {
431 armada_drm_crtc_irq(dcrtc, stat);
432 return IRQ_HANDLED;
433 }
434 return IRQ_NONE;
435}
436
96f60e37
RK		 437/* These are locked by dev->vbl_lock */
438void armada_drm_crtc_disable_irq(struct armada_crtc *dcrtc, u32 mask)
439{
440 if (dcrtc->irq_ena & mask) {
441 dcrtc->irq_ena &= ~mask;
442 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
443 }
444}
445
446void armada_drm_crtc_enable_irq(struct armada_crtc *dcrtc, u32 mask)
447{
448 if ((dcrtc->irq_ena & mask) != mask) {
449 dcrtc->irq_ena |= mask;
450 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
451 if (readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR) & mask)
452 writel(0, dcrtc->base + LCD_SPU_IRQ_ISR);
453 }
454}
455
456static uint32_t armada_drm_crtc_calculate_csc(struct armada_crtc *dcrtc)
457{
458 struct drm_display_mode *adj = &dcrtc->crtc.mode;
459 uint32_t val = 0;
460
461 if (dcrtc->csc_yuv_mode == CSC_YUV_CCIR709)
462 val |= CFG_CSC_YUV_CCIR709;
463 if (dcrtc->csc_rgb_mode == CSC_RGB_STUDIO)
464 val |= CFG_CSC_RGB_STUDIO;
465
466 /*
467 * In auto mode, set the colorimetry, based upon the HDMI spec.
468 * 1280x720p, 1920x1080p and 1920x1080i use ITU709, others use
469 * ITU601. It may be more appropriate to set this depending on
470 * the source - but what if the graphic frame is YUV and the
471 * video frame is RGB?
472 */
473 if ((adj->hdisplay == 1280 && adj->vdisplay == 720 &&
474 !(adj->flags & DRM_MODE_FLAG_INTERLACE)) ||
475 (adj->hdisplay == 1920 && adj->vdisplay == 1080)) {
476 if (dcrtc->csc_yuv_mode == CSC_AUTO)
477 val |= CFG_CSC_YUV_CCIR709;
478 }
479
480 /*
481 * We assume we're connected to a TV-like device, so the YUV->RGB
482 * conversion should produce a limited range. We should set this
483 * depending on the connectors attached to this CRTC, and what
484 * kind of device they report being connected.
485 */
486 if (dcrtc->csc_rgb_mode == CSC_AUTO)
487 val |= CFG_CSC_RGB_STUDIO;
488
489 return val;
490}
491
492/* The mode_config.mutex will be held for this call */
493static int armada_drm_crtc_mode_set(struct drm_crtc *crtc,
494 struct drm_display_mode *mode, struct drm_display_mode *adj,
495 int x, int y, struct drm_framebuffer *old_fb)
496{
96f60e37
RK		 497 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
498 struct armada_regs regs[17];
499 uint32_t lm, rm, tm, bm, val, sclk;
500 unsigned long flags;
501 unsigned i;
502 bool interlaced;
503
f4510a27 504 drm_framebuffer_reference(crtc->primary->fb);
96f60e37
RK		 505
506 interlaced = !!(adj->flags & DRM_MODE_FLAG_INTERLACE);
507
f4510a27
MR		 508 i = armada_drm_crtc_calc_fb(dcrtc->crtc.primary->fb,
509 x, y, regs, interlaced);
96f60e37
RK		 510
511 rm = adj->crtc_hsync_start - adj->crtc_hdisplay;
512 lm = adj->crtc_htotal - adj->crtc_hsync_end;
513 bm = adj->crtc_vsync_start - adj->crtc_vdisplay;
514 tm = adj->crtc_vtotal - adj->crtc_vsync_end;
515
516 DRM_DEBUG_DRIVER("H: %d %d %d %d lm %d rm %d\n",
517 adj->crtc_hdisplay,
518 adj->crtc_hsync_start,
519 adj->crtc_hsync_end,
520 adj->crtc_htotal, lm, rm);
521 DRM_DEBUG_DRIVER("V: %d %d %d %d tm %d bm %d\n",
522 adj->crtc_vdisplay,
523 adj->crtc_vsync_start,
524 adj->crtc_vsync_end,
525 adj->crtc_vtotal, tm, bm);
526
527 /* Wait for pending flips to complete */
528 wait_event(dcrtc->frame_wait, !dcrtc->frame_work);
529
530 drm_vblank_pre_modeset(crtc->dev, dcrtc->num);
531
532 crtc->mode = *adj;
533
534 val = dcrtc->dumb_ctrl & ~CFG_DUMB_ENA;
535 if (val != dcrtc->dumb_ctrl) {
536 dcrtc->dumb_ctrl = val;
537 writel_relaxed(val, dcrtc->base + LCD_SPU_DUMB_CTRL);
538 }
539
540 /* Now compute the divider for real */
42e62ba7 541 dcrtc->variant->compute_clock(dcrtc, adj, &sclk);
96f60e37
RK		 542
543 /* Ensure graphic fifo is enabled */
544 armada_reg_queue_mod(regs, i, 0, CFG_PDWN64x66, LCD_SPU_SRAM_PARA1);
545 armada_reg_queue_set(regs, i, sclk, LCD_CFG_SCLK_DIV);
546
547 if (interlaced ^ dcrtc->interlaced) {
548 if (adj->flags & DRM_MODE_FLAG_INTERLACE)
549 drm_vblank_get(dcrtc->crtc.dev, dcrtc->num);
550 else
551 drm_vblank_put(dcrtc->crtc.dev, dcrtc->num);
552 dcrtc->interlaced = interlaced;
553 }
554
555 spin_lock_irqsave(&dcrtc->irq_lock, flags);
556
557 /* Even interlaced/progressive frame */
558 dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 |
559 adj->crtc_htotal;
560 dcrtc->v[1].spu_v_porch = tm << 16 | bm;
561 val = adj->crtc_hsync_start;
662af0d8 562 dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
42e62ba7 563 dcrtc->variant->spu_adv_reg;
96f60e37
RK		 564
565 if (interlaced) {
566 /* Odd interlaced frame */
567 dcrtc->v[0].spu_v_h_total = dcrtc->v[1].spu_v_h_total +
568 (1 << 16);
569 dcrtc->v[0].spu_v_porch = dcrtc->v[1].spu_v_porch + 1;
570 val = adj->crtc_hsync_start - adj->crtc_htotal / 2;
662af0d8 571 dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
42e62ba7 572 dcrtc->variant->spu_adv_reg;
96f60e37
RK		 573 } else {
574 dcrtc->v[0] = dcrtc->v[1];
575 }
576
577 val = adj->crtc_vdisplay << 16 | adj->crtc_hdisplay;
578
579 armada_reg_queue_set(regs, i, val, LCD_SPU_V_H_ACTIVE);
580 armada_reg_queue_set(regs, i, val, LCD_SPU_GRA_HPXL_VLN);
581 armada_reg_queue_set(regs, i, val, LCD_SPU_GZM_HPXL_VLN);
582 armada_reg_queue_set(regs, i, (lm << 16) | rm, LCD_SPU_H_PORCH);
583 armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH);
584 armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total,
585 LCD_SPUT_V_H_TOTAL);
586
42e62ba7 587 if (dcrtc->variant->has_spu_adv_reg) {
96f60e37
RK		 588 armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg,
589 ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF |
590 ADV_VSYNCOFFEN, LCD_SPU_ADV_REG);
662af0d8 591 }
96f60e37
RK		 592
593 val = CFG_GRA_ENA | CFG_GRA_HSMOOTH;
f4510a27
MR		 594 val |= CFG_GRA_FMT(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt);
595 val |= CFG_GRA_MOD(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->mod);
96f60e37 596
f4510a27 597 if (drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt > CFG_420)
96f60e37
RK		 598 val |= CFG_PALETTE_ENA;
599
600 if (interlaced)
601 val |= CFG_GRA_FTOGGLE;
602
603 armada_reg_queue_mod(regs, i, val, CFG_GRAFORMAT |
604 CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV |
605 CFG_SWAPYU | CFG_YUV2RGB) |
606 CFG_PALETTE_ENA | CFG_GRA_FTOGGLE,
607 LCD_SPU_DMA_CTRL0);
608
609 val = adj->flags & DRM_MODE_FLAG_NVSYNC ? CFG_VSYNC_INV : 0;
610 armada_reg_queue_mod(regs, i, val, CFG_VSYNC_INV, LCD_SPU_DMA_CTRL1);
611
612 val = dcrtc->spu_iopad_ctrl | armada_drm_crtc_calculate_csc(dcrtc);
613 armada_reg_queue_set(regs, i, val, LCD_SPU_IOPAD_CONTROL);
614 armada_reg_queue_end(regs, i);
615
616 armada_drm_crtc_update_regs(dcrtc, regs);
617 spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
618
619 armada_drm_crtc_update(dcrtc);
620
621 drm_vblank_post_modeset(crtc->dev, dcrtc->num);
622 armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms));
623
624 return 0;
625}
626
627/* The mode_config.mutex will be held for this call */
628static int armada_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
629 struct drm_framebuffer *old_fb)
630{
631 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
632 struct armada_regs regs[4];
633 unsigned i;
634
f4510a27 635 i = armada_drm_crtc_calc_fb(crtc->primary->fb, crtc->x, crtc->y, regs,
96f60e37
RK		 636 dcrtc->interlaced);
637 armada_reg_queue_end(regs, i);
638
639 /* Wait for pending flips to complete */
640 wait_event(dcrtc->frame_wait, !dcrtc->frame_work);
641
642 /* Take a reference to the new fb as we're using it */
f4510a27 643 drm_framebuffer_reference(crtc->primary->fb);
96f60e37
RK		 644
645 /* Update the base in the CRTC */
646 armada_drm_crtc_update_regs(dcrtc, regs);
647
648 /* Drop our previously held reference */
649 armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms));
650
651 return 0;
652}
653
654static void armada_drm_crtc_load_lut(struct drm_crtc *crtc)
655{
656}
657
658/* The mode_config.mutex will be held for this call */
659static void armada_drm_crtc_disable(struct drm_crtc *crtc)
660{
661 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
662
663 armada_drm_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
f4510a27 664 armada_drm_crtc_finish_fb(dcrtc, crtc->primary->fb, true);
96f60e37
RK		 665
666 /* Power down most RAMs and FIFOs */
667 writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
668 CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 |
669 CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1);
670}
671
672static const struct drm_crtc_helper_funcs armada_crtc_helper_funcs = {
673 .dpms = armada_drm_crtc_dpms,
674 .prepare = armada_drm_crtc_prepare,
675 .commit = armada_drm_crtc_commit,
676 .mode_fixup = armada_drm_crtc_mode_fixup,
677 .mode_set = armada_drm_crtc_mode_set,
678 .mode_set_base = armada_drm_crtc_mode_set_base,
679 .load_lut = armada_drm_crtc_load_lut,
680 .disable = armada_drm_crtc_disable,
681};
682
662af0d8
RK		 683static void armada_load_cursor_argb(void __iomem *base, uint32_t *pix,
684 unsigned stride, unsigned width, unsigned height)
685{
686 uint32_t addr;
687 unsigned y;
688
689 addr = SRAM_HWC32_RAM1;
690 for (y = 0; y < height; y++) {
691 uint32_t *p = &pix[y * stride];
692 unsigned x;
693
694 for (x = 0; x < width; x++, p++) {
695 uint32_t val = *p;
696
697 val = (val & 0xff00ff00) |
698 (val & 0x000000ff) << 16 |
699 (val & 0x00ff0000) >> 16;
700
701 writel_relaxed(val,
702 base + LCD_SPU_SRAM_WRDAT);
703 writel_relaxed(addr | SRAM_WRITE,
704 base + LCD_SPU_SRAM_CTRL);
c39b0695 705 readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN);
662af0d8
RK		 706 addr += 1;
707 if ((addr & 0x00ff) == 0)
708 addr += 0xf00;
709 if ((addr & 0x30ff) == 0)
710 addr = SRAM_HWC32_RAM2;
711 }
712 }
713}
714
715static void armada_drm_crtc_cursor_tran(void __iomem *base)
716{
717 unsigned addr;
718
719 for (addr = 0; addr < 256; addr++) {
720 /* write the default value */
721 writel_relaxed(0x55555555, base + LCD_SPU_SRAM_WRDAT);
722 writel_relaxed(addr | SRAM_WRITE | SRAM_HWC32_TRAN,
723 base + LCD_SPU_SRAM_CTRL);
724 }
725}
726
727static int armada_drm_crtc_cursor_update(struct armada_crtc *dcrtc, bool reload)
728{
729 uint32_t xoff, xscr, w = dcrtc->cursor_w, s;
730 uint32_t yoff, yscr, h = dcrtc->cursor_h;
731 uint32_t para1;
732
733 /*
734 * Calculate the visible width and height of the cursor,
735 * screen position, and the position in the cursor bitmap.
736 */
737 if (dcrtc->cursor_x < 0) {
738 xoff = -dcrtc->cursor_x;
739 xscr = 0;
740 w -= min(xoff, w);
741 } else if (dcrtc->cursor_x + w > dcrtc->crtc.mode.hdisplay) {
742 xoff = 0;
743 xscr = dcrtc->cursor_x;
744 w = max_t(int, dcrtc->crtc.mode.hdisplay - dcrtc->cursor_x, 0);
745 } else {
746 xoff = 0;
747 xscr = dcrtc->cursor_x;
748 }
749
750 if (dcrtc->cursor_y < 0) {
751 yoff = -dcrtc->cursor_y;
752 yscr = 0;
753 h -= min(yoff, h);
754 } else if (dcrtc->cursor_y + h > dcrtc->crtc.mode.vdisplay) {
755 yoff = 0;
756 yscr = dcrtc->cursor_y;
757 h = max_t(int, dcrtc->crtc.mode.vdisplay - dcrtc->cursor_y, 0);
758 } else {
759 yoff = 0;
760 yscr = dcrtc->cursor_y;
761 }
762
763 /* On interlaced modes, the vertical cursor size must be halved */
764 s = dcrtc->cursor_w;
765 if (dcrtc->interlaced) {
766 s *= 2;
767 yscr /= 2;
768 h /= 2;
769 }
770
771 if (!dcrtc->cursor_obj || !h || !w) {
772 spin_lock_irq(&dcrtc->irq_lock);
773 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
774 dcrtc->cursor_update = false;
775 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
776 spin_unlock_irq(&dcrtc->irq_lock);
777 return 0;
778 }
779
780 para1 = readl_relaxed(dcrtc->base + LCD_SPU_SRAM_PARA1);
781 armada_updatel(CFG_CSB_256x32, CFG_CSB_256x32 | CFG_PDWN256x32,
782 dcrtc->base + LCD_SPU_SRAM_PARA1);
783
784 /*
785 * Initialize the transparency if the SRAM was powered down.
786 * We must also reload the cursor data as well.
787 */
788 if (!(para1 & CFG_CSB_256x32)) {
789 armada_drm_crtc_cursor_tran(dcrtc->base);
790 reload = true;
791 }
792
793 if (dcrtc->cursor_hw_sz != (h << 16 | w)) {
794 spin_lock_irq(&dcrtc->irq_lock);
795 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
796 dcrtc->cursor_update = false;
797 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
798 spin_unlock_irq(&dcrtc->irq_lock);
799 reload = true;
800 }
801 if (reload) {
802 struct armada_gem_object *obj = dcrtc->cursor_obj;
803 uint32_t *pix;
804 /* Set the top-left corner of the cursor image */
805 pix = obj->addr;
806 pix += yoff * s + xoff;
807 armada_load_cursor_argb(dcrtc->base, pix, s, w, h);
808 }
809
810 /* Reload the cursor position, size and enable in the IRQ handler */
811 spin_lock_irq(&dcrtc->irq_lock);
812 dcrtc->cursor_hw_pos = yscr << 16 | xscr;
813 dcrtc->cursor_hw_sz = h << 16 | w;
814 dcrtc->cursor_update = true;
815 armada_drm_crtc_enable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
816 spin_unlock_irq(&dcrtc->irq_lock);
817
818 return 0;
819}
820
821static void cursor_update(void *data)
822{
823 armada_drm_crtc_cursor_update(data, true);
824}
825
826static int armada_drm_crtc_cursor_set(struct drm_crtc *crtc,
827 struct drm_file *file, uint32_t handle, uint32_t w, uint32_t h)
828{
829 struct drm_device *dev = crtc->dev;
830 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
662af0d8
RK		 831 struct armada_gem_object *obj = NULL;
832 int ret;
833
834 /* If no cursor support, replicate drm's return value */
42e62ba7 835 if (!dcrtc->variant->has_spu_adv_reg)
662af0d8
RK		 836 return -ENXIO;
837
838 if (handle && w > 0 && h > 0) {
839 /* maximum size is 64x32 or 32x64 */
840 if (w > 64 || h > 64 || (w > 32 && h > 32))
841 return -ENOMEM;
842
843 obj = armada_gem_object_lookup(dev, file, handle);
844 if (!obj)
845 return -ENOENT;
846
847 /* Must be a kernel-mapped object */
848 if (!obj->addr) {
849 drm_gem_object_unreference_unlocked(&obj->obj);
850 return -EINVAL;
851 }
852
853 if (obj->obj.size < w * h * 4) {
854 DRM_ERROR("buffer is too small\n");
855 drm_gem_object_unreference_unlocked(&obj->obj);
856 return -ENOMEM;
857 }
858 }
859
860 mutex_lock(&dev->struct_mutex);
861 if (dcrtc->cursor_obj) {
862 dcrtc->cursor_obj->update = NULL;
863 dcrtc->cursor_obj->update_data = NULL;
864 drm_gem_object_unreference(&dcrtc->cursor_obj->obj);
865 }
866 dcrtc->cursor_obj = obj;
867 dcrtc->cursor_w = w;
868 dcrtc->cursor_h = h;
869 ret = armada_drm_crtc_cursor_update(dcrtc, true);
870 if (obj) {
871 obj->update_data = dcrtc;
872 obj->update = cursor_update;
873 }
874 mutex_unlock(&dev->struct_mutex);
875
876 return ret;
877}
878
879static int armada_drm_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
880{
881 struct drm_device *dev = crtc->dev;
882 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
662af0d8
RK		 883 int ret;
884
885 /* If no cursor support, replicate drm's return value */
42e62ba7 886 if (!dcrtc->variant->has_spu_adv_reg)
662af0d8
RK		 887 return -EFAULT;
888
889 mutex_lock(&dev->struct_mutex);
890 dcrtc->cursor_x = x;
891 dcrtc->cursor_y = y;
892 ret = armada_drm_crtc_cursor_update(dcrtc, false);
893 mutex_unlock(&dev->struct_mutex);
894
895 return ret;
896}
897
96f60e37
RK		 898static void armada_drm_crtc_destroy(struct drm_crtc *crtc)
899{
900 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
901 struct armada_private *priv = crtc->dev->dev_private;
902
662af0d8
RK		 903 if (dcrtc->cursor_obj)
904 drm_gem_object_unreference(&dcrtc->cursor_obj->obj);
905
96f60e37
RK		 906 priv->dcrtc[dcrtc->num] = NULL;
907 drm_crtc_cleanup(&dcrtc->crtc);
908
909 if (!IS_ERR(dcrtc->clk))
910 clk_disable_unprepare(dcrtc->clk);
911
e5d9ddfb
RK		 912 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ENA);
913
9611cb93
RK		 914 of_node_put(dcrtc->crtc.port);
915
96f60e37
RK		 916 kfree(dcrtc);
917}
918
919/*
920 * The mode_config lock is held here, to prevent races between this
921 * and a mode_set.
922 */
923static int armada_drm_crtc_page_flip(struct drm_crtc *crtc,
5e4e3ba9 924 struct drm_framebuffer *fb, struct drm_pending_vblank_event *event, uint32_t page_flip_flags)
96f60e37
RK		 925{
926 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
927 struct armada_frame_work *work;
928 struct drm_device *dev = crtc->dev;
929 unsigned long flags;
930 unsigned i;
931 int ret;
932
933 /* We don't support changing the pixel format */
f4510a27 934 if (fb->pixel_format != crtc->primary->fb->pixel_format)
96f60e37
RK		 935 return -EINVAL;
936
937 work = kmalloc(sizeof(*work), GFP_KERNEL);
938 if (!work)
939 return -ENOMEM;
940
941 work->event = event;
f4510a27 942 work->old_fb = dcrtc->crtc.primary->fb;
96f60e37
RK		 943
944 i = armada_drm_crtc_calc_fb(fb, crtc->x, crtc->y, work->regs,
945 dcrtc->interlaced);
946 armada_reg_queue_end(work->regs, i);
947
948 /*
949 * Hold the old framebuffer for the work - DRM appears to drop our
950 * reference to the old framebuffer in drm_mode_page_flip_ioctl().
951 */
952 drm_framebuffer_reference(work->old_fb);
953
954 ret = armada_drm_crtc_queue_frame_work(dcrtc, work);
955 if (ret) {
956 /*
957 * Undo our reference above; DRM does not drop the reference
958 * to this object on error, so that's okay.
959 */
960 drm_framebuffer_unreference(work->old_fb);
961 kfree(work);
962 return ret;
963 }
964
965 /*
966 * Don't take a reference on the new framebuffer;
967 * drm_mode_page_flip_ioctl() has already grabbed a reference and
968 * will _not_ drop that reference on successful return from this
969 * function. Simply mark this new framebuffer as the current one.
970 */
f4510a27 971 dcrtc->crtc.primary->fb = fb;
96f60e37
RK		 972
973 /*
974 * Finally, if the display is blanked, we won't receive an
975 * interrupt, so complete it now.
976 */
977 if (dpms_blanked(dcrtc->dpms)) {
978 spin_lock_irqsave(&dev->event_lock, flags);
979 if (dcrtc->frame_work)
980 armada_drm_crtc_complete_frame_work(dcrtc);
981 spin_unlock_irqrestore(&dev->event_lock, flags);
982 }
983
984 return 0;
985}
986
987static int
988armada_drm_crtc_set_property(struct drm_crtc *crtc,
989 struct drm_property *property, uint64_t val)
990{
991 struct armada_private *priv = crtc->dev->dev_private;
992 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
993 bool update_csc = false;
994
995 if (property == priv->csc_yuv_prop) {
996 dcrtc->csc_yuv_mode = val;
997 update_csc = true;
998 } else if (property == priv->csc_rgb_prop) {
999 dcrtc->csc_rgb_mode = val;
1000 update_csc = true;
1001 }
1002
1003 if (update_csc) {
1004 uint32_t val;
1005
1006 val = dcrtc->spu_iopad_ctrl |
1007 armada_drm_crtc_calculate_csc(dcrtc);
1008 writel_relaxed(val, dcrtc->base + LCD_SPU_IOPAD_CONTROL);
1009 }
1010
1011 return 0;
1012}
1013
1014static struct drm_crtc_funcs armada_crtc_funcs = {
662af0d8
RK		 1015 .cursor_set = armada_drm_crtc_cursor_set,
1016 .cursor_move = armada_drm_crtc_cursor_move,
96f60e37
RK		 1017 .destroy = armada_drm_crtc_destroy,
1018 .set_config = drm_crtc_helper_set_config,
1019 .page_flip = armada_drm_crtc_page_flip,
1020 .set_property = armada_drm_crtc_set_property,
1021};
1022
1023static struct drm_prop_enum_list armada_drm_csc_yuv_enum_list[] = {
1024 { CSC_AUTO, "Auto" },
1025 { CSC_YUV_CCIR601, "CCIR601" },
1026 { CSC_YUV_CCIR709, "CCIR709" },
1027};
1028
1029static struct drm_prop_enum_list armada_drm_csc_rgb_enum_list[] = {
1030 { CSC_AUTO, "Auto" },
1031 { CSC_RGB_COMPUTER, "Computer system" },
1032 { CSC_RGB_STUDIO, "Studio" },
1033};
1034
1035static int armada_drm_crtc_create_properties(struct drm_device *dev)
1036{
1037 struct armada_private *priv = dev->dev_private;
1038
1039 if (priv->csc_yuv_prop)
1040 return 0;
1041
1042 priv->csc_yuv_prop = drm_property_create_enum(dev, 0,
1043 "CSC_YUV", armada_drm_csc_yuv_enum_list,
1044 ARRAY_SIZE(armada_drm_csc_yuv_enum_list));
1045 priv->csc_rgb_prop = drm_property_create_enum(dev, 0,
1046 "CSC_RGB", armada_drm_csc_rgb_enum_list,
1047 ARRAY_SIZE(armada_drm_csc_rgb_enum_list));
1048
1049 if (!priv->csc_yuv_prop || !priv->csc_rgb_prop)
1050 return -ENOMEM;
1051
1052 return 0;
1053}
1054
d8c96083 1055int armada_drm_crtc_create(struct drm_device *drm, struct device *dev,
9611cb93
RK		 1056 struct resource *res, int irq, const struct armada_variant *variant,
1057 struct device_node *port)
96f60e37 1058{
d8c96083 1059 struct armada_private *priv = drm->dev_private;
96f60e37
RK		 1060 struct armada_crtc *dcrtc;
1061 void __iomem *base;
1062 int ret;
1063
d8c96083 1064 ret = armada_drm_crtc_create_properties(drm);
96f60e37
RK		 1065 if (ret)
1066 return ret;
1067
a7d7a143 1068 base = devm_ioremap_resource(dev, res);
c9d53c0f
JH		 1069 if (IS_ERR(base))
1070 return PTR_ERR(base);
96f60e37
RK		 1071
1072 dcrtc = kzalloc(sizeof(*dcrtc), GFP_KERNEL);
1073 if (!dcrtc) {
1074 DRM_ERROR("failed to allocate Armada crtc\n");
1075 return -ENOMEM;
1076 }
1077
d8c96083
RK		 1078 if (dev != drm->dev)
1079 dev_set_drvdata(dev, dcrtc);
1080
42e62ba7 1081 dcrtc->variant = variant;
96f60e37 1082 dcrtc->base = base;
d8c96083 1083 dcrtc->num = drm->mode_config.num_crtc;
96f60e37
RK		 1084 dcrtc->clk = ERR_PTR(-EINVAL);
1085 dcrtc->csc_yuv_mode = CSC_AUTO;
1086 dcrtc->csc_rgb_mode = CSC_AUTO;
1087 dcrtc->cfg_dumb_ctrl = DUMB24_RGB888_0;
1088 dcrtc->spu_iopad_ctrl = CFG_VSCALE_LN_EN | CFG_IOPAD_DUMB24;
1089 spin_lock_init(&dcrtc->irq_lock);
1090 dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR;
1091 INIT_LIST_HEAD(&dcrtc->vbl_list);
1092 init_waitqueue_head(&dcrtc->frame_wait);
1093
1094 /* Initialize some registers which we don't otherwise set */
1095 writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV);
1096 writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_BLANKCOLOR);
1097 writel_relaxed(dcrtc->spu_iopad_ctrl,
1098 dcrtc->base + LCD_SPU_IOPAD_CONTROL);
1099 writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_SRAM_PARA0);
1100 writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
1101 CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 |
1102 CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1);
1103 writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1);
1104 writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_GRA_OVSA_HPXL_VLN);
e5d9ddfb
RK		 1105 writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
1106 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
1107
1108 ret = devm_request_irq(dev, irq, armada_drm_irq, 0, "armada_drm_crtc",
1109 dcrtc);
1110 if (ret < 0) {
1111 kfree(dcrtc);
1112 return ret;
1113 }
96f60e37 1114
42e62ba7 1115 if (dcrtc->variant->init) {
d8c96083 1116 ret = dcrtc->variant->init(dcrtc, dev);
96f60e37
RK		 1117 if (ret) {
1118 kfree(dcrtc);
1119 return ret;
1120 }
1121 }
1122
1123 /* Ensure AXI pipeline is enabled */
1124 armada_updatel(CFG_ARBFAST_ENA, 0, dcrtc->base + LCD_SPU_DMA_CTRL0);
1125
1126 priv->dcrtc[dcrtc->num] = dcrtc;
1127
9611cb93 1128 dcrtc->crtc.port = port;
d8c96083 1129 drm_crtc_init(drm, &dcrtc->crtc, &armada_crtc_funcs);
96f60e37
RK		 1130 drm_crtc_helper_add(&dcrtc->crtc, &armada_crtc_helper_funcs);
1131
1132 drm_object_attach_property(&dcrtc->crtc.base, priv->csc_yuv_prop,
1133 dcrtc->csc_yuv_mode);
1134 drm_object_attach_property(&dcrtc->crtc.base, priv->csc_rgb_prop,
1135 dcrtc->csc_rgb_mode);
1136
d8c96083
RK		 1137 return armada_overlay_plane_create(drm, 1 << dcrtc->num);
1138}
1139
1140static int
1141armada_lcd_bind(struct device *dev, struct device *master, void *data)
1142{
1143 struct platform_device *pdev = to_platform_device(dev);
1144 struct drm_device *drm = data;
1145 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1146 int irq = platform_get_irq(pdev, 0);
1147 const struct armada_variant *variant;
9611cb93 1148 struct device_node *port = NULL;
d8c96083
RK		 1149
1150 if (irq < 0)
1151 return irq;
1152
1153 if (!dev->of_node) {
1154 const struct platform_device_id *id;
1155
1156 id = platform_get_device_id(pdev);
1157 if (!id)
1158 return -ENXIO;
1159
1160 variant = (const struct armada_variant *)id->driver_data;
1161 } else {
1162 const struct of_device_id *match;
9611cb93 1163 struct device_node *np, *parent = dev->of_node;
d8c96083
RK		 1164
1165 match = of_match_device(dev->driver->of_match_table, dev);
1166 if (!match)
1167 return -ENXIO;
1168
9611cb93
RK		 1169 np = of_get_child_by_name(parent, "ports");
1170 if (np)
1171 parent = np;
1172 port = of_get_child_by_name(parent, "port");
1173 of_node_put(np);
1174 if (!port) {
1175 dev_err(dev, "no port node found in %s\n",
1176 parent->full_name);
1177 return -ENXIO;
1178 }
1179
d8c96083
RK		 1180 variant = match->data;
1181 }
1182
9611cb93 1183 return armada_drm_crtc_create(drm, dev, res, irq, variant, port);
d8c96083
RK		 1184}
1185
1186static void
1187armada_lcd_unbind(struct device *dev, struct device *master, void *data)
1188{
1189 struct armada_crtc *dcrtc = dev_get_drvdata(dev);
1190
1191 armada_drm_crtc_destroy(&dcrtc->crtc);
96f60e37 1192}
d8c96083
RK		 1193
1194static const struct component_ops armada_lcd_ops = {
1195 .bind = armada_lcd_bind,
1196 .unbind = armada_lcd_unbind,
1197};
1198
1199static int armada_lcd_probe(struct platform_device *pdev)
1200{
1201 return component_add(&pdev->dev, &armada_lcd_ops);
1202}
1203
1204static int armada_lcd_remove(struct platform_device *pdev)
1205{
1206 component_del(&pdev->dev, &armada_lcd_ops);
1207 return 0;
96f60e37 1208}
d8c96083
RK		 1209
1210static struct of_device_id armada_lcd_of_match[] = {
1211 {
1212 .compatible = "marvell,dove-lcd",
1213 .data = &armada510_ops,
1214 },
1215 {}
1216};
1217MODULE_DEVICE_TABLE(of, armada_lcd_of_match);
1218
1219static const struct platform_device_id armada_lcd_platform_ids[] = {
1220 {
1221 .name = "armada-lcd",
1222 .driver_data = (unsigned long)&armada510_ops,
1223 }, {
1224 .name = "armada-510-lcd",
1225 .driver_data = (unsigned long)&armada510_ops,
1226 },
1227 { },
1228};
1229MODULE_DEVICE_TABLE(platform, armada_lcd_platform_ids);
1230
1231struct platform_driver armada_lcd_platform_driver = {
1232 .probe = armada_lcd_probe,
1233 .remove = armada_lcd_remove,
1234 .driver = {
1235 .name = "armada-lcd",
1236 .owner = THIS_MODULE,
1237 .of_match_table = armada_lcd_of_match,
1238 },
1239 .id_table = armada_lcd_platform_ids,
1240};
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