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312fec14 DA |
1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the | |
6 | * "Software"), to deal in the Software without restriction, including | |
7 | * without limitation the rights to use, copy, modify, merge, publish, | |
8 | * distribute, sub license, and/or sell copies of the Software, and to | |
9 | * permit persons to whom the Software is furnished to do so, subject to | |
10 | * the following conditions: | |
11 | * | |
12 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
13 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
14 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
15 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
16 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
17 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
18 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
19 | * | |
20 | * The above copyright notice and this permission notice (including the | |
21 | * next paragraph) shall be included in all copies or substantial portions | |
22 | * of the Software. | |
23 | * | |
24 | */ | |
25 | /* | |
26 | * Authors: Dave Airlie <airlied@redhat.com> | |
27 | */ | |
760285e7 | 28 | #include <drm/drmP.h> |
312fec14 DA |
29 | #include "ast_drv.h" |
30 | ||
31 | ||
760285e7 DH |
32 | #include <drm/drm_fb_helper.h> |
33 | #include <drm/drm_crtc_helper.h> | |
312fec14 DA |
34 | |
35 | #include "ast_dram_tables.h" | |
36 | ||
37 | void ast_set_index_reg_mask(struct ast_private *ast, | |
38 | uint32_t base, uint8_t index, | |
39 | uint8_t mask, uint8_t val) | |
40 | { | |
41 | u8 tmp; | |
42 | ast_io_write8(ast, base, index); | |
43 | tmp = (ast_io_read8(ast, base + 1) & mask) | val; | |
44 | ast_set_index_reg(ast, base, index, tmp); | |
45 | } | |
46 | ||
47 | uint8_t ast_get_index_reg(struct ast_private *ast, | |
48 | uint32_t base, uint8_t index) | |
49 | { | |
50 | uint8_t ret; | |
51 | ast_io_write8(ast, base, index); | |
52 | ret = ast_io_read8(ast, base + 1); | |
53 | return ret; | |
54 | } | |
55 | ||
56 | uint8_t ast_get_index_reg_mask(struct ast_private *ast, | |
57 | uint32_t base, uint8_t index, uint8_t mask) | |
58 | { | |
59 | uint8_t ret; | |
60 | ast_io_write8(ast, base, index); | |
61 | ret = ast_io_read8(ast, base + 1) & mask; | |
62 | return ret; | |
63 | } | |
64 | ||
65 | ||
d1b98557 | 66 | static int ast_detect_chip(struct drm_device *dev, bool *need_post) |
312fec14 DA |
67 | { |
68 | struct ast_private *ast = dev->dev_private; | |
f1f62f2c | 69 | uint32_t data, jreg; |
8f372e25 | 70 | ast_open_key(ast); |
312fec14 DA |
71 | |
72 | if (dev->pdev->device == PCI_CHIP_AST1180) { | |
73 | ast->chip = AST1100; | |
74 | DRM_INFO("AST 1180 detected\n"); | |
75 | } else { | |
1453bf4c DA |
76 | if (dev->pdev->revision >= 0x30) { |
77 | ast->chip = AST2400; | |
78 | DRM_INFO("AST 2400 detected\n"); | |
79 | } else if (dev->pdev->revision >= 0x20) { | |
312fec14 DA |
80 | ast->chip = AST2300; |
81 | DRM_INFO("AST 2300 detected\n"); | |
82 | } else if (dev->pdev->revision >= 0x10) { | |
83 | uint32_t data; | |
84 | ast_write32(ast, 0xf004, 0x1e6e0000); | |
85 | ast_write32(ast, 0xf000, 0x1); | |
86 | ||
87 | data = ast_read32(ast, 0x1207c); | |
88 | switch (data & 0x0300) { | |
89 | case 0x0200: | |
90 | ast->chip = AST1100; | |
91 | DRM_INFO("AST 1100 detected\n"); | |
92 | break; | |
93 | case 0x0100: | |
94 | ast->chip = AST2200; | |
95 | DRM_INFO("AST 2200 detected\n"); | |
96 | break; | |
97 | case 0x0000: | |
98 | ast->chip = AST2150; | |
99 | DRM_INFO("AST 2150 detected\n"); | |
100 | break; | |
101 | default: | |
102 | ast->chip = AST2100; | |
103 | DRM_INFO("AST 2100 detected\n"); | |
104 | break; | |
105 | } | |
106 | ast->vga2_clone = false; | |
107 | } else { | |
83502a5d | 108 | ast->chip = AST2000; |
312fec14 DA |
109 | DRM_INFO("AST 2000 detected\n"); |
110 | } | |
111 | } | |
f1f62f2c | 112 | |
d1b98557 BH |
113 | /* |
114 | * If VGA isn't enabled, we need to enable now or subsequent | |
115 | * access to the scratch registers will fail. We also inform | |
116 | * our caller that it needs to POST the chip | |
117 | * (Assumption: VGA not enabled -> need to POST) | |
118 | */ | |
119 | if (!ast_is_vga_enabled(dev)) { | |
120 | ast_enable_vga(dev); | |
121 | ast_enable_mmio(dev); | |
122 | DRM_INFO("VGA not enabled on entry, requesting chip POST\n"); | |
123 | *need_post = true; | |
124 | } else | |
125 | *need_post = false; | |
126 | ||
127 | /* Check if we support wide screen */ | |
f1f62f2c DA |
128 | switch (ast->chip) { |
129 | case AST1180: | |
130 | ast->support_wide_screen = true; | |
131 | break; | |
132 | case AST2000: | |
133 | ast->support_wide_screen = false; | |
134 | break; | |
135 | default: | |
136 | jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); | |
137 | if (!(jreg & 0x80)) | |
138 | ast->support_wide_screen = true; | |
139 | else if (jreg & 0x01) | |
140 | ast->support_wide_screen = true; | |
141 | else { | |
142 | ast->support_wide_screen = false; | |
d1b98557 | 143 | /* Read SCU7c (silicon revision register) */ |
1453bf4c DA |
144 | ast_write32(ast, 0xf004, 0x1e6e0000); |
145 | ast_write32(ast, 0xf000, 0x1); | |
146 | data = ast_read32(ast, 0x1207c); | |
147 | data &= 0x300; | |
148 | if (ast->chip == AST2300 && data == 0x0) /* ast1300 */ | |
149 | ast->support_wide_screen = true; | |
150 | if (ast->chip == AST2400 && data == 0x100) /* ast1400 */ | |
151 | ast->support_wide_screen = true; | |
f1f62f2c DA |
152 | } |
153 | break; | |
154 | } | |
155 | ||
d1b98557 | 156 | /* Check 3rd Tx option (digital output afaik) */ |
83c6620b | 157 | ast->tx_chip_type = AST_TX_NONE; |
d1b98557 BH |
158 | |
159 | /* | |
160 | * VGACRA3 Enhanced Color Mode Register, check if DVO is already | |
161 | * enabled, in that case, assume we have a SIL164 TMDS transmitter | |
42fb1427 BH |
162 | * |
163 | * Don't make that assumption if we the chip wasn't enabled and | |
164 | * is at power-on reset, otherwise we'll incorrectly "detect" a | |
165 | * SIL164 when there is none. | |
d1b98557 | 166 | */ |
42fb1427 BH |
167 | if (!*need_post) { |
168 | jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xff); | |
169 | if (jreg & 0x80) | |
170 | ast->tx_chip_type = AST_TX_SIL164; | |
171 | } | |
d1b98557 | 172 | |
83c6620b | 173 | if ((ast->chip == AST2300) || (ast->chip == AST2400)) { |
d1b98557 BH |
174 | /* |
175 | * On AST2300 and 2400, look the configuration set by the SoC in | |
176 | * the SOC scratch register #1 bits 11:8 (interestingly marked | |
42fb1427 | 177 | * as "reserved" in the spec) |
d1b98557 | 178 | */ |
83c6620b DA |
179 | jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); |
180 | switch (jreg) { | |
181 | case 0x04: | |
182 | ast->tx_chip_type = AST_TX_SIL164; | |
183 | break; | |
184 | case 0x08: | |
185 | ast->dp501_fw_addr = kzalloc(32*1024, GFP_KERNEL); | |
186 | if (ast->dp501_fw_addr) { | |
187 | /* backup firmware */ | |
188 | if (ast_backup_fw(dev, ast->dp501_fw_addr, 32*1024)) { | |
189 | kfree(ast->dp501_fw_addr); | |
190 | ast->dp501_fw_addr = NULL; | |
191 | } | |
192 | } | |
193 | /* fallthrough */ | |
194 | case 0x0c: | |
195 | ast->tx_chip_type = AST_TX_DP501; | |
196 | } | |
197 | } | |
198 | ||
d1b98557 BH |
199 | /* Print stuff for diagnostic purposes */ |
200 | switch(ast->tx_chip_type) { | |
201 | case AST_TX_SIL164: | |
202 | DRM_INFO("Using Sil164 TMDS transmitter\n"); | |
203 | break; | |
204 | case AST_TX_DP501: | |
205 | DRM_INFO("Using DP501 DisplayPort transmitter\n"); | |
206 | break; | |
207 | default: | |
208 | DRM_INFO("Analog VGA only\n"); | |
209 | } | |
312fec14 DA |
210 | return 0; |
211 | } | |
212 | ||
213 | static int ast_get_dram_info(struct drm_device *dev) | |
214 | { | |
215 | struct ast_private *ast = dev->dev_private; | |
216 | uint32_t data, data2; | |
217 | uint32_t denum, num, div, ref_pll; | |
218 | ||
219 | ast_write32(ast, 0xf004, 0x1e6e0000); | |
220 | ast_write32(ast, 0xf000, 0x1); | |
221 | ||
222 | ||
223 | ast_write32(ast, 0x10000, 0xfc600309); | |
224 | ||
225 | do { | |
226 | ; | |
227 | } while (ast_read32(ast, 0x10000) != 0x01); | |
228 | data = ast_read32(ast, 0x10004); | |
229 | ||
230 | if (data & 0x400) | |
231 | ast->dram_bus_width = 16; | |
232 | else | |
233 | ast->dram_bus_width = 32; | |
234 | ||
1453bf4c | 235 | if (ast->chip == AST2300 || ast->chip == AST2400) { |
312fec14 DA |
236 | switch (data & 0x03) { |
237 | case 0: | |
238 | ast->dram_type = AST_DRAM_512Mx16; | |
239 | break; | |
240 | default: | |
241 | case 1: | |
242 | ast->dram_type = AST_DRAM_1Gx16; | |
243 | break; | |
244 | case 2: | |
245 | ast->dram_type = AST_DRAM_2Gx16; | |
246 | break; | |
247 | case 3: | |
248 | ast->dram_type = AST_DRAM_4Gx16; | |
249 | break; | |
250 | } | |
251 | } else { | |
252 | switch (data & 0x0c) { | |
253 | case 0: | |
254 | case 4: | |
255 | ast->dram_type = AST_DRAM_512Mx16; | |
256 | break; | |
257 | case 8: | |
258 | if (data & 0x40) | |
259 | ast->dram_type = AST_DRAM_1Gx16; | |
260 | else | |
261 | ast->dram_type = AST_DRAM_512Mx32; | |
262 | break; | |
263 | case 0xc: | |
264 | ast->dram_type = AST_DRAM_1Gx32; | |
265 | break; | |
266 | } | |
267 | } | |
268 | ||
269 | data = ast_read32(ast, 0x10120); | |
270 | data2 = ast_read32(ast, 0x10170); | |
271 | if (data2 & 0x2000) | |
272 | ref_pll = 14318; | |
273 | else | |
274 | ref_pll = 12000; | |
275 | ||
276 | denum = data & 0x1f; | |
277 | num = (data & 0x3fe0) >> 5; | |
278 | data = (data & 0xc000) >> 14; | |
279 | switch (data) { | |
280 | case 3: | |
281 | div = 0x4; | |
282 | break; | |
283 | case 2: | |
284 | case 1: | |
285 | div = 0x2; | |
286 | break; | |
287 | default: | |
288 | div = 0x1; | |
289 | break; | |
290 | } | |
291 | ast->mclk = ref_pll * (num + 2) / (denum + 2) * (div * 1000); | |
292 | return 0; | |
293 | } | |
294 | ||
312fec14 DA |
295 | static void ast_user_framebuffer_destroy(struct drm_framebuffer *fb) |
296 | { | |
297 | struct ast_framebuffer *ast_fb = to_ast_framebuffer(fb); | |
298 | if (ast_fb->obj) | |
299 | drm_gem_object_unreference_unlocked(ast_fb->obj); | |
300 | ||
301 | drm_framebuffer_cleanup(fb); | |
302 | kfree(fb); | |
303 | } | |
304 | ||
312fec14 DA |
305 | static const struct drm_framebuffer_funcs ast_fb_funcs = { |
306 | .destroy = ast_user_framebuffer_destroy, | |
312fec14 DA |
307 | }; |
308 | ||
309 | ||
310 | int ast_framebuffer_init(struct drm_device *dev, | |
311 | struct ast_framebuffer *ast_fb, | |
1eb83451 | 312 | const struct drm_mode_fb_cmd2 *mode_cmd, |
312fec14 DA |
313 | struct drm_gem_object *obj) |
314 | { | |
315 | int ret; | |
316 | ||
c7d73f6a DV |
317 | drm_helper_mode_fill_fb_struct(&ast_fb->base, mode_cmd); |
318 | ast_fb->obj = obj; | |
312fec14 DA |
319 | ret = drm_framebuffer_init(dev, &ast_fb->base, &ast_fb_funcs); |
320 | if (ret) { | |
321 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
322 | return ret; | |
323 | } | |
312fec14 DA |
324 | return 0; |
325 | } | |
326 | ||
327 | static struct drm_framebuffer * | |
328 | ast_user_framebuffer_create(struct drm_device *dev, | |
329 | struct drm_file *filp, | |
1eb83451 | 330 | const struct drm_mode_fb_cmd2 *mode_cmd) |
312fec14 DA |
331 | { |
332 | struct drm_gem_object *obj; | |
333 | struct ast_framebuffer *ast_fb; | |
334 | int ret; | |
335 | ||
336 | obj = drm_gem_object_lookup(dev, filp, mode_cmd->handles[0]); | |
337 | if (obj == NULL) | |
338 | return ERR_PTR(-ENOENT); | |
339 | ||
340 | ast_fb = kzalloc(sizeof(*ast_fb), GFP_KERNEL); | |
341 | if (!ast_fb) { | |
342 | drm_gem_object_unreference_unlocked(obj); | |
343 | return ERR_PTR(-ENOMEM); | |
344 | } | |
345 | ||
346 | ret = ast_framebuffer_init(dev, ast_fb, mode_cmd, obj); | |
347 | if (ret) { | |
348 | drm_gem_object_unreference_unlocked(obj); | |
349 | kfree(ast_fb); | |
350 | return ERR_PTR(ret); | |
351 | } | |
352 | return &ast_fb->base; | |
353 | } | |
354 | ||
355 | static const struct drm_mode_config_funcs ast_mode_funcs = { | |
356 | .fb_create = ast_user_framebuffer_create, | |
357 | }; | |
358 | ||
359 | static u32 ast_get_vram_info(struct drm_device *dev) | |
360 | { | |
361 | struct ast_private *ast = dev->dev_private; | |
362 | u8 jreg; | |
83c6620b | 363 | u32 vram_size; |
312fec14 DA |
364 | ast_open_key(ast); |
365 | ||
83c6620b | 366 | vram_size = AST_VIDMEM_DEFAULT_SIZE; |
312fec14 DA |
367 | jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xaa, 0xff); |
368 | switch (jreg & 3) { | |
83c6620b DA |
369 | case 0: vram_size = AST_VIDMEM_SIZE_8M; break; |
370 | case 1: vram_size = AST_VIDMEM_SIZE_16M; break; | |
371 | case 2: vram_size = AST_VIDMEM_SIZE_32M; break; | |
372 | case 3: vram_size = AST_VIDMEM_SIZE_64M; break; | |
312fec14 | 373 | } |
83c6620b DA |
374 | |
375 | jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x99, 0xff); | |
376 | switch (jreg & 0x03) { | |
377 | case 1: | |
378 | vram_size -= 0x100000; | |
379 | break; | |
380 | case 2: | |
381 | vram_size -= 0x200000; | |
382 | break; | |
383 | case 3: | |
384 | vram_size -= 0x400000; | |
385 | break; | |
386 | } | |
387 | ||
388 | return vram_size; | |
312fec14 DA |
389 | } |
390 | ||
391 | int ast_driver_load(struct drm_device *dev, unsigned long flags) | |
392 | { | |
393 | struct ast_private *ast; | |
d1b98557 | 394 | bool need_post; |
312fec14 DA |
395 | int ret = 0; |
396 | ||
397 | ast = kzalloc(sizeof(struct ast_private), GFP_KERNEL); | |
398 | if (!ast) | |
399 | return -ENOMEM; | |
400 | ||
401 | dev->dev_private = ast; | |
402 | ast->dev = dev; | |
403 | ||
404 | ast->regs = pci_iomap(dev->pdev, 1, 0); | |
405 | if (!ast->regs) { | |
406 | ret = -EIO; | |
407 | goto out_free; | |
408 | } | |
0dd68309 BH |
409 | |
410 | /* | |
411 | * If we don't have IO space at all, use MMIO now and | |
412 | * assume the chip has MMIO enabled by default (rev 0x20 | |
413 | * and higher). | |
414 | */ | |
415 | if (!(pci_resource_flags(dev->pdev, 2) & IORESOURCE_IO)) { | |
416 | DRM_INFO("platform has no IO space, trying MMIO\n"); | |
417 | ast->ioregs = ast->regs + AST_IO_MM_OFFSET; | |
418 | } | |
419 | ||
420 | /* "map" IO regs if the above hasn't done so already */ | |
312fec14 | 421 | if (!ast->ioregs) { |
0dd68309 BH |
422 | ast->ioregs = pci_iomap(dev->pdev, 2, 0); |
423 | if (!ast->ioregs) { | |
424 | ret = -EIO; | |
425 | goto out_free; | |
426 | } | |
312fec14 DA |
427 | } |
428 | ||
d1b98557 | 429 | ast_detect_chip(dev, &need_post); |
312fec14 DA |
430 | |
431 | if (ast->chip != AST1180) { | |
432 | ast_get_dram_info(dev); | |
433 | ast->vram_size = ast_get_vram_info(dev); | |
434 | DRM_INFO("dram %d %d %d %08x\n", ast->mclk, ast->dram_type, ast->dram_bus_width, ast->vram_size); | |
435 | } | |
436 | ||
d1b98557 BH |
437 | if (need_post) |
438 | ast_post_gpu(dev); | |
439 | ||
312fec14 DA |
440 | ret = ast_mm_init(ast); |
441 | if (ret) | |
442 | goto out_free; | |
443 | ||
444 | drm_mode_config_init(dev); | |
445 | ||
446 | dev->mode_config.funcs = (void *)&ast_mode_funcs; | |
447 | dev->mode_config.min_width = 0; | |
448 | dev->mode_config.min_height = 0; | |
449 | dev->mode_config.preferred_depth = 24; | |
450 | dev->mode_config.prefer_shadow = 1; | |
28fb4cb7 | 451 | dev->mode_config.fb_base = pci_resource_start(ast->dev->pdev, 0); |
312fec14 DA |
452 | |
453 | if (ast->chip == AST2100 || | |
454 | ast->chip == AST2200 || | |
455 | ast->chip == AST2300 || | |
1453bf4c | 456 | ast->chip == AST2400 || |
312fec14 DA |
457 | ast->chip == AST1180) { |
458 | dev->mode_config.max_width = 1920; | |
459 | dev->mode_config.max_height = 2048; | |
460 | } else { | |
461 | dev->mode_config.max_width = 1600; | |
462 | dev->mode_config.max_height = 1200; | |
463 | } | |
464 | ||
465 | ret = ast_mode_init(dev); | |
466 | if (ret) | |
467 | goto out_free; | |
468 | ||
469 | ret = ast_fbdev_init(dev); | |
470 | if (ret) | |
471 | goto out_free; | |
472 | ||
473 | return 0; | |
474 | out_free: | |
475 | kfree(ast); | |
476 | dev->dev_private = NULL; | |
477 | return ret; | |
478 | } | |
479 | ||
480 | int ast_driver_unload(struct drm_device *dev) | |
481 | { | |
482 | struct ast_private *ast = dev->dev_private; | |
483 | ||
83c6620b | 484 | kfree(ast->dp501_fw_addr); |
312fec14 DA |
485 | ast_mode_fini(dev); |
486 | ast_fbdev_fini(dev); | |
487 | drm_mode_config_cleanup(dev); | |
488 | ||
489 | ast_mm_fini(ast); | |
490 | pci_iounmap(dev->pdev, ast->ioregs); | |
491 | pci_iounmap(dev->pdev, ast->regs); | |
492 | kfree(ast); | |
493 | return 0; | |
494 | } | |
495 | ||
496 | int ast_gem_create(struct drm_device *dev, | |
497 | u32 size, bool iskernel, | |
498 | struct drm_gem_object **obj) | |
499 | { | |
500 | struct ast_bo *astbo; | |
501 | int ret; | |
502 | ||
503 | *obj = NULL; | |
504 | ||
505 | size = roundup(size, PAGE_SIZE); | |
506 | if (size == 0) | |
507 | return -EINVAL; | |
508 | ||
509 | ret = ast_bo_create(dev, size, 0, 0, &astbo); | |
510 | if (ret) { | |
511 | if (ret != -ERESTARTSYS) | |
512 | DRM_ERROR("failed to allocate GEM object\n"); | |
513 | return ret; | |
514 | } | |
515 | *obj = &astbo->gem; | |
516 | return 0; | |
517 | } | |
518 | ||
519 | int ast_dumb_create(struct drm_file *file, | |
520 | struct drm_device *dev, | |
521 | struct drm_mode_create_dumb *args) | |
522 | { | |
523 | int ret; | |
524 | struct drm_gem_object *gobj; | |
525 | u32 handle; | |
526 | ||
527 | args->pitch = args->width * ((args->bpp + 7) / 8); | |
528 | args->size = args->pitch * args->height; | |
529 | ||
530 | ret = ast_gem_create(dev, args->size, false, | |
531 | &gobj); | |
532 | if (ret) | |
533 | return ret; | |
534 | ||
535 | ret = drm_gem_handle_create(file, gobj, &handle); | |
536 | drm_gem_object_unreference_unlocked(gobj); | |
537 | if (ret) | |
538 | return ret; | |
539 | ||
540 | args->handle = handle; | |
541 | return 0; | |
542 | } | |
543 | ||
f6109803 | 544 | static void ast_bo_unref(struct ast_bo **bo) |
312fec14 DA |
545 | { |
546 | struct ttm_buffer_object *tbo; | |
547 | ||
548 | if ((*bo) == NULL) | |
549 | return; | |
550 | ||
551 | tbo = &((*bo)->bo); | |
552 | ttm_bo_unref(&tbo); | |
eb649a61 | 553 | *bo = NULL; |
312fec14 | 554 | } |
eb649a61 | 555 | |
312fec14 DA |
556 | void ast_gem_free_object(struct drm_gem_object *obj) |
557 | { | |
558 | struct ast_bo *ast_bo = gem_to_ast_bo(obj); | |
559 | ||
312fec14 DA |
560 | ast_bo_unref(&ast_bo); |
561 | } | |
562 | ||
563 | ||
564 | static inline u64 ast_bo_mmap_offset(struct ast_bo *bo) | |
565 | { | |
72525b3f | 566 | return drm_vma_node_offset_addr(&bo->bo.vma_node); |
312fec14 DA |
567 | } |
568 | int | |
569 | ast_dumb_mmap_offset(struct drm_file *file, | |
570 | struct drm_device *dev, | |
571 | uint32_t handle, | |
572 | uint64_t *offset) | |
573 | { | |
574 | struct drm_gem_object *obj; | |
312fec14 DA |
575 | struct ast_bo *bo; |
576 | ||
312fec14 | 577 | obj = drm_gem_object_lookup(dev, file, handle); |
a66b2ea2 DV |
578 | if (obj == NULL) |
579 | return -ENOENT; | |
312fec14 DA |
580 | |
581 | bo = gem_to_ast_bo(obj); | |
582 | *offset = ast_bo_mmap_offset(bo); | |
583 | ||
a66b2ea2 DV |
584 | drm_gem_object_unreference_unlocked(obj); |
585 | ||
586 | return 0; | |
312fec14 DA |
587 | |
588 | } | |
589 |