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drm/tilcdc: Fix build breakage
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / ast / ast_mode.c
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312fec14
DA		 1/*
2 * Copyright 2012 Red Hat Inc.
3 * Parts based on xf86-video-ast
4 * Copyright (c) 2005 ASPEED Technology Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
18 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
19 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
24 * of the Software.
25 *
26 */
27/*
28 * Authors: Dave Airlie <airlied@redhat.com>
29 */
30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
312fec14
DA		 34#include "ast_drv.h"
35
36#include "ast_tables.h"
37
38static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev);
39static void ast_i2c_destroy(struct ast_i2c_chan *i2c);
40static int ast_cursor_set(struct drm_crtc *crtc,
41 struct drm_file *file_priv,
42 uint32_t handle,
43 uint32_t width,
44 uint32_t height);
45static int ast_cursor_move(struct drm_crtc *crtc,
46 int x, int y);
47
48static inline void ast_load_palette_index(struct ast_private *ast,
49 u8 index, u8 red, u8 green,
50 u8 blue)
51{
52 ast_io_write8(ast, AST_IO_DAC_INDEX_WRITE, index);
53 ast_io_read8(ast, AST_IO_SEQ_PORT);
54 ast_io_write8(ast, AST_IO_DAC_DATA, red);
55 ast_io_read8(ast, AST_IO_SEQ_PORT);
56 ast_io_write8(ast, AST_IO_DAC_DATA, green);
57 ast_io_read8(ast, AST_IO_SEQ_PORT);
58 ast_io_write8(ast, AST_IO_DAC_DATA, blue);
59 ast_io_read8(ast, AST_IO_SEQ_PORT);
60}
61
62static void ast_crtc_load_lut(struct drm_crtc *crtc)
63{
64 struct ast_private *ast = crtc->dev->dev_private;
65 struct ast_crtc *ast_crtc = to_ast_crtc(crtc);
66 int i;
67
68 if (!crtc->enabled)
69 return;
70
71 for (i = 0; i < 256; i++)
72 ast_load_palette_index(ast, i, ast_crtc->lut_r[i],
73 ast_crtc->lut_g[i], ast_crtc->lut_b[i]);
74}
75
76static bool ast_get_vbios_mode_info(struct drm_crtc *crtc, struct drm_display_mode *mode,
77 struct drm_display_mode *adjusted_mode,
78 struct ast_vbios_mode_info *vbios_mode)
79{
80 struct ast_private *ast = crtc->dev->dev_private;
81 u32 refresh_rate_index = 0, mode_id, color_index, refresh_rate;
82 u32 hborder, vborder;
83
f4510a27 84 switch (crtc->primary->fb->bits_per_pixel) {
312fec14
DA		 85 case 8:
86 vbios_mode->std_table = &vbios_stdtable[VGAModeIndex];
87 color_index = VGAModeIndex - 1;
88 break;
89 case 16:
90 vbios_mode->std_table = &vbios_stdtable[HiCModeIndex];
91 color_index = HiCModeIndex;
92 break;
93 case 24:
94 case 32:
95 vbios_mode->std_table = &vbios_stdtable[TrueCModeIndex];
96 color_index = TrueCModeIndex;
97 break;
98 default:
99 return false;
100 }
101
102 switch (crtc->mode.crtc_hdisplay) {
103 case 640:
104 vbios_mode->enh_table = &res_640x480[refresh_rate_index];
105 break;
106 case 800:
107 vbios_mode->enh_table = &res_800x600[refresh_rate_index];
108 break;
109 case 1024:
110 vbios_mode->enh_table = &res_1024x768[refresh_rate_index];
111 break;
112 case 1280:
113 if (crtc->mode.crtc_vdisplay == 800)
114 vbios_mode->enh_table = &res_1280x800[refresh_rate_index];
115 else
116 vbios_mode->enh_table = &res_1280x1024[refresh_rate_index];
117 break;
f1f62f2c
DA		 118 case 1360:
119 vbios_mode->enh_table = &res_1360x768[refresh_rate_index];
120 break;
312fec14
DA		 121 case 1440:
122 vbios_mode->enh_table = &res_1440x900[refresh_rate_index];
123 break;
124 case 1600:
f1f62f2c
DA		 125 if (crtc->mode.crtc_vdisplay == 900)
126 vbios_mode->enh_table = &res_1600x900[refresh_rate_index];
127 else
128 vbios_mode->enh_table = &res_1600x1200[refresh_rate_index];
312fec14
DA		 129 break;
130 case 1680:
131 vbios_mode->enh_table = &res_1680x1050[refresh_rate_index];
132 break;
133 case 1920:
134 if (crtc->mode.crtc_vdisplay == 1080)
135 vbios_mode->enh_table = &res_1920x1080[refresh_rate_index];
136 else
137 vbios_mode->enh_table = &res_1920x1200[refresh_rate_index];
138 break;
139 default:
140 return false;
141 }
142
143 refresh_rate = drm_mode_vrefresh(mode);
144 while (vbios_mode->enh_table->refresh_rate < refresh_rate) {
145 vbios_mode->enh_table++;
146 if ((vbios_mode->enh_table->refresh_rate > refresh_rate) ||
147 (vbios_mode->enh_table->refresh_rate == 0xff)) {
148 vbios_mode->enh_table--;
149 break;
150 }
151 }
152
153 hborder = (vbios_mode->enh_table->flags & HBorder) ? 8 : 0;
154 vborder = (vbios_mode->enh_table->flags & VBorder) ? 8 : 0;
155
156 adjusted_mode->crtc_htotal = vbios_mode->enh_table->ht;
157 adjusted_mode->crtc_hblank_start = vbios_mode->enh_table->hde + hborder;
158 adjusted_mode->crtc_hblank_end = vbios_mode->enh_table->ht - hborder;
159 adjusted_mode->crtc_hsync_start = vbios_mode->enh_table->hde + hborder +
160 vbios_mode->enh_table->hfp;
161 adjusted_mode->crtc_hsync_end = (vbios_mode->enh_table->hde + hborder +
162 vbios_mode->enh_table->hfp +
163 vbios_mode->enh_table->hsync);
164
165 adjusted_mode->crtc_vtotal = vbios_mode->enh_table->vt;
166 adjusted_mode->crtc_vblank_start = vbios_mode->enh_table->vde + vborder;
167 adjusted_mode->crtc_vblank_end = vbios_mode->enh_table->vt - vborder;
168 adjusted_mode->crtc_vsync_start = vbios_mode->enh_table->vde + vborder +
169 vbios_mode->enh_table->vfp;
170 adjusted_mode->crtc_vsync_end = (vbios_mode->enh_table->vde + vborder +
171 vbios_mode->enh_table->vfp +
172 vbios_mode->enh_table->vsync);
173
174 refresh_rate_index = vbios_mode->enh_table->refresh_rate_index;
175 mode_id = vbios_mode->enh_table->mode_id;
176
177 if (ast->chip == AST1180) {
178 /* TODO 1180 */
179 } else {
180 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8c, (u8)((color_index & 0xf) << 4));
181 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8d, refresh_rate_index & 0xff);
182 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8e, mode_id & 0xff);
183
f1f62f2c
DA		 184 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00);
185 if (vbios_mode->enh_table->flags & NewModeInfo) {
186 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8);
263432b0 187 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92, crtc->primary->fb->bits_per_pixel);
f1f62f2c
DA		 188 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x93, adjusted_mode->clock / 1000);
189 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x94, adjusted_mode->crtc_hdisplay);
190 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x95, adjusted_mode->crtc_hdisplay >> 8);
312fec14 191
f1f62f2c
DA		 192 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x96, adjusted_mode->crtc_vdisplay);
193 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x97, adjusted_mode->crtc_vdisplay >> 8);
194 }
312fec14
DA		 195 }
196
197 return true;
198
199
200}
201static void ast_set_std_reg(struct drm_crtc *crtc, struct drm_display_mode *mode,
202 struct ast_vbios_mode_info *vbios_mode)
203{
204 struct ast_private *ast = crtc->dev->dev_private;
205 struct ast_vbios_stdtable *stdtable;
206 u32 i;
207 u8 jreg;
208
209 stdtable = vbios_mode->std_table;
210
211 jreg = stdtable->misc;
212 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg);
213
214 /* Set SEQ */
215 ast_set_index_reg(ast, AST_IO_SEQ_PORT, 0x00, 0x03);
216 for (i = 0; i < 4; i++) {
217 jreg = stdtable->seq[i];
218 if (!i)
219 jreg |= 0x20;
220 ast_set_index_reg(ast, AST_IO_SEQ_PORT, (i + 1) , jreg);
221 }
222
223 /* Set CRTC */
224 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
225 for (i = 0; i < 25; i++)
226 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]);
227
228 /* set AR */
229 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
230 for (i = 0; i < 20; i++) {
231 jreg = stdtable->ar[i];
232 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, (u8)i);
233 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, jreg);
234 }
235 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x14);
236 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x00);
237
238 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
239 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x20);
240
241 /* Set GR */
242 for (i = 0; i < 9; i++)
243 ast_set_index_reg(ast, AST_IO_GR_PORT, i, stdtable->gr[i]);
244}
245
246static void ast_set_crtc_reg(struct drm_crtc *crtc, struct drm_display_mode *mode,
247 struct ast_vbios_mode_info *vbios_mode)
248{
249 struct ast_private *ast = crtc->dev->dev_private;
250 u8 jreg05 = 0, jreg07 = 0, jreg09 = 0, jregAC = 0, jregAD = 0, jregAE = 0;
251 u16 temp;
252
253 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
254
255 temp = (mode->crtc_htotal >> 3) - 5;
256 if (temp & 0x100)
257 jregAC |= 0x01; /* HT D[8] */
258 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x00, 0x00, temp);
259
260 temp = (mode->crtc_hdisplay >> 3) - 1;
261 if (temp & 0x100)
262 jregAC |= 0x04; /* HDE D[8] */
263 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x01, 0x00, temp);
264
265 temp = (mode->crtc_hblank_start >> 3) - 1;
266 if (temp & 0x100)
267 jregAC |= 0x10; /* HBS D[8] */
268 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x02, 0x00, temp);
269
270 temp = ((mode->crtc_hblank_end >> 3) - 1) & 0x7f;
271 if (temp & 0x20)
272 jreg05 |= 0x80; /* HBE D[5] */
273 if (temp & 0x40)
274 jregAD |= 0x01; /* HBE D[5] */
275 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f));
276
277 temp = (mode->crtc_hsync_start >> 3) - 1;
278 if (temp & 0x100)
279 jregAC |= 0x40; /* HRS D[5] */
280 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp);
281
282 temp = ((mode->crtc_hsync_end >> 3) - 1) & 0x3f;
283 if (temp & 0x20)
284 jregAD |= 0x04; /* HRE D[5] */
285 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05));
286
287 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAC, 0x00, jregAC);
288 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAD, 0x00, jregAD);
289
290 /* vert timings */
291 temp = (mode->crtc_vtotal) - 2;
292 if (temp & 0x100)
293 jreg07 |= 0x01;
294 if (temp & 0x200)
295 jreg07 |= 0x20;
296 if (temp & 0x400)
297 jregAE |= 0x01;
298 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x06, 0x00, temp);
299
300 temp = (mode->crtc_vsync_start) - 1;
301 if (temp & 0x100)
302 jreg07 |= 0x04;
303 if (temp & 0x200)
304 jreg07 |= 0x80;
305 if (temp & 0x400)
306 jregAE |= 0x08;
307 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x10, 0x00, temp);
308
309 temp = (mode->crtc_vsync_end - 1) & 0x3f;
310 if (temp & 0x10)
311 jregAE |= 0x20;
312 if (temp & 0x20)
313 jregAE |= 0x40;
314 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x70, temp & 0xf);
315
316 temp = mode->crtc_vdisplay - 1;
317 if (temp & 0x100)
318 jreg07 |= 0x02;
319 if (temp & 0x200)
320 jreg07 |= 0x40;
321 if (temp & 0x400)
322 jregAE |= 0x02;
323 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x12, 0x00, temp);
324
325 temp = mode->crtc_vblank_start - 1;
326 if (temp & 0x100)
327 jreg07 |= 0x08;
328 if (temp & 0x200)
329 jreg09 |= 0x20;
330 if (temp & 0x400)
331 jregAE |= 0x04;
332 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x15, 0x00, temp);
333
334 temp = mode->crtc_vblank_end - 1;
335 if (temp & 0x100)
336 jregAE |= 0x10;
337 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x16, 0x00, temp);
338
339 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x07, 0x00, jreg07);
340 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x09, 0xdf, jreg09);
341 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAE, 0x00, (jregAE | 0x80));
342
343 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x80);
344}
345
346static void ast_set_offset_reg(struct drm_crtc *crtc)
347{
348 struct ast_private *ast = crtc->dev->dev_private;
349
350 u16 offset;
351
f4510a27 352 offset = crtc->primary->fb->pitches[0] >> 3;
312fec14
DA		 353 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x13, (offset & 0xff));
354 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xb0, (offset >> 8) & 0x3f);
355}
356
357static void ast_set_dclk_reg(struct drm_device *dev, struct drm_display_mode *mode,
358 struct ast_vbios_mode_info *vbios_mode)
359{
360 struct ast_private *ast = dev->dev_private;
361 struct ast_vbios_dclk_info *clk_info;
362
363 clk_info = &dclk_table[vbios_mode->enh_table->dclk_index];
364
365 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1);
366 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2);
367 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xbb, 0x0f,
368 (clk_info->param3 & 0x80) | ((clk_info->param3 & 0x3) << 4));
369}
370
371static void ast_set_ext_reg(struct drm_crtc *crtc, struct drm_display_mode *mode,
372 struct ast_vbios_mode_info *vbios_mode)
373{
374 struct ast_private *ast = crtc->dev->dev_private;
375 u8 jregA0 = 0, jregA3 = 0, jregA8 = 0;
376
f4510a27 377 switch (crtc->primary->fb->bits_per_pixel) {
312fec14
DA		 378 case 8:
379 jregA0 = 0x70;
380 jregA3 = 0x01;
381 jregA8 = 0x00;
382 break;
383 case 15:
384 case 16:
385 jregA0 = 0x70;
386 jregA3 = 0x04;
387 jregA8 = 0x02;
388 break;
389 case 32:
390 jregA0 = 0x70;
391 jregA3 = 0x08;
392 jregA8 = 0x02;
393 break;
394 }
395
396 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa0, 0x8f, jregA0);
397 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xf0, jregA3);
398 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8);
399
400 /* Set Threshold */
1453bf4c 401 if (ast->chip == AST2300 || ast->chip == AST2400) {
312fec14
DA		 402 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78);
403 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60);
404 } else if (ast->chip == AST2100 ||
405 ast->chip == AST1100 ||
406 ast->chip == AST2200 ||
407 ast->chip == AST2150) {
408 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x3f);
409 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x2f);
410 } else {
411 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x2f);
412 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x1f);
413 }
414}
415
7f5ccd44 416static void ast_set_sync_reg(struct drm_device *dev, struct drm_display_mode *mode,
312fec14
DA		 417 struct ast_vbios_mode_info *vbios_mode)
418{
419 struct ast_private *ast = dev->dev_private;
420 u8 jreg;
421
422 jreg = ast_io_read8(ast, AST_IO_MISC_PORT_READ);
423 jreg |= (vbios_mode->enh_table->flags & SyncNN);
424 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg);
425}
426
7f5ccd44 427static bool ast_set_dac_reg(struct drm_crtc *crtc, struct drm_display_mode *mode,
312fec14
DA		 428 struct ast_vbios_mode_info *vbios_mode)
429{
f4510a27 430 switch (crtc->primary->fb->bits_per_pixel) {
312fec14
DA		 431 case 8:
432 break;
433 default:
434 return false;
435 }
436 return true;
437}
438
7f5ccd44 439static void ast_set_start_address_crt1(struct drm_crtc *crtc, unsigned offset)
312fec14
DA		 440{
441 struct ast_private *ast = crtc->dev->dev_private;
442 u32 addr;
443
444 addr = offset >> 2;
445 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0d, (u8)(addr & 0xff));
446 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0c, (u8)((addr >> 8) & 0xff));
447 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xaf, (u8)((addr >> 16) & 0xff));
448
449}
450
451static void ast_crtc_dpms(struct drm_crtc *crtc, int mode)
452{
453 struct ast_private *ast = crtc->dev->dev_private;
454
455 if (ast->chip == AST1180)
456 return;
457
458 switch (mode) {
459 case DRM_MODE_DPMS_ON:
460 case DRM_MODE_DPMS_STANDBY:
461 case DRM_MODE_DPMS_SUSPEND:
462 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0);
83c6620b
DA		 463 if (ast->tx_chip_type == AST_TX_DP501)
464 ast_set_dp501_video_output(crtc->dev, 1);
312fec14
DA		 465 ast_crtc_load_lut(crtc);
466 break;
467 case DRM_MODE_DPMS_OFF:
83c6620b
DA		 468 if (ast->tx_chip_type == AST_TX_DP501)
469 ast_set_dp501_video_output(crtc->dev, 0);
312fec14
DA		 470 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x20);
471 break;
472 }
473}
474
475static bool ast_crtc_mode_fixup(struct drm_crtc *crtc,
e811f5ae
LP		 476 const struct drm_display_mode *mode,
477 struct drm_display_mode *adjusted_mode)
312fec14
DA		 478{
479 return true;
480}
481
482/* ast is different - we will force move buffers out of VRAM */
483static int ast_crtc_do_set_base(struct drm_crtc *crtc,
484 struct drm_framebuffer *fb,
485 int x, int y, int atomic)
486{
487 struct ast_private *ast = crtc->dev->dev_private;
488 struct drm_gem_object *obj;
489 struct ast_framebuffer *ast_fb;
490 struct ast_bo *bo;
491 int ret;
492 u64 gpu_addr;
493
494 /* push the previous fb to system ram */
495 if (!atomic && fb) {
496 ast_fb = to_ast_framebuffer(fb);
497 obj = ast_fb->obj;
498 bo = gem_to_ast_bo(obj);
499 ret = ast_bo_reserve(bo, false);
500 if (ret)
501 return ret;
502 ast_bo_push_sysram(bo);
503 ast_bo_unreserve(bo);
504 }
505
f4510a27 506 ast_fb = to_ast_framebuffer(crtc->primary->fb);
312fec14
DA		 507 obj = ast_fb->obj;
508 bo = gem_to_ast_bo(obj);
509
510 ret = ast_bo_reserve(bo, false);
511 if (ret)
512 return ret;
513
514 ret = ast_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr);
515 if (ret) {
516 ast_bo_unreserve(bo);
517 return ret;
518 }
519
520 if (&ast->fbdev->afb == ast_fb) {
521 /* if pushing console in kmap it */
522 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap);
523 if (ret)
524 DRM_ERROR("failed to kmap fbcon\n");
525 }
526 ast_bo_unreserve(bo);
527
528 ast_set_start_address_crt1(crtc, (u32)gpu_addr);
529
530 return 0;
531}
532
533static int ast_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
534 struct drm_framebuffer *old_fb)
535{
536 return ast_crtc_do_set_base(crtc, old_fb, x, y, 0);
537}
538
539static int ast_crtc_mode_set(struct drm_crtc *crtc,
540 struct drm_display_mode *mode,
541 struct drm_display_mode *adjusted_mode,
542 int x, int y,
543 struct drm_framebuffer *old_fb)
544{
545 struct drm_device *dev = crtc->dev;
546 struct ast_private *ast = crtc->dev->dev_private;
547 struct ast_vbios_mode_info vbios_mode;
548 bool ret;
549 if (ast->chip == AST1180) {
550 DRM_ERROR("AST 1180 modesetting not supported\n");
551 return -EINVAL;
552 }
553
554 ret = ast_get_vbios_mode_info(crtc, mode, adjusted_mode, &vbios_mode);
555 if (ret == false)
556 return -EINVAL;
557 ast_open_key(ast);
558
559 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x04);
560
561 ast_set_std_reg(crtc, adjusted_mode, &vbios_mode);
562 ast_set_crtc_reg(crtc, adjusted_mode, &vbios_mode);
563 ast_set_offset_reg(crtc);
564 ast_set_dclk_reg(dev, adjusted_mode, &vbios_mode);
565 ast_set_ext_reg(crtc, adjusted_mode, &vbios_mode);
566 ast_set_sync_reg(dev, adjusted_mode, &vbios_mode);
567 ast_set_dac_reg(crtc, adjusted_mode, &vbios_mode);
568
569 ast_crtc_mode_set_base(crtc, x, y, old_fb);
570
571 return 0;
572}
573
574static void ast_crtc_disable(struct drm_crtc *crtc)
575{
576
577}
578
579static void ast_crtc_prepare(struct drm_crtc *crtc)
580{
581
582}
583
584static void ast_crtc_commit(struct drm_crtc *crtc)
585{
586 struct ast_private *ast = crtc->dev->dev_private;
587 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0);
588}
589
590
591static const struct drm_crtc_helper_funcs ast_crtc_helper_funcs = {
592 .dpms = ast_crtc_dpms,
593 .mode_fixup = ast_crtc_mode_fixup,
594 .mode_set = ast_crtc_mode_set,
595 .mode_set_base = ast_crtc_mode_set_base,
596 .disable = ast_crtc_disable,
597 .load_lut = ast_crtc_load_lut,
312fec14
DA		 598 .prepare = ast_crtc_prepare,
599 .commit = ast_crtc_commit,
600
601};
602
603static void ast_crtc_reset(struct drm_crtc *crtc)
604{
605
606}
607
608static void ast_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
609 u16 *blue, uint32_t start, uint32_t size)
610{
611 struct ast_crtc *ast_crtc = to_ast_crtc(crtc);
612 int end = (start + size > 256) ? 256 : start + size, i;
613
614 /* userspace palettes are always correct as is */
615 for (i = start; i < end; i++) {
616 ast_crtc->lut_r[i] = red[i] >> 8;
617 ast_crtc->lut_g[i] = green[i] >> 8;
618 ast_crtc->lut_b[i] = blue[i] >> 8;
619 }
620 ast_crtc_load_lut(crtc);
621}
622
623
624static void ast_crtc_destroy(struct drm_crtc *crtc)
625{
626 drm_crtc_cleanup(crtc);
627 kfree(crtc);
628}
629
630static const struct drm_crtc_funcs ast_crtc_funcs = {
631 .cursor_set = ast_cursor_set,
632 .cursor_move = ast_cursor_move,
633 .reset = ast_crtc_reset,
634 .set_config = drm_crtc_helper_set_config,
635 .gamma_set = ast_crtc_gamma_set,
636 .destroy = ast_crtc_destroy,
637};
638
7f5ccd44 639static int ast_crtc_init(struct drm_device *dev)
312fec14
DA		 640{
641 struct ast_crtc *crtc;
642 int i;
643
644 crtc = kzalloc(sizeof(struct ast_crtc), GFP_KERNEL);
645 if (!crtc)
646 return -ENOMEM;
647
648 drm_crtc_init(dev, &crtc->base, &ast_crtc_funcs);
649 drm_mode_crtc_set_gamma_size(&crtc->base, 256);
650 drm_crtc_helper_add(&crtc->base, &ast_crtc_helper_funcs);
651
652 for (i = 0; i < 256; i++) {
653 crtc->lut_r[i] = i;
654 crtc->lut_g[i] = i;
655 crtc->lut_b[i] = i;
656 }
657 return 0;
658}
659
660static void ast_encoder_destroy(struct drm_encoder *encoder)
661{
662 drm_encoder_cleanup(encoder);
663 kfree(encoder);
664}
665
666
667static struct drm_encoder *ast_best_single_encoder(struct drm_connector *connector)
668{
669 int enc_id = connector->encoder_ids[0];
670 struct drm_mode_object *obj;
671 struct drm_encoder *encoder;
672
673 /* pick the encoder ids */
674 if (enc_id) {
675 obj = drm_mode_object_find(connector->dev, enc_id, DRM_MODE_OBJECT_ENCODER);
676 if (!obj)
677 return NULL;
678 encoder = obj_to_encoder(obj);
679 return encoder;
680 }
681 return NULL;
682}
683
684
685static const struct drm_encoder_funcs ast_enc_funcs = {
686 .destroy = ast_encoder_destroy,
687};
688
689static void ast_encoder_dpms(struct drm_encoder *encoder, int mode)
690{
691
692}
693
694static bool ast_mode_fixup(struct drm_encoder *encoder,
e811f5ae 695 const struct drm_display_mode *mode,
312fec14
DA		 696 struct drm_display_mode *adjusted_mode)
697{
698 return true;
699}
700
701static void ast_encoder_mode_set(struct drm_encoder *encoder,
702 struct drm_display_mode *mode,
703 struct drm_display_mode *adjusted_mode)
704{
705}
706
707static void ast_encoder_prepare(struct drm_encoder *encoder)
708{
709
710}
711
712static void ast_encoder_commit(struct drm_encoder *encoder)
713{
714
715}
716
717
718static const struct drm_encoder_helper_funcs ast_enc_helper_funcs = {
719 .dpms = ast_encoder_dpms,
720 .mode_fixup = ast_mode_fixup,
721 .prepare = ast_encoder_prepare,
722 .commit = ast_encoder_commit,
723 .mode_set = ast_encoder_mode_set,
724};
725
7f5ccd44 726static int ast_encoder_init(struct drm_device *dev)
312fec14
DA		 727{
728 struct ast_encoder *ast_encoder;
729
730 ast_encoder = kzalloc(sizeof(struct ast_encoder), GFP_KERNEL);
731 if (!ast_encoder)
732 return -ENOMEM;
733
734 drm_encoder_init(dev, &ast_encoder->base, &ast_enc_funcs,
735 DRM_MODE_ENCODER_DAC);
736 drm_encoder_helper_add(&ast_encoder->base, &ast_enc_helper_funcs);
737
738 ast_encoder->base.possible_crtcs = 1;
739 return 0;
740}
741
742static int ast_get_modes(struct drm_connector *connector)
743{
744 struct ast_connector *ast_connector = to_ast_connector(connector);
83c6620b 745 struct ast_private *ast = connector->dev->dev_private;
312fec14
DA		 746 struct edid *edid;
747 int ret;
83c6620b
DA		 748 bool flags = false;
749 if (ast->tx_chip_type == AST_TX_DP501) {
750 ast->dp501_maxclk = 0xff;
751 edid = kmalloc(128, GFP_KERNEL);
752 if (!edid)
753 return -ENOMEM;
754
755 flags = ast_dp501_read_edid(connector->dev, (u8 *)edid);
756 if (flags)
757 ast->dp501_maxclk = ast_get_dp501_max_clk(connector->dev);
758 else
759 kfree(edid);
760 }
761 if (!flags)
762 edid = drm_get_edid(connector, &ast_connector->i2c->adapter);
312fec14
DA		 763 if (edid) {
764 drm_mode_connector_update_edid_property(&ast_connector->base, edid);
765 ret = drm_add_edid_modes(connector, edid);
993dcb05 766 kfree(edid);
312fec14
DA		 767 return ret;
768 } else
769 drm_mode_connector_update_edid_property(&ast_connector->base, NULL);
770 return 0;
771}
772
773static int ast_mode_valid(struct drm_connector *connector,
774 struct drm_display_mode *mode)
775{
f1f62f2c
DA		 776 struct ast_private *ast = connector->dev->dev_private;
777 int flags = MODE_NOMODE;
778 uint32_t jtemp;
779
780 if (ast->support_wide_screen) {
781 if ((mode->hdisplay == 1680) && (mode->vdisplay == 1050))
782 return MODE_OK;
783 if ((mode->hdisplay == 1280) && (mode->vdisplay == 800))
784 return MODE_OK;
785 if ((mode->hdisplay == 1440) && (mode->vdisplay == 900))
786 return MODE_OK;
787 if ((mode->hdisplay == 1360) && (mode->vdisplay == 768))
788 return MODE_OK;
789 if ((mode->hdisplay == 1600) && (mode->vdisplay == 900))
790 return MODE_OK;
791
1453bf4c 792 if ((ast->chip == AST2100) || (ast->chip == AST2200) || (ast->chip == AST2300) || (ast->chip == AST2400) || (ast->chip == AST1180)) {
f1f62f2c
DA		 793 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1080))
794 return MODE_OK;
795
796 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1200)) {
797 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
798 if (jtemp & 0x01)
799 return MODE_NOMODE;
800 else
801 return MODE_OK;
802 }
803 }
804 }
805 switch (mode->hdisplay) {
806 case 640:
807 if (mode->vdisplay == 480) flags = MODE_OK;
808 break;
809 case 800:
810 if (mode->vdisplay == 600) flags = MODE_OK;
811 break;
812 case 1024:
813 if (mode->vdisplay == 768) flags = MODE_OK;
814 break;
815 case 1280:
816 if (mode->vdisplay == 1024) flags = MODE_OK;
817 break;
818 case 1600:
819 if (mode->vdisplay == 1200) flags = MODE_OK;
820 break;
821 default:
822 return flags;
823 }
824
825 return flags;
312fec14
DA		 826}
827
828static void ast_connector_destroy(struct drm_connector *connector)
829{
830 struct ast_connector *ast_connector = to_ast_connector(connector);
831 ast_i2c_destroy(ast_connector->i2c);
34ea3d38 832 drm_connector_unregister(connector);
312fec14
DA		 833 drm_connector_cleanup(connector);
834 kfree(connector);
835}
836
837static enum drm_connector_status
838ast_connector_detect(struct drm_connector *connector, bool force)
839{
840 return connector_status_connected;
841}
842
843static const struct drm_connector_helper_funcs ast_connector_helper_funcs = {
844 .mode_valid = ast_mode_valid,
845 .get_modes = ast_get_modes,
846 .best_encoder = ast_best_single_encoder,
847};
848
849static const struct drm_connector_funcs ast_connector_funcs = {
850 .dpms = drm_helper_connector_dpms,
851 .detect = ast_connector_detect,
852 .fill_modes = drm_helper_probe_single_connector_modes,
853 .destroy = ast_connector_destroy,
854};
855
7f5ccd44 856static int ast_connector_init(struct drm_device *dev)
312fec14
DA		 857{
858 struct ast_connector *ast_connector;
859 struct drm_connector *connector;
860 struct drm_encoder *encoder;
861
862 ast_connector = kzalloc(sizeof(struct ast_connector), GFP_KERNEL);
863 if (!ast_connector)
864 return -ENOMEM;
865
866 connector = &ast_connector->base;
867 drm_connector_init(dev, connector, &ast_connector_funcs, DRM_MODE_CONNECTOR_VGA);
868
869 drm_connector_helper_add(connector, &ast_connector_helper_funcs);
870
871 connector->interlace_allowed = 0;
872 connector->doublescan_allowed = 0;
873
34ea3d38 874 drm_connector_register(connector);
312fec14
DA		 875
876 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
877
878 encoder = list_first_entry(&dev->mode_config.encoder_list, struct drm_encoder, head);
879 drm_mode_connector_attach_encoder(connector, encoder);
880
881 ast_connector->i2c = ast_i2c_create(dev);
882 if (!ast_connector->i2c)
883 DRM_ERROR("failed to add ddc bus for connector\n");
884
885 return 0;
886}
887
888/* allocate cursor cache and pin at start of VRAM */
7f5ccd44 889static int ast_cursor_init(struct drm_device *dev)
312fec14
DA		 890{
891 struct ast_private *ast = dev->dev_private;
892 int size;
893 int ret;
894 struct drm_gem_object *obj;
895 struct ast_bo *bo;
896 uint64_t gpu_addr;
897
898 size = (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE) * AST_DEFAULT_HWC_NUM;
899
900 ret = ast_gem_create(dev, size, true, &obj);
901 if (ret)
902 return ret;
903 bo = gem_to_ast_bo(obj);
904 ret = ast_bo_reserve(bo, false);
905 if (unlikely(ret != 0))
906 goto fail;
907
908 ret = ast_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr);
909 ast_bo_unreserve(bo);
910 if (ret)
911 goto fail;
912
913 /* kmap the object */
914 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &ast->cache_kmap);
915 if (ret)
916 goto fail;
917
918 ast->cursor_cache = obj;
919 ast->cursor_cache_gpu_addr = gpu_addr;
0273de08 920 DRM_DEBUG_KMS("pinned cursor cache at %llx\n", ast->cursor_cache_gpu_addr);
312fec14
DA		 921 return 0;
922fail:
923 return ret;
924}
925
7f5ccd44 926static void ast_cursor_fini(struct drm_device *dev)
312fec14
DA		 927{
928 struct ast_private *ast = dev->dev_private;
929 ttm_bo_kunmap(&ast->cache_kmap);
930 drm_gem_object_unreference_unlocked(ast->cursor_cache);
931}
932
933int ast_mode_init(struct drm_device *dev)
934{
935 ast_cursor_init(dev);
936 ast_crtc_init(dev);
937 ast_encoder_init(dev);
938 ast_connector_init(dev);
939 return 0;
940}
941
942void ast_mode_fini(struct drm_device *dev)
943{
944 ast_cursor_fini(dev);
945}
946
947static int get_clock(void *i2c_priv)
948{
949 struct ast_i2c_chan *i2c = i2c_priv;
950 struct ast_private *ast = i2c->dev->dev_private;
951 uint32_t val;
952
953 val = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4;
954 return val & 1 ? 1 : 0;
955}
956
957static int get_data(void *i2c_priv)
958{
959 struct ast_i2c_chan *i2c = i2c_priv;
960 struct ast_private *ast = i2c->dev->dev_private;
961 uint32_t val;
962
963 val = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5;
964 return val & 1 ? 1 : 0;
965}
966
967static void set_clock(void *i2c_priv, int clock)
968{
969 struct ast_i2c_chan *i2c = i2c_priv;
970 struct ast_private *ast = i2c->dev->dev_private;
971 int i;
972 u8 ujcrb7, jtemp;
973
974 for (i = 0; i < 0x10000; i++) {
975 ujcrb7 = ((clock & 0x01) ? 0 : 1);
976 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xfe, ujcrb7);
977 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x01);
978 if (ujcrb7 == jtemp)
979 break;
980 }
981}
982
983static void set_data(void *i2c_priv, int data)
984{
985 struct ast_i2c_chan *i2c = i2c_priv;
986 struct ast_private *ast = i2c->dev->dev_private;
987 int i;
988 u8 ujcrb7, jtemp;
989
990 for (i = 0; i < 0x10000; i++) {
991 ujcrb7 = ((data & 0x01) ? 0 : 1) << 2;
992 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xfb, ujcrb7);
993 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x04);
994 if (ujcrb7 == jtemp)
995 break;
996 }
997}
998
999static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev)
1000{
1001 struct ast_i2c_chan *i2c;
1002 int ret;
1003
1004 i2c = kzalloc(sizeof(struct ast_i2c_chan), GFP_KERNEL);
1005 if (!i2c)
1006 return NULL;
1007
1008 i2c->adapter.owner = THIS_MODULE;
1009 i2c->adapter.class = I2C_CLASS_DDC;
1010 i2c->adapter.dev.parent = &dev->pdev->dev;
1011 i2c->dev = dev;
1012 i2c_set_adapdata(&i2c->adapter, i2c);
1013 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
1014 "AST i2c bit bus");
1015 i2c->adapter.algo_data = &i2c->bit;
1016
1017 i2c->bit.udelay = 20;
1018 i2c->bit.timeout = 2;
1019 i2c->bit.data = i2c;
1020 i2c->bit.setsda = set_data;
1021 i2c->bit.setscl = set_clock;
1022 i2c->bit.getsda = get_data;
1023 i2c->bit.getscl = get_clock;
1024 ret = i2c_bit_add_bus(&i2c->adapter);
1025 if (ret) {
1026 DRM_ERROR("Failed to register bit i2c\n");
1027 goto out_free;
1028 }
1029
1030 return i2c;
1031out_free:
1032 kfree(i2c);
1033 return NULL;
1034}
1035
1036static void ast_i2c_destroy(struct ast_i2c_chan *i2c)
1037{
1038 if (!i2c)
1039 return;
1040 i2c_del_adapter(&i2c->adapter);
1041 kfree(i2c);
1042}
1043
7f5ccd44 1044static void ast_show_cursor(struct drm_crtc *crtc)
312fec14
DA		 1045{
1046 struct ast_private *ast = crtc->dev->dev_private;
1047 u8 jreg;
1048
1049 jreg = 0x2;
1050 /* enable ARGB cursor */
1051 jreg |= 1;
1052 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, jreg);
1053}
1054
7f5ccd44 1055static void ast_hide_cursor(struct drm_crtc *crtc)
312fec14
DA		 1056{
1057 struct ast_private *ast = crtc->dev->dev_private;
1058 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, 0x00);
1059}
1060
1061static u32 copy_cursor_image(u8 *src, u8 *dst, int width, int height)
1062{
1063 union {
1064 u32 ul;
1065 u8 b[4];
1066 } srcdata32[2], data32;
1067 union {
1068 u16 us;
1069 u8 b[2];
1070 } data16;
1071 u32 csum = 0;
1072 s32 alpha_dst_delta, last_alpha_dst_delta;
1073 u8 *srcxor, *dstxor;
1074 int i, j;
1075 u32 per_pixel_copy, two_pixel_copy;
1076
1077 alpha_dst_delta = AST_MAX_HWC_WIDTH << 1;
1078 last_alpha_dst_delta = alpha_dst_delta - (width << 1);
1079
1080 srcxor = src;
1081 dstxor = (u8 *)dst + last_alpha_dst_delta + (AST_MAX_HWC_HEIGHT - height) * alpha_dst_delta;
1082 per_pixel_copy = width & 1;
1083 two_pixel_copy = width >> 1;
1084
1085 for (j = 0; j < height; j++) {
1086 for (i = 0; i < two_pixel_copy; i++) {
1087 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0;
1088 srcdata32[1].ul = *((u32 *)(srcxor + 4)) & 0xf0f0f0f0;
1089 data32.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4);
1090 data32.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4);
1091 data32.b[2] = srcdata32[0].b[1] | (srcdata32[1].b[0] >> 4);
1092 data32.b[3] = srcdata32[0].b[3] | (srcdata32[1].b[2] >> 4);
1093
1094 writel(data32.ul, dstxor);
1095 csum += data32.ul;
1096
1097 dstxor += 4;
1098 srcxor += 8;
1099
1100 }
1101
1102 for (i = 0; i < per_pixel_copy; i++) {
1103 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0;
1104 data16.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4);
1105 data16.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4);
1106 writew(data16.us, dstxor);
1107 csum += (u32)data16.us;
1108
1109 dstxor += 2;
1110 srcxor += 4;
1111 }
1112 dstxor += last_alpha_dst_delta;
1113 }
1114 return csum;
1115}
1116
1117static int ast_cursor_set(struct drm_crtc *crtc,
1118 struct drm_file *file_priv,
1119 uint32_t handle,
1120 uint32_t width,
1121 uint32_t height)
1122{
1123 struct ast_private *ast = crtc->dev->dev_private;
1124 struct ast_crtc *ast_crtc = to_ast_crtc(crtc);
1125 struct drm_gem_object *obj;
1126 struct ast_bo *bo;
1127 uint64_t gpu_addr;
1128 u32 csum;
1129 int ret;
1130 struct ttm_bo_kmap_obj uobj_map;
1131 u8 *src, *dst;
1132 bool src_isiomem, dst_isiomem;
1133 if (!handle) {
1134 ast_hide_cursor(crtc);
1135 return 0;
1136 }
1137
1138 if (width > AST_MAX_HWC_WIDTH || height > AST_MAX_HWC_HEIGHT)
1139 return -EINVAL;
1140
1141 obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
1142 if (!obj) {
1143 DRM_ERROR("Cannot find cursor object %x for crtc\n", handle);
1144 return -ENOENT;
1145 }
1146 bo = gem_to_ast_bo(obj);
1147
1148 ret = ast_bo_reserve(bo, false);
1149 if (ret)
1150 goto fail;
1151
1152 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &uobj_map);
1153
1154 src = ttm_kmap_obj_virtual(&uobj_map, &src_isiomem);
1155 dst = ttm_kmap_obj_virtual(&ast->cache_kmap, &dst_isiomem);
1156
1157 if (src_isiomem == true)
1158 DRM_ERROR("src cursor bo should be in main memory\n");
1159 if (dst_isiomem == false)
1160 DRM_ERROR("dst bo should be in VRAM\n");
1161
1162 dst += (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor;
1163
1164 /* do data transfer to cursor cache */
1165 csum = copy_cursor_image(src, dst, width, height);
1166
1167 /* write checksum + signature */
1168 ttm_bo_kunmap(&uobj_map);
1169 ast_bo_unreserve(bo);
1170 {
1171 u8 *dst = (u8 *)ast->cache_kmap.virtual + (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor + AST_HWC_SIZE;
1172 writel(csum, dst);
1173 writel(width, dst + AST_HWC_SIGNATURE_SizeX);
1174 writel(height, dst + AST_HWC_SIGNATURE_SizeY);
1175 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTX);
1176 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTY);
1177
1178 /* set pattern offset */
1179 gpu_addr = ast->cursor_cache_gpu_addr;
1180 gpu_addr += (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor;
1181 gpu_addr >>= 3;
1182 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc8, gpu_addr & 0xff);
1183 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc9, (gpu_addr >> 8) & 0xff);
1184 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xca, (gpu_addr >> 16) & 0xff);
1185 }
1186 ast_crtc->cursor_width = width;
1187 ast_crtc->cursor_height = height;
1188 ast_crtc->offset_x = AST_MAX_HWC_WIDTH - width;
1189 ast_crtc->offset_y = AST_MAX_HWC_WIDTH - height;
1190
1191 ast->next_cursor = (ast->next_cursor + 1) % AST_DEFAULT_HWC_NUM;
1192
1193 ast_show_cursor(crtc);
1194
1195 drm_gem_object_unreference_unlocked(obj);
1196 return 0;
1197fail:
1198 drm_gem_object_unreference_unlocked(obj);
1199 return ret;
1200}
1201
1202static int ast_cursor_move(struct drm_crtc *crtc,
1203 int x, int y)
1204{
1205 struct ast_crtc *ast_crtc = to_ast_crtc(crtc);
1206 struct ast_private *ast = crtc->dev->dev_private;
1207 int x_offset, y_offset;
1208 u8 *sig;
1209
1210 sig = (u8 *)ast->cache_kmap.virtual + (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor + AST_HWC_SIZE;
1211 writel(x, sig + AST_HWC_SIGNATURE_X);
1212 writel(y, sig + AST_HWC_SIGNATURE_Y);
1213
1214 x_offset = ast_crtc->offset_x;
1215 y_offset = ast_crtc->offset_y;
1216 if (x < 0) {
1217 x_offset = (-x) + ast_crtc->offset_x;
1218 x = 0;
1219 }
1220
1221 if (y < 0) {
1222 y_offset = (-y) + ast_crtc->offset_y;
1223 y = 0;
1224 }
1225 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc2, x_offset);
1226 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc3, y_offset);
1227 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc4, (x & 0xff));
1228 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc5, ((x >> 8) & 0x0f));
1229 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc6, (y & 0xff));
1230 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc7, ((y >> 8) & 0x07));
1231
1232 /* dummy write to fire HWC */
1233 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xCB, 0xFF, 0x00);
1234
1235 return 0;
1236}
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