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[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / ast / ast_mode.c
CommitLineData
312fec14
DA		 1/*
2 * Copyright 2012 Red Hat Inc.
3 * Parts based on xf86-video-ast
4 * Copyright (c) 2005 ASPEED Technology Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
18 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
19 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
24 * of the Software.
25 *
26 */
27/*
28 * Authors: Dave Airlie <airlied@redhat.com>
29 */
30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
3cb9ae4f 34#include <drm/drm_plane_helper.h>
312fec14
DA		 35#include "ast_drv.h"
36
37#include "ast_tables.h"
38
39static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev);
40static void ast_i2c_destroy(struct ast_i2c_chan *i2c);
41static int ast_cursor_set(struct drm_crtc *crtc,
42 struct drm_file *file_priv,
43 uint32_t handle,
44 uint32_t width,
45 uint32_t height);
46static int ast_cursor_move(struct drm_crtc *crtc,
47 int x, int y);
48
49static inline void ast_load_palette_index(struct ast_private *ast,
50 u8 index, u8 red, u8 green,
51 u8 blue)
52{
53 ast_io_write8(ast, AST_IO_DAC_INDEX_WRITE, index);
54 ast_io_read8(ast, AST_IO_SEQ_PORT);
55 ast_io_write8(ast, AST_IO_DAC_DATA, red);
56 ast_io_read8(ast, AST_IO_SEQ_PORT);
57 ast_io_write8(ast, AST_IO_DAC_DATA, green);
58 ast_io_read8(ast, AST_IO_SEQ_PORT);
59 ast_io_write8(ast, AST_IO_DAC_DATA, blue);
60 ast_io_read8(ast, AST_IO_SEQ_PORT);
61}
62
63static void ast_crtc_load_lut(struct drm_crtc *crtc)
64{
65 struct ast_private *ast = crtc->dev->dev_private;
3bffd962 66 u16 *r, *g, *b;
312fec14
DA		 67 int i;
68
69 if (!crtc->enabled)
70 return;
71
3bffd962
PR		 72 r = crtc->gamma_store;
73 g = r + crtc->gamma_size;
74 b = g + crtc->gamma_size;
75
312fec14 76 for (i = 0; i < 256; i++)
3bffd962 77 ast_load_palette_index(ast, i, *r++ >> 8, *g++ >> 8, *b++ >> 8);
312fec14
DA		 78}
79
80static bool ast_get_vbios_mode_info(struct drm_crtc *crtc, struct drm_display_mode *mode,
81 struct drm_display_mode *adjusted_mode,
82 struct ast_vbios_mode_info *vbios_mode)
83{
84 struct ast_private *ast = crtc->dev->dev_private;
7445283a 85 const struct drm_framebuffer *fb = crtc->primary->fb;
312fec14 86 u32 refresh_rate_index = 0, mode_id, color_index, refresh_rate;
22acdbb1 87 const struct ast_vbios_enhtable *best = NULL;
312fec14 88 u32 hborder, vborder;
94d12b13 89 bool check_sync;
312fec14 90
272725c7 91 switch (fb->format->cpp[0] * 8) {
312fec14
DA		 92 case 8:
93 vbios_mode->std_table = &vbios_stdtable[VGAModeIndex];
94 color_index = VGAModeIndex - 1;
95 break;
96 case 16:
97 vbios_mode->std_table = &vbios_stdtable[HiCModeIndex];
98 color_index = HiCModeIndex;
99 break;
100 case 24:
101 case 32:
102 vbios_mode->std_table = &vbios_stdtable[TrueCModeIndex];
103 color_index = TrueCModeIndex;
104 break;
105 default:
106 return false;
107 }
108
109 switch (crtc->mode.crtc_hdisplay) {
110 case 640:
111 vbios_mode->enh_table = &res_640x480[refresh_rate_index];
112 break;
113 case 800:
114 vbios_mode->enh_table = &res_800x600[refresh_rate_index];
115 break;
116 case 1024:
117 vbios_mode->enh_table = &res_1024x768[refresh_rate_index];
118 break;
119 case 1280:
120 if (crtc->mode.crtc_vdisplay == 800)
121 vbios_mode->enh_table = &res_1280x800[refresh_rate_index];
122 else
123 vbios_mode->enh_table = &res_1280x1024[refresh_rate_index];
124 break;
f1f62f2c
DA		 125 case 1360:
126 vbios_mode->enh_table = &res_1360x768[refresh_rate_index];
127 break;
312fec14
DA		 128 case 1440:
129 vbios_mode->enh_table = &res_1440x900[refresh_rate_index];
130 break;
131 case 1600:
f1f62f2c
DA		 132 if (crtc->mode.crtc_vdisplay == 900)
133 vbios_mode->enh_table = &res_1600x900[refresh_rate_index];
134 else
135 vbios_mode->enh_table = &res_1600x1200[refresh_rate_index];
312fec14
DA		 136 break;
137 case 1680:
138 vbios_mode->enh_table = &res_1680x1050[refresh_rate_index];
139 break;
140 case 1920:
141 if (crtc->mode.crtc_vdisplay == 1080)
142 vbios_mode->enh_table = &res_1920x1080[refresh_rate_index];
143 else
144 vbios_mode->enh_table = &res_1920x1200[refresh_rate_index];
145 break;
146 default:
147 return false;
148 }
149
150 refresh_rate = drm_mode_vrefresh(mode);
94d12b13
C		 151 check_sync = vbios_mode->enh_table->flags & WideScreenMode;
152 do {
22acdbb1 153 const struct ast_vbios_enhtable *loop = vbios_mode->enh_table;
94d12b13
C		 154
155 while (loop->refresh_rate != 0xff) {
156 if ((check_sync) &&
157 (((mode->flags & DRM_MODE_FLAG_NVSYNC) &&
158 (loop->flags & PVSync)) ||
159 ((mode->flags & DRM_MODE_FLAG_PVSYNC) &&
160 (loop->flags & NVSync)) ||
161 ((mode->flags & DRM_MODE_FLAG_NHSYNC) &&
162 (loop->flags & PHSync)) ||
163 ((mode->flags & DRM_MODE_FLAG_PHSYNC) &&
164 (loop->flags & NHSync)))) {
165 loop++;
166 continue;
167 }
168 if (loop->refresh_rate <= refresh_rate
169 && (!best || loop->refresh_rate > best->refresh_rate))
170 best = loop;
171 loop++;
312fec14 172 }
94d12b13
C		 173 if (best || !check_sync)
174 break;
175 check_sync = 0;
176 } while (1);
177 if (best)
178 vbios_mode->enh_table = best;
312fec14
DA		 179
180 hborder = (vbios_mode->enh_table->flags & HBorder) ? 8 : 0;
181 vborder = (vbios_mode->enh_table->flags & VBorder) ? 8 : 0;
182
183 adjusted_mode->crtc_htotal = vbios_mode->enh_table->ht;
184 adjusted_mode->crtc_hblank_start = vbios_mode->enh_table->hde + hborder;
185 adjusted_mode->crtc_hblank_end = vbios_mode->enh_table->ht - hborder;
186 adjusted_mode->crtc_hsync_start = vbios_mode->enh_table->hde + hborder +
187 vbios_mode->enh_table->hfp;
188 adjusted_mode->crtc_hsync_end = (vbios_mode->enh_table->hde + hborder +
189 vbios_mode->enh_table->hfp +
190 vbios_mode->enh_table->hsync);
191
192 adjusted_mode->crtc_vtotal = vbios_mode->enh_table->vt;
193 adjusted_mode->crtc_vblank_start = vbios_mode->enh_table->vde + vborder;
194 adjusted_mode->crtc_vblank_end = vbios_mode->enh_table->vt - vborder;
195 adjusted_mode->crtc_vsync_start = vbios_mode->enh_table->vde + vborder +
196 vbios_mode->enh_table->vfp;
197 adjusted_mode->crtc_vsync_end = (vbios_mode->enh_table->vde + vborder +
198 vbios_mode->enh_table->vfp +
199 vbios_mode->enh_table->vsync);
200
201 refresh_rate_index = vbios_mode->enh_table->refresh_rate_index;
202 mode_id = vbios_mode->enh_table->mode_id;
203
204 if (ast->chip == AST1180) {
205 /* TODO 1180 */
206 } else {
207 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8c, (u8)((color_index & 0xf) << 4));
208 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8d, refresh_rate_index & 0xff);
209 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8e, mode_id & 0xff);
210
f1f62f2c
DA		 211 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00);
212 if (vbios_mode->enh_table->flags & NewModeInfo) {
213 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8);
272725c7
VS		 214 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92,
215 fb->format->cpp[0] * 8);
f1f62f2c
DA		 216 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x93, adjusted_mode->clock / 1000);
217 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x94, adjusted_mode->crtc_hdisplay);
218 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x95, adjusted_mode->crtc_hdisplay >> 8);
312fec14 219
f1f62f2c
DA		 220 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x96, adjusted_mode->crtc_vdisplay);
221 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x97, adjusted_mode->crtc_vdisplay >> 8);
222 }
312fec14
DA		 223 }
224
225 return true;
226
227
228}
229static void ast_set_std_reg(struct drm_crtc *crtc, struct drm_display_mode *mode,
230 struct ast_vbios_mode_info *vbios_mode)
231{
232 struct ast_private *ast = crtc->dev->dev_private;
22acdbb1 233 const struct ast_vbios_stdtable *stdtable;
312fec14
DA		 234 u32 i;
235 u8 jreg;
236
237 stdtable = vbios_mode->std_table;
238
239 jreg = stdtable->misc;
240 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg);
241
242 /* Set SEQ */
243 ast_set_index_reg(ast, AST_IO_SEQ_PORT, 0x00, 0x03);
244 for (i = 0; i < 4; i++) {
245 jreg = stdtable->seq[i];
246 if (!i)
247 jreg |= 0x20;
248 ast_set_index_reg(ast, AST_IO_SEQ_PORT, (i + 1) , jreg);
249 }
250
251 /* Set CRTC */
252 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
253 for (i = 0; i < 25; i++)
254 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]);
255
256 /* set AR */
257 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
258 for (i = 0; i < 20; i++) {
259 jreg = stdtable->ar[i];
260 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, (u8)i);
261 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, jreg);
262 }
263 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x14);
264 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x00);
265
266 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
267 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x20);
268
269 /* Set GR */
270 for (i = 0; i < 9; i++)
271 ast_set_index_reg(ast, AST_IO_GR_PORT, i, stdtable->gr[i]);
272}
273
274static void ast_set_crtc_reg(struct drm_crtc *crtc, struct drm_display_mode *mode,
275 struct ast_vbios_mode_info *vbios_mode)
276{
277 struct ast_private *ast = crtc->dev->dev_private;
278 u8 jreg05 = 0, jreg07 = 0, jreg09 = 0, jregAC = 0, jregAD = 0, jregAE = 0;
9f93c8b3
C		 279 u16 temp, precache = 0;
280
281 if ((ast->chip == AST2500) &&
282 (vbios_mode->enh_table->flags & AST2500PreCatchCRT))
283 precache = 40;
312fec14
DA		 284
285 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
286
287 temp = (mode->crtc_htotal >> 3) - 5;
288 if (temp & 0x100)
289 jregAC |= 0x01; /* HT D[8] */
290 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x00, 0x00, temp);
291
292 temp = (mode->crtc_hdisplay >> 3) - 1;
293 if (temp & 0x100)
294 jregAC |= 0x04; /* HDE D[8] */
295 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x01, 0x00, temp);
296
297 temp = (mode->crtc_hblank_start >> 3) - 1;
298 if (temp & 0x100)
299 jregAC |= 0x10; /* HBS D[8] */
300 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x02, 0x00, temp);
301
302 temp = ((mode->crtc_hblank_end >> 3) - 1) & 0x7f;
303 if (temp & 0x20)
304 jreg05 |= 0x80; /* HBE D[5] */
305 if (temp & 0x40)
306 jregAD |= 0x01; /* HBE D[5] */
307 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f));
308
9f93c8b3 309 temp = ((mode->crtc_hsync_start-precache) >> 3) - 1;
312fec14
DA		 310 if (temp & 0x100)
311 jregAC |= 0x40; /* HRS D[5] */
312 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp);
313
9f93c8b3 314 temp = (((mode->crtc_hsync_end-precache) >> 3) - 1) & 0x3f;
312fec14
DA		 315 if (temp & 0x20)
316 jregAD |= 0x04; /* HRE D[5] */
317 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05));
318
319 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAC, 0x00, jregAC);
320 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAD, 0x00, jregAD);
321
322 /* vert timings */
323 temp = (mode->crtc_vtotal) - 2;
324 if (temp & 0x100)
325 jreg07 |= 0x01;
326 if (temp & 0x200)
327 jreg07 |= 0x20;
328 if (temp & 0x400)
329 jregAE |= 0x01;
330 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x06, 0x00, temp);
331
332 temp = (mode->crtc_vsync_start) - 1;
333 if (temp & 0x100)
334 jreg07 |= 0x04;
335 if (temp & 0x200)
336 jreg07 |= 0x80;
337 if (temp & 0x400)
338 jregAE |= 0x08;
339 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x10, 0x00, temp);
340
341 temp = (mode->crtc_vsync_end - 1) & 0x3f;
342 if (temp & 0x10)
343 jregAE |= 0x20;
344 if (temp & 0x20)
345 jregAE |= 0x40;
346 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x70, temp & 0xf);
347
348 temp = mode->crtc_vdisplay - 1;
349 if (temp & 0x100)
350 jreg07 |= 0x02;
351 if (temp & 0x200)
352 jreg07 |= 0x40;
353 if (temp & 0x400)
354 jregAE |= 0x02;
355 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x12, 0x00, temp);
356
357 temp = mode->crtc_vblank_start - 1;
358 if (temp & 0x100)
359 jreg07 |= 0x08;
360 if (temp & 0x200)
361 jreg09 |= 0x20;
362 if (temp & 0x400)
363 jregAE |= 0x04;
364 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x15, 0x00, temp);
365
366 temp = mode->crtc_vblank_end - 1;
367 if (temp & 0x100)
368 jregAE |= 0x10;
369 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x16, 0x00, temp);
370
371 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x07, 0x00, jreg07);
372 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x09, 0xdf, jreg09);
373 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAE, 0x00, (jregAE | 0x80));
374
9f93c8b3
C		 375 if (precache)
376 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x80);
377 else
378 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x00);
379
312fec14
DA		 380 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x80);
381}
382
383static void ast_set_offset_reg(struct drm_crtc *crtc)
384{
385 struct ast_private *ast = crtc->dev->dev_private;
7445283a 386 const struct drm_framebuffer *fb = crtc->primary->fb;
312fec14
DA		 387
388 u16 offset;
389
7445283a 390 offset = fb->pitches[0] >> 3;
312fec14
DA		 391 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x13, (offset & 0xff));
392 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xb0, (offset >> 8) & 0x3f);
393}
394
395static void ast_set_dclk_reg(struct drm_device *dev, struct drm_display_mode *mode,
396 struct ast_vbios_mode_info *vbios_mode)
397{
398 struct ast_private *ast = dev->dev_private;
22acdbb1 399 const struct ast_vbios_dclk_info *clk_info;
312fec14 400
9f93c8b3
C		 401 if (ast->chip == AST2500)
402 clk_info = &dclk_table_ast2500[vbios_mode->enh_table->dclk_index];
403 else
404 clk_info = &dclk_table[vbios_mode->enh_table->dclk_index];
312fec14
DA		 405
406 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1);
407 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2);
408 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xbb, 0x0f,
9f93c8b3
C		 409 (clk_info->param3 & 0xc0) |
410 ((clk_info->param3 & 0x3) << 4));
312fec14
DA		 411}
412
413static void ast_set_ext_reg(struct drm_crtc *crtc, struct drm_display_mode *mode,
414 struct ast_vbios_mode_info *vbios_mode)
415{
416 struct ast_private *ast = crtc->dev->dev_private;
7445283a 417 const struct drm_framebuffer *fb = crtc->primary->fb;
312fec14
DA		 418 u8 jregA0 = 0, jregA3 = 0, jregA8 = 0;
419
272725c7 420 switch (fb->format->cpp[0] * 8) {
312fec14
DA		 421 case 8:
422 jregA0 = 0x70;
423 jregA3 = 0x01;
424 jregA8 = 0x00;
425 break;
426 case 15:
427 case 16:
428 jregA0 = 0x70;
429 jregA3 = 0x04;
430 jregA8 = 0x02;
431 break;
432 case 32:
433 jregA0 = 0x70;
434 jregA3 = 0x08;
435 jregA8 = 0x02;
436 break;
437 }
438
439 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa0, 0x8f, jregA0);
440 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xf0, jregA3);
441 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8);
442
443 /* Set Threshold */
9f93c8b3
C		 444 if (ast->chip == AST2300 || ast->chip == AST2400 ||
445 ast->chip == AST2500) {
312fec14
DA		 446 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78);
447 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60);
448 } else if (ast->chip == AST2100 ||
449 ast->chip == AST1100 ||
450 ast->chip == AST2200 ||
451 ast->chip == AST2150) {
452 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x3f);
453 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x2f);
454 } else {
455 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x2f);
456 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x1f);
457 }
458}
459
7f5ccd44 460static void ast_set_sync_reg(struct drm_device *dev, struct drm_display_mode *mode,
312fec14
DA		 461 struct ast_vbios_mode_info *vbios_mode)
462{
463 struct ast_private *ast = dev->dev_private;
464 u8 jreg;
465
94d12b13
C		 466 jreg = ast_io_read8(ast, AST_IO_MISC_PORT_READ);
467 jreg &= ~0xC0;
468 if (vbios_mode->enh_table->flags & NVSync) jreg |= 0x80;
469 if (vbios_mode->enh_table->flags & NHSync) jreg |= 0x40;
312fec14
DA		 470 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg);
471}
472
7f5ccd44 473static bool ast_set_dac_reg(struct drm_crtc *crtc, struct drm_display_mode *mode,
312fec14
DA		 474 struct ast_vbios_mode_info *vbios_mode)
475{
7445283a
VS		 476 const struct drm_framebuffer *fb = crtc->primary->fb;
477
272725c7 478 switch (fb->format->cpp[0] * 8) {
312fec14
DA		 479 case 8:
480 break;
481 default:
482 return false;
483 }
484 return true;
485}
486
7f5ccd44 487static void ast_set_start_address_crt1(struct drm_crtc *crtc, unsigned offset)
312fec14
DA		 488{
489 struct ast_private *ast = crtc->dev->dev_private;
490 u32 addr;
491
492 addr = offset >> 2;
493 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0d, (u8)(addr & 0xff));
494 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0c, (u8)((addr >> 8) & 0xff));
495 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xaf, (u8)((addr >> 16) & 0xff));
496
497}
498
499static void ast_crtc_dpms(struct drm_crtc *crtc, int mode)
500{
501 struct ast_private *ast = crtc->dev->dev_private;
502
503 if (ast->chip == AST1180)
504 return;
505
506 switch (mode) {
507 case DRM_MODE_DPMS_ON:
508 case DRM_MODE_DPMS_STANDBY:
509 case DRM_MODE_DPMS_SUSPEND:
510 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0);
83c6620b
DA		 511 if (ast->tx_chip_type == AST_TX_DP501)
512 ast_set_dp501_video_output(crtc->dev, 1);
312fec14
DA		 513 ast_crtc_load_lut(crtc);
514 break;
515 case DRM_MODE_DPMS_OFF:
83c6620b
DA		 516 if (ast->tx_chip_type == AST_TX_DP501)
517 ast_set_dp501_video_output(crtc->dev, 0);
312fec14
DA		 518 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x20);
519 break;
520 }
521}
522
312fec14
DA		 523/* ast is different - we will force move buffers out of VRAM */
524static int ast_crtc_do_set_base(struct drm_crtc *crtc,
525 struct drm_framebuffer *fb,
526 int x, int y, int atomic)
527{
528 struct ast_private *ast = crtc->dev->dev_private;
529 struct drm_gem_object *obj;
530 struct ast_framebuffer *ast_fb;
531 struct ast_bo *bo;
532 int ret;
533 u64 gpu_addr;
534
535 /* push the previous fb to system ram */
536 if (!atomic && fb) {
537 ast_fb = to_ast_framebuffer(fb);
538 obj = ast_fb->obj;
539 bo = gem_to_ast_bo(obj);
540 ret = ast_bo_reserve(bo, false);
541 if (ret)
542 return ret;
543 ast_bo_push_sysram(bo);
544 ast_bo_unreserve(bo);
545 }
546
f4510a27 547 ast_fb = to_ast_framebuffer(crtc->primary->fb);
312fec14
DA		 548 obj = ast_fb->obj;
549 bo = gem_to_ast_bo(obj);
550
551 ret = ast_bo_reserve(bo, false);
552 if (ret)
553 return ret;
554
555 ret = ast_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr);
556 if (ret) {
557 ast_bo_unreserve(bo);
558 return ret;
559 }
560
561 if (&ast->fbdev->afb == ast_fb) {
562 /* if pushing console in kmap it */
563 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap);
564 if (ret)
565 DRM_ERROR("failed to kmap fbcon\n");
28fb4cb7
EE		 566 else
567 ast_fbdev_set_base(ast, gpu_addr);
312fec14
DA		 568 }
569 ast_bo_unreserve(bo);
570
571 ast_set_start_address_crt1(crtc, (u32)gpu_addr);
572
573 return 0;
574}
575
576static int ast_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
577 struct drm_framebuffer *old_fb)
578{
579 return ast_crtc_do_set_base(crtc, old_fb, x, y, 0);
580}
581
582static int ast_crtc_mode_set(struct drm_crtc *crtc,
583 struct drm_display_mode *mode,
584 struct drm_display_mode *adjusted_mode,
585 int x, int y,
586 struct drm_framebuffer *old_fb)
587{
588 struct drm_device *dev = crtc->dev;
589 struct ast_private *ast = crtc->dev->dev_private;
590 struct ast_vbios_mode_info vbios_mode;
591 bool ret;
592 if (ast->chip == AST1180) {
593 DRM_ERROR("AST 1180 modesetting not supported\n");
594 return -EINVAL;
595 }
596
597 ret = ast_get_vbios_mode_info(crtc, mode, adjusted_mode, &vbios_mode);
598 if (ret == false)
599 return -EINVAL;
600 ast_open_key(ast);
601
602 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x04);
603
604 ast_set_std_reg(crtc, adjusted_mode, &vbios_mode);
605 ast_set_crtc_reg(crtc, adjusted_mode, &vbios_mode);
606 ast_set_offset_reg(crtc);
607 ast_set_dclk_reg(dev, adjusted_mode, &vbios_mode);
608 ast_set_ext_reg(crtc, adjusted_mode, &vbios_mode);
609 ast_set_sync_reg(dev, adjusted_mode, &vbios_mode);
610 ast_set_dac_reg(crtc, adjusted_mode, &vbios_mode);
611
612 ast_crtc_mode_set_base(crtc, x, y, old_fb);
613
614 return 0;
615}
616
617static void ast_crtc_disable(struct drm_crtc *crtc)
618{
ab209c32
EE		 619 int ret;
620
621 DRM_DEBUG_KMS("\n");
622 ast_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
623 if (crtc->primary->fb) {
624 struct ast_framebuffer *ast_fb = to_ast_framebuffer(crtc->primary->fb);
625 struct drm_gem_object *obj = ast_fb->obj;
626 struct ast_bo *bo = gem_to_ast_bo(obj);
627
628 ret = ast_bo_reserve(bo, false);
629 if (ret)
630 return;
312fec14 631
ab209c32
EE		 632 ast_bo_push_sysram(bo);
633 ast_bo_unreserve(bo);
634 }
635 crtc->primary->fb = NULL;
312fec14
DA		 636}
637
638static void ast_crtc_prepare(struct drm_crtc *crtc)
639{
640
641}
642
643static void ast_crtc_commit(struct drm_crtc *crtc)
644{
645 struct ast_private *ast = crtc->dev->dev_private;
646 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0);
647}
648
649
650static const struct drm_crtc_helper_funcs ast_crtc_helper_funcs = {
651 .dpms = ast_crtc_dpms,
312fec14
DA		 652 .mode_set = ast_crtc_mode_set,
653 .mode_set_base = ast_crtc_mode_set_base,
654 .disable = ast_crtc_disable,
312fec14
DA		 655 .prepare = ast_crtc_prepare,
656 .commit = ast_crtc_commit,
657
658};
659
660static void ast_crtc_reset(struct drm_crtc *crtc)
661{
662
663}
664
7ea77283 665static int ast_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6d124ff8
DV		 666 u16 *blue, uint32_t size,
667 struct drm_modeset_acquire_ctx *ctx)
312fec14 668{
312fec14 669 ast_crtc_load_lut(crtc);
7ea77283
ML		 670
671 return 0;
312fec14
DA		 672}
673
674
675static void ast_crtc_destroy(struct drm_crtc *crtc)
676{
677 drm_crtc_cleanup(crtc);
678 kfree(crtc);
679}
680
681static const struct drm_crtc_funcs ast_crtc_funcs = {
682 .cursor_set = ast_cursor_set,
683 .cursor_move = ast_cursor_move,
684 .reset = ast_crtc_reset,
685 .set_config = drm_crtc_helper_set_config,
686 .gamma_set = ast_crtc_gamma_set,
687 .destroy = ast_crtc_destroy,
688};
689
7f5ccd44 690static int ast_crtc_init(struct drm_device *dev)
312fec14
DA		 691{
692 struct ast_crtc *crtc;
312fec14
DA		 693
694 crtc = kzalloc(sizeof(struct ast_crtc), GFP_KERNEL);
695 if (!crtc)
696 return -ENOMEM;
697
698 drm_crtc_init(dev, &crtc->base, &ast_crtc_funcs);
699 drm_mode_crtc_set_gamma_size(&crtc->base, 256);
700 drm_crtc_helper_add(&crtc->base, &ast_crtc_helper_funcs);
312fec14
DA		 701 return 0;
702}
703
704static void ast_encoder_destroy(struct drm_encoder *encoder)
705{
706 drm_encoder_cleanup(encoder);
707 kfree(encoder);
708}
709
710
711static struct drm_encoder *ast_best_single_encoder(struct drm_connector *connector)
712{
713 int enc_id = connector->encoder_ids[0];
312fec14 714 /* pick the encoder ids */
70e26260 715 if (enc_id)
418da172 716 return drm_encoder_find(connector->dev, NULL, enc_id);
312fec14
DA		 717 return NULL;
718}
719
720
721static const struct drm_encoder_funcs ast_enc_funcs = {
722 .destroy = ast_encoder_destroy,
723};
724
725static void ast_encoder_dpms(struct drm_encoder *encoder, int mode)
726{
727
728}
729
312fec14
DA		 730static void ast_encoder_mode_set(struct drm_encoder *encoder,
731 struct drm_display_mode *mode,
732 struct drm_display_mode *adjusted_mode)
733{
734}
735
736static void ast_encoder_prepare(struct drm_encoder *encoder)
737{
738
739}
740
741static void ast_encoder_commit(struct drm_encoder *encoder)
742{
743
744}
745
746
747static const struct drm_encoder_helper_funcs ast_enc_helper_funcs = {
748 .dpms = ast_encoder_dpms,
312fec14
DA		 749 .prepare = ast_encoder_prepare,
750 .commit = ast_encoder_commit,
751 .mode_set = ast_encoder_mode_set,
752};
753
7f5ccd44 754static int ast_encoder_init(struct drm_device *dev)
312fec14
DA		 755{
756 struct ast_encoder *ast_encoder;
757
758 ast_encoder = kzalloc(sizeof(struct ast_encoder), GFP_KERNEL);
759 if (!ast_encoder)
760 return -ENOMEM;
761
762 drm_encoder_init(dev, &ast_encoder->base, &ast_enc_funcs,
13a3d91f 763 DRM_MODE_ENCODER_DAC, NULL);
312fec14
DA		 764 drm_encoder_helper_add(&ast_encoder->base, &ast_enc_helper_funcs);
765
766 ast_encoder->base.possible_crtcs = 1;
767 return 0;
768}
769
770static int ast_get_modes(struct drm_connector *connector)
771{
772 struct ast_connector *ast_connector = to_ast_connector(connector);
83c6620b 773 struct ast_private *ast = connector->dev->dev_private;
312fec14
DA		 774 struct edid *edid;
775 int ret;
83c6620b
DA		 776 bool flags = false;
777 if (ast->tx_chip_type == AST_TX_DP501) {
778 ast->dp501_maxclk = 0xff;
779 edid = kmalloc(128, GFP_KERNEL);
780 if (!edid)
781 return -ENOMEM;
782
783 flags = ast_dp501_read_edid(connector->dev, (u8 *)edid);
784 if (flags)
785 ast->dp501_maxclk = ast_get_dp501_max_clk(connector->dev);
786 else
787 kfree(edid);
788 }
789 if (!flags)
790 edid = drm_get_edid(connector, &ast_connector->i2c->adapter);
312fec14
DA		 791 if (edid) {
792 drm_mode_connector_update_edid_property(&ast_connector->base, edid);
793 ret = drm_add_edid_modes(connector, edid);
993dcb05 794 kfree(edid);
312fec14
DA		 795 return ret;
796 } else
797 drm_mode_connector_update_edid_property(&ast_connector->base, NULL);
798 return 0;
799}
800
801static int ast_mode_valid(struct drm_connector *connector,
802 struct drm_display_mode *mode)
803{
f1f62f2c
DA		 804 struct ast_private *ast = connector->dev->dev_private;
805 int flags = MODE_NOMODE;
806 uint32_t jtemp;
807
808 if (ast->support_wide_screen) {
809 if ((mode->hdisplay == 1680) && (mode->vdisplay == 1050))
810 return MODE_OK;
811 if ((mode->hdisplay == 1280) && (mode->vdisplay == 800))
812 return MODE_OK;
813 if ((mode->hdisplay == 1440) && (mode->vdisplay == 900))
814 return MODE_OK;
815 if ((mode->hdisplay == 1360) && (mode->vdisplay == 768))
816 return MODE_OK;
817 if ((mode->hdisplay == 1600) && (mode->vdisplay == 900))
818 return MODE_OK;
819
9f93c8b3
C		 820 if ((ast->chip == AST2100) || (ast->chip == AST2200) ||
821 (ast->chip == AST2300) || (ast->chip == AST2400) ||
822 (ast->chip == AST2500) || (ast->chip == AST1180)) {
f1f62f2c
DA		 823 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1080))
824 return MODE_OK;
825
826 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1200)) {
827 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
828 if (jtemp & 0x01)
829 return MODE_NOMODE;
830 else
831 return MODE_OK;
832 }
833 }
834 }
835 switch (mode->hdisplay) {
836 case 640:
837 if (mode->vdisplay == 480) flags = MODE_OK;
838 break;
839 case 800:
840 if (mode->vdisplay == 600) flags = MODE_OK;
841 break;
842 case 1024:
843 if (mode->vdisplay == 768) flags = MODE_OK;
844 break;
845 case 1280:
846 if (mode->vdisplay == 1024) flags = MODE_OK;
847 break;
848 case 1600:
849 if (mode->vdisplay == 1200) flags = MODE_OK;
850 break;
851 default:
852 return flags;
853 }
854
855 return flags;
312fec14
DA		 856}
857
858static void ast_connector_destroy(struct drm_connector *connector)
859{
860 struct ast_connector *ast_connector = to_ast_connector(connector);
861 ast_i2c_destroy(ast_connector->i2c);
34ea3d38 862 drm_connector_unregister(connector);
312fec14
DA		 863 drm_connector_cleanup(connector);
864 kfree(connector);
865}
866
312fec14
DA		 867static const struct drm_connector_helper_funcs ast_connector_helper_funcs = {
868 .mode_valid = ast_mode_valid,
869 .get_modes = ast_get_modes,
870 .best_encoder = ast_best_single_encoder,
871};
872
873static const struct drm_connector_funcs ast_connector_funcs = {
874 .dpms = drm_helper_connector_dpms,
312fec14
DA		 875 .fill_modes = drm_helper_probe_single_connector_modes,
876 .destroy = ast_connector_destroy,
877};
878
7f5ccd44 879static int ast_connector_init(struct drm_device *dev)
312fec14
DA		 880{
881 struct ast_connector *ast_connector;
882 struct drm_connector *connector;
883 struct drm_encoder *encoder;
884
885 ast_connector = kzalloc(sizeof(struct ast_connector), GFP_KERNEL);
886 if (!ast_connector)
887 return -ENOMEM;
888
889 connector = &ast_connector->base;
890 drm_connector_init(dev, connector, &ast_connector_funcs, DRM_MODE_CONNECTOR_VGA);
891
892 drm_connector_helper_add(connector, &ast_connector_helper_funcs);
893
894 connector->interlace_allowed = 0;
895 connector->doublescan_allowed = 0;
896
34ea3d38 897 drm_connector_register(connector);
312fec14
DA		 898
899 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
900
901 encoder = list_first_entry(&dev->mode_config.encoder_list, struct drm_encoder, head);
902 drm_mode_connector_attach_encoder(connector, encoder);
903
904 ast_connector->i2c = ast_i2c_create(dev);
905 if (!ast_connector->i2c)
906 DRM_ERROR("failed to add ddc bus for connector\n");
907
908 return 0;
909}
910
911/* allocate cursor cache and pin at start of VRAM */
7f5ccd44 912static int ast_cursor_init(struct drm_device *dev)
312fec14
DA		 913{
914 struct ast_private *ast = dev->dev_private;
915 int size;
916 int ret;
917 struct drm_gem_object *obj;
918 struct ast_bo *bo;
919 uint64_t gpu_addr;
920
921 size = (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE) * AST_DEFAULT_HWC_NUM;
922
923 ret = ast_gem_create(dev, size, true, &obj);
924 if (ret)
925 return ret;
926 bo = gem_to_ast_bo(obj);
927 ret = ast_bo_reserve(bo, false);
928 if (unlikely(ret != 0))
929 goto fail;
930
931 ret = ast_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr);
932 ast_bo_unreserve(bo);
933 if (ret)
934 goto fail;
935
936 /* kmap the object */
937 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &ast->cache_kmap);
938 if (ret)
939 goto fail;
940
941 ast->cursor_cache = obj;
942 ast->cursor_cache_gpu_addr = gpu_addr;
0273de08 943 DRM_DEBUG_KMS("pinned cursor cache at %llx\n", ast->cursor_cache_gpu_addr);
312fec14
DA		 944 return 0;
945fail:
946 return ret;
947}
948
7f5ccd44 949static void ast_cursor_fini(struct drm_device *dev)
312fec14
DA		 950{
951 struct ast_private *ast = dev->dev_private;
952 ttm_bo_kunmap(&ast->cache_kmap);
1feba03f 953 drm_gem_object_put_unlocked(ast->cursor_cache);
312fec14
DA		 954}
955
956int ast_mode_init(struct drm_device *dev)
957{
958 ast_cursor_init(dev);
959 ast_crtc_init(dev);
960 ast_encoder_init(dev);
961 ast_connector_init(dev);
962 return 0;
963}
964
965void ast_mode_fini(struct drm_device *dev)
966{
967 ast_cursor_fini(dev);
968}
969
970static int get_clock(void *i2c_priv)
971{
972 struct ast_i2c_chan *i2c = i2c_priv;
973 struct ast_private *ast = i2c->dev->dev_private;
974 uint32_t val;
975
976 val = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4;
977 return val & 1 ? 1 : 0;
978}
979
980static int get_data(void *i2c_priv)
981{
982 struct ast_i2c_chan *i2c = i2c_priv;
983 struct ast_private *ast = i2c->dev->dev_private;
984 uint32_t val;
985
986 val = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5;
987 return val & 1 ? 1 : 0;
988}
989
990static void set_clock(void *i2c_priv, int clock)
991{
992 struct ast_i2c_chan *i2c = i2c_priv;
993 struct ast_private *ast = i2c->dev->dev_private;
994 int i;
995 u8 ujcrb7, jtemp;
996
997 for (i = 0; i < 0x10000; i++) {
998 ujcrb7 = ((clock & 0x01) ? 0 : 1);
999 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xfe, ujcrb7);
1000 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x01);
1001 if (ujcrb7 == jtemp)
1002 break;
1003 }
1004}
1005
1006static void set_data(void *i2c_priv, int data)
1007{
1008 struct ast_i2c_chan *i2c = i2c_priv;
1009 struct ast_private *ast = i2c->dev->dev_private;
1010 int i;
1011 u8 ujcrb7, jtemp;
1012
1013 for (i = 0; i < 0x10000; i++) {
1014 ujcrb7 = ((data & 0x01) ? 0 : 1) << 2;
1015 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xfb, ujcrb7);
1016 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x04);
1017 if (ujcrb7 == jtemp)
1018 break;
1019 }
1020}
1021
1022static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev)
1023{
1024 struct ast_i2c_chan *i2c;
1025 int ret;
1026
1027 i2c = kzalloc(sizeof(struct ast_i2c_chan), GFP_KERNEL);
1028 if (!i2c)
1029 return NULL;
1030
1031 i2c->adapter.owner = THIS_MODULE;
1032 i2c->adapter.class = I2C_CLASS_DDC;
1033 i2c->adapter.dev.parent = &dev->pdev->dev;
1034 i2c->dev = dev;
1035 i2c_set_adapdata(&i2c->adapter, i2c);
1036 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
1037 "AST i2c bit bus");
1038 i2c->adapter.algo_data = &i2c->bit;
1039
1040 i2c->bit.udelay = 20;
1041 i2c->bit.timeout = 2;
1042 i2c->bit.data = i2c;
1043 i2c->bit.setsda = set_data;
1044 i2c->bit.setscl = set_clock;
1045 i2c->bit.getsda = get_data;
1046 i2c->bit.getscl = get_clock;
1047 ret = i2c_bit_add_bus(&i2c->adapter);
1048 if (ret) {
1049 DRM_ERROR("Failed to register bit i2c\n");
1050 goto out_free;
1051 }
1052
1053 return i2c;
1054out_free:
1055 kfree(i2c);
1056 return NULL;
1057}
1058
1059static void ast_i2c_destroy(struct ast_i2c_chan *i2c)
1060{
1061 if (!i2c)
1062 return;
1063 i2c_del_adapter(&i2c->adapter);
1064 kfree(i2c);
1065}
1066
7f5ccd44 1067static void ast_show_cursor(struct drm_crtc *crtc)
312fec14
DA		 1068{
1069 struct ast_private *ast = crtc->dev->dev_private;
1070 u8 jreg;
1071
1072 jreg = 0x2;
1073 /* enable ARGB cursor */
1074 jreg |= 1;
1075 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, jreg);
1076}
1077
7f5ccd44 1078static void ast_hide_cursor(struct drm_crtc *crtc)
312fec14
DA		 1079{
1080 struct ast_private *ast = crtc->dev->dev_private;
1081 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, 0x00);
1082}
1083
1084static u32 copy_cursor_image(u8 *src, u8 *dst, int width, int height)
1085{
1086 union {
1087 u32 ul;
1088 u8 b[4];
1089 } srcdata32[2], data32;
1090 union {
1091 u16 us;
1092 u8 b[2];
1093 } data16;
1094 u32 csum = 0;
1095 s32 alpha_dst_delta, last_alpha_dst_delta;
1096 u8 *srcxor, *dstxor;
1097 int i, j;
1098 u32 per_pixel_copy, two_pixel_copy;
1099
1100 alpha_dst_delta = AST_MAX_HWC_WIDTH << 1;
1101 last_alpha_dst_delta = alpha_dst_delta - (width << 1);
1102
1103 srcxor = src;
1104 dstxor = (u8 *)dst + last_alpha_dst_delta + (AST_MAX_HWC_HEIGHT - height) * alpha_dst_delta;
1105 per_pixel_copy = width & 1;
1106 two_pixel_copy = width >> 1;
1107
1108 for (j = 0; j < height; j++) {
1109 for (i = 0; i < two_pixel_copy; i++) {
1110 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0;
1111 srcdata32[1].ul = *((u32 *)(srcxor + 4)) & 0xf0f0f0f0;
1112 data32.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4);
1113 data32.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4);
1e99cfa8
BH		 1114 data32.b[2] = srcdata32[1].b[1] | (srcdata32[1].b[0] >> 4);
1115 data32.b[3] = srcdata32[1].b[3] | (srcdata32[1].b[2] >> 4);
312fec14
DA		 1116
1117 writel(data32.ul, dstxor);
1118 csum += data32.ul;
1119
1120 dstxor += 4;
1121 srcxor += 8;
1122
1123 }
1124
1125 for (i = 0; i < per_pixel_copy; i++) {
1126 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0;
1127 data16.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4);
1128 data16.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4);
1129 writew(data16.us, dstxor);
1130 csum += (u32)data16.us;
1131
1132 dstxor += 2;
1133 srcxor += 4;
1134 }
1135 dstxor += last_alpha_dst_delta;
1136 }
1137 return csum;
1138}
1139
1140static int ast_cursor_set(struct drm_crtc *crtc,
1141 struct drm_file *file_priv,
1142 uint32_t handle,
1143 uint32_t width,
1144 uint32_t height)
1145{
1146 struct ast_private *ast = crtc->dev->dev_private;
1147 struct ast_crtc *ast_crtc = to_ast_crtc(crtc);
1148 struct drm_gem_object *obj;
1149 struct ast_bo *bo;
1150 uint64_t gpu_addr;
1151 u32 csum;
1152 int ret;
1153 struct ttm_bo_kmap_obj uobj_map;
1154 u8 *src, *dst;
1155 bool src_isiomem, dst_isiomem;
1156 if (!handle) {
1157 ast_hide_cursor(crtc);
1158 return 0;
1159 }
1160
1161 if (width > AST_MAX_HWC_WIDTH || height > AST_MAX_HWC_HEIGHT)
1162 return -EINVAL;
1163
a8ad0bd8 1164 obj = drm_gem_object_lookup(file_priv, handle);
312fec14
DA		 1165 if (!obj) {
1166 DRM_ERROR("Cannot find cursor object %x for crtc\n", handle);
1167 return -ENOENT;
1168 }
1169 bo = gem_to_ast_bo(obj);
1170
1171 ret = ast_bo_reserve(bo, false);
1172 if (ret)
1173 goto fail;
1174
1175 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &uobj_map);
1176
1177 src = ttm_kmap_obj_virtual(&uobj_map, &src_isiomem);
1178 dst = ttm_kmap_obj_virtual(&ast->cache_kmap, &dst_isiomem);
1179
1180 if (src_isiomem == true)
1181 DRM_ERROR("src cursor bo should be in main memory\n");
1182 if (dst_isiomem == false)
1183 DRM_ERROR("dst bo should be in VRAM\n");
1184
1185 dst += (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor;
1186
1187 /* do data transfer to cursor cache */
1188 csum = copy_cursor_image(src, dst, width, height);
1189
1190 /* write checksum + signature */
1191 ttm_bo_kunmap(&uobj_map);
1192 ast_bo_unreserve(bo);
1193 {
1194 u8 *dst = (u8 *)ast->cache_kmap.virtual + (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor + AST_HWC_SIZE;
1195 writel(csum, dst);
1196 writel(width, dst + AST_HWC_SIGNATURE_SizeX);
1197 writel(height, dst + AST_HWC_SIGNATURE_SizeY);
1198 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTX);
1199 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTY);
1200
1201 /* set pattern offset */
1202 gpu_addr = ast->cursor_cache_gpu_addr;
1203 gpu_addr += (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor;
1204 gpu_addr >>= 3;
1205 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc8, gpu_addr & 0xff);
1206 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc9, (gpu_addr >> 8) & 0xff);
1207 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xca, (gpu_addr >> 16) & 0xff);
1208 }
1209 ast_crtc->cursor_width = width;
1210 ast_crtc->cursor_height = height;
1211 ast_crtc->offset_x = AST_MAX_HWC_WIDTH - width;
1212 ast_crtc->offset_y = AST_MAX_HWC_WIDTH - height;
1213
1214 ast->next_cursor = (ast->next_cursor + 1) % AST_DEFAULT_HWC_NUM;
1215
1216 ast_show_cursor(crtc);
1217
1feba03f 1218 drm_gem_object_put_unlocked(obj);
312fec14
DA		 1219 return 0;
1220fail:
1feba03f 1221 drm_gem_object_put_unlocked(obj);
312fec14
DA		 1222 return ret;
1223}
1224
1225static int ast_cursor_move(struct drm_crtc *crtc,
1226 int x, int y)
1227{
1228 struct ast_crtc *ast_crtc = to_ast_crtc(crtc);
1229 struct ast_private *ast = crtc->dev->dev_private;
1230 int x_offset, y_offset;
1231 u8 *sig;
1232
1233 sig = (u8 *)ast->cache_kmap.virtual + (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor + AST_HWC_SIZE;
1234 writel(x, sig + AST_HWC_SIGNATURE_X);
1235 writel(y, sig + AST_HWC_SIGNATURE_Y);
1236
1237 x_offset = ast_crtc->offset_x;
1238 y_offset = ast_crtc->offset_y;
1239 if (x < 0) {
1240 x_offset = (-x) + ast_crtc->offset_x;
1241 x = 0;
1242 }
1243
1244 if (y < 0) {
1245 y_offset = (-y) + ast_crtc->offset_y;
1246 y = 0;
1247 }
1248 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc2, x_offset);
1249 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc3, y_offset);
1250 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc4, (x & 0xff));
1251 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc5, ((x >> 8) & 0x0f));
1252 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc6, (y & 0xff));
1253 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc7, ((y >> 8) & 0x07));
1254
1255 /* dummy write to fire HWC */
1256 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xCB, 0xFF, 0x00);
1257
1258 return 0;
1259}
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