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1da177e4 | 1 | /** |
b5e89ed5 | 2 | * \file ati_pcigart.c |
1da177e4 LT |
3 | * ATI PCI GART support |
4 | * | |
5 | * \author Gareth Hughes <gareth@valinux.com> | |
6 | */ | |
7 | ||
8 | /* | |
9 | * Created: Wed Dec 13 21:52:19 2000 by gareth@valinux.com | |
10 | * | |
11 | * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. | |
12 | * All Rights Reserved. | |
13 | * | |
14 | * Permission is hereby granted, free of charge, to any person obtaining a | |
15 | * copy of this software and associated documentation files (the "Software"), | |
16 | * to deal in the Software without restriction, including without limitation | |
17 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
18 | * and/or sell copies of the Software, and to permit persons to whom the | |
19 | * Software is furnished to do so, subject to the following conditions: | |
20 | * | |
21 | * The above copyright notice and this permission notice (including the next | |
22 | * paragraph) shall be included in all copies or substantial portions of the | |
23 | * Software. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
26 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
27 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
28 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
29 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
30 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
31 | * DEALINGS IN THE SOFTWARE. | |
32 | */ | |
33 | ||
34 | #include "drmP.h" | |
35 | ||
1da177e4 LT |
36 | # define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */ |
37 | ||
b05c2385 DA |
38 | static int drm_ati_alloc_pcigart_table(struct drm_device *dev, |
39 | struct drm_ati_pcigart_info *gart_info) | |
1da177e4 | 40 | { |
b05c2385 DA |
41 | gart_info->table_handle = drm_pci_alloc(dev, gart_info->table_size, |
42 | PAGE_SIZE, | |
43 | gart_info->table_mask); | |
44 | if (gart_info->table_handle == NULL) | |
45 | return -ENOMEM; | |
1da177e4 | 46 | |
b05c2385 | 47 | return 0; |
1da177e4 LT |
48 | } |
49 | ||
b05c2385 DA |
50 | static void drm_ati_free_pcigart_table(struct drm_device *dev, |
51 | struct drm_ati_pcigart_info *gart_info) | |
1da177e4 | 52 | { |
b05c2385 DA |
53 | drm_pci_free(dev, gart_info->table_handle); |
54 | gart_info->table_handle = NULL; | |
1da177e4 LT |
55 | } |
56 | ||
55910517 | 57 | int drm_ati_pcigart_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info) |
1da177e4 | 58 | { |
55910517 | 59 | struct drm_sg_mem *entry = dev->sg; |
1da177e4 LT |
60 | unsigned long pages; |
61 | int i; | |
b05c2385 | 62 | int max_pages; |
1da177e4 LT |
63 | |
64 | /* we need to support large memory configurations */ | |
b5e89ed5 DA |
65 | if (!entry) { |
66 | DRM_ERROR("no scatter/gather memory!\n"); | |
1da177e4 LT |
67 | return 0; |
68 | } | |
69 | ||
ea98a92f | 70 | if (gart_info->bus_addr) { |
1da177e4 | 71 | |
f2b04cd2 DA |
72 | max_pages = (gart_info->table_size / sizeof(u32)); |
73 | pages = (entry->pages <= max_pages) | |
74 | ? entry->pages : max_pages; | |
1da177e4 | 75 | |
b5e89ed5 DA |
76 | for (i = 0; i < pages; i++) { |
77 | if (!entry->busaddr[i]) | |
78 | break; | |
7ec700fc | 79 | pci_unmap_page(dev->pdev, entry->busaddr[i], |
296c6ae0 | 80 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
1da177e4 | 81 | } |
b5e89ed5 DA |
82 | |
83 | if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) | |
84 | gart_info->bus_addr = 0; | |
1da177e4 LT |
85 | } |
86 | ||
b05c2385 DA |
87 | if (gart_info->gart_table_location == DRM_ATI_GART_MAIN && |
88 | gart_info->table_handle) { | |
89 | drm_ati_free_pcigart_table(dev, gart_info); | |
1da177e4 LT |
90 | } |
91 | ||
92 | return 1; | |
93 | } | |
94 | EXPORT_SYMBOL(drm_ati_pcigart_cleanup); | |
95 | ||
55910517 | 96 | int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info) |
1da177e4 | 97 | { |
5a7aad9a | 98 | struct drm_local_map *map = &gart_info->mapping; |
55910517 | 99 | struct drm_sg_mem *entry = dev->sg; |
f26c473c | 100 | void *address = NULL; |
1da177e4 | 101 | unsigned long pages; |
5a7aad9a | 102 | u32 *pci_gart, page_base, gart_idx; |
b05c2385 | 103 | dma_addr_t bus_address = 0; |
1da177e4 | 104 | int i, j, ret = 0; |
d30333bb | 105 | int max_ati_pages, max_real_pages; |
1da177e4 | 106 | |
b5e89ed5 DA |
107 | if (!entry) { |
108 | DRM_ERROR("no scatter/gather memory!\n"); | |
1da177e4 LT |
109 | goto done; |
110 | } | |
111 | ||
b5e89ed5 | 112 | if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) { |
ea98a92f | 113 | DRM_DEBUG("PCI: no table in VRAM: using normal RAM\n"); |
b5e89ed5 | 114 | |
b05c2385 DA |
115 | ret = drm_ati_alloc_pcigart_table(dev, gart_info); |
116 | if (ret) { | |
b5e89ed5 | 117 | DRM_ERROR("cannot allocate PCI GART page!\n"); |
ea98a92f DA |
118 | goto done; |
119 | } | |
b5e89ed5 | 120 | |
b05c2385 DA |
121 | address = gart_info->table_handle->vaddr; |
122 | bus_address = gart_info->table_handle->busaddr; | |
b5e89ed5 | 123 | } else { |
ea98a92f DA |
124 | address = gart_info->addr; |
125 | bus_address = gart_info->bus_addr; | |
f67e74ca AM |
126 | DRM_DEBUG("PCI: Gart Table: VRAM %08LX mapped at %08lX\n", |
127 | (unsigned long long)bus_address, | |
128 | (unsigned long)address); | |
1da177e4 LT |
129 | } |
130 | ||
b5e89ed5 | 131 | pci_gart = (u32 *) address; |
1da177e4 | 132 | |
d30333bb DM |
133 | max_ati_pages = (gart_info->table_size / sizeof(u32)); |
134 | max_real_pages = max_ati_pages / (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); | |
135 | pages = (entry->pages <= max_real_pages) | |
136 | ? entry->pages : max_real_pages; | |
1da177e4 | 137 | |
5a7aad9a | 138 | if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) { |
d30333bb | 139 | memset(pci_gart, 0, max_ati_pages * sizeof(u32)); |
5a7aad9a | 140 | } else { |
d30333bb | 141 | for (gart_idx = 0; gart_idx < max_ati_pages; gart_idx++) |
5a7aad9a DM |
142 | DRM_WRITE32(map, gart_idx * sizeof(u32), 0); |
143 | } | |
1da177e4 | 144 | |
5a7aad9a | 145 | gart_idx = 0; |
b5e89ed5 | 146 | for (i = 0; i < pages; i++) { |
1da177e4 | 147 | /* we need to support large memory configurations */ |
7ec700fc | 148 | entry->busaddr[i] = pci_map_page(dev->pdev, entry->pagelist[i], |
296c6ae0 | 149 | 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
1da177e4 | 150 | if (entry->busaddr[i] == 0) { |
b5e89ed5 | 151 | DRM_ERROR("unable to map PCIGART pages!\n"); |
ea98a92f | 152 | drm_ati_pcigart_cleanup(dev, gart_info); |
f26c473c | 153 | address = NULL; |
1da177e4 LT |
154 | bus_address = 0; |
155 | goto done; | |
156 | } | |
157 | page_base = (u32) entry->busaddr[i]; | |
158 | ||
159 | for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) { | |
5a7aad9a DM |
160 | u32 val; |
161 | ||
f2b04cd2 DA |
162 | switch(gart_info->gart_reg_if) { |
163 | case DRM_ATI_GART_IGP: | |
5a7aad9a | 164 | val = page_base | 0xc; |
f2b04cd2 DA |
165 | break; |
166 | case DRM_ATI_GART_PCIE: | |
5a7aad9a | 167 | val = (page_base >> 8) | 0xc; |
f2b04cd2 DA |
168 | break; |
169 | default: | |
170 | case DRM_ATI_GART_PCI: | |
5a7aad9a | 171 | val = page_base; |
f2b04cd2 DA |
172 | break; |
173 | } | |
5a7aad9a DM |
174 | if (gart_info->gart_table_location == |
175 | DRM_ATI_GART_MAIN) | |
176 | pci_gart[gart_idx] = cpu_to_le32(val); | |
177 | else | |
178 | DRM_WRITE32(map, gart_idx * sizeof(u32), val); | |
179 | gart_idx++; | |
1da177e4 LT |
180 | page_base += ATI_PCIGART_PAGE_SIZE; |
181 | } | |
182 | } | |
1da177e4 LT |
183 | ret = 1; |
184 | ||
185 | #if defined(__i386__) || defined(__x86_64__) | |
186 | wbinvd(); | |
187 | #else | |
188 | mb(); | |
189 | #endif | |
190 | ||
b5e89ed5 | 191 | done: |
ea98a92f | 192 | gart_info->addr = address; |
b5e89ed5 | 193 | gart_info->bus_addr = bus_address; |
1da177e4 LT |
194 | return ret; |
195 | } | |
196 | EXPORT_SYMBOL(drm_ati_pcigart_init); |