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1da177e4 | 1 | /** |
b5e89ed5 | 2 | * \file ati_pcigart.c |
1da177e4 LT |
3 | * ATI PCI GART support |
4 | * | |
5 | * \author Gareth Hughes <gareth@valinux.com> | |
6 | */ | |
7 | ||
8 | /* | |
9 | * Created: Wed Dec 13 21:52:19 2000 by gareth@valinux.com | |
10 | * | |
11 | * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. | |
12 | * All Rights Reserved. | |
13 | * | |
14 | * Permission is hereby granted, free of charge, to any person obtaining a | |
15 | * copy of this software and associated documentation files (the "Software"), | |
16 | * to deal in the Software without restriction, including without limitation | |
17 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
18 | * and/or sell copies of the Software, and to permit persons to whom the | |
19 | * Software is furnished to do so, subject to the following conditions: | |
20 | * | |
21 | * The above copyright notice and this permission notice (including the next | |
22 | * paragraph) shall be included in all copies or substantial portions of the | |
23 | * Software. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
26 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
27 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
28 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
29 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
30 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
31 | * DEALINGS IN THE SOFTWARE. | |
32 | */ | |
33 | ||
34 | #include "drmP.h" | |
35 | ||
1da177e4 LT |
36 | # define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */ |
37 | ||
b05c2385 DA |
38 | static int drm_ati_alloc_pcigart_table(struct drm_device *dev, |
39 | struct drm_ati_pcigart_info *gart_info) | |
1da177e4 | 40 | { |
b05c2385 | 41 | gart_info->table_handle = drm_pci_alloc(dev, gart_info->table_size, |
e6be8d9d | 42 | PAGE_SIZE); |
b05c2385 DA |
43 | if (gart_info->table_handle == NULL) |
44 | return -ENOMEM; | |
1da177e4 | 45 | |
b05c2385 | 46 | return 0; |
1da177e4 LT |
47 | } |
48 | ||
b05c2385 DA |
49 | static void drm_ati_free_pcigart_table(struct drm_device *dev, |
50 | struct drm_ati_pcigart_info *gart_info) | |
1da177e4 | 51 | { |
b05c2385 DA |
52 | drm_pci_free(dev, gart_info->table_handle); |
53 | gart_info->table_handle = NULL; | |
1da177e4 LT |
54 | } |
55 | ||
55910517 | 56 | int drm_ati_pcigart_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info) |
1da177e4 | 57 | { |
55910517 | 58 | struct drm_sg_mem *entry = dev->sg; |
1da177e4 LT |
59 | unsigned long pages; |
60 | int i; | |
b05c2385 | 61 | int max_pages; |
1da177e4 LT |
62 | |
63 | /* we need to support large memory configurations */ | |
b5e89ed5 DA |
64 | if (!entry) { |
65 | DRM_ERROR("no scatter/gather memory!\n"); | |
1da177e4 LT |
66 | return 0; |
67 | } | |
68 | ||
ea98a92f | 69 | if (gart_info->bus_addr) { |
1da177e4 | 70 | |
f2b04cd2 DA |
71 | max_pages = (gart_info->table_size / sizeof(u32)); |
72 | pages = (entry->pages <= max_pages) | |
73 | ? entry->pages : max_pages; | |
1da177e4 | 74 | |
b5e89ed5 DA |
75 | for (i = 0; i < pages; i++) { |
76 | if (!entry->busaddr[i]) | |
77 | break; | |
7ec700fc | 78 | pci_unmap_page(dev->pdev, entry->busaddr[i], |
296c6ae0 | 79 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
1da177e4 | 80 | } |
b5e89ed5 DA |
81 | |
82 | if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) | |
83 | gart_info->bus_addr = 0; | |
1da177e4 LT |
84 | } |
85 | ||
b05c2385 DA |
86 | if (gart_info->gart_table_location == DRM_ATI_GART_MAIN && |
87 | gart_info->table_handle) { | |
88 | drm_ati_free_pcigart_table(dev, gart_info); | |
1da177e4 LT |
89 | } |
90 | ||
91 | return 1; | |
92 | } | |
93 | EXPORT_SYMBOL(drm_ati_pcigart_cleanup); | |
94 | ||
55910517 | 95 | int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info) |
1da177e4 | 96 | { |
5a7aad9a | 97 | struct drm_local_map *map = &gart_info->mapping; |
55910517 | 98 | struct drm_sg_mem *entry = dev->sg; |
f26c473c | 99 | void *address = NULL; |
1da177e4 | 100 | unsigned long pages; |
6abf6601 | 101 | u32 *pci_gart = NULL, page_base, gart_idx; |
b05c2385 | 102 | dma_addr_t bus_address = 0; |
1da177e4 | 103 | int i, j, ret = 0; |
d30333bb | 104 | int max_ati_pages, max_real_pages; |
1da177e4 | 105 | |
b5e89ed5 DA |
106 | if (!entry) { |
107 | DRM_ERROR("no scatter/gather memory!\n"); | |
1da177e4 LT |
108 | goto done; |
109 | } | |
110 | ||
b5e89ed5 | 111 | if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) { |
ea98a92f | 112 | DRM_DEBUG("PCI: no table in VRAM: using normal RAM\n"); |
b5e89ed5 | 113 | |
e6be8d9d ZW |
114 | if (pci_set_dma_mask(dev->pdev, gart_info->table_mask)) { |
115 | DRM_ERROR("fail to set dma mask to 0x%Lx\n", | |
116 | gart_info->table_mask); | |
117 | ret = 1; | |
118 | goto done; | |
119 | } | |
120 | ||
b05c2385 DA |
121 | ret = drm_ati_alloc_pcigart_table(dev, gart_info); |
122 | if (ret) { | |
b5e89ed5 | 123 | DRM_ERROR("cannot allocate PCI GART page!\n"); |
ea98a92f DA |
124 | goto done; |
125 | } | |
b5e89ed5 | 126 | |
6abf6601 | 127 | pci_gart = gart_info->table_handle->vaddr; |
b05c2385 DA |
128 | address = gart_info->table_handle->vaddr; |
129 | bus_address = gart_info->table_handle->busaddr; | |
b5e89ed5 | 130 | } else { |
ea98a92f DA |
131 | address = gart_info->addr; |
132 | bus_address = gart_info->bus_addr; | |
f67e74ca AM |
133 | DRM_DEBUG("PCI: Gart Table: VRAM %08LX mapped at %08lX\n", |
134 | (unsigned long long)bus_address, | |
135 | (unsigned long)address); | |
1da177e4 LT |
136 | } |
137 | ||
1da177e4 | 138 | |
d30333bb DM |
139 | max_ati_pages = (gart_info->table_size / sizeof(u32)); |
140 | max_real_pages = max_ati_pages / (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); | |
141 | pages = (entry->pages <= max_real_pages) | |
142 | ? entry->pages : max_real_pages; | |
1da177e4 | 143 | |
5a7aad9a | 144 | if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) { |
d30333bb | 145 | memset(pci_gart, 0, max_ati_pages * sizeof(u32)); |
5a7aad9a | 146 | } else { |
6abf6601 | 147 | memset_io((void __iomem *)map->handle, 0, max_ati_pages * sizeof(u32)); |
5a7aad9a | 148 | } |
1da177e4 | 149 | |
5a7aad9a | 150 | gart_idx = 0; |
b5e89ed5 | 151 | for (i = 0; i < pages; i++) { |
1da177e4 | 152 | /* we need to support large memory configurations */ |
7ec700fc | 153 | entry->busaddr[i] = pci_map_page(dev->pdev, entry->pagelist[i], |
296c6ae0 | 154 | 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
1da177e4 | 155 | if (entry->busaddr[i] == 0) { |
b5e89ed5 | 156 | DRM_ERROR("unable to map PCIGART pages!\n"); |
ea98a92f | 157 | drm_ati_pcigart_cleanup(dev, gart_info); |
f26c473c | 158 | address = NULL; |
1da177e4 LT |
159 | bus_address = 0; |
160 | goto done; | |
161 | } | |
162 | page_base = (u32) entry->busaddr[i]; | |
163 | ||
164 | for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) { | |
5a7aad9a DM |
165 | u32 val; |
166 | ||
f2b04cd2 DA |
167 | switch(gart_info->gart_reg_if) { |
168 | case DRM_ATI_GART_IGP: | |
5a7aad9a | 169 | val = page_base | 0xc; |
f2b04cd2 DA |
170 | break; |
171 | case DRM_ATI_GART_PCIE: | |
5a7aad9a | 172 | val = (page_base >> 8) | 0xc; |
f2b04cd2 DA |
173 | break; |
174 | default: | |
175 | case DRM_ATI_GART_PCI: | |
5a7aad9a | 176 | val = page_base; |
f2b04cd2 DA |
177 | break; |
178 | } | |
5a7aad9a DM |
179 | if (gart_info->gart_table_location == |
180 | DRM_ATI_GART_MAIN) | |
181 | pci_gart[gart_idx] = cpu_to_le32(val); | |
182 | else | |
183 | DRM_WRITE32(map, gart_idx * sizeof(u32), val); | |
184 | gart_idx++; | |
1da177e4 LT |
185 | page_base += ATI_PCIGART_PAGE_SIZE; |
186 | } | |
187 | } | |
1da177e4 LT |
188 | ret = 1; |
189 | ||
190 | #if defined(__i386__) || defined(__x86_64__) | |
191 | wbinvd(); | |
192 | #else | |
193 | mb(); | |
194 | #endif | |
195 | ||
b5e89ed5 | 196 | done: |
ea98a92f | 197 | gart_info->addr = address; |
b5e89ed5 | 198 | gart_info->bus_addr = bus_address; |
1da177e4 LT |
199 | return ret; |
200 | } | |
201 | EXPORT_SYMBOL(drm_ati_pcigart_init); |