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drm/bridge: tc358767: filter out too high modes
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / bridge / tc358767.c
CommitLineData
7caff0fc
AG		 1/*
2 * tc358767 eDP bridge driver
3 *
4 * Copyright (C) 2016 CogentEmbedded Inc
5 * Author: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
6 *
7 * Copyright (C) 2016 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de>
8 *
9 * Initially based on: drivers/gpu/drm/i2c/tda998x_drv.c
10 *
11 * Copyright (C) 2012 Texas Instruments
12 * Author: Rob Clark <robdclark@gmail.com>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 */
24
25#include <linux/clk.h>
26#include <linux/device.h>
27#include <linux/gpio/consumer.h>
28#include <linux/i2c.h>
29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/regmap.h>
32#include <linux/slab.h>
33
34#include <drm/drm_atomic_helper.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_dp_helper.h>
37#include <drm/drm_edid.h>
38#include <drm/drm_of.h>
39#include <drm/drm_panel.h>
40
41/* Registers */
42
43/* Display Parallel Interface */
44#define DPIPXLFMT 0x0440
45#define VS_POL_ACTIVE_LOW (1 << 10)
46#define HS_POL_ACTIVE_LOW (1 << 9)
47#define DE_POL_ACTIVE_HIGH (0 << 8)
48#define SUB_CFG_TYPE_CONFIG1 (0 << 2) /* LSB aligned */
49#define SUB_CFG_TYPE_CONFIG2 (1 << 2) /* Loosely Packed */
50#define SUB_CFG_TYPE_CONFIG3 (2 << 2) /* LSB aligned 8-bit */
51#define DPI_BPP_RGB888 (0 << 0)
52#define DPI_BPP_RGB666 (1 << 0)
53#define DPI_BPP_RGB565 (2 << 0)
54
55/* Video Path */
56#define VPCTRL0 0x0450
57#define OPXLFMT_RGB666 (0 << 8)
58#define OPXLFMT_RGB888 (1 << 8)
59#define FRMSYNC_DISABLED (0 << 4) /* Video Timing Gen Disabled */
60#define FRMSYNC_ENABLED (1 << 4) /* Video Timing Gen Enabled */
61#define MSF_DISABLED (0 << 0) /* Magic Square FRC disabled */
62#define MSF_ENABLED (1 << 0) /* Magic Square FRC enabled */
63#define HTIM01 0x0454
64#define HTIM02 0x0458
65#define VTIM01 0x045c
66#define VTIM02 0x0460
67#define VFUEN0 0x0464
68#define VFUEN BIT(0) /* Video Frame Timing Upload */
69
70/* System */
71#define TC_IDREG 0x0500
72#define SYSCTRL 0x0510
73#define DP0_AUDSRC_NO_INPUT (0 << 3)
74#define DP0_AUDSRC_I2S_RX (1 << 3)
75#define DP0_VIDSRC_NO_INPUT (0 << 0)
76#define DP0_VIDSRC_DSI_RX (1 << 0)
77#define DP0_VIDSRC_DPI_RX (2 << 0)
78#define DP0_VIDSRC_COLOR_BAR (3 << 0)
79
80/* Control */
81#define DP0CTL 0x0600
82#define VID_MN_GEN BIT(6) /* Auto-generate M/N values */
83#define EF_EN BIT(5) /* Enable Enhanced Framing */
84#define VID_EN BIT(1) /* Video transmission enable */
85#define DP_EN BIT(0) /* Enable DPTX function */
86
87/* Clocks */
88#define DP0_VIDMNGEN0 0x0610
89#define DP0_VIDMNGEN1 0x0614
90#define DP0_VMNGENSTATUS 0x0618
91
92/* Main Channel */
93#define DP0_SECSAMPLE 0x0640
94#define DP0_VIDSYNCDELAY 0x0644
95#define DP0_TOTALVAL 0x0648
96#define DP0_STARTVAL 0x064c
97#define DP0_ACTIVEVAL 0x0650
98#define DP0_SYNCVAL 0x0654
99#define DP0_MISC 0x0658
100#define TU_SIZE_RECOMMENDED (0x3f << 16) /* LSCLK cycles per TU */
101#define BPC_6 (0 << 5)
102#define BPC_8 (1 << 5)
103
104/* AUX channel */
105#define DP0_AUXCFG0 0x0660
106#define DP0_AUXCFG1 0x0664
107#define AUX_RX_FILTER_EN BIT(16)
108
109#define DP0_AUXADDR 0x0668
110#define DP0_AUXWDATA(i) (0x066c + (i) * 4)
111#define DP0_AUXRDATA(i) (0x067c + (i) * 4)
112#define DP0_AUXSTATUS 0x068c
113#define AUX_STATUS_MASK 0xf0
114#define AUX_STATUS_SHIFT 4
115#define AUX_TIMEOUT BIT(1)
116#define AUX_BUSY BIT(0)
117#define DP0_AUXI2CADR 0x0698
118
119/* Link Training */
120#define DP0_SRCCTRL 0x06a0
121#define DP0_SRCCTRL_SCRMBLDIS BIT(13)
122#define DP0_SRCCTRL_EN810B BIT(12)
123#define DP0_SRCCTRL_NOTP (0 << 8)
124#define DP0_SRCCTRL_TP1 (1 << 8)
125#define DP0_SRCCTRL_TP2 (2 << 8)
126#define DP0_SRCCTRL_LANESKEW BIT(7)
127#define DP0_SRCCTRL_SSCG BIT(3)
128#define DP0_SRCCTRL_LANES_1 (0 << 2)
129#define DP0_SRCCTRL_LANES_2 (1 << 2)
130#define DP0_SRCCTRL_BW27 (1 << 1)
131#define DP0_SRCCTRL_BW162 (0 << 1)
132#define DP0_SRCCTRL_AUTOCORRECT BIT(0)
133#define DP0_LTSTAT 0x06d0
134#define LT_LOOPDONE BIT(13)
135#define LT_STATUS_MASK (0x1f << 8)
136#define LT_CHANNEL1_EQ_BITS (DP_CHANNEL_EQ_BITS << 4)
137#define LT_INTERLANE_ALIGN_DONE BIT(3)
138#define LT_CHANNEL0_EQ_BITS (DP_CHANNEL_EQ_BITS)
139#define DP0_SNKLTCHGREQ 0x06d4
140#define DP0_LTLOOPCTRL 0x06d8
141#define DP0_SNKLTCTRL 0x06e4
142
143/* PHY */
144#define DP_PHY_CTRL 0x0800
145#define DP_PHY_RST BIT(28) /* DP PHY Global Soft Reset */
146#define BGREN BIT(25) /* AUX PHY BGR Enable */
147#define PWR_SW_EN BIT(24) /* PHY Power Switch Enable */
148#define PHY_M1_RST BIT(12) /* Reset PHY1 Main Channel */
149#define PHY_RDY BIT(16) /* PHY Main Channels Ready */
150#define PHY_M0_RST BIT(8) /* Reset PHY0 Main Channel */
151#define PHY_A0_EN BIT(1) /* PHY Aux Channel0 Enable */
152#define PHY_M0_EN BIT(0) /* PHY Main Channel0 Enable */
153
154/* PLL */
155#define DP0_PLLCTRL 0x0900
156#define DP1_PLLCTRL 0x0904 /* not defined in DS */
157#define PXL_PLLCTRL 0x0908
158#define PLLUPDATE BIT(2)
159#define PLLBYP BIT(1)
160#define PLLEN BIT(0)
161#define PXL_PLLPARAM 0x0914
162#define IN_SEL_REFCLK (0 << 14)
163#define SYS_PLLPARAM 0x0918
164#define REF_FREQ_38M4 (0 << 8) /* 38.4 MHz */
165#define REF_FREQ_19M2 (1 << 8) /* 19.2 MHz */
166#define REF_FREQ_26M (2 << 8) /* 26 MHz */
167#define REF_FREQ_13M (3 << 8) /* 13 MHz */
168#define SYSCLK_SEL_LSCLK (0 << 4)
169#define LSCLK_DIV_1 (0 << 0)
170#define LSCLK_DIV_2 (1 << 0)
171
172/* Test & Debug */
173#define TSTCTL 0x0a00
174#define PLL_DBG 0x0a04
175
176static bool tc_test_pattern;
177module_param_named(test, tc_test_pattern, bool, 0644);
178
179struct tc_edp_link {
180 struct drm_dp_link base;
181 u8 assr;
182 int scrambler_dis;
183 int spread;
184 int coding8b10b;
185 u8 swing;
186 u8 preemp;
187};
188
189struct tc_data {
190 struct device *dev;
191 struct regmap *regmap;
192 struct drm_dp_aux aux;
193
194 struct drm_bridge bridge;
195 struct drm_connector connector;
196 struct drm_panel *panel;
197
198 /* link settings */
199 struct tc_edp_link link;
200
201 /* display edid */
202 struct edid *edid;
203 /* current mode */
204 struct drm_display_mode *mode;
205
206 u32 rev;
207 u8 assr;
208
209 struct gpio_desc *sd_gpio;
210 struct gpio_desc *reset_gpio;
211 struct clk *refclk;
212};
213
214static inline struct tc_data *aux_to_tc(struct drm_dp_aux *a)
215{
216 return container_of(a, struct tc_data, aux);
217}
218
219static inline struct tc_data *bridge_to_tc(struct drm_bridge *b)
220{
221 return container_of(b, struct tc_data, bridge);
222}
223
224static inline struct tc_data *connector_to_tc(struct drm_connector *c)
225{
226 return container_of(c, struct tc_data, connector);
227}
228
229/* Simple macros to avoid repeated error checks */
230#define tc_write(reg, var) \
231 do { \
232 ret = regmap_write(tc->regmap, reg, var); \
233 if (ret) \
234 goto err; \
235 } while (0)
236#define tc_read(reg, var) \
237 do { \
238 ret = regmap_read(tc->regmap, reg, var); \
239 if (ret) \
240 goto err; \
241 } while (0)
242
243static inline int tc_poll_timeout(struct regmap *map, unsigned int addr,
244 unsigned int cond_mask,
245 unsigned int cond_value,
246 unsigned long sleep_us, u64 timeout_us)
247{
248 ktime_t timeout = ktime_add_us(ktime_get(), timeout_us);
249 unsigned int val;
250 int ret;
251
252 for (;;) {
253 ret = regmap_read(map, addr, &val);
254 if (ret)
255 break;
256 if ((val & cond_mask) == cond_value)
257 break;
258 if (timeout_us && ktime_compare(ktime_get(), timeout) > 0) {
259 ret = regmap_read(map, addr, &val);
260 break;
261 }
262 if (sleep_us)
263 usleep_range((sleep_us >> 2) + 1, sleep_us);
264 }
265 return ret ?: (((val & cond_mask) == cond_value) ? 0 : -ETIMEDOUT);
266}
267
268static int tc_aux_wait_busy(struct tc_data *tc, unsigned int timeout_ms)
269{
270 return tc_poll_timeout(tc->regmap, DP0_AUXSTATUS, AUX_BUSY, 0,
271 1000, 1000 * timeout_ms);
272}
273
274static int tc_aux_get_status(struct tc_data *tc, u8 *reply)
275{
276 int ret;
277 u32 value;
278
279 ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &value);
280 if (ret < 0)
281 return ret;
282 if (value & AUX_BUSY) {
283 if (value & AUX_TIMEOUT) {
284 dev_err(tc->dev, "i2c access timeout!\n");
285 return -ETIMEDOUT;
286 }
287 return -EBUSY;
288 }
289
290 *reply = (value & AUX_STATUS_MASK) >> AUX_STATUS_SHIFT;
291 return 0;
292}
293
294static ssize_t tc_aux_transfer(struct drm_dp_aux *aux,
295 struct drm_dp_aux_msg *msg)
296{
297 struct tc_data *tc = aux_to_tc(aux);
298 size_t size = min_t(size_t, 8, msg->size);
299 u8 request = msg->request & ~DP_AUX_I2C_MOT;
300 u8 *buf = msg->buffer;
301 u32 tmp = 0;
302 int i = 0;
303 int ret;
304
305 if (size == 0)
306 return 0;
307
308 ret = tc_aux_wait_busy(tc, 100);
309 if (ret)
310 goto err;
311
312 if (request == DP_AUX_I2C_WRITE || request == DP_AUX_NATIVE_WRITE) {
313 /* Store data */
314 while (i < size) {
315 if (request == DP_AUX_NATIVE_WRITE)
316 tmp = tmp | (buf[i] << (8 * (i & 0x3)));
317 else
318 tmp = (tmp << 8) | buf[i];
319 i++;
320 if (((i % 4) == 0) || (i == size)) {
321 tc_write(DP0_AUXWDATA(i >> 2), tmp);
322 tmp = 0;
323 }
324 }
325 } else if (request != DP_AUX_I2C_READ &&
326 request != DP_AUX_NATIVE_READ) {
327 return -EINVAL;
328 }
329
330 /* Store address */
331 tc_write(DP0_AUXADDR, msg->address);
332 /* Start transfer */
333 tc_write(DP0_AUXCFG0, ((size - 1) << 8) | request);
334
335 ret = tc_aux_wait_busy(tc, 100);
336 if (ret)
337 goto err;
338
339 ret = tc_aux_get_status(tc, &msg->reply);
340 if (ret)
341 goto err;
342
343 if (request == DP_AUX_I2C_READ || request == DP_AUX_NATIVE_READ) {
344 /* Read data */
345 while (i < size) {
346 if ((i % 4) == 0)
347 tc_read(DP0_AUXRDATA(i >> 2), &tmp);
348 buf[i] = tmp & 0xff;
349 tmp = tmp >> 8;
350 i++;
351 }
352 }
353
354 return size;
355err:
356 return ret;
357}
358
359static const char * const training_pattern1_errors[] = {
360 "No errors",
361 "Aux write error",
362 "Aux read error",
363 "Max voltage reached error",
364 "Loop counter expired error",
365 "res", "res", "res"
366};
367
368static const char * const training_pattern2_errors[] = {
369 "No errors",
370 "Aux write error",
371 "Aux read error",
372 "Clock recovery failed error",
373 "Loop counter expired error",
374 "res", "res", "res"
375};
376
377static u32 tc_srcctrl(struct tc_data *tc)
378{
379 /*
380 * No training pattern, skew lane 1 data by two LSCLK cycles with
381 * respect to lane 0 data, AutoCorrect Mode = 0
382 */
383 u32 reg = DP0_SRCCTRL_NOTP | DP0_SRCCTRL_LANESKEW;
384
385 if (tc->link.scrambler_dis)
386 reg |= DP0_SRCCTRL_SCRMBLDIS; /* Scrambler Disabled */
387 if (tc->link.coding8b10b)
388 /* Enable 8/10B Encoder (TxData[19:16] not used) */
389 reg |= DP0_SRCCTRL_EN810B;
390 if (tc->link.spread)
391 reg |= DP0_SRCCTRL_SSCG; /* Spread Spectrum Enable */
392 if (tc->link.base.num_lanes == 2)
393 reg |= DP0_SRCCTRL_LANES_2; /* Two Main Channel Lanes */
394 if (tc->link.base.rate != 162000)
395 reg |= DP0_SRCCTRL_BW27; /* 2.7 Gbps link */
396 return reg;
397}
398
399static void tc_wait_pll_lock(struct tc_data *tc)
400{
401 /* Wait for PLL to lock: up to 2.09 ms, depending on refclk */
402 usleep_range(3000, 6000);
403}
404
405static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
406{
407 int ret;
408 int i_pre, best_pre = 1;
409 int i_post, best_post = 1;
410 int div, best_div = 1;
411 int mul, best_mul = 1;
412 int delta, best_delta;
413 int ext_div[] = {1, 2, 3, 5, 7};
414 int best_pixelclock = 0;
415 int vco_hi = 0;
416
417 dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock,
418 refclk);
419 best_delta = pixelclock;
420 /* Loop over all possible ext_divs, skipping invalid configurations */
421 for (i_pre = 0; i_pre < ARRAY_SIZE(ext_div); i_pre++) {
422 /*
423 * refclk / ext_pre_div should be in the 1 to 200 MHz range.
424 * We don't allow any refclk > 200 MHz, only check lower bounds.
425 */
426 if (refclk / ext_div[i_pre] < 1000000)
427 continue;
428 for (i_post = 0; i_post < ARRAY_SIZE(ext_div); i_post++) {
429 for (div = 1; div <= 16; div++) {
430 u32 clk;
431 u64 tmp;
432
433 tmp = pixelclock * ext_div[i_pre] *
434 ext_div[i_post] * div;
435 do_div(tmp, refclk);
436 mul = tmp;
437
438 /* Check limits */
439 if ((mul < 1) || (mul > 128))
440 continue;
441
442 clk = (refclk / ext_div[i_pre] / div) * mul;
443 /*
444 * refclk * mul / (ext_pre_div * pre_div)
445 * should be in the 150 to 650 MHz range
446 */
447 if ((clk > 650000000) || (clk < 150000000))
448 continue;
449
450 clk = clk / ext_div[i_post];
451 delta = clk - pixelclock;
452
453 if (abs(delta) < abs(best_delta)) {
454 best_pre = i_pre;
455 best_post = i_post;
456 best_div = div;
457 best_mul = mul;
458 best_delta = delta;
459 best_pixelclock = clk;
460 }
461 }
462 }
463 }
464 if (best_pixelclock == 0) {
465 dev_err(tc->dev, "Failed to calc clock for %d pixelclock\n",
466 pixelclock);
467 return -EINVAL;
468 }
469
470 dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock,
471 best_delta);
472 dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk,
473 ext_div[best_pre], best_div, best_mul, ext_div[best_post]);
474
475 /* if VCO >= 300 MHz */
476 if (refclk / ext_div[best_pre] / best_div * best_mul >= 300000000)
477 vco_hi = 1;
478 /* see DS */
479 if (best_div == 16)
480 best_div = 0;
481 if (best_mul == 128)
482 best_mul = 0;
483
484 /* Power up PLL and switch to bypass */
485 tc_write(PXL_PLLCTRL, PLLBYP | PLLEN);
486
487 tc_write(PXL_PLLPARAM,
488 (vco_hi << 24) | /* For PLL VCO >= 300 MHz = 1 */
489 (ext_div[best_pre] << 20) | /* External Pre-divider */
490 (ext_div[best_post] << 16) | /* External Post-divider */
491 IN_SEL_REFCLK | /* Use RefClk as PLL input */
492 (best_div << 8) | /* Divider for PLL RefClk */
493 (best_mul << 0)); /* Multiplier for PLL */
494
495 /* Force PLL parameter update and disable bypass */
496 tc_write(PXL_PLLCTRL, PLLUPDATE | PLLEN);
497
498 tc_wait_pll_lock(tc);
499
500 return 0;
501err:
502 return ret;
503}
504
505static int tc_pxl_pll_dis(struct tc_data *tc)
506{
507 /* Enable PLL bypass, power down PLL */
508 return regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP);
509}
510
511static int tc_stream_clock_calc(struct tc_data *tc)
512{
513 int ret;
514 /*
515 * If the Stream clock and Link Symbol clock are
516 * asynchronous with each other, the value of M changes over
517 * time. This way of generating link clock and stream
518 * clock is called Asynchronous Clock mode. The value M
519 * must change while the value N stays constant. The
520 * value of N in this Asynchronous Clock mode must be set
521 * to 2^15 or 32,768.
522 *
523 * LSCLK = 1/10 of high speed link clock
524 *
525 * f_STRMCLK = M/N * f_LSCLK
526 * M/N = f_STRMCLK / f_LSCLK
527 *
528 */
529 tc_write(DP0_VIDMNGEN1, 32768);
530
531 return 0;
532err:
533 return ret;
534}
535
536static int tc_aux_link_setup(struct tc_data *tc)
537{
538 unsigned long rate;
539 u32 value;
540 int ret;
541
542 rate = clk_get_rate(tc->refclk);
543 switch (rate) {
544 case 38400000:
545 value = REF_FREQ_38M4;
546 break;
547 case 26000000:
548 value = REF_FREQ_26M;
549 break;
550 case 19200000:
551 value = REF_FREQ_19M2;
552 break;
553 case 13000000:
554 value = REF_FREQ_13M;
555 break;
556 default:
557 dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate);
558 return -EINVAL;
559 }
560
561 /* Setup DP-PHY / PLL */
562 value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
563 tc_write(SYS_PLLPARAM, value);
564
565 tc_write(DP_PHY_CTRL, BGREN | PWR_SW_EN | BIT(2) | PHY_A0_EN);
566
567 /*
568 * Initially PLLs are in bypass. Force PLL parameter update,
569 * disable PLL bypass, enable PLL
570 */
571 tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN);
572 tc_wait_pll_lock(tc);
573
574 tc_write(DP1_PLLCTRL, PLLUPDATE | PLLEN);
575 tc_wait_pll_lock(tc);
576
577 ret = tc_poll_timeout(tc->regmap, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 1,
578 1000);
579 if (ret == -ETIMEDOUT) {
580 dev_err(tc->dev, "Timeout waiting for PHY to become ready");
581 return ret;
582 } else if (ret)
583 goto err;
584
585 /* Setup AUX link */
586 tc_write(DP0_AUXCFG1, AUX_RX_FILTER_EN |
587 (0x06 << 8) | /* Aux Bit Period Calculator Threshold */
588 (0x3f << 0)); /* Aux Response Timeout Timer */
589
590 return 0;
591err:
592 dev_err(tc->dev, "tc_aux_link_setup failed: %d\n", ret);
593 return ret;
594}
595
596static int tc_get_display_props(struct tc_data *tc)
597{
598 int ret;
599 /* temp buffer */
600 u8 tmp[8];
601
602 /* Read DP Rx Link Capability */
603 ret = drm_dp_link_probe(&tc->aux, &tc->link.base);
604 if (ret < 0)
605 goto err_dpcd_read;
cffd2b16
AG		 606 if (tc->link.base.rate != 162000 && tc->link.base.rate != 270000) {
607 dev_dbg(tc->dev, "Falling to 2.7 Gbps rate\n");
608 tc->link.base.rate = 270000;
609 }
610
611 if (tc->link.base.num_lanes > 2) {
612 dev_dbg(tc->dev, "Falling to 2 lanes\n");
613 tc->link.base.num_lanes = 2;
614 }
7caff0fc
AG		 615
616 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, tmp);
617 if (ret < 0)
618 goto err_dpcd_read;
619 tc->link.spread = tmp[0] & BIT(0); /* 0.5% down spread */
620
621 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, tmp);
622 if (ret < 0)
623 goto err_dpcd_read;
624 tc->link.coding8b10b = tmp[0] & BIT(0);
625 tc->link.scrambler_dis = 0;
626 /* read assr */
627 ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, tmp);
628 if (ret < 0)
629 goto err_dpcd_read;
630 tc->link.assr = tmp[0] & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;
631
632 dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n",
633 tc->link.base.revision >> 4, tc->link.base.revision & 0x0f,
634 (tc->link.base.rate == 162000) ? "1.62Gbps" : "2.7Gbps",
635 tc->link.base.num_lanes,
636 (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) ?
637 "enhanced" : "non-enhanced");
638 dev_dbg(tc->dev, "ANSI 8B/10B: %d\n", tc->link.coding8b10b);
639 dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n",
640 tc->link.assr, tc->assr);
641
642 return 0;
643
644err_dpcd_read:
645 dev_err(tc->dev, "failed to read DPCD: %d\n", ret);
646 return ret;
7caff0fc
AG		 647}
648
649static int tc_set_video_mode(struct tc_data *tc, struct drm_display_mode *mode)
650{
651 int ret;
652 int vid_sync_dly;
653 int max_tu_symbol;
654
655 int left_margin = mode->htotal - mode->hsync_end;
656 int right_margin = mode->hsync_start - mode->hdisplay;
657 int hsync_len = mode->hsync_end - mode->hsync_start;
658 int upper_margin = mode->vtotal - mode->vsync_end;
659 int lower_margin = mode->vsync_start - mode->vdisplay;
660 int vsync_len = mode->vsync_end - mode->vsync_start;
661
662 dev_dbg(tc->dev, "set mode %dx%d\n",
663 mode->hdisplay, mode->vdisplay);
664 dev_dbg(tc->dev, "H margin %d,%d sync %d\n",
665 left_margin, right_margin, hsync_len);
666 dev_dbg(tc->dev, "V margin %d,%d sync %d\n",
667 upper_margin, lower_margin, vsync_len);
668 dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal);
669
670
671 /* LCD Ctl Frame Size */
672 tc_write(VPCTRL0, (0x40 << 20) /* VSDELAY */ |
673 OPXLFMT_RGB888 | FRMSYNC_DISABLED | MSF_DISABLED);
674 tc_write(HTIM01, (left_margin << 16) | /* H back porch */
675 (hsync_len << 0)); /* Hsync */
676 tc_write(HTIM02, (right_margin << 16) | /* H front porch */
677 (mode->hdisplay << 0)); /* width */
678 tc_write(VTIM01, (upper_margin << 16) | /* V back porch */
679 (vsync_len << 0)); /* Vsync */
680 tc_write(VTIM02, (lower_margin << 16) | /* V front porch */
681 (mode->vdisplay << 0)); /* height */
682 tc_write(VFUEN0, VFUEN); /* update settings */
683
684 /* Test pattern settings */
685 tc_write(TSTCTL,
686 (120 << 24) | /* Red Color component value */
687 (20 << 16) | /* Green Color component value */
688 (99 << 8) | /* Blue Color component value */
689 (1 << 4) | /* Enable I2C Filter */
690 (2 << 0) | /* Color bar Mode */
691 0);
692
693 /* DP Main Stream Attributes */
694 vid_sync_dly = hsync_len + left_margin + mode->hdisplay;
695 tc_write(DP0_VIDSYNCDELAY,
696 (0x003e << 16) | /* thresh_dly */
697 (vid_sync_dly << 0));
698
699 tc_write(DP0_TOTALVAL, (mode->vtotal << 16) | (mode->htotal));
700
701 tc_write(DP0_STARTVAL,
702 ((upper_margin + vsync_len) << 16) |
703 ((left_margin + hsync_len) << 0));
704
705 tc_write(DP0_ACTIVEVAL, (mode->vdisplay << 16) | (mode->hdisplay));
706
707 tc_write(DP0_SYNCVAL, (vsync_len << 16) | (hsync_len << 0));
708
709 tc_write(DPIPXLFMT, VS_POL_ACTIVE_LOW | HS_POL_ACTIVE_LOW |
710 DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 | DPI_BPP_RGB888);
711
712 /*
713 * Recommended maximum number of symbols transferred in a transfer unit:
714 * DIV_ROUND_UP((input active video bandwidth in bytes) * tu_size,
715 * (output active video bandwidth in bytes))
716 * Must be less than tu_size.
717 */
718 max_tu_symbol = TU_SIZE_RECOMMENDED - 1;
719 tc_write(DP0_MISC, (max_tu_symbol << 23) | TU_SIZE_RECOMMENDED | BPC_8);
720
721 return 0;
722err:
723 return ret;
724}
725
726static int tc_link_training(struct tc_data *tc, int pattern)
727{
728 const char * const *errors;
729 u32 srcctrl = tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
730 DP0_SRCCTRL_AUTOCORRECT;
731 int timeout;
732 int retry;
733 u32 value;
734 int ret;
735
736 if (pattern == DP_TRAINING_PATTERN_1) {
737 srcctrl |= DP0_SRCCTRL_TP1;
738 errors = training_pattern1_errors;
739 } else {
740 srcctrl |= DP0_SRCCTRL_TP2;
741 errors = training_pattern2_errors;
742 }
743
744 /* Set DPCD 0x102 for Training Part 1 or 2 */
745 tc_write(DP0_SNKLTCTRL, DP_LINK_SCRAMBLING_DISABLE | pattern);
746
747 tc_write(DP0_LTLOOPCTRL,
748 (0x0f << 28) | /* Defer Iteration Count */
749 (0x0f << 24) | /* Loop Iteration Count */
750 (0x0d << 0)); /* Loop Timer Delay */
751
752 retry = 5;
753 do {
754 /* Set DP0 Training Pattern */
755 tc_write(DP0_SRCCTRL, srcctrl);
756
757 /* Enable DP0 to start Link Training */
758 tc_write(DP0CTL, DP_EN);
759
760 /* wait */
761 timeout = 1000;
762 do {
763 tc_read(DP0_LTSTAT, &value);
764 udelay(1);
765 } while ((!(value & LT_LOOPDONE)) && (--timeout));
766 if (timeout == 0) {
767 dev_err(tc->dev, "Link training timeout!\n");
768 } else {
769 int pattern = (value >> 11) & 0x3;
770 int error = (value >> 8) & 0x7;
771
772 dev_dbg(tc->dev,
773 "Link training phase %d done after %d uS: %s\n",
774 pattern, 1000 - timeout, errors[error]);
775 if (pattern == DP_TRAINING_PATTERN_1 && error == 0)
776 break;
777 if (pattern == DP_TRAINING_PATTERN_2) {
778 value &= LT_CHANNEL1_EQ_BITS |
779 LT_INTERLANE_ALIGN_DONE |
780 LT_CHANNEL0_EQ_BITS;
781 /* in case of two lanes */
782 if ((tc->link.base.num_lanes == 2) &&
783 (value == (LT_CHANNEL1_EQ_BITS |
784 LT_INTERLANE_ALIGN_DONE |
785 LT_CHANNEL0_EQ_BITS)))
786 break;
787 /* in case of one line */
788 if ((tc->link.base.num_lanes == 1) &&
789 (value == (LT_INTERLANE_ALIGN_DONE |
790 LT_CHANNEL0_EQ_BITS)))
791 break;
792 }
793 }
794 /* restart */
795 tc_write(DP0CTL, 0);
796 usleep_range(10, 20);
797 } while (--retry);
798 if (retry == 0) {
799 dev_err(tc->dev, "Failed to finish training phase %d\n",
800 pattern);
801 }
802
803 return 0;
804err:
805 return ret;
806}
807
808static int tc_main_link_setup(struct tc_data *tc)
809{
810 struct drm_dp_aux *aux = &tc->aux;
811 struct device *dev = tc->dev;
812 unsigned int rate;
813 u32 dp_phy_ctrl;
814 int timeout;
815 bool aligned;
816 bool ready;
817 u32 value;
818 int ret;
819 u8 tmp[8];
820
821 /* display mode should be set at this point */
822 if (!tc->mode)
823 return -EINVAL;
824
825 /* from excel file - DP0_SrcCtrl */
826 tc_write(DP0_SRCCTRL, DP0_SRCCTRL_SCRMBLDIS | DP0_SRCCTRL_EN810B |
827 DP0_SRCCTRL_LANESKEW | DP0_SRCCTRL_LANES_2 |
828 DP0_SRCCTRL_BW27 | DP0_SRCCTRL_AUTOCORRECT);
829 /* from excel file - DP1_SrcCtrl */
830 tc_write(0x07a0, 0x00003083);
831
832 rate = clk_get_rate(tc->refclk);
833 switch (rate) {
834 case 38400000:
835 value = REF_FREQ_38M4;
836 break;
837 case 26000000:
838 value = REF_FREQ_26M;
839 break;
840 case 19200000:
841 value = REF_FREQ_19M2;
842 break;
843 case 13000000:
844 value = REF_FREQ_13M;
845 break;
846 default:
847 return -EINVAL;
848 }
849 value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
850 tc_write(SYS_PLLPARAM, value);
851 /* Setup Main Link */
852 dp_phy_ctrl = BGREN | PWR_SW_EN | BIT(2) | PHY_A0_EN | PHY_M0_EN;
853 tc_write(DP_PHY_CTRL, dp_phy_ctrl);
854 msleep(100);
855
856 /* PLL setup */
857 tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN);
858 tc_wait_pll_lock(tc);
859
860 tc_write(DP1_PLLCTRL, PLLUPDATE | PLLEN);
861 tc_wait_pll_lock(tc);
862
863 /* PXL PLL setup */
864 if (tc_test_pattern) {
865 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk),
866 1000 * tc->mode->clock);
867 if (ret)
868 goto err;
869 }
870
871 /* Reset/Enable Main Links */
872 dp_phy_ctrl |= DP_PHY_RST | PHY_M1_RST | PHY_M0_RST;
873 tc_write(DP_PHY_CTRL, dp_phy_ctrl);
874 usleep_range(100, 200);
875 dp_phy_ctrl &= ~(DP_PHY_RST | PHY_M1_RST | PHY_M0_RST);
876 tc_write(DP_PHY_CTRL, dp_phy_ctrl);
877
878 timeout = 1000;
879 do {
880 tc_read(DP_PHY_CTRL, &value);
881 udelay(1);
882 } while ((!(value & PHY_RDY)) && (--timeout));
883
884 if (timeout == 0) {
885 dev_err(dev, "timeout waiting for phy become ready");
886 return -ETIMEDOUT;
887 }
888
889 /* Set misc: 8 bits per color */
890 ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8);
891 if (ret)
892 goto err;
893
894 /*
895 * ASSR mode
896 * on TC358767 side ASSR configured through strap pin
897 * seems there is no way to change this setting from SW
898 *
899 * check is tc configured for same mode
900 */
901 if (tc->assr != tc->link.assr) {
902 dev_dbg(dev, "Trying to set display to ASSR: %d\n",
903 tc->assr);
904 /* try to set ASSR on display side */
905 tmp[0] = tc->assr;
906 ret = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, tmp[0]);
907 if (ret < 0)
908 goto err_dpcd_read;
909 /* read back */
910 ret = drm_dp_dpcd_readb(aux, DP_EDP_CONFIGURATION_SET, tmp);
911 if (ret < 0)
912 goto err_dpcd_read;
913
914 if (tmp[0] != tc->assr) {
87291e5d 915 dev_dbg(dev, "Failed to switch display ASSR to %d, falling back to unscrambled mode\n",
7caff0fc
AG		 916 tc->assr);
917 /* trying with disabled scrambler */
918 tc->link.scrambler_dis = 1;
919 }
920 }
921
922 /* Setup Link & DPRx Config for Training */
923 ret = drm_dp_link_configure(aux, &tc->link.base);
924 if (ret < 0)
925 goto err_dpcd_write;
926
927 /* DOWNSPREAD_CTRL */
928 tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00;
929 /* MAIN_LINK_CHANNEL_CODING_SET */
930 tmp[1] = tc->link.coding8b10b ? DP_SET_ANSI_8B10B : 0x00;
931 ret = drm_dp_dpcd_write(aux, DP_DOWNSPREAD_CTRL, tmp, 2);
932 if (ret < 0)
933 goto err_dpcd_write;
934
935 ret = tc_link_training(tc, DP_TRAINING_PATTERN_1);
936 if (ret)
937 goto err;
938
939 ret = tc_link_training(tc, DP_TRAINING_PATTERN_2);
940 if (ret)
941 goto err;
942
943 /* Clear DPCD 0x102 */
944 /* Note: Can Not use DP0_SNKLTCTRL (0x06E4) short cut */
945 tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00;
946 ret = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, tmp[0]);
947 if (ret < 0)
948 goto err_dpcd_write;
949
950 /* Clear Training Pattern, set AutoCorrect Mode = 1 */
951 tc_write(DP0_SRCCTRL, tc_srcctrl(tc) | DP0_SRCCTRL_AUTOCORRECT);
952
953 /* Wait */
954 timeout = 100;
955 do {
956 udelay(1);
957 /* Read DPCD 0x202-0x207 */
958 ret = drm_dp_dpcd_read_link_status(aux, tmp + 2);
959 if (ret < 0)
960 goto err_dpcd_read;
961 ready = (tmp[2] == ((DP_CHANNEL_EQ_BITS << 4) | /* Lane1 */
962 DP_CHANNEL_EQ_BITS)); /* Lane0 */
963 aligned = tmp[4] & DP_INTERLANE_ALIGN_DONE;
964 } while ((--timeout) && !(ready && aligned));
965
966 if (timeout == 0) {
967 /* Read DPCD 0x200-0x201 */
968 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT, tmp, 2);
969 if (ret < 0)
970 goto err_dpcd_read;
971 dev_info(dev, "0x0200 SINK_COUNT: 0x%02x\n", tmp[0]);
972 dev_info(dev, "0x0201 DEVICE_SERVICE_IRQ_VECTOR: 0x%02x\n",
973 tmp[1]);
974 dev_info(dev, "0x0202 LANE0_1_STATUS: 0x%02x\n", tmp[2]);
975 dev_info(dev, "0x0204 LANE_ALIGN_STATUS_UPDATED: 0x%02x\n",
976 tmp[4]);
977 dev_info(dev, "0x0205 SINK_STATUS: 0x%02x\n", tmp[5]);
978 dev_info(dev, "0x0206 ADJUST_REQUEST_LANE0_1: 0x%02x\n",
979 tmp[6]);
980
981 if (!ready)
982 dev_err(dev, "Lane0/1 not ready\n");
983 if (!aligned)
984 dev_err(dev, "Lane0/1 not aligned\n");
985 return -EAGAIN;
986 }
987
988 ret = tc_set_video_mode(tc, tc->mode);
989 if (ret)
990 goto err;
991
992 /* Set M/N */
993 ret = tc_stream_clock_calc(tc);
994 if (ret)
995 goto err;
996
997 return 0;
998err_dpcd_read:
999 dev_err(tc->dev, "Failed to read DPCD: %d\n", ret);
1000 return ret;
1001err_dpcd_write:
1002 dev_err(tc->dev, "Failed to write DPCD: %d\n", ret);
1003err:
1004 return ret;
1005}
1006
1007static int tc_main_link_stream(struct tc_data *tc, int state)
1008{
1009 int ret;
1010 u32 value;
1011
1012 dev_dbg(tc->dev, "stream: %d\n", state);
1013
1014 if (state) {
1015 value = VID_MN_GEN | DP_EN;
1016 if (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
1017 value |= EF_EN;
1018 tc_write(DP0CTL, value);
1019 /*
1020 * VID_EN assertion should be delayed by at least N * LSCLK
1021 * cycles from the time VID_MN_GEN is enabled in order to
1022 * generate stable values for VID_M. LSCLK is 270 MHz or
1023 * 162 MHz, VID_N is set to 32768 in tc_stream_clock_calc(),
1024 * so a delay of at least 203 us should suffice.
1025 */
1026 usleep_range(500, 1000);
1027 value |= VID_EN;
1028 tc_write(DP0CTL, value);
1029 /* Set input interface */
1030 value = DP0_AUDSRC_NO_INPUT;
1031 if (tc_test_pattern)
1032 value |= DP0_VIDSRC_COLOR_BAR;
1033 else
1034 value |= DP0_VIDSRC_DPI_RX;
1035 tc_write(SYSCTRL, value);
1036 } else {
1037 tc_write(DP0CTL, 0);
1038 }
1039
1040 return 0;
1041err:
1042 return ret;
1043}
1044
7caff0fc
AG		 1045static void tc_bridge_pre_enable(struct drm_bridge *bridge)
1046{
1047 struct tc_data *tc = bridge_to_tc(bridge);
1048
1049 drm_panel_prepare(tc->panel);
1050}
1051
1052static void tc_bridge_enable(struct drm_bridge *bridge)
1053{
1054 struct tc_data *tc = bridge_to_tc(bridge);
1055 int ret;
1056
1057 ret = tc_main_link_setup(tc);
1058 if (ret < 0) {
1059 dev_err(tc->dev, "main link setup error: %d\n", ret);
1060 return;
1061 }
1062
1063 ret = tc_main_link_stream(tc, 1);
1064 if (ret < 0) {
1065 dev_err(tc->dev, "main link stream start error: %d\n", ret);
1066 return;
1067 }
1068
1069 drm_panel_enable(tc->panel);
1070}
1071
1072static void tc_bridge_disable(struct drm_bridge *bridge)
1073{
1074 struct tc_data *tc = bridge_to_tc(bridge);
1075 int ret;
1076
1077 drm_panel_disable(tc->panel);
1078
1079 ret = tc_main_link_stream(tc, 0);
1080 if (ret < 0)
1081 dev_err(tc->dev, "main link stream stop error: %d\n", ret);
1082}
1083
1084static void tc_bridge_post_disable(struct drm_bridge *bridge)
1085{
1086 struct tc_data *tc = bridge_to_tc(bridge);
1087
1088 drm_panel_unprepare(tc->panel);
1089}
1090
1091static bool tc_bridge_mode_fixup(struct drm_bridge *bridge,
1092 const struct drm_display_mode *mode,
1093 struct drm_display_mode *adj)
1094{
1095 /* Fixup sync polarities, both hsync and vsync are active low */
1096 adj->flags = mode->flags;
1097 adj->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
1098 adj->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
1099
1100 return true;
1101}
1102
1103static int tc_connector_mode_valid(struct drm_connector *connector,
1104 struct drm_display_mode *mode)
1105{
99fc8e96
AG		 1106 /* DPI interface clock limitation: upto 154 MHz */
1107 if (mode->clock > 154000)
1108 return MODE_CLOCK_HIGH;
1109
7caff0fc
AG		 1110 return MODE_OK;
1111}
1112
1113static void tc_bridge_mode_set(struct drm_bridge *bridge,
1114 struct drm_display_mode *mode,
1115 struct drm_display_mode *adj)
1116{
1117 struct tc_data *tc = bridge_to_tc(bridge);
1118
1119 tc->mode = mode;
1120}
1121
1122static int tc_connector_get_modes(struct drm_connector *connector)
1123{
1124 struct tc_data *tc = connector_to_tc(connector);
1125 struct edid *edid;
1126 unsigned int count;
1127
1128 if (tc->panel && tc->panel->funcs && tc->panel->funcs->get_modes) {
1129 count = tc->panel->funcs->get_modes(tc->panel);
1130 if (count > 0)
1131 return count;
1132 }
1133
1134 edid = drm_get_edid(connector, &tc->aux.ddc);
1135
1136 kfree(tc->edid);
1137 tc->edid = edid;
1138 if (!edid)
1139 return 0;
1140
1141 drm_mode_connector_update_edid_property(connector, edid);
1142 count = drm_add_edid_modes(connector, edid);
1143
1144 return count;
1145}
1146
1147static void tc_connector_set_polling(struct tc_data *tc,
1148 struct drm_connector *connector)
1149{
1150 /* TODO: add support for HPD */
1151 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1152 DRM_CONNECTOR_POLL_DISCONNECT;
1153}
1154
1155static struct drm_encoder *
1156tc_connector_best_encoder(struct drm_connector *connector)
1157{
1158 struct tc_data *tc = connector_to_tc(connector);
1159
1160 return tc->bridge.encoder;
1161}
1162
1163static const struct drm_connector_helper_funcs tc_connector_helper_funcs = {
1164 .get_modes = tc_connector_get_modes,
1165 .mode_valid = tc_connector_mode_valid,
1166 .best_encoder = tc_connector_best_encoder,
1167};
1168
7caff0fc 1169static const struct drm_connector_funcs tc_connector_funcs = {
7caff0fc 1170 .fill_modes = drm_helper_probe_single_connector_modes,
fdd8326a 1171 .destroy = drm_connector_cleanup,
7caff0fc
AG		 1172 .reset = drm_atomic_helper_connector_reset,
1173 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1174 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1175};
1176
1177static int tc_bridge_attach(struct drm_bridge *bridge)
1178{
1179 u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1180 struct tc_data *tc = bridge_to_tc(bridge);
1181 struct drm_device *drm = bridge->dev;
1182 int ret;
1183
1184 /* Create eDP connector */
1185 drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs);
1186 ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs,
1187 DRM_MODE_CONNECTOR_eDP);
1188 if (ret)
1189 return ret;
1190
1191 if (tc->panel)
1192 drm_panel_attach(tc->panel, &tc->connector);
1193
1194 drm_display_info_set_bus_formats(&tc->connector.display_info,
1195 &bus_format, 1);
1196 drm_mode_connector_attach_encoder(&tc->connector, tc->bridge.encoder);
1197
1198 return 0;
1199}
1200
1201static const struct drm_bridge_funcs tc_bridge_funcs = {
1202 .attach = tc_bridge_attach,
1203 .mode_set = tc_bridge_mode_set,
1204 .pre_enable = tc_bridge_pre_enable,
1205 .enable = tc_bridge_enable,
1206 .disable = tc_bridge_disable,
1207 .post_disable = tc_bridge_post_disable,
1208 .mode_fixup = tc_bridge_mode_fixup,
1209};
1210
1211static bool tc_readable_reg(struct device *dev, unsigned int reg)
1212{
1213 return reg != SYSCTRL;
1214}
1215
1216static const struct regmap_range tc_volatile_ranges[] = {
1217 regmap_reg_range(DP0_AUXWDATA(0), DP0_AUXSTATUS),
1218 regmap_reg_range(DP0_LTSTAT, DP0_SNKLTCHGREQ),
1219 regmap_reg_range(DP_PHY_CTRL, DP_PHY_CTRL),
1220 regmap_reg_range(DP0_PLLCTRL, PXL_PLLCTRL),
1221 regmap_reg_range(VFUEN0, VFUEN0),
1222};
1223
1224static const struct regmap_access_table tc_volatile_table = {
1225 .yes_ranges = tc_volatile_ranges,
1226 .n_yes_ranges = ARRAY_SIZE(tc_volatile_ranges),
1227};
1228
1229static bool tc_writeable_reg(struct device *dev, unsigned int reg)
1230{
1231 return (reg != TC_IDREG) &&
1232 (reg != DP0_LTSTAT) &&
1233 (reg != DP0_SNKLTCHGREQ);
1234}
1235
1236static const struct regmap_config tc_regmap_config = {
1237 .name = "tc358767",
1238 .reg_bits = 16,
1239 .val_bits = 32,
1240 .reg_stride = 4,
1241 .max_register = PLL_DBG,
1242 .cache_type = REGCACHE_RBTREE,
1243 .readable_reg = tc_readable_reg,
1244 .volatile_table = &tc_volatile_table,
1245 .writeable_reg = tc_writeable_reg,
1246 .reg_format_endian = REGMAP_ENDIAN_BIG,
1247 .val_format_endian = REGMAP_ENDIAN_LITTLE,
1248};
1249
1250static int tc_probe(struct i2c_client *client, const struct i2c_device_id *id)
1251{
1252 struct device *dev = &client->dev;
7caff0fc
AG		 1253 struct tc_data *tc;
1254 int ret;
1255
1256 tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL);
1257 if (!tc)
1258 return -ENOMEM;
1259
1260 tc->dev = dev;
1261
1262 /* port@2 is the output port */
ebc94461 1263 ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &tc->panel, NULL);
d630213f 1264 if (ret && ret != -ENODEV)
ebc94461 1265 return ret;
7caff0fc
AG		 1266
1267 /* Shut down GPIO is optional */
1268 tc->sd_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH);
1269 if (IS_ERR(tc->sd_gpio))
1270 return PTR_ERR(tc->sd_gpio);
1271
1272 if (tc->sd_gpio) {
1273 gpiod_set_value_cansleep(tc->sd_gpio, 0);
1274 usleep_range(5000, 10000);
1275 }
1276
1277 /* Reset GPIO is optional */
1278 tc->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
1279 if (IS_ERR(tc->reset_gpio))
1280 return PTR_ERR(tc->reset_gpio);
1281
1282 if (tc->reset_gpio) {
1283 gpiod_set_value_cansleep(tc->reset_gpio, 1);
1284 usleep_range(5000, 10000);
1285 }
1286
1287 tc->refclk = devm_clk_get(dev, "ref");
1288 if (IS_ERR(tc->refclk)) {
1289 ret = PTR_ERR(tc->refclk);
1290 dev_err(dev, "Failed to get refclk: %d\n", ret);
1291 return ret;
1292 }
1293
1294 tc->regmap = devm_regmap_init_i2c(client, &tc_regmap_config);
1295 if (IS_ERR(tc->regmap)) {
1296 ret = PTR_ERR(tc->regmap);
1297 dev_err(dev, "Failed to initialize regmap: %d\n", ret);
1298 return ret;
1299 }
1300
1301 ret = regmap_read(tc->regmap, TC_IDREG, &tc->rev);
1302 if (ret) {
1303 dev_err(tc->dev, "can not read device ID: %d\n", ret);
1304 return ret;
1305 }
1306
1307 if ((tc->rev != 0x6601) && (tc->rev != 0x6603)) {
1308 dev_err(tc->dev, "invalid device ID: 0x%08x\n", tc->rev);
1309 return -EINVAL;
1310 }
1311
1312 tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */
1313
1314 ret = tc_aux_link_setup(tc);
1315 if (ret)
1316 return ret;
1317
1318 /* Register DP AUX channel */
1319 tc->aux.name = "TC358767 AUX i2c adapter";
1320 tc->aux.dev = tc->dev;
1321 tc->aux.transfer = tc_aux_transfer;
1322 ret = drm_dp_aux_register(&tc->aux);
1323 if (ret)
1324 return ret;
1325
1326 ret = tc_get_display_props(tc);
1327 if (ret)
1328 goto err_unregister_aux;
1329
1330 tc_connector_set_polling(tc, &tc->connector);
1331
1332 tc->bridge.funcs = &tc_bridge_funcs;
1333 tc->bridge.of_node = dev->of_node;
dc01732e 1334 drm_bridge_add(&tc->bridge);
7caff0fc
AG		 1335
1336 i2c_set_clientdata(client, tc);
1337
1338 return 0;
1339err_unregister_aux:
1340 drm_dp_aux_unregister(&tc->aux);
1341 return ret;
1342}
1343
1344static int tc_remove(struct i2c_client *client)
1345{
1346 struct tc_data *tc = i2c_get_clientdata(client);
1347
1348 drm_bridge_remove(&tc->bridge);
1349 drm_dp_aux_unregister(&tc->aux);
1350
1351 tc_pxl_pll_dis(tc);
1352
1353 return 0;
1354}
1355
1356static const struct i2c_device_id tc358767_i2c_ids[] = {
1357 { "tc358767", 0 },
1358 { }
1359};
1360MODULE_DEVICE_TABLE(i2c, tc358767_i2c_ids);
1361
1362static const struct of_device_id tc358767_of_ids[] = {
1363 { .compatible = "toshiba,tc358767", },
1364 { }
1365};
1366MODULE_DEVICE_TABLE(of, tc358767_of_ids);
1367
1368static struct i2c_driver tc358767_driver = {
1369 .driver = {
1370 .name = "tc358767",
1371 .of_match_table = tc358767_of_ids,
1372 },
1373 .id_table = tc358767_i2c_ids,
1374 .probe = tc_probe,
1375 .remove = tc_remove,
1376};
1377module_i2c_driver(tc358767_driver);
1378
1379MODULE_AUTHOR("Andrey Gusakov <andrey.gusakov@cogentembedded.com>");
1380MODULE_DESCRIPTION("tc358767 eDP encoder driver");
1381MODULE_LICENSE("GPL");
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