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673a394b EA |
1 | /************************************************************************** |
2 | * | |
3 | * Copyright (c) 2006-2007 Tungsten Graphics, Inc., Cedar Park, TX., USA | |
4 | * All Rights Reserved. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the | |
8 | * "Software"), to deal in the Software without restriction, including | |
9 | * without limitation the rights to use, copy, modify, merge, publish, | |
10 | * distribute, sub license, and/or sell copies of the Software, and to | |
11 | * permit persons to whom the Software is furnished to do so, subject to | |
12 | * the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice (including the | |
15 | * next paragraph) shall be included in all copies or substantial portions | |
16 | * of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
22 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
23 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
24 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
25 | * | |
26 | **************************************************************************/ | |
27 | /* | |
28 | * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com> | |
29 | */ | |
30 | ||
2d1a8a48 | 31 | #include <linux/export.h> |
760285e7 | 32 | #include <drm/drmP.h> |
673a394b EA |
33 | |
34 | #if defined(CONFIG_X86) | |
2a0c772f RZ |
35 | |
36 | /* | |
37 | * clflushopt is an unordered instruction which needs fencing with mfence or | |
38 | * sfence to avoid ordering issues. For drm_clflush_page this fencing happens | |
39 | * in the caller. | |
40 | */ | |
673a394b EA |
41 | static void |
42 | drm_clflush_page(struct page *page) | |
43 | { | |
44 | uint8_t *page_virtual; | |
45 | unsigned int i; | |
87229ad9 | 46 | const int size = boot_cpu_data.x86_clflush_size; |
673a394b EA |
47 | |
48 | if (unlikely(page == NULL)) | |
49 | return; | |
50 | ||
1c9c20f6 | 51 | page_virtual = kmap_atomic(page); |
87229ad9 | 52 | for (i = 0; i < PAGE_SIZE; i += size) |
2a0c772f | 53 | clflushopt(page_virtual + i); |
1c9c20f6 | 54 | kunmap_atomic(page_virtual); |
673a394b | 55 | } |
673a394b | 56 | |
c9c97b8c DA |
57 | static void drm_cache_flush_clflush(struct page *pages[], |
58 | unsigned long num_pages) | |
59 | { | |
60 | unsigned long i; | |
61 | ||
62 | mb(); | |
63 | for (i = 0; i < num_pages; i++) | |
64 | drm_clflush_page(*pages++); | |
65 | mb(); | |
66 | } | |
67 | ||
68 | static void | |
69 | drm_clflush_ipi_handler(void *null) | |
70 | { | |
71 | wbinvd(); | |
72 | } | |
c9c97b8c | 73 | #endif |
ed017d9f | 74 | |
673a394b EA |
75 | void |
76 | drm_clflush_pages(struct page *pages[], unsigned long num_pages) | |
77 | { | |
78 | ||
79 | #if defined(CONFIG_X86) | |
80 | if (cpu_has_clflush) { | |
c9c97b8c | 81 | drm_cache_flush_clflush(pages, num_pages); |
673a394b EA |
82 | return; |
83 | } | |
673a394b | 84 | |
c9c97b8c DA |
85 | if (on_each_cpu(drm_clflush_ipi_handler, NULL, 1) != 0) |
86 | printk(KERN_ERR "Timed out waiting for cache flush.\n"); | |
87 | ||
88 | #elif defined(__powerpc__) | |
89 | unsigned long i; | |
90 | for (i = 0; i < num_pages; i++) { | |
91 | struct page *page = pages[i]; | |
92 | void *page_virtual; | |
93 | ||
94 | if (unlikely(page == NULL)) | |
95 | continue; | |
96 | ||
1c9c20f6 | 97 | page_virtual = kmap_atomic(page); |
c9c97b8c DA |
98 | flush_dcache_range((unsigned long)page_virtual, |
99 | (unsigned long)page_virtual + PAGE_SIZE); | |
1c9c20f6 | 100 | kunmap_atomic(page_virtual); |
c9c97b8c DA |
101 | } |
102 | #else | |
ed017d9f DA |
103 | printk(KERN_ERR "Architecture has no drm_cache.c support\n"); |
104 | WARN_ON_ONCE(1); | |
e0f0754f | 105 | #endif |
673a394b EA |
106 | } |
107 | EXPORT_SYMBOL(drm_clflush_pages); | |
6d5cd9cb | 108 | |
9da3da66 CW |
109 | void |
110 | drm_clflush_sg(struct sg_table *st) | |
111 | { | |
112 | #if defined(CONFIG_X86) | |
113 | if (cpu_has_clflush) { | |
f5ddf697 | 114 | struct sg_page_iter sg_iter; |
9da3da66 CW |
115 | |
116 | mb(); | |
f5ddf697 | 117 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) |
2db76d7c | 118 | drm_clflush_page(sg_page_iter_page(&sg_iter)); |
9da3da66 CW |
119 | mb(); |
120 | ||
121 | return; | |
122 | } | |
123 | ||
124 | if (on_each_cpu(drm_clflush_ipi_handler, NULL, 1) != 0) | |
125 | printk(KERN_ERR "Timed out waiting for cache flush.\n"); | |
126 | #else | |
127 | printk(KERN_ERR "Architecture has no drm_cache.c support\n"); | |
128 | WARN_ON_ONCE(1); | |
129 | #endif | |
130 | } | |
131 | EXPORT_SYMBOL(drm_clflush_sg); | |
132 | ||
6d5cd9cb | 133 | void |
c2d15359 | 134 | drm_clflush_virt_range(void *addr, unsigned long length) |
6d5cd9cb DV |
135 | { |
136 | #if defined(CONFIG_X86) | |
137 | if (cpu_has_clflush) { | |
c2d15359 | 138 | void *end = addr + length; |
6d5cd9cb DV |
139 | mb(); |
140 | for (; addr < end; addr += boot_cpu_data.x86_clflush_size) | |
141 | clflush(addr); | |
2a0788dc | 142 | clflushopt(end - 1); |
6d5cd9cb DV |
143 | mb(); |
144 | return; | |
145 | } | |
146 | ||
147 | if (on_each_cpu(drm_clflush_ipi_handler, NULL, 1) != 0) | |
148 | printk(KERN_ERR "Timed out waiting for cache flush.\n"); | |
149 | #else | |
150 | printk(KERN_ERR "Architecture has no drm_cache.c support\n"); | |
151 | WARN_ON_ONCE(1); | |
152 | #endif | |
153 | } | |
154 | EXPORT_SYMBOL(drm_clflush_virt_range); |