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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2009 Keith Packard | |
3 | * | |
4 | * Permission to use, copy, modify, distribute, and sell this software and its | |
5 | * documentation for any purpose is hereby granted without fee, provided that | |
6 | * the above copyright notice appear in all copies and that both that copyright | |
7 | * notice and this permission notice appear in supporting documentation, and | |
8 | * that the name of the copyright holders not be used in advertising or | |
9 | * publicity pertaining to distribution of the software without specific, | |
10 | * written prior permission. The copyright holders make no representations | |
11 | * about the suitability of this software for any purpose. It is provided "as | |
12 | * is" without express or implied warranty. | |
13 | * | |
14 | * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, | |
15 | * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO | |
16 | * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR | |
17 | * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, | |
18 | * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER | |
19 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE | |
20 | * OF THIS SOFTWARE. | |
21 | */ | |
22 | ||
23 | #include <linux/kernel.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/delay.h> | |
a4fc5ed6 KP |
26 | #include <linux/init.h> |
27 | #include <linux/errno.h> | |
28 | #include <linux/sched.h> | |
29 | #include <linux/i2c.h> | |
760285e7 DH |
30 | #include <drm/drm_dp_helper.h> |
31 | #include <drm/drmP.h> | |
a4fc5ed6 | 32 | |
28164fda DV |
33 | /** |
34 | * DOC: dp helpers | |
35 | * | |
36 | * These functions contain some common logic and helpers at various abstraction | |
37 | * levels to deal with Display Port sink devices and related things like DP aux | |
38 | * channel transfers, EDID reading over DP aux channels, decoding certain DPCD | |
39 | * blocks, ... | |
40 | */ | |
41 | ||
a4fc5ed6 | 42 | /* Run a single AUX_CH I2C transaction, writing/reading data as necessary */ |
a4fc5ed6 KP |
43 | static int |
44 | i2c_algo_dp_aux_transaction(struct i2c_adapter *adapter, int mode, | |
45 | uint8_t write_byte, uint8_t *read_byte) | |
46 | { | |
47 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; | |
a4fc5ed6 | 48 | int ret; |
00ae9a45 | 49 | |
ab2c0672 DA |
50 | ret = (*algo_data->aux_ch)(adapter, mode, |
51 | write_byte, read_byte); | |
52 | return ret; | |
a4fc5ed6 KP |
53 | } |
54 | ||
55 | /* | |
56 | * I2C over AUX CH | |
57 | */ | |
58 | ||
59 | /* | |
60 | * Send the address. If the I2C link is running, this 'restarts' | |
61 | * the connection with the new address, this is used for doing | |
62 | * a write followed by a read (as needed for DDC) | |
63 | */ | |
64 | static int | |
65 | i2c_algo_dp_aux_address(struct i2c_adapter *adapter, u16 address, bool reading) | |
66 | { | |
67 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; | |
68 | int mode = MODE_I2C_START; | |
69 | int ret; | |
70 | ||
71 | if (reading) | |
72 | mode |= MODE_I2C_READ; | |
73 | else | |
74 | mode |= MODE_I2C_WRITE; | |
75 | algo_data->address = address; | |
76 | algo_data->running = true; | |
77 | ret = i2c_algo_dp_aux_transaction(adapter, mode, 0, NULL); | |
78 | return ret; | |
79 | } | |
80 | ||
81 | /* | |
82 | * Stop the I2C transaction. This closes out the link, sending | |
83 | * a bare address packet with the MOT bit turned off | |
84 | */ | |
85 | static void | |
86 | i2c_algo_dp_aux_stop(struct i2c_adapter *adapter, bool reading) | |
87 | { | |
88 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; | |
89 | int mode = MODE_I2C_STOP; | |
90 | ||
91 | if (reading) | |
92 | mode |= MODE_I2C_READ; | |
93 | else | |
94 | mode |= MODE_I2C_WRITE; | |
95 | if (algo_data->running) { | |
96 | (void) i2c_algo_dp_aux_transaction(adapter, mode, 0, NULL); | |
97 | algo_data->running = false; | |
98 | } | |
99 | } | |
100 | ||
101 | /* | |
102 | * Write a single byte to the current I2C address, the | |
103 | * the I2C link must be running or this returns -EIO | |
104 | */ | |
105 | static int | |
106 | i2c_algo_dp_aux_put_byte(struct i2c_adapter *adapter, u8 byte) | |
107 | { | |
108 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; | |
109 | int ret; | |
110 | ||
111 | if (!algo_data->running) | |
112 | return -EIO; | |
113 | ||
114 | ret = i2c_algo_dp_aux_transaction(adapter, MODE_I2C_WRITE, byte, NULL); | |
115 | return ret; | |
116 | } | |
117 | ||
118 | /* | |
119 | * Read a single byte from the current I2C address, the | |
120 | * I2C link must be running or this returns -EIO | |
121 | */ | |
122 | static int | |
123 | i2c_algo_dp_aux_get_byte(struct i2c_adapter *adapter, u8 *byte_ret) | |
124 | { | |
125 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; | |
126 | int ret; | |
127 | ||
128 | if (!algo_data->running) | |
129 | return -EIO; | |
130 | ||
131 | ret = i2c_algo_dp_aux_transaction(adapter, MODE_I2C_READ, 0, byte_ret); | |
132 | return ret; | |
133 | } | |
134 | ||
135 | static int | |
136 | i2c_algo_dp_aux_xfer(struct i2c_adapter *adapter, | |
137 | struct i2c_msg *msgs, | |
138 | int num) | |
139 | { | |
140 | int ret = 0; | |
141 | bool reading = false; | |
142 | int m; | |
143 | int b; | |
144 | ||
145 | for (m = 0; m < num; m++) { | |
146 | u16 len = msgs[m].len; | |
147 | u8 *buf = msgs[m].buf; | |
148 | reading = (msgs[m].flags & I2C_M_RD) != 0; | |
149 | ret = i2c_algo_dp_aux_address(adapter, msgs[m].addr, reading); | |
150 | if (ret < 0) | |
151 | break; | |
152 | if (reading) { | |
153 | for (b = 0; b < len; b++) { | |
154 | ret = i2c_algo_dp_aux_get_byte(adapter, &buf[b]); | |
155 | if (ret < 0) | |
156 | break; | |
157 | } | |
158 | } else { | |
159 | for (b = 0; b < len; b++) { | |
160 | ret = i2c_algo_dp_aux_put_byte(adapter, buf[b]); | |
161 | if (ret < 0) | |
162 | break; | |
163 | } | |
164 | } | |
165 | if (ret < 0) | |
166 | break; | |
167 | } | |
168 | if (ret >= 0) | |
169 | ret = num; | |
170 | i2c_algo_dp_aux_stop(adapter, reading); | |
28c97730 | 171 | DRM_DEBUG_KMS("dp_aux_xfer return %d\n", ret); |
a4fc5ed6 KP |
172 | return ret; |
173 | } | |
174 | ||
175 | static u32 | |
176 | i2c_algo_dp_aux_functionality(struct i2c_adapter *adapter) | |
177 | { | |
178 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | | |
179 | I2C_FUNC_SMBUS_READ_BLOCK_DATA | | |
180 | I2C_FUNC_SMBUS_BLOCK_PROC_CALL | | |
181 | I2C_FUNC_10BIT_ADDR; | |
182 | } | |
183 | ||
184 | static const struct i2c_algorithm i2c_dp_aux_algo = { | |
185 | .master_xfer = i2c_algo_dp_aux_xfer, | |
186 | .functionality = i2c_algo_dp_aux_functionality, | |
187 | }; | |
188 | ||
189 | static void | |
190 | i2c_dp_aux_reset_bus(struct i2c_adapter *adapter) | |
191 | { | |
192 | (void) i2c_algo_dp_aux_address(adapter, 0, false); | |
193 | (void) i2c_algo_dp_aux_stop(adapter, false); | |
a4fc5ed6 KP |
194 | } |
195 | ||
196 | static int | |
197 | i2c_dp_aux_prepare_bus(struct i2c_adapter *adapter) | |
198 | { | |
199 | adapter->algo = &i2c_dp_aux_algo; | |
200 | adapter->retries = 3; | |
201 | i2c_dp_aux_reset_bus(adapter); | |
202 | return 0; | |
203 | } | |
204 | ||
28164fda DV |
205 | /** |
206 | * i2c_dp_aux_add_bus() - register an i2c adapter using the aux ch helper | |
207 | * @adapter: i2c adapter to register | |
208 | * | |
209 | * This registers an i2c adapater that uses dp aux channel as it's underlaying | |
210 | * transport. The driver needs to fill out the &i2c_algo_dp_aux_data structure | |
211 | * and store it in the algo_data member of the @adapter argument. This will be | |
212 | * used by the i2c over dp aux algorithm to drive the hardware. | |
213 | * | |
214 | * RETURNS: | |
215 | * 0 on success, -ERRNO on failure. | |
216 | */ | |
a4fc5ed6 KP |
217 | int |
218 | i2c_dp_aux_add_bus(struct i2c_adapter *adapter) | |
219 | { | |
220 | int error; | |
00ae9a45 | 221 | |
a4fc5ed6 KP |
222 | error = i2c_dp_aux_prepare_bus(adapter); |
223 | if (error) | |
224 | return error; | |
225 | error = i2c_add_adapter(adapter); | |
226 | return error; | |
227 | } | |
228 | EXPORT_SYMBOL(i2c_dp_aux_add_bus); | |
1ffdff13 DV |
229 | |
230 | /* Helpers for DP link training */ | |
0aec2881 | 231 | static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r) |
1ffdff13 DV |
232 | { |
233 | return link_status[r - DP_LANE0_1_STATUS]; | |
234 | } | |
235 | ||
0aec2881 | 236 | static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE], |
1ffdff13 DV |
237 | int lane) |
238 | { | |
239 | int i = DP_LANE0_1_STATUS + (lane >> 1); | |
240 | int s = (lane & 1) * 4; | |
241 | u8 l = dp_link_status(link_status, i); | |
242 | return (l >> s) & 0xf; | |
243 | } | |
244 | ||
0aec2881 | 245 | bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], |
1ffdff13 DV |
246 | int lane_count) |
247 | { | |
248 | u8 lane_align; | |
249 | u8 lane_status; | |
250 | int lane; | |
251 | ||
252 | lane_align = dp_link_status(link_status, | |
253 | DP_LANE_ALIGN_STATUS_UPDATED); | |
254 | if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) | |
255 | return false; | |
256 | for (lane = 0; lane < lane_count; lane++) { | |
257 | lane_status = dp_get_lane_status(link_status, lane); | |
258 | if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS) | |
259 | return false; | |
260 | } | |
261 | return true; | |
262 | } | |
263 | EXPORT_SYMBOL(drm_dp_channel_eq_ok); | |
264 | ||
0aec2881 | 265 | bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], |
1ffdff13 DV |
266 | int lane_count) |
267 | { | |
268 | int lane; | |
269 | u8 lane_status; | |
270 | ||
271 | for (lane = 0; lane < lane_count; lane++) { | |
272 | lane_status = dp_get_lane_status(link_status, lane); | |
273 | if ((lane_status & DP_LANE_CR_DONE) == 0) | |
274 | return false; | |
275 | } | |
276 | return true; | |
277 | } | |
278 | EXPORT_SYMBOL(drm_dp_clock_recovery_ok); | |
0f037bde | 279 | |
0aec2881 | 280 | u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], |
0f037bde DV |
281 | int lane) |
282 | { | |
283 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); | |
284 | int s = ((lane & 1) ? | |
285 | DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : | |
286 | DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); | |
287 | u8 l = dp_link_status(link_status, i); | |
288 | ||
289 | return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; | |
290 | } | |
291 | EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage); | |
292 | ||
0aec2881 | 293 | u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], |
0f037bde DV |
294 | int lane) |
295 | { | |
296 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); | |
297 | int s = ((lane & 1) ? | |
298 | DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : | |
299 | DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); | |
300 | u8 l = dp_link_status(link_status, i); | |
301 | ||
302 | return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; | |
303 | } | |
304 | EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis); | |
305 | ||
0aec2881 | 306 | void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { |
1a644cd4 DV |
307 | if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0) |
308 | udelay(100); | |
309 | else | |
310 | mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4); | |
311 | } | |
312 | EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay); | |
313 | ||
0aec2881 | 314 | void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { |
1a644cd4 DV |
315 | if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0) |
316 | udelay(400); | |
317 | else | |
318 | mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4); | |
319 | } | |
320 | EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay); | |
3b5c662e DV |
321 | |
322 | u8 drm_dp_link_rate_to_bw_code(int link_rate) | |
323 | { | |
324 | switch (link_rate) { | |
325 | case 162000: | |
326 | default: | |
327 | return DP_LINK_BW_1_62; | |
328 | case 270000: | |
329 | return DP_LINK_BW_2_7; | |
330 | case 540000: | |
331 | return DP_LINK_BW_5_4; | |
332 | } | |
333 | } | |
334 | EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code); | |
335 | ||
336 | int drm_dp_bw_code_to_link_rate(u8 link_bw) | |
337 | { | |
338 | switch (link_bw) { | |
339 | case DP_LINK_BW_1_62: | |
340 | default: | |
341 | return 162000; | |
342 | case DP_LINK_BW_2_7: | |
343 | return 270000; | |
344 | case DP_LINK_BW_5_4: | |
345 | return 540000; | |
346 | } | |
347 | } | |
348 | EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate); |