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drm/i915: make mappable struct resource centric
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / drm_edid.c
CommitLineData
f453ba04
DA		 1/*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
61e57a8d 5 * Copyright 2010 Red Hat, Inc.
f453ba04
DA		 6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30#include <linux/kernel.h>
5a0e3ad6 31#include <linux/slab.h>
10a85120 32#include <linux/hdmi.h>
f453ba04 33#include <linux/i2c.h>
47819ba2 34#include <linux/module.h>
5cb8eaa2 35#include <linux/vga_switcheroo.h>
760285e7
DH		 36#include <drm/drmP.h>
37#include <drm/drm_edid.h>
9338203c 38#include <drm/drm_encoder.h>
40d9b043 39#include <drm/drm_displayid.h>
62c58af3 40#include <drm/drm_scdc_helper.h>
f453ba04 41
969218fe
TI		 42#include "drm_crtc_internal.h"
43
13931579
AJ		 44#define version_greater(edid, maj, min) \
45 (((edid)->version > (maj)) || \
46 ((edid)->version == (maj) && (edid)->revision > (min)))
f453ba04 47
d1ff6409
AJ		 48#define EDID_EST_TIMINGS 16
49#define EDID_STD_TIMINGS 8
50#define EDID_DETAILED_TIMINGS 4
f453ba04
DA		 51
52/*
53 * EDID blocks out in the wild have a variety of bugs, try to collect
54 * them here (note that userspace may work around broken monitors first,
55 * but fixes should make their way here so that the kernel "just works"
56 * on as many displays as possible).
57 */
58
59/* First detailed mode wrong, use largest 60Hz mode */
60#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
61/* Reported 135MHz pixel clock is too high, needs adjustment */
62#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
63/* Prefer the largest mode at 75 Hz */
64#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
65/* Detail timing is in cm not mm */
66#define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
67/* Detailed timing descriptors have bogus size values, so just take the
68 * maximum size and use that.
69 */
70#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
71/* Monitor forgot to set the first detailed is preferred bit. */
72#define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
73/* use +hsync +vsync for detailed mode */
74#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
bc42aabc
AJ		 75/* Force reduced-blanking timings for detailed modes */
76#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
49d45a31
RM		 77/* Force 8bpc */
78#define EDID_QUIRK_FORCE_8BPC (1 << 8)
bc5b9641
MK		 79/* Force 12bpc */
80#define EDID_QUIRK_FORCE_12BPC (1 << 9)
e10aec65
MK		 81/* Force 6bpc */
82#define EDID_QUIRK_FORCE_6BPC (1 << 10)
e345da82
MK		 83/* Force 10bpc */
84#define EDID_QUIRK_FORCE_10BPC (1 << 11)
66660d4c
DA		 85/* Non desktop display (i.e. HMD) */
86#define EDID_QUIRK_NON_DESKTOP (1 << 12)
3c537889 87
13931579
AJ		 88struct detailed_mode_closure {
89 struct drm_connector *connector;
90 struct edid *edid;
91 bool preferred;
92 u32 quirks;
93 int modes;
94};
f453ba04 95
5c61259e
ZY		 96#define LEVEL_DMT 0
97#define LEVEL_GTF 1
7a374350
AJ		 98#define LEVEL_GTF2 2
99#define LEVEL_CVT 3
5c61259e 100
23c4cfbd 101static const struct edid_quirk {
c51a3fd6 102 char vendor[4];
f453ba04
DA		 103 int product_id;
104 u32 quirks;
105} edid_quirk_list[] = {
106 /* Acer AL1706 */
107 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
108 /* Acer F51 */
109 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
110 /* Unknown Acer */
111 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
112
e10aec65
MK		 113 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
114 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
115
50d112e5
KHF		 116 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
117 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
118
f453ba04
DA		 119 /* Belinea 10 15 55 */
120 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
121 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
122
123 /* Envision Peripherals, Inc. EN-7100e */
124 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
ba1163de
AJ		 125 /* Envision EN2028 */
126 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
f453ba04
DA		 127
128 /* Funai Electronics PM36B */
129 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
130 EDID_QUIRK_DETAILED_IN_CM },
131
e345da82
MK		 132 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
133 { "LGD", 764, EDID_QUIRK_FORCE_10BPC },
134
f453ba04
DA		 135 /* LG Philips LCD LP154W01-A5 */
136 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
137 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
138
139 /* Philips 107p5 CRT */
140 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
141
142 /* Proview AY765C */
143 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
144
145 /* Samsung SyncMaster 205BW. Note: irony */
146 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
147 /* Samsung SyncMaster 22[5-6]BW */
148 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
149 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
bc42aabc 150
bc5b9641
MK		 151 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
152 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
153
bc42aabc
AJ		 154 /* ViewSonic VA2026w */
155 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
118bdbd8
AD		 156
157 /* Medion MD 30217 PG */
158 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
49d45a31
RM		 159
160 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
161 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
36fc5797
TV		 162
163 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
164 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
acb1d8ee
DA		 165
166 /* HTC Vive VR Headset */
167 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
f453ba04
DA		 168};
169
a6b21831
TR		 170/*
171 * Autogenerated from the DMT spec.
172 * This table is copied from xfree86/modes/xf86EdidModes.c.
173 */
174static const struct drm_display_mode drm_dmt_modes[] = {
24b856b1 175 /* 0x01 - 640x350@85Hz */
a6b21831
TR		 176 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
177 736, 832, 0, 350, 382, 385, 445, 0,
178 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 179 /* 0x02 - 640x400@85Hz */
a6b21831
TR		 180 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
181 736, 832, 0, 400, 401, 404, 445, 0,
182 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 183 /* 0x03 - 720x400@85Hz */
a6b21831
TR		 184 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
185 828, 936, 0, 400, 401, 404, 446, 0,
186 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 187 /* 0x04 - 640x480@60Hz */
a6b21831 188 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
fcf22d05 189 752, 800, 0, 480, 490, 492, 525, 0,
a6b21831 190 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 191 /* 0x05 - 640x480@72Hz */
a6b21831
TR		 192 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
193 704, 832, 0, 480, 489, 492, 520, 0,
194 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 195 /* 0x06 - 640x480@75Hz */
a6b21831
TR		 196 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
197 720, 840, 0, 480, 481, 484, 500, 0,
198 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 199 /* 0x07 - 640x480@85Hz */
a6b21831
TR		 200 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
201 752, 832, 0, 480, 481, 484, 509, 0,
202 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 203 /* 0x08 - 800x600@56Hz */
a6b21831
TR		 204 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
205 896, 1024, 0, 600, 601, 603, 625, 0,
206 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 207 /* 0x09 - 800x600@60Hz */
a6b21831
TR		 208 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
209 968, 1056, 0, 600, 601, 605, 628, 0,
210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 211 /* 0x0a - 800x600@72Hz */
a6b21831
TR		 212 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
213 976, 1040, 0, 600, 637, 643, 666, 0,
214 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 215 /* 0x0b - 800x600@75Hz */
a6b21831
TR		 216 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
217 896, 1056, 0, 600, 601, 604, 625, 0,
218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 219 /* 0x0c - 800x600@85Hz */
a6b21831
TR		 220 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
221 896, 1048, 0, 600, 601, 604, 631, 0,
222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 223 /* 0x0d - 800x600@120Hz RB */
a6b21831
TR		 224 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
225 880, 960, 0, 600, 603, 607, 636, 0,
226 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 227 /* 0x0e - 848x480@60Hz */
a6b21831
TR		 228 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
229 976, 1088, 0, 480, 486, 494, 517, 0,
230 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 231 /* 0x0f - 1024x768@43Hz, interlace */
a6b21831 232 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
735b100f 233 1208, 1264, 0, 768, 768, 776, 817, 0,
a6b21831 234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
fcf22d05 235 DRM_MODE_FLAG_INTERLACE) },
24b856b1 236 /* 0x10 - 1024x768@60Hz */
a6b21831
TR		 237 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
238 1184, 1344, 0, 768, 771, 777, 806, 0,
239 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 240 /* 0x11 - 1024x768@70Hz */
a6b21831
TR		 241 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
242 1184, 1328, 0, 768, 771, 777, 806, 0,
243 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 244 /* 0x12 - 1024x768@75Hz */
a6b21831
TR		 245 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
246 1136, 1312, 0, 768, 769, 772, 800, 0,
247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 248 /* 0x13 - 1024x768@85Hz */
a6b21831
TR		 249 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
250 1168, 1376, 0, 768, 769, 772, 808, 0,
251 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 252 /* 0x14 - 1024x768@120Hz RB */
a6b21831
TR		 253 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
254 1104, 1184, 0, 768, 771, 775, 813, 0,
255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 256 /* 0x15 - 1152x864@75Hz */
a6b21831
TR		 257 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
258 1344, 1600, 0, 864, 865, 868, 900, 0,
259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
bfcd74d2
VS		 260 /* 0x55 - 1280x720@60Hz */
261 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
262 1430, 1650, 0, 720, 725, 730, 750, 0,
263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 264 /* 0x16 - 1280x768@60Hz RB */
a6b21831
TR		 265 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
266 1360, 1440, 0, 768, 771, 778, 790, 0,
267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 268 /* 0x17 - 1280x768@60Hz */
a6b21831
TR		 269 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
270 1472, 1664, 0, 768, 771, 778, 798, 0,
271 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 272 /* 0x18 - 1280x768@75Hz */
a6b21831
TR		 273 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
274 1488, 1696, 0, 768, 771, 778, 805, 0,
fcf22d05 275 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 276 /* 0x19 - 1280x768@85Hz */
a6b21831
TR		 277 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
278 1496, 1712, 0, 768, 771, 778, 809, 0,
279 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 280 /* 0x1a - 1280x768@120Hz RB */
a6b21831
TR		 281 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
282 1360, 1440, 0, 768, 771, 778, 813, 0,
283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 284 /* 0x1b - 1280x800@60Hz RB */
a6b21831
TR		 285 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
286 1360, 1440, 0, 800, 803, 809, 823, 0,
287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 288 /* 0x1c - 1280x800@60Hz */
a6b21831
TR		 289 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
290 1480, 1680, 0, 800, 803, 809, 831, 0,
fcf22d05 291 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 292 /* 0x1d - 1280x800@75Hz */
a6b21831
TR		 293 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
294 1488, 1696, 0, 800, 803, 809, 838, 0,
295 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 296 /* 0x1e - 1280x800@85Hz */
a6b21831
TR		 297 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
298 1496, 1712, 0, 800, 803, 809, 843, 0,
299 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 300 /* 0x1f - 1280x800@120Hz RB */
a6b21831
TR		 301 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
302 1360, 1440, 0, 800, 803, 809, 847, 0,
303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 304 /* 0x20 - 1280x960@60Hz */
a6b21831
TR		 305 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
306 1488, 1800, 0, 960, 961, 964, 1000, 0,
307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 308 /* 0x21 - 1280x960@85Hz */
a6b21831
TR		 309 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
310 1504, 1728, 0, 960, 961, 964, 1011, 0,
311 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 312 /* 0x22 - 1280x960@120Hz RB */
a6b21831
TR		 313 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
314 1360, 1440, 0, 960, 963, 967, 1017, 0,
315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 316 /* 0x23 - 1280x1024@60Hz */
a6b21831
TR		 317 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
318 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
319 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 320 /* 0x24 - 1280x1024@75Hz */
a6b21831
TR		 321 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
322 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
323 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 324 /* 0x25 - 1280x1024@85Hz */
a6b21831
TR		 325 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
326 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
327 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 328 /* 0x26 - 1280x1024@120Hz RB */
a6b21831
TR		 329 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
330 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
331 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 332 /* 0x27 - 1360x768@60Hz */
a6b21831
TR		 333 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
334 1536, 1792, 0, 768, 771, 777, 795, 0,
335 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 336 /* 0x28 - 1360x768@120Hz RB */
a6b21831
TR		 337 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
338 1440, 1520, 0, 768, 771, 776, 813, 0,
339 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 340 /* 0x51 - 1366x768@60Hz */
341 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
342 1579, 1792, 0, 768, 771, 774, 798, 0,
343 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
344 /* 0x56 - 1366x768@60Hz */
345 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
346 1436, 1500, 0, 768, 769, 772, 800, 0,
347 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 348 /* 0x29 - 1400x1050@60Hz RB */
a6b21831
TR		 349 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
350 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
351 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 352 /* 0x2a - 1400x1050@60Hz */
a6b21831
TR		 353 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
354 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
355 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 356 /* 0x2b - 1400x1050@75Hz */
a6b21831
TR		 357 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
358 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
359 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 360 /* 0x2c - 1400x1050@85Hz */
a6b21831
TR		 361 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
362 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
363 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 364 /* 0x2d - 1400x1050@120Hz RB */
a6b21831
TR		 365 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
366 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
367 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 368 /* 0x2e - 1440x900@60Hz RB */
a6b21831
TR		 369 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
370 1520, 1600, 0, 900, 903, 909, 926, 0,
371 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 372 /* 0x2f - 1440x900@60Hz */
a6b21831
TR		 373 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
374 1672, 1904, 0, 900, 903, 909, 934, 0,
375 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 376 /* 0x30 - 1440x900@75Hz */
a6b21831
TR		 377 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
378 1688, 1936, 0, 900, 903, 909, 942, 0,
379 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 380 /* 0x31 - 1440x900@85Hz */
a6b21831
TR		 381 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
382 1696, 1952, 0, 900, 903, 909, 948, 0,
383 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 384 /* 0x32 - 1440x900@120Hz RB */
a6b21831
TR		 385 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
386 1520, 1600, 0, 900, 903, 909, 953, 0,
387 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 388 /* 0x53 - 1600x900@60Hz */
389 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
390 1704, 1800, 0, 900, 901, 904, 1000, 0,
391 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 392 /* 0x33 - 1600x1200@60Hz */
a6b21831
TR		 393 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
394 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
395 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 396 /* 0x34 - 1600x1200@65Hz */
a6b21831
TR		 397 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
398 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
399 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 400 /* 0x35 - 1600x1200@70Hz */
a6b21831
TR		 401 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
402 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 404 /* 0x36 - 1600x1200@75Hz */
a6b21831
TR		 405 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
406 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
407 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 408 /* 0x37 - 1600x1200@85Hz */
a6b21831
TR		 409 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
410 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
411 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 412 /* 0x38 - 1600x1200@120Hz RB */
a6b21831
TR		 413 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
414 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
415 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 416 /* 0x39 - 1680x1050@60Hz RB */
a6b21831
TR		 417 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
418 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
419 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 420 /* 0x3a - 1680x1050@60Hz */
a6b21831
TR		 421 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
422 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
423 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 424 /* 0x3b - 1680x1050@75Hz */
a6b21831
TR		 425 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
426 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
427 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 428 /* 0x3c - 1680x1050@85Hz */
a6b21831
TR		 429 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
430 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
431 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 432 /* 0x3d - 1680x1050@120Hz RB */
a6b21831
TR		 433 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
434 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
435 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 436 /* 0x3e - 1792x1344@60Hz */
a6b21831
TR		 437 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
438 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
439 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 440 /* 0x3f - 1792x1344@75Hz */
a6b21831
TR		 441 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
442 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
443 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 444 /* 0x40 - 1792x1344@120Hz RB */
a6b21831
TR		 445 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
446 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
447 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 448 /* 0x41 - 1856x1392@60Hz */
a6b21831
TR		 449 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
450 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
451 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 452 /* 0x42 - 1856x1392@75Hz */
a6b21831 453 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
fcf22d05 454 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
a6b21831 455 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 456 /* 0x43 - 1856x1392@120Hz RB */
a6b21831
TR		 457 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
458 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
459 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 460 /* 0x52 - 1920x1080@60Hz */
461 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
462 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
463 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 464 /* 0x44 - 1920x1200@60Hz RB */
a6b21831
TR		 465 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
466 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
467 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 468 /* 0x45 - 1920x1200@60Hz */
a6b21831
TR		 469 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
470 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
471 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 472 /* 0x46 - 1920x1200@75Hz */
a6b21831
TR		 473 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
474 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
475 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 476 /* 0x47 - 1920x1200@85Hz */
a6b21831
TR		 477 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
478 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
479 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 480 /* 0x48 - 1920x1200@120Hz RB */
a6b21831
TR		 481 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
482 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
483 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 484 /* 0x49 - 1920x1440@60Hz */
a6b21831
TR		 485 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
486 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
487 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 488 /* 0x4a - 1920x1440@75Hz */
a6b21831
TR		 489 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
490 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
491 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 492 /* 0x4b - 1920x1440@120Hz RB */
a6b21831
TR		 493 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
494 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
495 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 496 /* 0x54 - 2048x1152@60Hz */
497 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
498 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
499 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 500 /* 0x4c - 2560x1600@60Hz RB */
a6b21831
TR		 501 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
502 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
503 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 504 /* 0x4d - 2560x1600@60Hz */
a6b21831
TR		 505 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
506 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
507 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 508 /* 0x4e - 2560x1600@75Hz */
a6b21831
TR		 509 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
510 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
511 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 512 /* 0x4f - 2560x1600@85Hz */
a6b21831
TR		 513 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
514 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
515 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 516 /* 0x50 - 2560x1600@120Hz RB */
a6b21831
TR		 517 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
518 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
519 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 520 /* 0x57 - 4096x2160@60Hz RB */
521 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
522 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
524 /* 0x58 - 4096x2160@59.94Hz RB */
525 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
526 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
527 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
a6b21831
TR		 528};
529
e7bfa5c4
VS		 530/*
531 * These more or less come from the DMT spec. The 720x400 modes are
532 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
533 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
534 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
535 * mode.
536 *
537 * The DMT modes have been fact-checked; the rest are mild guesses.
538 */
a6b21831
TR		 539static const struct drm_display_mode edid_est_modes[] = {
540 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
541 968, 1056, 0, 600, 601, 605, 628, 0,
542 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
543 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
544 896, 1024, 0, 600, 601, 603, 625, 0,
545 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
546 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
547 720, 840, 0, 480, 481, 484, 500, 0,
548 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
549 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
87707cfd 550 704, 832, 0, 480, 489, 492, 520, 0,
a6b21831
TR		 551 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
552 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
553 768, 864, 0, 480, 483, 486, 525, 0,
554 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
87707cfd 555 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
a6b21831
TR		 556 752, 800, 0, 480, 490, 492, 525, 0,
557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
558 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
559 846, 900, 0, 400, 421, 423, 449, 0,
560 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
561 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
562 846, 900, 0, 400, 412, 414, 449, 0,
563 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
564 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
565 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
566 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
87707cfd 567 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
a6b21831
TR		 568 1136, 1312, 0, 768, 769, 772, 800, 0,
569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
570 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
571 1184, 1328, 0, 768, 771, 777, 806, 0,
572 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
573 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
574 1184, 1344, 0, 768, 771, 777, 806, 0,
575 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
576 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
577 1208, 1264, 0, 768, 768, 776, 817, 0,
578 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
579 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
580 928, 1152, 0, 624, 625, 628, 667, 0,
581 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
582 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
583 896, 1056, 0, 600, 601, 604, 625, 0,
584 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
585 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
586 976, 1040, 0, 600, 637, 643, 666, 0,
587 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
588 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
589 1344, 1600, 0, 864, 865, 868, 900, 0,
590 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
591};
592
593struct minimode {
594 short w;
595 short h;
596 short r;
597 short rb;
598};
599
600static const struct minimode est3_modes[] = {
601 /* byte 6 */
602 { 640, 350, 85, 0 },
603 { 640, 400, 85, 0 },
604 { 720, 400, 85, 0 },
605 { 640, 480, 85, 0 },
606 { 848, 480, 60, 0 },
607 { 800, 600, 85, 0 },
608 { 1024, 768, 85, 0 },
609 { 1152, 864, 75, 0 },
610 /* byte 7 */
611 { 1280, 768, 60, 1 },
612 { 1280, 768, 60, 0 },
613 { 1280, 768, 75, 0 },
614 { 1280, 768, 85, 0 },
615 { 1280, 960, 60, 0 },
616 { 1280, 960, 85, 0 },
617 { 1280, 1024, 60, 0 },
618 { 1280, 1024, 85, 0 },
619 /* byte 8 */
620 { 1360, 768, 60, 0 },
621 { 1440, 900, 60, 1 },
622 { 1440, 900, 60, 0 },
623 { 1440, 900, 75, 0 },
624 { 1440, 900, 85, 0 },
625 { 1400, 1050, 60, 1 },
626 { 1400, 1050, 60, 0 },
627 { 1400, 1050, 75, 0 },
628 /* byte 9 */
629 { 1400, 1050, 85, 0 },
630 { 1680, 1050, 60, 1 },
631 { 1680, 1050, 60, 0 },
632 { 1680, 1050, 75, 0 },
633 { 1680, 1050, 85, 0 },
634 { 1600, 1200, 60, 0 },
635 { 1600, 1200, 65, 0 },
636 { 1600, 1200, 70, 0 },
637 /* byte 10 */
638 { 1600, 1200, 75, 0 },
639 { 1600, 1200, 85, 0 },
640 { 1792, 1344, 60, 0 },
c068b32a 641 { 1792, 1344, 75, 0 },
a6b21831
TR		 642 { 1856, 1392, 60, 0 },
643 { 1856, 1392, 75, 0 },
644 { 1920, 1200, 60, 1 },
645 { 1920, 1200, 60, 0 },
646 /* byte 11 */
647 { 1920, 1200, 75, 0 },
648 { 1920, 1200, 85, 0 },
649 { 1920, 1440, 60, 0 },
650 { 1920, 1440, 75, 0 },
651};
652
653static const struct minimode extra_modes[] = {
654 { 1024, 576, 60, 0 },
655 { 1366, 768, 60, 0 },
656 { 1600, 900, 60, 0 },
657 { 1680, 945, 60, 0 },
658 { 1920, 1080, 60, 0 },
659 { 2048, 1152, 60, 0 },
660 { 2048, 1536, 60, 0 },
661};
662
663/*
664 * Probably taken from CEA-861 spec.
665 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
d9278b4c
JN		 666 *
667 * Index using the VIC.
a6b21831
TR		 668 */
669static const struct drm_display_mode edid_cea_modes[] = {
d9278b4c
JN		 670 /* 0 - dummy, VICs start at 1 */
671 { },
a6b21831
TR		 672 /* 1 - 640x480@60Hz */
673 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
674 752, 800, 0, 480, 490, 492, 525, 0,
ee7925bb 675 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 676 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 677 /* 2 - 720x480@60Hz */
678 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
679 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 680 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 681 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 682 /* 3 - 720x480@60Hz */
683 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
684 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 685 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 686 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 687 /* 4 - 1280x720@60Hz */
688 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
689 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 690 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 691 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 692 /* 5 - 1920x1080i@60Hz */
693 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
694 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
695 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
ee7925bb 696 DRM_MODE_FLAG_INTERLACE),
985e5dc2 697 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 698 /* 6 - 720(1440)x480i@60Hz */
699 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
700 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 701 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 702 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 703 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 704 /* 7 - 720(1440)x480i@60Hz */
705 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
706 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 707 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 708 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 709 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 710 /* 8 - 720(1440)x240@60Hz */
711 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
712 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 713 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 714 DRM_MODE_FLAG_DBLCLK),
985e5dc2 715 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 716 /* 9 - 720(1440)x240@60Hz */
717 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
718 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 719 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 720 DRM_MODE_FLAG_DBLCLK),
985e5dc2 721 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 722 /* 10 - 2880x480i@60Hz */
723 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
724 3204, 3432, 0, 480, 488, 494, 525, 0,
725 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 726 DRM_MODE_FLAG_INTERLACE),
985e5dc2 727 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 728 /* 11 - 2880x480i@60Hz */
729 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
730 3204, 3432, 0, 480, 488, 494, 525, 0,
731 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 732 DRM_MODE_FLAG_INTERLACE),
985e5dc2 733 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 734 /* 12 - 2880x240@60Hz */
735 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
736 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 737 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 738 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 739 /* 13 - 2880x240@60Hz */
740 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
741 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 742 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 743 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 744 /* 14 - 1440x480@60Hz */
745 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
746 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 747 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 748 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 749 /* 15 - 1440x480@60Hz */
750 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
751 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 752 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 753 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 754 /* 16 - 1920x1080@60Hz */
755 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
756 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 757 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 758 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 759 /* 17 - 720x576@50Hz */
760 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
761 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 762 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 763 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 764 /* 18 - 720x576@50Hz */
765 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
766 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 767 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 768 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 769 /* 19 - 1280x720@50Hz */
770 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
771 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 772 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 773 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 774 /* 20 - 1920x1080i@50Hz */
775 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
776 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
777 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
ee7925bb 778 DRM_MODE_FLAG_INTERLACE),
985e5dc2 779 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 780 /* 21 - 720(1440)x576i@50Hz */
781 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
782 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 783 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 784 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 785 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 786 /* 22 - 720(1440)x576i@50Hz */
787 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
788 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 789 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 790 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 791 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 792 /* 23 - 720(1440)x288@50Hz */
793 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
794 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 795 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 796 DRM_MODE_FLAG_DBLCLK),
985e5dc2 797 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 798 /* 24 - 720(1440)x288@50Hz */
799 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
800 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 801 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 802 DRM_MODE_FLAG_DBLCLK),
985e5dc2 803 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 804 /* 25 - 2880x576i@50Hz */
805 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
806 3180, 3456, 0, 576, 580, 586, 625, 0,
807 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 808 DRM_MODE_FLAG_INTERLACE),
985e5dc2 809 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 810 /* 26 - 2880x576i@50Hz */
811 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
812 3180, 3456, 0, 576, 580, 586, 625, 0,
813 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 814 DRM_MODE_FLAG_INTERLACE),
985e5dc2 815 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 816 /* 27 - 2880x288@50Hz */
817 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
818 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 819 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 820 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 821 /* 28 - 2880x288@50Hz */
822 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
823 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 824 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 825 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 826 /* 29 - 1440x576@50Hz */
827 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
828 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 829 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 830 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 831 /* 30 - 1440x576@50Hz */
832 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
833 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 834 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 835 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 836 /* 31 - 1920x1080@50Hz */
837 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
838 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 839 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 840 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 841 /* 32 - 1920x1080@24Hz */
842 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
843 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 844 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 845 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 846 /* 33 - 1920x1080@25Hz */
847 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
848 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 849 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 850 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 851 /* 34 - 1920x1080@30Hz */
852 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
853 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 854 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 855 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 856 /* 35 - 2880x480@60Hz */
857 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
858 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 859 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 860 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 861 /* 36 - 2880x480@60Hz */
862 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
863 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 864 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 865 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 866 /* 37 - 2880x576@50Hz */
867 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
868 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 869 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 870 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 871 /* 38 - 2880x576@50Hz */
872 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
873 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 874 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 875 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 876 /* 39 - 1920x1080i@50Hz */
877 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
878 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
879 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 880 DRM_MODE_FLAG_INTERLACE),
985e5dc2 881 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 882 /* 40 - 1920x1080i@100Hz */
883 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
884 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
885 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
ee7925bb 886 DRM_MODE_FLAG_INTERLACE),
985e5dc2 887 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 888 /* 41 - 1280x720@100Hz */
889 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
890 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 891 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 892 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 893 /* 42 - 720x576@100Hz */
894 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
895 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 896 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 897 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 898 /* 43 - 720x576@100Hz */
899 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
900 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 901 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 902 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 903 /* 44 - 720(1440)x576i@100Hz */
904 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
905 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 906 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
5a11f7f8 907 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 908 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 909 /* 45 - 720(1440)x576i@100Hz */
910 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
911 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 912 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
5a11f7f8 913 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 914 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 915 /* 46 - 1920x1080i@120Hz */
916 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
917 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
918 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
ee7925bb 919 DRM_MODE_FLAG_INTERLACE),
985e5dc2 920 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 921 /* 47 - 1280x720@120Hz */
922 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
923 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 924 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 925 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 926 /* 48 - 720x480@120Hz */
927 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
928 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 929 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 930 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 931 /* 49 - 720x480@120Hz */
932 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
933 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 934 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 935 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 936 /* 50 - 720(1440)x480i@120Hz */
937 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
938 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 939 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 940 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 941 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 942 /* 51 - 720(1440)x480i@120Hz */
943 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
944 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 945 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 946 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 947 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 948 /* 52 - 720x576@200Hz */
949 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
950 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 951 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 952 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 953 /* 53 - 720x576@200Hz */
954 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
955 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 956 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 957 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 958 /* 54 - 720(1440)x576i@200Hz */
959 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
960 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 961 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 962 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 963 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 964 /* 55 - 720(1440)x576i@200Hz */
965 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
966 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 967 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 968 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 969 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 970 /* 56 - 720x480@240Hz */
971 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
972 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 973 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 974 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 975 /* 57 - 720x480@240Hz */
976 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
977 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 978 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 979 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
e587803c 980 /* 58 - 720(1440)x480i@240Hz */
fb01d280
CT		 981 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
982 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 983 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 984 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 985 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
e587803c 986 /* 59 - 720(1440)x480i@240Hz */
fb01d280
CT		 987 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
988 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 989 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 990 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 991 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 992 /* 60 - 1280x720@24Hz */
993 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
994 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 995 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 996 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 997 /* 61 - 1280x720@25Hz */
998 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
999 3740, 3960, 0, 720, 725, 730, 750, 0,
ee7925bb 1000 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 1001 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 1002 /* 62 - 1280x720@30Hz */
1003 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1004 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 1005 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 1006 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 1007 /* 63 - 1920x1080@120Hz */
1008 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1009 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 1010 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 1011 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 1012 /* 64 - 1920x1080@100Hz */
1013 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
8f0e4907 1014 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 1015 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 1016 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
8ec6e075
SS		 1017 /* 65 - 1280x720@24Hz */
1018 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1019 3080, 3300, 0, 720, 725, 730, 750, 0,
1020 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1021 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1022 /* 66 - 1280x720@25Hz */
1023 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1024 3740, 3960, 0, 720, 725, 730, 750, 0,
1025 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1026 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1027 /* 67 - 1280x720@30Hz */
1028 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1029 3080, 3300, 0, 720, 725, 730, 750, 0,
1030 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1031 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1032 /* 68 - 1280x720@50Hz */
1033 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1034 1760, 1980, 0, 720, 725, 730, 750, 0,
1035 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1036 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1037 /* 69 - 1280x720@60Hz */
1038 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1039 1430, 1650, 0, 720, 725, 730, 750, 0,
1040 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1041 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1042 /* 70 - 1280x720@100Hz */
1043 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1044 1760, 1980, 0, 720, 725, 730, 750, 0,
1045 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1046 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1047 /* 71 - 1280x720@120Hz */
1048 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1049 1430, 1650, 0, 720, 725, 730, 750, 0,
1050 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1051 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1052 /* 72 - 1920x1080@24Hz */
1053 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1054 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1055 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1056 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1057 /* 73 - 1920x1080@25Hz */
1058 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1059 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1060 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1061 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1062 /* 74 - 1920x1080@30Hz */
1063 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1064 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1065 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1066 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1067 /* 75 - 1920x1080@50Hz */
1068 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1069 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1070 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1071 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1072 /* 76 - 1920x1080@60Hz */
1073 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1074 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1075 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1076 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1077 /* 77 - 1920x1080@100Hz */
1078 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1079 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1080 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1081 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1082 /* 78 - 1920x1080@120Hz */
1083 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1084 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1085 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1086 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1087 /* 79 - 1680x720@24Hz */
1088 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1089 3080, 3300, 0, 720, 725, 730, 750, 0,
1090 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1091 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1092 /* 80 - 1680x720@25Hz */
1093 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1094 2948, 3168, 0, 720, 725, 730, 750, 0,
1095 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1096 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1097 /* 81 - 1680x720@30Hz */
1098 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1099 2420, 2640, 0, 720, 725, 730, 750, 0,
1100 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1101 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1102 /* 82 - 1680x720@50Hz */
1103 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1104 1980, 2200, 0, 720, 725, 730, 750, 0,
1105 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1106 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1107 /* 83 - 1680x720@60Hz */
1108 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1109 1980, 2200, 0, 720, 725, 730, 750, 0,
1110 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1111 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1112 /* 84 - 1680x720@100Hz */
1113 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1114 1780, 2000, 0, 720, 725, 730, 825, 0,
1115 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1116 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1117 /* 85 - 1680x720@120Hz */
1118 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1119 1780, 2000, 0, 720, 725, 730, 825, 0,
1120 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1121 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1122 /* 86 - 2560x1080@24Hz */
1123 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1124 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1125 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1126 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1127 /* 87 - 2560x1080@25Hz */
1128 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1129 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1130 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1131 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1132 /* 88 - 2560x1080@30Hz */
1133 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1134 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1135 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1136 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1137 /* 89 - 2560x1080@50Hz */
1138 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1139 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1140 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1141 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1142 /* 90 - 2560x1080@60Hz */
1143 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1144 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1145 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1146 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1147 /* 91 - 2560x1080@100Hz */
1148 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1149 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1150 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1151 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1152 /* 92 - 2560x1080@120Hz */
1153 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1154 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1155 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1156 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1157 /* 93 - 3840x2160p@24Hz 16:9 */
1158 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1159 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1160 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1161 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1162 /* 94 - 3840x2160p@25Hz 16:9 */
1163 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1164 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1165 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1166 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1167 /* 95 - 3840x2160p@30Hz 16:9 */
1168 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1169 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1170 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1171 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1172 /* 96 - 3840x2160p@50Hz 16:9 */
1173 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1174 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1175 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1176 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1177 /* 97 - 3840x2160p@60Hz 16:9 */
1178 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1179 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1180 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1181 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1182 /* 98 - 4096x2160p@24Hz 256:135 */
1183 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1184 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1185 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1186 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1187 /* 99 - 4096x2160p@25Hz 256:135 */
1188 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1189 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1190 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1191 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1192 /* 100 - 4096x2160p@30Hz 256:135 */
1193 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1194 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1195 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1196 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1197 /* 101 - 4096x2160p@50Hz 256:135 */
1198 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1199 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1200 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1201 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1202 /* 102 - 4096x2160p@60Hz 256:135 */
1203 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1204 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1205 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1206 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1207 /* 103 - 3840x2160p@24Hz 64:27 */
1208 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1209 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1211 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1212 /* 104 - 3840x2160p@25Hz 64:27 */
1213 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1214 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1215 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1216 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1217 /* 105 - 3840x2160p@30Hz 64:27 */
1218 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1219 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1220 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1221 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1222 /* 106 - 3840x2160p@50Hz 64:27 */
1223 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1224 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1225 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1226 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1227 /* 107 - 3840x2160p@60Hz 64:27 */
1228 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1229 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1230 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1231 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
a6b21831
TR		 1232};
1233
7ebe1963 1234/*
d9278b4c 1235 * HDMI 1.4 4k modes. Index using the VIC.
7ebe1963
LD		 1236 */
1237static const struct drm_display_mode edid_4k_modes[] = {
d9278b4c
JN		 1238 /* 0 - dummy, VICs start at 1 */
1239 { },
7ebe1963
LD		 1240 /* 1 - 3840x2160@30Hz */
1241 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1242 3840, 4016, 4104, 4400, 0,
1243 2160, 2168, 2178, 2250, 0,
1244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1245 .vrefresh = 30, },
1246 /* 2 - 3840x2160@25Hz */
1247 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1248 3840, 4896, 4984, 5280, 0,
1249 2160, 2168, 2178, 2250, 0,
1250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1251 .vrefresh = 25, },
1252 /* 3 - 3840x2160@24Hz */
1253 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1254 3840, 5116, 5204, 5500, 0,
1255 2160, 2168, 2178, 2250, 0,
1256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1257 .vrefresh = 24, },
1258 /* 4 - 4096x2160@24Hz (SMPTE) */
1259 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1260 4096, 5116, 5204, 5500, 0,
1261 2160, 2168, 2178, 2250, 0,
1262 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1263 .vrefresh = 24, },
1264};
1265
61e57a8d 1266/*** DDC fetch and block validation ***/
f453ba04 1267
083ae056
AJ		 1268static const u8 edid_header[] = {
1269 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1270};
f453ba04 1271
db6cf833
TR		 1272/**
1273 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1274 * @raw_edid: pointer to raw base EDID block
1275 *
1276 * Sanity check the header of the base EDID block.
1277 *
1278 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
051963d4
TR		 1279 */
1280int drm_edid_header_is_valid(const u8 *raw_edid)
1281{
1282 int i, score = 0;
1283
1284 for (i = 0; i < sizeof(edid_header); i++)
1285 if (raw_edid[i] == edid_header[i])
1286 score++;
1287
1288 return score;
1289}
1290EXPORT_SYMBOL(drm_edid_header_is_valid);
1291
47819ba2
AJ		 1292static int edid_fixup __read_mostly = 6;
1293module_param_named(edid_fixup, edid_fixup, int, 0400);
1294MODULE_PARM_DESC(edid_fixup,
1295 "Minimum number of valid EDID header bytes (0-8, default 6)");
051963d4 1296
40d9b043
DA		 1297static void drm_get_displayid(struct drm_connector *connector,
1298 struct edid *edid);
da9df2f4 1299
c465bbc8
SB		 1300static int drm_edid_block_checksum(const u8 *raw_edid)
1301{
1302 int i;
1303 u8 csum = 0;
1304 for (i = 0; i < EDID_LENGTH; i++)
1305 csum += raw_edid[i];
1306
1307 return csum;
1308}
1309
d6885d65
SB		 1310static bool drm_edid_is_zero(const u8 *in_edid, int length)
1311{
1312 if (memchr_inv(in_edid, 0, length))
1313 return false;
1314
1315 return true;
1316}
1317
db6cf833
TR		 1318/**
1319 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1320 * @raw_edid: pointer to raw EDID block
1321 * @block: type of block to validate (0 for base, extension otherwise)
1322 * @print_bad_edid: if true, dump bad EDID blocks to the console
6ba2bd3d 1323 * @edid_corrupt: if true, the header or checksum is invalid
db6cf833
TR		 1324 *
1325 * Validate a base or extension EDID block and optionally dump bad blocks to
1326 * the console.
1327 *
1328 * Return: True if the block is valid, false otherwise.
f453ba04 1329 */
6ba2bd3d
TP		 1330bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1331 bool *edid_corrupt)
f453ba04 1332{
c465bbc8 1333 u8 csum;
61e57a8d 1334 struct edid *edid = (struct edid *)raw_edid;
f453ba04 1335
fe2ef780
SWK		 1336 if (WARN_ON(!raw_edid))
1337 return false;
1338
47819ba2
AJ		 1339 if (edid_fixup > 8 || edid_fixup < 0)
1340 edid_fixup = 6;
1341
f89ec8a4 1342 if (block == 0) {
051963d4 1343 int score = drm_edid_header_is_valid(raw_edid);
6ba2bd3d
TP		 1344 if (score == 8) {
1345 if (edid_corrupt)
ac6f2e29 1346 *edid_corrupt = false;
6ba2bd3d
TP		 1347 } else if (score >= edid_fixup) {
1348 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1349 * The corrupt flag needs to be set here otherwise, the
1350 * fix-up code here will correct the problem, the
1351 * checksum is correct and the test fails
1352 */
1353 if (edid_corrupt)
ac6f2e29 1354 *edid_corrupt = true;
61e57a8d
AJ		 1355 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1356 memcpy(raw_edid, edid_header, sizeof(edid_header));
1357 } else {
6ba2bd3d 1358 if (edid_corrupt)
ac6f2e29 1359 *edid_corrupt = true;
61e57a8d
AJ		 1360 goto bad;
1361 }
1362 }
f453ba04 1363
c465bbc8 1364 csum = drm_edid_block_checksum(raw_edid);
f453ba04 1365 if (csum) {
6ba2bd3d 1366 if (edid_corrupt)
ac6f2e29 1367 *edid_corrupt = true;
6ba2bd3d 1368
4a638b4e 1369 /* allow CEA to slide through, switches mangle this */
82d75356
TV		 1370 if (raw_edid[0] == CEA_EXT) {
1371 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1372 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1373 } else {
1374 if (print_bad_edid)
813a7878 1375 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
82d75356 1376
4a638b4e 1377 goto bad;
82d75356 1378 }
f453ba04
DA		 1379 }
1380
61e57a8d
AJ		 1381 /* per-block-type checks */
1382 switch (raw_edid[0]) {
1383 case 0: /* base */
1384 if (edid->version != 1) {
813a7878 1385 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
61e57a8d
AJ		 1386 goto bad;
1387 }
862b89c0 1388
61e57a8d
AJ		 1389 if (edid->revision > 4)
1390 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1391 break;
862b89c0 1392
61e57a8d
AJ		 1393 default:
1394 break;
1395 }
47ee4ccf 1396
fe2ef780 1397 return true;
f453ba04
DA		 1398
1399bad:
fe2ef780 1400 if (print_bad_edid) {
da4c07b7 1401 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
499447db 1402 pr_notice("EDID block is all zeroes\n");
da4c07b7 1403 } else {
499447db 1404 pr_notice("Raw EDID:\n");
813a7878
CW		 1405 print_hex_dump(KERN_NOTICE,
1406 " \t", DUMP_PREFIX_NONE, 16, 1,
1407 raw_edid, EDID_LENGTH, false);
da4c07b7 1408 }
f453ba04 1409 }
fe2ef780 1410 return false;
f453ba04 1411}
da0df92b 1412EXPORT_SYMBOL(drm_edid_block_valid);
61e57a8d
AJ		 1413
1414/**
1415 * drm_edid_is_valid - sanity check EDID data
1416 * @edid: EDID data
1417 *
1418 * Sanity-check an entire EDID record (including extensions)
db6cf833
TR		 1419 *
1420 * Return: True if the EDID data is valid, false otherwise.
61e57a8d
AJ		 1421 */
1422bool drm_edid_is_valid(struct edid *edid)
1423{
1424 int i;
1425 u8 *raw = (u8 *)edid;
1426
1427 if (!edid)
1428 return false;
1429
1430 for (i = 0; i <= edid->extensions; i++)
6ba2bd3d 1431 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
61e57a8d
AJ		 1432 return false;
1433
1434 return true;
1435}
3c537889 1436EXPORT_SYMBOL(drm_edid_is_valid);
f453ba04 1437
61e57a8d
AJ		 1438#define DDC_SEGMENT_ADDR 0x30
1439/**
db6cf833 1440 * drm_do_probe_ddc_edid() - get EDID information via I2C
7c58e87e 1441 * @data: I2C device adapter
fc66811c
DV		 1442 * @buf: EDID data buffer to be filled
1443 * @block: 128 byte EDID block to start fetching from
1444 * @len: EDID data buffer length to fetch
1445 *
db6cf833 1446 * Try to fetch EDID information by calling I2C driver functions.
61e57a8d 1447 *
db6cf833 1448 * Return: 0 on success or -1 on failure.
61e57a8d
AJ		 1449 */
1450static int
18df89fe 1451drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
61e57a8d 1452{
18df89fe 1453 struct i2c_adapter *adapter = data;
61e57a8d 1454 unsigned char start = block * EDID_LENGTH;
cd004b3f
S		 1455 unsigned char segment = block >> 1;
1456 unsigned char xfers = segment ? 3 : 2;
4819d2e4
CW		 1457 int ret, retries = 5;
1458
db6cf833
TR		 1459 /*
1460 * The core I2C driver will automatically retry the transfer if the
4819d2e4
CW		 1461 * adapter reports EAGAIN. However, we find that bit-banging transfers
1462 * are susceptible to errors under a heavily loaded machine and
1463 * generate spurious NAKs and timeouts. Retrying the transfer
1464 * of the individual block a few times seems to overcome this.
1465 */
1466 do {
1467 struct i2c_msg msgs[] = {
1468 {
cd004b3f
S		 1469 .addr = DDC_SEGMENT_ADDR,
1470 .flags = 0,
1471 .len = 1,
1472 .buf = &segment,
1473 }, {
4819d2e4
CW		 1474 .addr = DDC_ADDR,
1475 .flags = 0,
1476 .len = 1,
1477 .buf = &start,
1478 }, {
1479 .addr = DDC_ADDR,
1480 .flags = I2C_M_RD,
1481 .len = len,
1482 .buf = buf,
1483 }
1484 };
cd004b3f 1485
db6cf833
TR		 1486 /*
1487 * Avoid sending the segment addr to not upset non-compliant
1488 * DDC monitors.
1489 */
cd004b3f
S		 1490 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1491
9292f37e
ED		 1492 if (ret == -ENXIO) {
1493 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1494 adapter->name);
1495 break;
1496 }
cd004b3f 1497 } while (ret != xfers && --retries);
4819d2e4 1498
cd004b3f 1499 return ret == xfers ? 0 : -1;
61e57a8d
AJ		 1500}
1501
14544d09
CW		 1502static void connector_bad_edid(struct drm_connector *connector,
1503 u8 *edid, int num_blocks)
1504{
1505 int i;
1506
1507 if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS))
1508 return;
1509
1510 dev_warn(connector->dev->dev,
1511 "%s: EDID is invalid:\n",
1512 connector->name);
1513 for (i = 0; i < num_blocks; i++) {
1514 u8 *block = edid + i * EDID_LENGTH;
1515 char prefix[20];
1516
1517 if (drm_edid_is_zero(block, EDID_LENGTH))
1518 sprintf(prefix, "\t[%02x] ZERO ", i);
1519 else if (!drm_edid_block_valid(block, i, false, NULL))
1520 sprintf(prefix, "\t[%02x] BAD ", i);
1521 else
1522 sprintf(prefix, "\t[%02x] GOOD ", i);
1523
1524 print_hex_dump(KERN_WARNING,
1525 prefix, DUMP_PREFIX_NONE, 16, 1,
1526 block, EDID_LENGTH, false);
1527 }
1528}
1529
18df89fe
LPC		 1530/**
1531 * drm_do_get_edid - get EDID data using a custom EDID block read function
1532 * @connector: connector we're probing
1533 * @get_edid_block: EDID block read function
1534 * @data: private data passed to the block read function
1535 *
1536 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1537 * exposes a different interface to read EDID blocks this function can be used
1538 * to get EDID data using a custom block read function.
1539 *
1540 * As in the general case the DDC bus is accessible by the kernel at the I2C
1541 * level, drivers must make all reasonable efforts to expose it as an I2C
1542 * adapter and use drm_get_edid() instead of abusing this function.
1543 *
53fd40a9
JN		 1544 * The EDID may be overridden using debugfs override_edid or firmare EDID
1545 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
1546 * order. Having either of them bypasses actual EDID reads.
1547 *
18df89fe
LPC		 1548 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1549 */
1550struct edid *drm_do_get_edid(struct drm_connector *connector,
1551 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1552 size_t len),
1553 void *data)
61e57a8d 1554{
0ea75e23 1555 int i, j = 0, valid_extensions = 0;
f14f3686 1556 u8 *edid, *new;
53fd40a9
JN		 1557 struct edid *override = NULL;
1558
1559 if (connector->override_edid)
1560 override = drm_edid_duplicate((const struct edid *)
1561 connector->edid_blob_ptr->data);
1562
1563 if (!override)
1564 override = drm_load_edid_firmware(connector);
1565
1566 if (!IS_ERR_OR_NULL(override))
1567 return override;
61e57a8d 1568
f14f3686 1569 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
61e57a8d
AJ		 1570 return NULL;
1571
1572 /* base block fetch */
1573 for (i = 0; i < 4; i++) {
f14f3686 1574 if (get_edid_block(data, edid, 0, EDID_LENGTH))
61e57a8d 1575 goto out;
14544d09 1576 if (drm_edid_block_valid(edid, 0, false,
6ba2bd3d 1577 &connector->edid_corrupt))
61e57a8d 1578 break;
f14f3686 1579 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
4a9a8b71
DA		 1580 connector->null_edid_counter++;
1581 goto carp;
1582 }
61e57a8d
AJ		 1583 }
1584 if (i == 4)
1585 goto carp;
1586
1587 /* if there's no extensions, we're done */
14544d09
CW		 1588 valid_extensions = edid[0x7e];
1589 if (valid_extensions == 0)
f14f3686 1590 return (struct edid *)edid;
61e57a8d 1591
14544d09 1592 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
61e57a8d
AJ		 1593 if (!new)
1594 goto out;
f14f3686 1595 edid = new;
61e57a8d 1596
f14f3686 1597 for (j = 1; j <= edid[0x7e]; j++) {
14544d09 1598 u8 *block = edid + j * EDID_LENGTH;
a28187cc 1599
61e57a8d 1600 for (i = 0; i < 4; i++) {
a28187cc 1601 if (get_edid_block(data, block, j, EDID_LENGTH))
61e57a8d 1602 goto out;
14544d09 1603 if (drm_edid_block_valid(block, j, false, NULL))
61e57a8d
AJ		 1604 break;
1605 }
f934ec8c 1606
14544d09
CW		 1607 if (i == 4)
1608 valid_extensions--;
0ea75e23
ST		 1609 }
1610
f14f3686 1611 if (valid_extensions != edid[0x7e]) {
14544d09
CW		 1612 u8 *base;
1613
1614 connector_bad_edid(connector, edid, edid[0x7e] + 1);
1615
f14f3686
CW		 1616 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
1617 edid[0x7e] = valid_extensions;
14544d09
CW		 1618
1619 new = kmalloc((valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
0ea75e23
ST		 1620 if (!new)
1621 goto out;
14544d09
CW		 1622
1623 base = new;
1624 for (i = 0; i <= edid[0x7e]; i++) {
1625 u8 *block = edid + i * EDID_LENGTH;
1626
1627 if (!drm_edid_block_valid(block, i, false, NULL))
1628 continue;
1629
1630 memcpy(base, block, EDID_LENGTH);
1631 base += EDID_LENGTH;
1632 }
1633
1634 kfree(edid);
f14f3686 1635 edid = new;
61e57a8d
AJ		 1636 }
1637
f14f3686 1638 return (struct edid *)edid;
61e57a8d
AJ		 1639
1640carp:
14544d09 1641 connector_bad_edid(connector, edid, 1);
61e57a8d 1642out:
f14f3686 1643 kfree(edid);
61e57a8d
AJ		 1644 return NULL;
1645}
18df89fe 1646EXPORT_SYMBOL_GPL(drm_do_get_edid);
61e57a8d
AJ		 1647
1648/**
db6cf833
TR		 1649 * drm_probe_ddc() - probe DDC presence
1650 * @adapter: I2C adapter to probe
fc66811c 1651 *
db6cf833 1652 * Return: True on success, false on failure.
61e57a8d 1653 */
fbff4690 1654bool
61e57a8d
AJ		 1655drm_probe_ddc(struct i2c_adapter *adapter)
1656{
1657 unsigned char out;
1658
1659 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1660}
fbff4690 1661EXPORT_SYMBOL(drm_probe_ddc);
61e57a8d
AJ		 1662
1663/**
1664 * drm_get_edid - get EDID data, if available
1665 * @connector: connector we're probing
db6cf833 1666 * @adapter: I2C adapter to use for DDC
61e57a8d 1667 *
db6cf833 1668 * Poke the given I2C channel to grab EDID data if possible. If found,
61e57a8d
AJ		 1669 * attach it to the connector.
1670 *
db6cf833 1671 * Return: Pointer to valid EDID or NULL if we couldn't find any.
61e57a8d
AJ		 1672 */
1673struct edid *drm_get_edid(struct drm_connector *connector,
1674 struct i2c_adapter *adapter)
1675{
40d9b043
DA		 1676 struct edid *edid;
1677
15f080f0
JN		 1678 if (connector->force == DRM_FORCE_OFF)
1679 return NULL;
1680
1681 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
18df89fe 1682 return NULL;
61e57a8d 1683
40d9b043
DA		 1684 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
1685 if (edid)
1686 drm_get_displayid(connector, edid);
1687 return edid;
61e57a8d
AJ		 1688}
1689EXPORT_SYMBOL(drm_get_edid);
1690
5cb8eaa2
LW		 1691/**
1692 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
1693 * @connector: connector we're probing
1694 * @adapter: I2C adapter to use for DDC
1695 *
1696 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
1697 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
1698 * switch DDC to the GPU which is retrieving EDID.
1699 *
1700 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
1701 */
1702struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
1703 struct i2c_adapter *adapter)
1704{
1705 struct pci_dev *pdev = connector->dev->pdev;
1706 struct edid *edid;
1707
1708 vga_switcheroo_lock_ddc(pdev);
1709 edid = drm_get_edid(connector, adapter);
1710 vga_switcheroo_unlock_ddc(pdev);
1711
1712 return edid;
1713}
1714EXPORT_SYMBOL(drm_get_edid_switcheroo);
1715
51f8da59
JN		 1716/**
1717 * drm_edid_duplicate - duplicate an EDID and the extensions
1718 * @edid: EDID to duplicate
1719 *
db6cf833 1720 * Return: Pointer to duplicated EDID or NULL on allocation failure.
51f8da59
JN		 1721 */
1722struct edid *drm_edid_duplicate(const struct edid *edid)
1723{
1724 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1725}
1726EXPORT_SYMBOL(drm_edid_duplicate);
1727
61e57a8d
AJ		 1728/*** EDID parsing ***/
1729
f453ba04
DA		 1730/**
1731 * edid_vendor - match a string against EDID's obfuscated vendor field
1732 * @edid: EDID to match
1733 * @vendor: vendor string
1734 *
1735 * Returns true if @vendor is in @edid, false otherwise
1736 */
4b4df570 1737static bool edid_vendor(const struct edid *edid, const char *vendor)
f453ba04
DA		 1738{
1739 char edid_vendor[3];
1740
1741 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1742 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1743 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
16456c87 1744 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
f453ba04
DA		 1745
1746 return !strncmp(edid_vendor, vendor, 3);
1747}
1748
1749/**
1750 * edid_get_quirks - return quirk flags for a given EDID
1751 * @edid: EDID to process
1752 *
1753 * This tells subsequent routines what fixes they need to apply.
1754 */
4b4df570 1755static u32 edid_get_quirks(const struct edid *edid)
f453ba04 1756{
23c4cfbd 1757 const struct edid_quirk *quirk;
f453ba04
DA		 1758 int i;
1759
1760 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1761 quirk = &edid_quirk_list[i];
1762
1763 if (edid_vendor(edid, quirk->vendor) &&
1764 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1765 return quirk->quirks;
1766 }
1767
1768 return 0;
1769}
1770
1771#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
339d202c 1772#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
f453ba04 1773
f453ba04
DA		 1774/**
1775 * edid_fixup_preferred - set preferred modes based on quirk list
1776 * @connector: has mode list to fix up
1777 * @quirks: quirks list
1778 *
1779 * Walk the mode list for @connector, clearing the preferred status
1780 * on existing modes and setting it anew for the right mode ala @quirks.
1781 */
1782static void edid_fixup_preferred(struct drm_connector *connector,
1783 u32 quirks)
1784{
1785 struct drm_display_mode *t, *cur_mode, *preferred_mode;
f890607b 1786 int target_refresh = 0;
339d202c 1787 int cur_vrefresh, preferred_vrefresh;
f453ba04
DA		 1788
1789 if (list_empty(&connector->probed_modes))
1790 return;
1791
1792 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1793 target_refresh = 60;
1794 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1795 target_refresh = 75;
1796
1797 preferred_mode = list_first_entry(&connector->probed_modes,
1798 struct drm_display_mode, head);
1799
1800 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1801 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1802
1803 if (cur_mode == preferred_mode)
1804 continue;
1805
1806 /* Largest mode is preferred */
1807 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1808 preferred_mode = cur_mode;
1809
339d202c
AD		 1810 cur_vrefresh = cur_mode->vrefresh ?
1811 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1812 preferred_vrefresh = preferred_mode->vrefresh ?
1813 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
f453ba04
DA		 1814 /* At a given size, try to get closest to target refresh */
1815 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
339d202c
AD		 1816 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1817 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
f453ba04
DA		 1818 preferred_mode = cur_mode;
1819 }
1820 }
1821
1822 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1823}
1824
f6e252ba
AJ		 1825static bool
1826mode_is_rb(const struct drm_display_mode *mode)
1827{
1828 return (mode->htotal - mode->hdisplay == 160) &&
1829 (mode->hsync_end - mode->hdisplay == 80) &&
1830 (mode->hsync_end - mode->hsync_start == 32) &&
1831 (mode->vsync_start - mode->vdisplay == 3);
1832}
1833
33c7531d
AJ		 1834/*
1835 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1836 * @dev: Device to duplicate against
1837 * @hsize: Mode width
1838 * @vsize: Mode height
1839 * @fresh: Mode refresh rate
f6e252ba 1840 * @rb: Mode reduced-blanking-ness
33c7531d
AJ		 1841 *
1842 * Walk the DMT mode list looking for a match for the given parameters.
db6cf833
TR		 1843 *
1844 * Return: A newly allocated copy of the mode, or NULL if not found.
33c7531d 1845 */
1d42bbc8 1846struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
f6e252ba
AJ		 1847 int hsize, int vsize, int fresh,
1848 bool rb)
559ee21d 1849{
07a5e632 1850 int i;
559ee21d 1851
a6b21831 1852 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
b1f559ec 1853 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
f8b46a05
AJ		 1854 if (hsize != ptr->hdisplay)
1855 continue;
1856 if (vsize != ptr->vdisplay)
1857 continue;
1858 if (fresh != drm_mode_vrefresh(ptr))
1859 continue;
f6e252ba
AJ		 1860 if (rb != mode_is_rb(ptr))
1861 continue;
f8b46a05
AJ		 1862
1863 return drm_mode_duplicate(dev, ptr);
559ee21d 1864 }
f8b46a05
AJ		 1865
1866 return NULL;
559ee21d 1867}
1d42bbc8 1868EXPORT_SYMBOL(drm_mode_find_dmt);
23425cae 1869
d1ff6409
AJ		 1870typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1871
4d76a221
AJ		 1872static void
1873cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1874{
1875 int i, n = 0;
4966b2a9 1876 u8 d = ext[0x02];
4d76a221
AJ		 1877 u8 *det_base = ext + d;
1878
4966b2a9 1879 n = (127 - d) / 18;
4d76a221
AJ		 1880 for (i = 0; i < n; i++)
1881 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1882}
1883
cbba98f8
AJ		 1884static void
1885vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1886{
1887 unsigned int i, n = min((int)ext[0x02], 6);
1888 u8 *det_base = ext + 5;
1889
1890 if (ext[0x01] != 1)
1891 return; /* unknown version */
1892
1893 for (i = 0; i < n; i++)
1894 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1895}
1896
d1ff6409
AJ		 1897static void
1898drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1899{
1900 int i;
1901 struct edid *edid = (struct edid *)raw_edid;
1902
1903 if (edid == NULL)
1904 return;
1905
1906 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1907 cb(&(edid->detailed_timings[i]), closure);
1908
4d76a221
AJ		 1909 for (i = 1; i <= raw_edid[0x7e]; i++) {
1910 u8 *ext = raw_edid + (i * EDID_LENGTH);
1911 switch (*ext) {
1912 case CEA_EXT:
1913 cea_for_each_detailed_block(ext, cb, closure);
1914 break;
cbba98f8
AJ		 1915 case VTB_EXT:
1916 vtb_for_each_detailed_block(ext, cb, closure);
1917 break;
4d76a221
AJ		 1918 default:
1919 break;
1920 }
1921 }
d1ff6409
AJ		 1922}
1923
1924static void
1925is_rb(struct detailed_timing *t, void *data)
1926{
1927 u8 *r = (u8 *)t;
1928 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
1929 if (r[15] & 0x10)
1930 *(bool *)data = true;
1931}
1932
1933/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
1934static bool
1935drm_monitor_supports_rb(struct edid *edid)
1936{
1937 if (edid->revision >= 4) {
b196a498 1938 bool ret = false;
d1ff6409
AJ		 1939 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
1940 return ret;
1941 }
1942
1943 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
1944}
1945
7a374350
AJ		 1946static void
1947find_gtf2(struct detailed_timing *t, void *data)
1948{
1949 u8 *r = (u8 *)t;
1950 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
1951 *(u8 **)data = r;
1952}
1953
1954/* Secondary GTF curve kicks in above some break frequency */
1955static int
1956drm_gtf2_hbreak(struct edid *edid)
1957{
1958 u8 *r = NULL;
1959 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1960 return r ? (r[12] * 2) : 0;
1961}
1962
1963static int
1964drm_gtf2_2c(struct edid *edid)
1965{
1966 u8 *r = NULL;
1967 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1968 return r ? r[13] : 0;
1969}
1970
1971static int
1972drm_gtf2_m(struct edid *edid)
1973{
1974 u8 *r = NULL;
1975 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1976 return r ? (r[15] << 8) + r[14] : 0;
1977}
1978
1979static int
1980drm_gtf2_k(struct edid *edid)
1981{
1982 u8 *r = NULL;
1983 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1984 return r ? r[16] : 0;
1985}
1986
1987static int
1988drm_gtf2_2j(struct edid *edid)
1989{
1990 u8 *r = NULL;
1991 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1992 return r ? r[17] : 0;
1993}
1994
1995/**
1996 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
1997 * @edid: EDID block to scan
1998 */
1999static int standard_timing_level(struct edid *edid)
2000{
2001 if (edid->revision >= 2) {
2002 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2003 return LEVEL_CVT;
2004 if (drm_gtf2_hbreak(edid))
2005 return LEVEL_GTF2;
2006 return LEVEL_GTF;
2007 }
2008 return LEVEL_DMT;
2009}
2010
23425cae
AJ		 2011/*
2012 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
2013 * monitors fill with ascii space (0x20) instead.
2014 */
2015static int
2016bad_std_timing(u8 a, u8 b)
2017{
2018 return (a == 0x00 && b == 0x00) ||
2019 (a == 0x01 && b == 0x01) ||
2020 (a == 0x20 && b == 0x20);
2021}
2022
f453ba04
DA		 2023/**
2024 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
fc66811c
DV		 2025 * @connector: connector of for the EDID block
2026 * @edid: EDID block to scan
f453ba04
DA		 2027 * @t: standard timing params
2028 *
2029 * Take the standard timing params (in this case width, aspect, and refresh)
5c61259e 2030 * and convert them into a real mode using CVT/GTF/DMT.
f453ba04 2031 */
7ca6adb3 2032static struct drm_display_mode *
7a374350 2033drm_mode_std(struct drm_connector *connector, struct edid *edid,
464fdeca 2034 struct std_timing *t)
f453ba04 2035{
7ca6adb3
AJ		 2036 struct drm_device *dev = connector->dev;
2037 struct drm_display_mode *m, *mode = NULL;
5c61259e
ZY		 2038 int hsize, vsize;
2039 int vrefresh_rate;
0454beab
MD		 2040 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2041 >> EDID_TIMING_ASPECT_SHIFT;
5c61259e
ZY		 2042 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2043 >> EDID_TIMING_VFREQ_SHIFT;
7a374350 2044 int timing_level = standard_timing_level(edid);
5c61259e 2045
23425cae
AJ		 2046 if (bad_std_timing(t->hsize, t->vfreq_aspect))
2047 return NULL;
2048
5c61259e
ZY		 2049 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2050 hsize = t->hsize * 8 + 248;
2051 /* vrefresh_rate = vfreq + 60 */
2052 vrefresh_rate = vfreq + 60;
2053 /* the vdisplay is calculated based on the aspect ratio */
f066a17d 2054 if (aspect_ratio == 0) {
464fdeca 2055 if (edid->revision < 3)
f066a17d
AJ		 2056 vsize = hsize;
2057 else
2058 vsize = (hsize * 10) / 16;
2059 } else if (aspect_ratio == 1)
f453ba04 2060 vsize = (hsize * 3) / 4;
0454beab 2061 else if (aspect_ratio == 2)
f453ba04
DA		 2062 vsize = (hsize * 4) / 5;
2063 else
2064 vsize = (hsize * 9) / 16;
a0910c8e
AJ		 2065
2066 /* HDTV hack, part 1 */
2067 if (vrefresh_rate == 60 &&
2068 ((hsize == 1360 && vsize == 765) ||
2069 (hsize == 1368 && vsize == 769))) {
2070 hsize = 1366;
2071 vsize = 768;
2072 }
2073
7ca6adb3
AJ		 2074 /*
2075 * If this connector already has a mode for this size and refresh
2076 * rate (because it came from detailed or CVT info), use that
2077 * instead. This way we don't have to guess at interlace or
2078 * reduced blanking.
2079 */
522032da 2080 list_for_each_entry(m, &connector->probed_modes, head)
7ca6adb3
AJ		 2081 if (m->hdisplay == hsize && m->vdisplay == vsize &&
2082 drm_mode_vrefresh(m) == vrefresh_rate)
2083 return NULL;
2084
a0910c8e
AJ		 2085 /* HDTV hack, part 2 */
2086 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2087 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
d50ba256 2088 false);
559ee21d 2089 mode->hdisplay = 1366;
a4967de6
AJ		 2090 mode->hsync_start = mode->hsync_start - 1;
2091 mode->hsync_end = mode->hsync_end - 1;
559ee21d
ZY		 2092 return mode;
2093 }
a0910c8e 2094
559ee21d 2095 /* check whether it can be found in default mode table */
f6e252ba
AJ		 2096 if (drm_monitor_supports_rb(edid)) {
2097 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2098 true);
2099 if (mode)
2100 return mode;
2101 }
2102 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
559ee21d
ZY		 2103 if (mode)
2104 return mode;
2105
f6e252ba 2106 /* okay, generate it */
5c61259e
ZY		 2107 switch (timing_level) {
2108 case LEVEL_DMT:
5c61259e
ZY		 2109 break;
2110 case LEVEL_GTF:
2111 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2112 break;
7a374350
AJ		 2113 case LEVEL_GTF2:
2114 /*
2115 * This is potentially wrong if there's ever a monitor with
2116 * more than one ranges section, each claiming a different
2117 * secondary GTF curve. Please don't do that.
2118 */
2119 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
fc48f169
TI		 2120 if (!mode)
2121 return NULL;
7a374350 2122 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
aefd330e 2123 drm_mode_destroy(dev, mode);
7a374350
AJ		 2124 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2125 vrefresh_rate, 0, 0,
2126 drm_gtf2_m(edid),
2127 drm_gtf2_2c(edid),
2128 drm_gtf2_k(edid),
2129 drm_gtf2_2j(edid));
2130 }
2131 break;
5c61259e 2132 case LEVEL_CVT:
d50ba256
DA		 2133 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2134 false);
5c61259e
ZY		 2135 break;
2136 }
f453ba04
DA		 2137 return mode;
2138}
2139
b58db2c6
AJ		 2140/*
2141 * EDID is delightfully ambiguous about how interlaced modes are to be
2142 * encoded. Our internal representation is of frame height, but some
2143 * HDTV detailed timings are encoded as field height.
2144 *
2145 * The format list here is from CEA, in frame size. Technically we
2146 * should be checking refresh rate too. Whatever.
2147 */
2148static void
2149drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2150 struct detailed_pixel_timing *pt)
2151{
2152 int i;
2153 static const struct {
2154 int w, h;
2155 } cea_interlaced[] = {
2156 { 1920, 1080 },
2157 { 720, 480 },
2158 { 1440, 480 },
2159 { 2880, 480 },
2160 { 720, 576 },
2161 { 1440, 576 },
2162 { 2880, 576 },
2163 };
b58db2c6
AJ		 2164
2165 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2166 return;
2167
3c581411 2168 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
b58db2c6
AJ		 2169 if ((mode->hdisplay == cea_interlaced[i].w) &&
2170 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2171 mode->vdisplay *= 2;
2172 mode->vsync_start *= 2;
2173 mode->vsync_end *= 2;
2174 mode->vtotal *= 2;
2175 mode->vtotal |= 1;
2176 }
2177 }
2178
2179 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2180}
2181
f453ba04
DA		 2182/**
2183 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2184 * @dev: DRM device (needed to create new mode)
2185 * @edid: EDID block
2186 * @timing: EDID detailed timing info
2187 * @quirks: quirks to apply
2188 *
2189 * An EDID detailed timing block contains enough info for us to create and
2190 * return a new struct drm_display_mode.
2191 */
2192static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2193 struct edid *edid,
2194 struct detailed_timing *timing,
2195 u32 quirks)
2196{
2197 struct drm_display_mode *mode;
2198 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
0454beab
MD		 2199 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2200 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2201 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2202 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
e14cbee4
MD		 2203 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2204 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
16dad1d7 2205 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
e14cbee4 2206 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
f453ba04 2207
fc438966 2208 /* ignore tiny modes */
0454beab 2209 if (hactive < 64 || vactive < 64)
fc438966
AJ		 2210 return NULL;
2211
0454beab 2212 if (pt->misc & DRM_EDID_PT_STEREO) {
c7d015f3 2213 DRM_DEBUG_KMS("stereo mode not supported\n");
f453ba04
DA		 2214 return NULL;
2215 }
0454beab 2216 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
c7d015f3 2217 DRM_DEBUG_KMS("composite sync not supported\n");
f453ba04
DA		 2218 }
2219
fcb45611
ZY		 2220 /* it is incorrect if hsync/vsync width is zero */
2221 if (!hsync_pulse_width || !vsync_pulse_width) {
2222 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2223 "Wrong Hsync/Vsync pulse width\n");
2224 return NULL;
2225 }
bc42aabc
AJ		 2226
2227 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2228 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2229 if (!mode)
2230 return NULL;
2231
2232 goto set_size;
2233 }
2234
f453ba04
DA		 2235 mode = drm_mode_create(dev);
2236 if (!mode)
2237 return NULL;
2238
f453ba04 2239 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
0454beab
MD		 2240 timing->pixel_clock = cpu_to_le16(1088);
2241
2242 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2243
2244 mode->hdisplay = hactive;
2245 mode->hsync_start = mode->hdisplay + hsync_offset;
2246 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2247 mode->htotal = mode->hdisplay + hblank;
2248
2249 mode->vdisplay = vactive;
2250 mode->vsync_start = mode->vdisplay + vsync_offset;
2251 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2252 mode->vtotal = mode->vdisplay + vblank;
f453ba04 2253
7064fef5
JB		 2254 /* Some EDIDs have bogus h/vtotal values */
2255 if (mode->hsync_end > mode->htotal)
2256 mode->htotal = mode->hsync_end + 1;
2257 if (mode->vsync_end > mode->vtotal)
2258 mode->vtotal = mode->vsync_end + 1;
2259
b58db2c6 2260 drm_mode_do_interlace_quirk(mode, pt);
f453ba04
DA		 2261
2262 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
0454beab 2263 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
f453ba04
DA		 2264 }
2265
0454beab
MD		 2266 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2267 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2268 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2269 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
f453ba04 2270
bc42aabc 2271set_size:
e14cbee4
MD		 2272 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2273 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
f453ba04
DA		 2274
2275 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2276 mode->width_mm *= 10;
2277 mode->height_mm *= 10;
2278 }
2279
2280 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2281 mode->width_mm = edid->width_cm * 10;
2282 mode->height_mm = edid->height_cm * 10;
2283 }
2284
bc42aabc 2285 mode->type = DRM_MODE_TYPE_DRIVER;
c19b3b0f 2286 mode->vrefresh = drm_mode_vrefresh(mode);
bc42aabc
AJ		 2287 drm_mode_set_name(mode);
2288
f453ba04
DA		 2289 return mode;
2290}
2291
b17e52ef 2292static bool
b1f559ec
CW		 2293mode_in_hsync_range(const struct drm_display_mode *mode,
2294 struct edid *edid, u8 *t)
b17e52ef
AJ		 2295{
2296 int hsync, hmin, hmax;
2297
2298 hmin = t[7];
2299 if (edid->revision >= 4)
2300 hmin += ((t[4] & 0x04) ? 255 : 0);
2301 hmax = t[8];
2302 if (edid->revision >= 4)
2303 hmax += ((t[4] & 0x08) ? 255 : 0);
07a5e632 2304 hsync = drm_mode_hsync(mode);
07a5e632 2305
b17e52ef
AJ		 2306 return (hsync <= hmax && hsync >= hmin);
2307}
2308
2309static bool
b1f559ec
CW		 2310mode_in_vsync_range(const struct drm_display_mode *mode,
2311 struct edid *edid, u8 *t)
b17e52ef
AJ		 2312{
2313 int vsync, vmin, vmax;
2314
2315 vmin = t[5];
2316 if (edid->revision >= 4)
2317 vmin += ((t[4] & 0x01) ? 255 : 0);
2318 vmax = t[6];
2319 if (edid->revision >= 4)
2320 vmax += ((t[4] & 0x02) ? 255 : 0);
2321 vsync = drm_mode_vrefresh(mode);
2322
2323 return (vsync <= vmax && vsync >= vmin);
2324}
2325
2326static u32
2327range_pixel_clock(struct edid *edid, u8 *t)
2328{
2329 /* unspecified */
2330 if (t[9] == 0 || t[9] == 255)
2331 return 0;
2332
2333 /* 1.4 with CVT support gives us real precision, yay */
2334 if (edid->revision >= 4 && t[10] == 0x04)
2335 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2336
2337 /* 1.3 is pathetic, so fuzz up a bit */
2338 return t[9] * 10000 + 5001;
2339}
2340
b17e52ef 2341static bool
b1f559ec 2342mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
b17e52ef
AJ		 2343 struct detailed_timing *timing)
2344{
2345 u32 max_clock;
2346 u8 *t = (u8 *)timing;
2347
2348 if (!mode_in_hsync_range(mode, edid, t))
07a5e632
AJ		 2349 return false;
2350
b17e52ef 2351 if (!mode_in_vsync_range(mode, edid, t))
07a5e632
AJ		 2352 return false;
2353
b17e52ef 2354 if ((max_clock = range_pixel_clock(edid, t)))
07a5e632
AJ		 2355 if (mode->clock > max_clock)
2356 return false;
b17e52ef
AJ		 2357
2358 /* 1.4 max horizontal check */
2359 if (edid->revision >= 4 && t[10] == 0x04)
2360 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2361 return false;
2362
2363 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2364 return false;
07a5e632
AJ		 2365
2366 return true;
2367}
2368
7b668ebe
TI		 2369static bool valid_inferred_mode(const struct drm_connector *connector,
2370 const struct drm_display_mode *mode)
2371{
85f8fcd6 2372 const struct drm_display_mode *m;
7b668ebe
TI		 2373 bool ok = false;
2374
2375 list_for_each_entry(m, &connector->probed_modes, head) {
2376 if (mode->hdisplay == m->hdisplay &&
2377 mode->vdisplay == m->vdisplay &&
2378 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2379 return false; /* duplicated */
2380 if (mode->hdisplay <= m->hdisplay &&
2381 mode->vdisplay <= m->vdisplay)
2382 ok = true;
2383 }
2384 return ok;
2385}
2386
b17e52ef 2387static int
cd4cd3de 2388drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
b17e52ef 2389 struct detailed_timing *timing)
07a5e632
AJ		 2390{
2391 int i, modes = 0;
2392 struct drm_display_mode *newmode;
2393 struct drm_device *dev = connector->dev;
2394
a6b21831 2395 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
7b668ebe
TI		 2396 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2397 valid_inferred_mode(connector, drm_dmt_modes + i)) {
07a5e632
AJ		 2398 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2399 if (newmode) {
2400 drm_mode_probed_add(connector, newmode);
2401 modes++;
2402 }
2403 }
2404 }
2405
2406 return modes;
2407}
2408
c09dedb7
TI		 2409/* fix up 1366x768 mode from 1368x768;
2410 * GFT/CVT can't express 1366 width which isn't dividable by 8
2411 */
969218fe 2412void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
c09dedb7
TI		 2413{
2414 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2415 mode->hdisplay = 1366;
2416 mode->hsync_start--;
2417 mode->hsync_end--;
2418 drm_mode_set_name(mode);
2419 }
2420}
2421
b309bd37
AJ		 2422static int
2423drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2424 struct detailed_timing *timing)
2425{
2426 int i, modes = 0;
2427 struct drm_display_mode *newmode;
2428 struct drm_device *dev = connector->dev;
2429
a6b21831 2430 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37
AJ		 2431 const struct minimode *m = &extra_modes[i];
2432 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
fc48f169
TI		 2433 if (!newmode)
2434 return modes;
b309bd37 2435
969218fe 2436 drm_mode_fixup_1366x768(newmode);
7b668ebe
TI		 2437 if (!mode_in_range(newmode, edid, timing) ||
2438 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 2439 drm_mode_destroy(dev, newmode);
2440 continue;
2441 }
2442
2443 drm_mode_probed_add(connector, newmode);
2444 modes++;
2445 }
2446
2447 return modes;
2448}
2449
2450static int
2451drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2452 struct detailed_timing *timing)
2453{
2454 int i, modes = 0;
2455 struct drm_display_mode *newmode;
2456 struct drm_device *dev = connector->dev;
2457 bool rb = drm_monitor_supports_rb(edid);
2458
a6b21831 2459 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37
AJ		 2460 const struct minimode *m = &extra_modes[i];
2461 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
fc48f169
TI		 2462 if (!newmode)
2463 return modes;
b309bd37 2464
969218fe 2465 drm_mode_fixup_1366x768(newmode);
7b668ebe
TI		 2466 if (!mode_in_range(newmode, edid, timing) ||
2467 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 2468 drm_mode_destroy(dev, newmode);
2469 continue;
2470 }
2471
2472 drm_mode_probed_add(connector, newmode);
2473 modes++;
2474 }
2475
2476 return modes;
2477}
2478
13931579
AJ		 2479static void
2480do_inferred_modes(struct detailed_timing *timing, void *c)
9340d8cf 2481{
13931579
AJ		 2482 struct detailed_mode_closure *closure = c;
2483 struct detailed_non_pixel *data = &timing->data.other_data;
b309bd37 2484 struct detailed_data_monitor_range *range = &data->data.range;
9340d8cf 2485
cb21aafe
AJ		 2486 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2487 return;
2488
2489 closure->modes += drm_dmt_modes_for_range(closure->connector,
2490 closure->edid,
2491 timing);
b309bd37
AJ		 2492
2493 if (!version_greater(closure->edid, 1, 1))
2494 return; /* GTF not defined yet */
2495
2496 switch (range->flags) {
2497 case 0x02: /* secondary gtf, XXX could do more */
2498 case 0x00: /* default gtf */
2499 closure->modes += drm_gtf_modes_for_range(closure->connector,
2500 closure->edid,
2501 timing);
2502 break;
2503 case 0x04: /* cvt, only in 1.4+ */
2504 if (!version_greater(closure->edid, 1, 3))
2505 break;
2506
2507 closure->modes += drm_cvt_modes_for_range(closure->connector,
2508 closure->edid,
2509 timing);
2510 break;
2511 case 0x01: /* just the ranges, no formula */
2512 default:
2513 break;
2514 }
13931579 2515}
69da3015 2516
13931579
AJ		 2517static int
2518add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2519{
2520 struct detailed_mode_closure closure = {
d456ea2e
JL		 2521 .connector = connector,
2522 .edid = edid,
13931579 2523 };
9340d8cf 2524
13931579
AJ		 2525 if (version_greater(edid, 1, 0))
2526 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2527 &closure);
9340d8cf 2528
13931579 2529 return closure.modes;
9340d8cf
AJ		 2530}
2531
2255be14
AJ		 2532static int
2533drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2534{
2535 int i, j, m, modes = 0;
2536 struct drm_display_mode *mode;
f3a32d74 2537 u8 *est = ((u8 *)timing) + 6;
2255be14
AJ		 2538
2539 for (i = 0; i < 6; i++) {
891a7469 2540 for (j = 7; j >= 0; j--) {
2255be14 2541 m = (i * 8) + (7 - j);
3c581411 2542 if (m >= ARRAY_SIZE(est3_modes))
2255be14
AJ		 2543 break;
2544 if (est[i] & (1 << j)) {
1d42bbc8
DA		 2545 mode = drm_mode_find_dmt(connector->dev,
2546 est3_modes[m].w,
2547 est3_modes[m].h,
f6e252ba
AJ		 2548 est3_modes[m].r,
2549 est3_modes[m].rb);
2255be14
AJ		 2550 if (mode) {
2551 drm_mode_probed_add(connector, mode);
2552 modes++;
2553 }
2554 }
2555 }
2556 }
2557
2558 return modes;
2559}
2560
13931579
AJ		 2561static void
2562do_established_modes(struct detailed_timing *timing, void *c)
9cf00977 2563{
13931579 2564 struct detailed_mode_closure *closure = c;
9cf00977 2565 struct detailed_non_pixel *data = &timing->data.other_data;
9cf00977 2566
13931579
AJ		 2567 if (data->type == EDID_DETAIL_EST_TIMINGS)
2568 closure->modes += drm_est3_modes(closure->connector, timing);
2569}
9cf00977 2570
13931579
AJ		 2571/**
2572 * add_established_modes - get est. modes from EDID and add them
db6cf833 2573 * @connector: connector to add mode(s) to
13931579
AJ		 2574 * @edid: EDID block to scan
2575 *
2576 * Each EDID block contains a bitmap of the supported "established modes" list
2577 * (defined above). Tease them out and add them to the global modes list.
2578 */
2579static int
2580add_established_modes(struct drm_connector *connector, struct edid *edid)
2581{
2582 struct drm_device *dev = connector->dev;
2583 unsigned long est_bits = edid->established_timings.t1 |
2584 (edid->established_timings.t2 << 8) |
2585 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2586 int i, modes = 0;
2587 struct detailed_mode_closure closure = {
d456ea2e
JL		 2588 .connector = connector,
2589 .edid = edid,
13931579 2590 };
9cf00977 2591
13931579
AJ		 2592 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2593 if (est_bits & (1<<i)) {
2594 struct drm_display_mode *newmode;
2595 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2596 if (newmode) {
2597 drm_mode_probed_add(connector, newmode);
2598 modes++;
2599 }
2600 }
9cf00977
AJ		 2601 }
2602
13931579
AJ		 2603 if (version_greater(edid, 1, 0))
2604 drm_for_each_detailed_block((u8 *)edid,
2605 do_established_modes, &closure);
2606
2607 return modes + closure.modes;
2608}
2609
2610static void
2611do_standard_modes(struct detailed_timing *timing, void *c)
2612{
2613 struct detailed_mode_closure *closure = c;
2614 struct detailed_non_pixel *data = &timing->data.other_data;
2615 struct drm_connector *connector = closure->connector;
2616 struct edid *edid = closure->edid;
2617
2618 if (data->type == EDID_DETAIL_STD_MODES) {
2619 int i;
9cf00977
AJ		 2620 for (i = 0; i < 6; i++) {
2621 struct std_timing *std;
2622 struct drm_display_mode *newmode;
2623
2624 std = &data->data.timings[i];
464fdeca 2625 newmode = drm_mode_std(connector, edid, std);
9cf00977
AJ		 2626 if (newmode) {
2627 drm_mode_probed_add(connector, newmode);
13931579 2628 closure->modes++;
9cf00977
AJ		 2629 }
2630 }
9cf00977 2631 }
9cf00977
AJ		 2632}
2633
f453ba04 2634/**
13931579 2635 * add_standard_modes - get std. modes from EDID and add them
db6cf833 2636 * @connector: connector to add mode(s) to
f453ba04 2637 * @edid: EDID block to scan
f453ba04 2638 *
13931579
AJ		 2639 * Standard modes can be calculated using the appropriate standard (DMT,
2640 * GTF or CVT. Grab them from @edid and add them to the list.
f453ba04 2641 */
13931579
AJ		 2642static int
2643add_standard_modes(struct drm_connector *connector, struct edid *edid)
f453ba04 2644{
9cf00977 2645 int i, modes = 0;
13931579 2646 struct detailed_mode_closure closure = {
d456ea2e
JL		 2647 .connector = connector,
2648 .edid = edid,
13931579
AJ		 2649 };
2650
2651 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2652 struct drm_display_mode *newmode;
2653
2654 newmode = drm_mode_std(connector, edid,
464fdeca 2655 &edid->standard_timings[i]);
13931579
AJ		 2656 if (newmode) {
2657 drm_mode_probed_add(connector, newmode);
2658 modes++;
2659 }
2660 }
2661
2662 if (version_greater(edid, 1, 0))
2663 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2664 &closure);
2665
2666 /* XXX should also look for standard codes in VTB blocks */
2667
2668 return modes + closure.modes;
2669}
f453ba04 2670
13931579
AJ		 2671static int drm_cvt_modes(struct drm_connector *connector,
2672 struct detailed_timing *timing)
2673{
2674 int i, j, modes = 0;
2675 struct drm_display_mode *newmode;
2676 struct drm_device *dev = connector->dev;
2677 struct cvt_timing *cvt;
2678 const int rates[] = { 60, 85, 75, 60, 50 };
2679 const u8 empty[3] = { 0, 0, 0 };
a327f6b8 2680
13931579
AJ		 2681 for (i = 0; i < 4; i++) {
2682 int uninitialized_var(width), height;
2683 cvt = &(timing->data.other_data.data.cvt[i]);
f453ba04 2684
13931579 2685 if (!memcmp(cvt->code, empty, 3))
9cf00977 2686 continue;
f453ba04 2687
13931579
AJ		 2688 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2689 switch (cvt->code[1] & 0x0c) {
2690 case 0x00:
2691 width = height * 4 / 3;
2692 break;
2693 case 0x04:
2694 width = height * 16 / 9;
2695 break;
2696 case 0x08:
2697 width = height * 16 / 10;
2698 break;
2699 case 0x0c:
2700 width = height * 15 / 9;
2701 break;
2702 }
2703
2704 for (j = 1; j < 5; j++) {
2705 if (cvt->code[2] & (1 << j)) {
2706 newmode = drm_cvt_mode(dev, width, height,
2707 rates[j], j == 0,
2708 false, false);
2709 if (newmode) {
2710 drm_mode_probed_add(connector, newmode);
2711 modes++;
2712 }
2713 }
2714 }
f453ba04
DA		 2715 }
2716
2717 return modes;
2718}
9cf00977 2719
13931579
AJ		 2720static void
2721do_cvt_mode(struct detailed_timing *timing, void *c)
882f0219 2722{
13931579
AJ		 2723 struct detailed_mode_closure *closure = c;
2724 struct detailed_non_pixel *data = &timing->data.other_data;
882f0219 2725
13931579
AJ		 2726 if (data->type == EDID_DETAIL_CVT_3BYTE)
2727 closure->modes += drm_cvt_modes(closure->connector, timing);
2728}
882f0219 2729
13931579
AJ		 2730static int
2731add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2732{
2733 struct detailed_mode_closure closure = {
d456ea2e
JL		 2734 .connector = connector,
2735 .edid = edid,
13931579 2736 };
882f0219 2737
13931579
AJ		 2738 if (version_greater(edid, 1, 2))
2739 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
882f0219 2740
13931579 2741 /* XXX should also look for CVT codes in VTB blocks */
882f0219 2742
13931579
AJ		 2743 return closure.modes;
2744}
2745
fa3a7340
VS		 2746static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
2747
13931579
AJ		 2748static void
2749do_detailed_mode(struct detailed_timing *timing, void *c)
2750{
2751 struct detailed_mode_closure *closure = c;
2752 struct drm_display_mode *newmode;
2753
2754 if (timing->pixel_clock) {
2755 newmode = drm_mode_detailed(closure->connector->dev,
2756 closure->edid, timing,
2757 closure->quirks);
2758 if (!newmode)
2759 return;
2760
2761 if (closure->preferred)
2762 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2763
fa3a7340
VS		 2764 /*
2765 * Detailed modes are limited to 10kHz pixel clock resolution,
2766 * so fix up anything that looks like CEA/HDMI mode, but the clock
2767 * is just slightly off.
2768 */
2769 fixup_detailed_cea_mode_clock(newmode);
2770
13931579
AJ		 2771 drm_mode_probed_add(closure->connector, newmode);
2772 closure->modes++;
2773 closure->preferred = 0;
882f0219 2774 }
13931579 2775}
882f0219 2776
13931579
AJ		 2777/*
2778 * add_detailed_modes - Add modes from detailed timings
2779 * @connector: attached connector
2780 * @edid: EDID block to scan
2781 * @quirks: quirks to apply
2782 */
2783static int
2784add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2785 u32 quirks)
2786{
2787 struct detailed_mode_closure closure = {
d456ea2e
JL		 2788 .connector = connector,
2789 .edid = edid,
2790 .preferred = 1,
2791 .quirks = quirks,
13931579
AJ		 2792 };
2793
2794 if (closure.preferred && !version_greater(edid, 1, 3))
2795 closure.preferred =
2796 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2797
2798 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2799
2800 return closure.modes;
882f0219 2801}
f453ba04 2802
8fe9790d 2803#define AUDIO_BLOCK 0x01
54ac76f8 2804#define VIDEO_BLOCK 0x02
f23c20c8 2805#define VENDOR_BLOCK 0x03
76adaa34 2806#define SPEAKER_BLOCK 0x04
87563fc0
SS		 2807#define USE_EXTENDED_TAG 0x07
2808#define EXT_VIDEO_CAPABILITY_BLOCK 0x00
832d4f2f
SS		 2809#define EXT_VIDEO_DATA_BLOCK_420 0x0E
2810#define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
8fe9790d 2811#define EDID_BASIC_AUDIO (1 << 6)
a988bc72
LPC		 2812#define EDID_CEA_YCRCB444 (1 << 5)
2813#define EDID_CEA_YCRCB422 (1 << 4)
b1edd6a6 2814#define EDID_CEA_VCDB_QS (1 << 6)
8fe9790d 2815
d4e4a31d 2816/*
8fe9790d 2817 * Search EDID for CEA extension block.
f23c20c8 2818 */
4b4df570 2819static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id)
f23c20c8 2820{
8fe9790d
ZW		 2821 u8 *edid_ext = NULL;
2822 int i;
f23c20c8
ML		 2823
2824 /* No EDID or EDID extensions */
2825 if (edid == NULL || edid->extensions == 0)
8fe9790d 2826 return NULL;
f23c20c8 2827
f23c20c8 2828 /* Find CEA extension */
7466f4cc 2829 for (i = 0; i < edid->extensions; i++) {
8fe9790d 2830 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
40d9b043 2831 if (edid_ext[0] == ext_id)
f23c20c8
ML		 2832 break;
2833 }
2834
7466f4cc 2835 if (i == edid->extensions)
8fe9790d
ZW		 2836 return NULL;
2837
2838 return edid_ext;
2839}
2840
4b4df570 2841static u8 *drm_find_cea_extension(const struct edid *edid)
40d9b043
DA		 2842{
2843 return drm_find_edid_extension(edid, CEA_EXT);
2844}
2845
4b4df570 2846static u8 *drm_find_displayid_extension(const struct edid *edid)
40d9b043
DA		 2847{
2848 return drm_find_edid_extension(edid, DISPLAYID_EXT);
2849}
2850
e6e79209
VS		 2851/*
2852 * Calculate the alternate clock for the CEA mode
2853 * (60Hz vs. 59.94Hz etc.)
2854 */
2855static unsigned int
2856cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2857{
2858 unsigned int clock = cea_mode->clock;
2859
2860 if (cea_mode->vrefresh % 6 != 0)
2861 return clock;
2862
2863 /*
2864 * edid_cea_modes contains the 59.94Hz
2865 * variant for 240 and 480 line modes,
2866 * and the 60Hz variant otherwise.
2867 */
2868 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
9afd808c 2869 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
e6e79209 2870 else
9afd808c 2871 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
e6e79209
VS		 2872
2873 return clock;
2874}
2875
c45a4e46
VS		 2876static bool
2877cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
2878{
2879 /*
2880 * For certain VICs the spec allows the vertical
2881 * front porch to vary by one or two lines.
2882 *
2883 * cea_modes[] stores the variant with the shortest
2884 * vertical front porch. We can adjust the mode to
2885 * get the other variants by simply increasing the
2886 * vertical front porch length.
2887 */
2888 BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 ||
2889 edid_cea_modes[9].vtotal != 262 ||
2890 edid_cea_modes[12].vtotal != 262 ||
2891 edid_cea_modes[13].vtotal != 262 ||
2892 edid_cea_modes[23].vtotal != 312 ||
2893 edid_cea_modes[24].vtotal != 312 ||
2894 edid_cea_modes[27].vtotal != 312 ||
2895 edid_cea_modes[28].vtotal != 312);
2896
2897 if (((vic == 8 || vic == 9 ||
2898 vic == 12 || vic == 13) && mode->vtotal < 263) ||
2899 ((vic == 23 || vic == 24 ||
2900 vic == 27 || vic == 28) && mode->vtotal < 314)) {
2901 mode->vsync_start++;
2902 mode->vsync_end++;
2903 mode->vtotal++;
2904
2905 return true;
2906 }
2907
2908 return false;
2909}
2910
4c6bcf44
VS		 2911static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
2912 unsigned int clock_tolerance)
2913{
d9278b4c 2914 u8 vic;
4c6bcf44
VS		 2915
2916 if (!to_match->clock)
2917 return 0;
2918
d9278b4c 2919 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
c45a4e46 2920 struct drm_display_mode cea_mode = edid_cea_modes[vic];
4c6bcf44
VS		 2921 unsigned int clock1, clock2;
2922
2923 /* Check both 60Hz and 59.94Hz */
c45a4e46
VS		 2924 clock1 = cea_mode.clock;
2925 clock2 = cea_mode_alternate_clock(&cea_mode);
4c6bcf44
VS		 2926
2927 if (abs(to_match->clock - clock1) > clock_tolerance &&
2928 abs(to_match->clock - clock2) > clock_tolerance)
2929 continue;
2930
c45a4e46
VS		 2931 do {
2932 if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode))
2933 return vic;
2934 } while (cea_mode_alternate_timings(vic, &cea_mode));
4c6bcf44
VS		 2935 }
2936
2937 return 0;
2938}
2939
18316c8c
TR		 2940/**
2941 * drm_match_cea_mode - look for a CEA mode matching given mode
2942 * @to_match: display mode
2943 *
db6cf833 2944 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
18316c8c 2945 * mode.
a4799037 2946 */
18316c8c 2947u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
a4799037 2948{
d9278b4c 2949 u8 vic;
a4799037 2950
a90b590e
VS		 2951 if (!to_match->clock)
2952 return 0;
2953
d9278b4c 2954 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
c45a4e46 2955 struct drm_display_mode cea_mode = edid_cea_modes[vic];
a90b590e
VS		 2956 unsigned int clock1, clock2;
2957
a90b590e 2958 /* Check both 60Hz and 59.94Hz */
c45a4e46
VS		 2959 clock1 = cea_mode.clock;
2960 clock2 = cea_mode_alternate_clock(&cea_mode);
a4799037 2961
c45a4e46
VS		 2962 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
2963 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
2964 continue;
2965
2966 do {
2967 if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode))
2968 return vic;
2969 } while (cea_mode_alternate_timings(vic, &cea_mode));
a4799037 2970 }
c45a4e46 2971
a4799037
SM		 2972 return 0;
2973}
2974EXPORT_SYMBOL(drm_match_cea_mode);
2975
d9278b4c
JN		 2976static bool drm_valid_cea_vic(u8 vic)
2977{
2978 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
2979}
2980
0967e6a5
VK		 2981/**
2982 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
2983 * the input VIC from the CEA mode list
2984 * @video_code: ID given to each of the CEA modes
2985 *
2986 * Returns picture aspect ratio
2987 */
2988enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
2989{
d9278b4c 2990 return edid_cea_modes[video_code].picture_aspect_ratio;
0967e6a5
VK		 2991}
2992EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
2993
3f2f6533
LD		 2994/*
2995 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
2996 * specific block).
2997 *
2998 * It's almost like cea_mode_alternate_clock(), we just need to add an
2999 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
3000 * one.
3001 */
3002static unsigned int
3003hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3004{
3005 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
3006 return hdmi_mode->clock;
3007
3008 return cea_mode_alternate_clock(hdmi_mode);
3009}
3010
4c6bcf44
VS		 3011static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3012 unsigned int clock_tolerance)
3013{
d9278b4c 3014 u8 vic;
4c6bcf44
VS		 3015
3016 if (!to_match->clock)
3017 return 0;
3018
d9278b4c
JN		 3019 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3020 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4c6bcf44
VS		 3021 unsigned int clock1, clock2;
3022
3023 /* Make sure to also match alternate clocks */
3024 clock1 = hdmi_mode->clock;
3025 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3026
3027 if (abs(to_match->clock - clock1) > clock_tolerance &&
3028 abs(to_match->clock - clock2) > clock_tolerance)
3029 continue;
3030
3031 if (drm_mode_equal_no_clocks(to_match, hdmi_mode))
d9278b4c 3032 return vic;
4c6bcf44
VS		 3033 }
3034
3035 return 0;
3036}
3037
3f2f6533
LD		 3038/*
3039 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3040 * @to_match: display mode
3041 *
3042 * An HDMI mode is one defined in the HDMI vendor specific block.
3043 *
3044 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3045 */
3046static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3047{
d9278b4c 3048 u8 vic;
3f2f6533
LD		 3049
3050 if (!to_match->clock)
3051 return 0;
3052
d9278b4c
JN		 3053 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3054 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3f2f6533
LD		 3055 unsigned int clock1, clock2;
3056
3057 /* Make sure to also match alternate clocks */
3058 clock1 = hdmi_mode->clock;
3059 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3060
3061 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3062 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
f2ecf2e3 3063 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode))
d9278b4c 3064 return vic;
3f2f6533
LD		 3065 }
3066 return 0;
3067}
3068
d9278b4c
JN		 3069static bool drm_valid_hdmi_vic(u8 vic)
3070{
3071 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3072}
3073
e6e79209
VS		 3074static int
3075add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
3076{
3077 struct drm_device *dev = connector->dev;
3078 struct drm_display_mode *mode, *tmp;
3079 LIST_HEAD(list);
3080 int modes = 0;
3081
3082 /* Don't add CEA modes if the CEA extension block is missing */
3083 if (!drm_find_cea_extension(edid))
3084 return 0;
3085
3086 /*
3087 * Go through all probed modes and create a new mode
3088 * with the alternate clock for certain CEA modes.
3089 */
3090 list_for_each_entry(mode, &connector->probed_modes, head) {
3f2f6533 3091 const struct drm_display_mode *cea_mode = NULL;
e6e79209 3092 struct drm_display_mode *newmode;
d9278b4c 3093 u8 vic = drm_match_cea_mode(mode);
e6e79209
VS		 3094 unsigned int clock1, clock2;
3095
d9278b4c
JN		 3096 if (drm_valid_cea_vic(vic)) {
3097 cea_mode = &edid_cea_modes[vic];
3f2f6533
LD		 3098 clock2 = cea_mode_alternate_clock(cea_mode);
3099 } else {
d9278b4c
JN		 3100 vic = drm_match_hdmi_mode(mode);
3101 if (drm_valid_hdmi_vic(vic)) {
3102 cea_mode = &edid_4k_modes[vic];
3f2f6533
LD		 3103 clock2 = hdmi_mode_alternate_clock(cea_mode);
3104 }
3105 }
e6e79209 3106
3f2f6533
LD		 3107 if (!cea_mode)
3108 continue;
e6e79209
VS		 3109
3110 clock1 = cea_mode->clock;
e6e79209
VS		 3111
3112 if (clock1 == clock2)
3113 continue;
3114
3115 if (mode->clock != clock1 && mode->clock != clock2)
3116 continue;
3117
3118 newmode = drm_mode_duplicate(dev, cea_mode);
3119 if (!newmode)
3120 continue;
3121
27130212
DL		 3122 /* Carry over the stereo flags */
3123 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3124
e6e79209
VS		 3125 /*
3126 * The current mode could be either variant. Make
3127 * sure to pick the "other" clock for the new mode.
3128 */
3129 if (mode->clock != clock1)
3130 newmode->clock = clock1;
3131 else
3132 newmode->clock = clock2;
3133
3134 list_add_tail(&newmode->head, &list);
3135 }
3136
3137 list_for_each_entry_safe(mode, tmp, &list, head) {
3138 list_del(&mode->head);
3139 drm_mode_probed_add(connector, mode);
3140 modes++;
3141 }
3142
3143 return modes;
3144}
a4799037 3145
8ec6e075
SS		 3146static u8 svd_to_vic(u8 svd)
3147{
3148 /* 0-6 bit vic, 7th bit native mode indicator */
3149 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
3150 return svd & 127;
3151
3152 return svd;
3153}
3154
aff04ace
TW		 3155static struct drm_display_mode *
3156drm_display_mode_from_vic_index(struct drm_connector *connector,
3157 const u8 *video_db, u8 video_len,
3158 u8 video_index)
54ac76f8
CS		 3159{
3160 struct drm_device *dev = connector->dev;
aff04ace 3161 struct drm_display_mode *newmode;
d9278b4c 3162 u8 vic;
54ac76f8 3163
aff04ace
TW		 3164 if (video_db == NULL || video_index >= video_len)
3165 return NULL;
3166
3167 /* CEA modes are numbered 1..127 */
8ec6e075 3168 vic = svd_to_vic(video_db[video_index]);
d9278b4c 3169 if (!drm_valid_cea_vic(vic))
aff04ace
TW		 3170 return NULL;
3171
d9278b4c 3172 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
409bbf1e
DL		 3173 if (!newmode)
3174 return NULL;
3175
aff04ace
TW		 3176 newmode->vrefresh = 0;
3177
3178 return newmode;
3179}
3180
832d4f2f
SS		 3181/*
3182 * do_y420vdb_modes - Parse YCBCR 420 only modes
3183 * @connector: connector corresponding to the HDMI sink
3184 * @svds: start of the data block of CEA YCBCR 420 VDB
3185 * @len: length of the CEA YCBCR 420 VDB
3186 *
3187 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3188 * which contains modes which can be supported in YCBCR 420
3189 * output format only.
3190 */
3191static int do_y420vdb_modes(struct drm_connector *connector,
3192 const u8 *svds, u8 svds_len)
3193{
3194 int modes = 0, i;
3195 struct drm_device *dev = connector->dev;
3196 struct drm_display_info *info = &connector->display_info;
3197 struct drm_hdmi_info *hdmi = &info->hdmi;
3198
3199 for (i = 0; i < svds_len; i++) {
3200 u8 vic = svd_to_vic(svds[i]);
3201 struct drm_display_mode *newmode;
3202
3203 if (!drm_valid_cea_vic(vic))
3204 continue;
3205
3206 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3207 if (!newmode)
3208 break;
3209 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3210 drm_mode_probed_add(connector, newmode);
3211 modes++;
3212 }
3213
3214 if (modes > 0)
3215 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3216 return modes;
3217}
3218
3219/*
3220 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3221 * @connector: connector corresponding to the HDMI sink
3222 * @vic: CEA vic for the video mode to be added in the map
3223 *
3224 * Makes an entry for a videomode in the YCBCR 420 bitmap
3225 */
3226static void
3227drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3228{
3229 u8 vic = svd_to_vic(svd);
3230 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3231
3232 if (!drm_valid_cea_vic(vic))
3233 return;
3234
3235 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3236}
3237
aff04ace
TW		 3238static int
3239do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3240{
3241 int i, modes = 0;
832d4f2f 3242 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
aff04ace
TW		 3243
3244 for (i = 0; i < len; i++) {
3245 struct drm_display_mode *mode;
3246 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3247 if (mode) {
832d4f2f
SS		 3248 /*
3249 * YCBCR420 capability block contains a bitmap which
3250 * gives the index of CEA modes from CEA VDB, which
3251 * can support YCBCR 420 sampling output also (apart
3252 * from RGB/YCBCR444 etc).
3253 * For example, if the bit 0 in bitmap is set,
3254 * first mode in VDB can support YCBCR420 output too.
3255 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3256 */
3257 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
3258 drm_add_cmdb_modes(connector, db[i]);
3259
aff04ace
TW		 3260 drm_mode_probed_add(connector, mode);
3261 modes++;
54ac76f8
CS		 3262 }
3263 }
3264
3265 return modes;
3266}
3267
c858cfca
DL		 3268struct stereo_mandatory_mode {
3269 int width, height, vrefresh;
3270 unsigned int flags;
3271};
3272
3273static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
f7e121b7
DL		 3274 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3275 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
c858cfca
DL		 3276 { 1920, 1080, 50,
3277 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3278 { 1920, 1080, 60,
3279 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
f7e121b7
DL		 3280 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3281 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3282 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3283 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
c858cfca
DL		 3284};
3285
3286static bool
3287stereo_match_mandatory(const struct drm_display_mode *mode,
3288 const struct stereo_mandatory_mode *stereo_mode)
3289{
3290 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3291
3292 return mode->hdisplay == stereo_mode->width &&
3293 mode->vdisplay == stereo_mode->height &&
3294 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3295 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3296}
3297
c858cfca
DL		 3298static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3299{
3300 struct drm_device *dev = connector->dev;
3301 const struct drm_display_mode *mode;
3302 struct list_head stereo_modes;
f7e121b7 3303 int modes = 0, i;
c858cfca
DL		 3304
3305 INIT_LIST_HEAD(&stereo_modes);
3306
3307 list_for_each_entry(mode, &connector->probed_modes, head) {
f7e121b7
DL		 3308 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3309 const struct stereo_mandatory_mode *mandatory;
c858cfca
DL		 3310 struct drm_display_mode *new_mode;
3311
f7e121b7
DL		 3312 if (!stereo_match_mandatory(mode,
3313 &stereo_mandatory_modes[i]))
3314 continue;
c858cfca 3315
f7e121b7 3316 mandatory = &stereo_mandatory_modes[i];
c858cfca
DL		 3317 new_mode = drm_mode_duplicate(dev, mode);
3318 if (!new_mode)
3319 continue;
3320
f7e121b7 3321 new_mode->flags |= mandatory->flags;
c858cfca
DL		 3322 list_add_tail(&new_mode->head, &stereo_modes);
3323 modes++;
f7e121b7 3324 }
c858cfca
DL		 3325 }
3326
3327 list_splice_tail(&stereo_modes, &connector->probed_modes);
3328
3329 return modes;
3330}
3331
1deee8d7
DL		 3332static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3333{
3334 struct drm_device *dev = connector->dev;
3335 struct drm_display_mode *newmode;
3336
d9278b4c 3337 if (!drm_valid_hdmi_vic(vic)) {
1deee8d7
DL		 3338 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3339 return 0;
3340 }
3341
3342 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3343 if (!newmode)
3344 return 0;
3345
3346 drm_mode_probed_add(connector, newmode);
3347
3348 return 1;
3349}
3350
fbf46025
TW		 3351static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3352 const u8 *video_db, u8 video_len, u8 video_index)
3353{
fbf46025
TW		 3354 struct drm_display_mode *newmode;
3355 int modes = 0;
fbf46025
TW		 3356
3357 if (structure & (1 << 0)) {
aff04ace
TW		 3358 newmode = drm_display_mode_from_vic_index(connector, video_db,
3359 video_len,
3360 video_index);
fbf46025
TW		 3361 if (newmode) {
3362 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3363 drm_mode_probed_add(connector, newmode);
3364 modes++;
3365 }
3366 }
3367 if (structure & (1 << 6)) {
aff04ace
TW		 3368 newmode = drm_display_mode_from_vic_index(connector, video_db,
3369 video_len,
3370 video_index);
fbf46025
TW		 3371 if (newmode) {
3372 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3373 drm_mode_probed_add(connector, newmode);
3374 modes++;
3375 }
3376 }
3377 if (structure & (1 << 8)) {
aff04ace
TW		 3378 newmode = drm_display_mode_from_vic_index(connector, video_db,
3379 video_len,
3380 video_index);
fbf46025 3381 if (newmode) {
89570eeb 3382 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
fbf46025
TW		 3383 drm_mode_probed_add(connector, newmode);
3384 modes++;
3385 }
3386 }
3387
3388 return modes;
3389}
3390
7ebe1963
LD		 3391/*
3392 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3393 * @connector: connector corresponding to the HDMI sink
3394 * @db: start of the CEA vendor specific block
3395 * @len: length of the CEA block payload, ie. one can access up to db[len]
3396 *
c858cfca
DL		 3397 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3398 * also adds the stereo 3d modes when applicable.
7ebe1963
LD		 3399 */
3400static int
fbf46025
TW		 3401do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3402 const u8 *video_db, u8 video_len)
7ebe1963 3403{
0e5083aa 3404 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
fbf46025
TW		 3405 u8 vic_len, hdmi_3d_len = 0;
3406 u16 mask;
3407 u16 structure_all;
7ebe1963
LD		 3408
3409 if (len < 8)
3410 goto out;
3411
3412 /* no HDMI_Video_Present */
3413 if (!(db[8] & (1 << 5)))
3414 goto out;
3415
3416 /* Latency_Fields_Present */
3417 if (db[8] & (1 << 7))
3418 offset += 2;
3419
3420 /* I_Latency_Fields_Present */
3421 if (db[8] & (1 << 6))
3422 offset += 2;
3423
3424 /* the declared length is not long enough for the 2 first bytes
3425 * of additional video format capabilities */
c858cfca 3426 if (len < (8 + offset + 2))
7ebe1963
LD		 3427 goto out;
3428
c858cfca
DL		 3429 /* 3D_Present */
3430 offset++;
fbf46025 3431 if (db[8 + offset] & (1 << 7)) {
c858cfca
DL		 3432 modes += add_hdmi_mandatory_stereo_modes(connector);
3433
fbf46025
TW		 3434 /* 3D_Multi_present */
3435 multi_present = (db[8 + offset] & 0x60) >> 5;
3436 }
3437
c858cfca 3438 offset++;
7ebe1963 3439 vic_len = db[8 + offset] >> 5;
fbf46025 3440 hdmi_3d_len = db[8 + offset] & 0x1f;
7ebe1963
LD		 3441
3442 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
7ebe1963
LD		 3443 u8 vic;
3444
3445 vic = db[9 + offset + i];
1deee8d7 3446 modes += add_hdmi_mode(connector, vic);
7ebe1963 3447 }
fbf46025
TW		 3448 offset += 1 + vic_len;
3449
0e5083aa
TW		 3450 if (multi_present == 1)
3451 multi_len = 2;
3452 else if (multi_present == 2)
3453 multi_len = 4;
3454 else
3455 multi_len = 0;
fbf46025 3456
0e5083aa 3457 if (len < (8 + offset + hdmi_3d_len - 1))
fbf46025
TW		 3458 goto out;
3459
0e5083aa 3460 if (hdmi_3d_len < multi_len)
fbf46025
TW		 3461 goto out;
3462
0e5083aa
TW		 3463 if (multi_present == 1 || multi_present == 2) {
3464 /* 3D_Structure_ALL */
3465 structure_all = (db[8 + offset] << 8) | db[9 + offset];
fbf46025 3466
0e5083aa
TW		 3467 /* check if 3D_MASK is present */
3468 if (multi_present == 2)
3469 mask = (db[10 + offset] << 8) | db[11 + offset];
3470 else
3471 mask = 0xffff;
3472
3473 for (i = 0; i < 16; i++) {
3474 if (mask & (1 << i))
3475 modes += add_3d_struct_modes(connector,
3476 structure_all,
3477 video_db,
3478 video_len, i);
3479 }
3480 }
3481
3482 offset += multi_len;
3483
3484 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3485 int vic_index;
3486 struct drm_display_mode *newmode = NULL;
3487 unsigned int newflag = 0;
3488 bool detail_present;
3489
3490 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3491
3492 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3493 break;
3494
3495 /* 2D_VIC_order_X */
3496 vic_index = db[8 + offset + i] >> 4;
3497
3498 /* 3D_Structure_X */
3499 switch (db[8 + offset + i] & 0x0f) {
3500 case 0:
3501 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3502 break;
3503 case 6:
3504 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3505 break;
3506 case 8:
3507 /* 3D_Detail_X */
3508 if ((db[9 + offset + i] >> 4) == 1)
3509 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3510 break;
3511 }
3512
3513 if (newflag != 0) {
3514 newmode = drm_display_mode_from_vic_index(connector,
3515 video_db,
3516 video_len,
3517 vic_index);
3518
3519 if (newmode) {
3520 newmode->flags |= newflag;
3521 drm_mode_probed_add(connector, newmode);
3522 modes++;
3523 }
3524 }
3525
3526 if (detail_present)
3527 i++;
fbf46025 3528 }
7ebe1963
LD		 3529
3530out:
3531 return modes;
3532}
3533
9e50b9d5
VS		 3534static int
3535cea_db_payload_len(const u8 *db)
3536{
3537 return db[0] & 0x1f;
3538}
3539
87563fc0
SS		 3540static int
3541cea_db_extended_tag(const u8 *db)
3542{
3543 return db[1];
3544}
3545
9e50b9d5
VS		 3546static int
3547cea_db_tag(const u8 *db)
3548{
3549 return db[0] >> 5;
3550}
3551
3552static int
3553cea_revision(const u8 *cea)
3554{
3555 return cea[1];
3556}
3557
3558static int
3559cea_db_offsets(const u8 *cea, int *start, int *end)
3560{
3561 /* Data block offset in CEA extension block */
3562 *start = 4;
3563 *end = cea[2];
3564 if (*end == 0)
3565 *end = 127;
3566 if (*end < 4 || *end > 127)
3567 return -ERANGE;
3568 return 0;
3569}
3570
7ebe1963
LD		 3571static bool cea_db_is_hdmi_vsdb(const u8 *db)
3572{
3573 int hdmi_id;
3574
3575 if (cea_db_tag(db) != VENDOR_BLOCK)
3576 return false;
3577
3578 if (cea_db_payload_len(db) < 5)
3579 return false;
3580
3581 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3582
6cb3b7f1 3583 return hdmi_id == HDMI_IEEE_OUI;
7ebe1963
LD		 3584}
3585
50dd1bd1
TR		 3586static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
3587{
3588 unsigned int oui;
3589
3590 if (cea_db_tag(db) != VENDOR_BLOCK)
3591 return false;
3592
3593 if (cea_db_payload_len(db) < 7)
3594 return false;
3595
3596 oui = db[3] << 16 | db[2] << 8 | db[1];
3597
3598 return oui == HDMI_FORUM_IEEE_OUI;
3599}
3600
832d4f2f
SS		 3601static bool cea_db_is_y420cmdb(const u8 *db)
3602{
3603 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3604 return false;
3605
3606 if (!cea_db_payload_len(db))
3607 return false;
3608
3609 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
3610 return false;
3611
3612 return true;
3613}
3614
3615static bool cea_db_is_y420vdb(const u8 *db)
3616{
3617 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3618 return false;
3619
3620 if (!cea_db_payload_len(db))
3621 return false;
3622
3623 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
3624 return false;
3625
3626 return true;
3627}
3628
9e50b9d5
VS		 3629#define for_each_cea_db(cea, i, start, end) \
3630 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3631
832d4f2f
SS		 3632static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
3633 const u8 *db)
3634{
3635 struct drm_display_info *info = &connector->display_info;
3636 struct drm_hdmi_info *hdmi = &info->hdmi;
3637 u8 map_len = cea_db_payload_len(db) - 1;
3638 u8 count;
3639 u64 map = 0;
3640
3641 if (map_len == 0) {
3642 /* All CEA modes support ycbcr420 sampling also.*/
3643 hdmi->y420_cmdb_map = U64_MAX;
3644 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3645 return;
3646 }
3647
3648 /*
3649 * This map indicates which of the existing CEA block modes
3650 * from VDB can support YCBCR420 output too. So if bit=0 is
3651 * set, first mode from VDB can support YCBCR420 output too.
3652 * We will parse and keep this map, before parsing VDB itself
3653 * to avoid going through the same block again and again.
3654 *
3655 * Spec is not clear about max possible size of this block.
3656 * Clamping max bitmap block size at 8 bytes. Every byte can
3657 * address 8 CEA modes, in this way this map can address
3658 * 8*8 = first 64 SVDs.
3659 */
3660 if (WARN_ON_ONCE(map_len > 8))
3661 map_len = 8;
3662
3663 for (count = 0; count < map_len; count++)
3664 map |= (u64)db[2 + count] << (8 * count);
3665
3666 if (map)
3667 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3668
3669 hdmi->y420_cmdb_map = map;
3670}
3671
54ac76f8
CS		 3672static int
3673add_cea_modes(struct drm_connector *connector, struct edid *edid)
3674{
13ac3f55 3675 const u8 *cea = drm_find_cea_extension(edid);
fbf46025
TW		 3676 const u8 *db, *hdmi = NULL, *video = NULL;
3677 u8 dbl, hdmi_len, video_len = 0;
54ac76f8
CS		 3678 int modes = 0;
3679
9e50b9d5
VS		 3680 if (cea && cea_revision(cea) >= 3) {
3681 int i, start, end;
3682
3683 if (cea_db_offsets(cea, &start, &end))
3684 return 0;
3685
3686 for_each_cea_db(cea, i, start, end) {
3687 db = &cea[i];
3688 dbl = cea_db_payload_len(db);
3689
fbf46025
TW		 3690 if (cea_db_tag(db) == VIDEO_BLOCK) {
3691 video = db + 1;
3692 video_len = dbl;
3693 modes += do_cea_modes(connector, video, dbl);
832d4f2f 3694 } else if (cea_db_is_hdmi_vsdb(db)) {
c858cfca
DL		 3695 hdmi = db;
3696 hdmi_len = dbl;
832d4f2f
SS		 3697 } else if (cea_db_is_y420vdb(db)) {
3698 const u8 *vdb420 = &db[2];
3699
3700 /* Add 4:2:0(only) modes present in EDID */
3701 modes += do_y420vdb_modes(connector,
3702 vdb420,
3703 dbl - 1);
c858cfca 3704 }
54ac76f8
CS		 3705 }
3706 }
3707
c858cfca
DL		 3708 /*
3709 * We parse the HDMI VSDB after having added the cea modes as we will
3710 * be patching their flags when the sink supports stereo 3D.
3711 */
3712 if (hdmi)
fbf46025
TW		 3713 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
3714 video_len);
c858cfca 3715
54ac76f8
CS		 3716 return modes;
3717}
3718
fa3a7340
VS		 3719static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
3720{
3721 const struct drm_display_mode *cea_mode;
3722 int clock1, clock2, clock;
d9278b4c 3723 u8 vic;
fa3a7340
VS		 3724 const char *type;
3725
4c6bcf44
VS		 3726 /*
3727 * allow 5kHz clock difference either way to account for
3728 * the 10kHz clock resolution limit of detailed timings.
3729 */
d9278b4c
JN		 3730 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
3731 if (drm_valid_cea_vic(vic)) {
fa3a7340 3732 type = "CEA";
d9278b4c 3733 cea_mode = &edid_cea_modes[vic];
fa3a7340
VS		 3734 clock1 = cea_mode->clock;
3735 clock2 = cea_mode_alternate_clock(cea_mode);
3736 } else {
d9278b4c
JN		 3737 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
3738 if (drm_valid_hdmi_vic(vic)) {
fa3a7340 3739 type = "HDMI";
d9278b4c 3740 cea_mode = &edid_4k_modes[vic];
fa3a7340
VS		 3741 clock1 = cea_mode->clock;
3742 clock2 = hdmi_mode_alternate_clock(cea_mode);
3743 } else {
3744 return;
3745 }
3746 }
3747
3748 /* pick whichever is closest */
3749 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
3750 clock = clock1;
3751 else
3752 clock = clock2;
3753
3754 if (mode->clock == clock)
3755 return;
3756
3757 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
d9278b4c 3758 type, vic, mode->clock, clock);
fa3a7340
VS		 3759 mode->clock = clock;
3760}
3761
76adaa34 3762static void
23ebf8b9 3763drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
76adaa34 3764{
8504072a 3765 u8 len = cea_db_payload_len(db);
76adaa34 3766
23ebf8b9 3767 if (len >= 6)
8504072a 3768 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */
8504072a
VS		 3769 if (len >= 8) {
3770 connector->latency_present[0] = db[8] >> 7;
3771 connector->latency_present[1] = (db[8] >> 6) & 1;
3772 }
3773 if (len >= 9)
3774 connector->video_latency[0] = db[9];
3775 if (len >= 10)
3776 connector->audio_latency[0] = db[10];
3777 if (len >= 11)
3778 connector->video_latency[1] = db[11];
3779 if (len >= 12)
3780 connector->audio_latency[1] = db[12];
76adaa34 3781
23ebf8b9
VS		 3782 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
3783 "video latency %d %d, "
3784 "audio latency %d %d\n",
3785 connector->latency_present[0],
3786 connector->latency_present[1],
3787 connector->video_latency[0],
3788 connector->video_latency[1],
3789 connector->audio_latency[0],
3790 connector->audio_latency[1]);
76adaa34
WF		 3791}
3792
3793static void
3794monitor_name(struct detailed_timing *t, void *data)
3795{
3796 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
3797 *(u8 **)data = t->data.other_data.data.str.str;
14f77fdd
VS		 3798}
3799
59f7c0fa
JB		 3800static int get_monitor_name(struct edid *edid, char name[13])
3801{
3802 char *edid_name = NULL;
3803 int mnl;
3804
3805 if (!edid || !name)
3806 return 0;
3807
3808 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
3809 for (mnl = 0; edid_name && mnl < 13; mnl++) {
3810 if (edid_name[mnl] == 0x0a)
3811 break;
3812
3813 name[mnl] = edid_name[mnl];
3814 }
3815
3816 return mnl;
3817}
3818
3819/**
3820 * drm_edid_get_monitor_name - fetch the monitor name from the edid
3821 * @edid: monitor EDID information
3822 * @name: pointer to a character array to hold the name of the monitor
3823 * @bufsize: The size of the name buffer (should be at least 14 chars.)
3824 *
3825 */
3826void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
3827{
3828 int name_length;
3829 char buf[13];
3830
3831 if (bufsize <= 0)
3832 return;
3833
3834 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
3835 memcpy(name, buf, name_length);
3836 name[name_length] = '\0';
3837}
3838EXPORT_SYMBOL(drm_edid_get_monitor_name);
3839
76adaa34
WF		 3840/**
3841 * drm_edid_to_eld - build ELD from EDID
3842 * @connector: connector corresponding to the HDMI/DP sink
3843 * @edid: EDID to parse
3844 *
db6cf833 3845 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
8deba626 3846 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
76adaa34
WF		 3847 */
3848void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
3849{
3850 uint8_t *eld = connector->eld;
3851 u8 *cea;
76adaa34 3852 u8 *db;
7c018782 3853 int total_sad_count = 0;
76adaa34
WF		 3854 int mnl;
3855 int dbl;
3856
3857 memset(eld, 0, sizeof(connector->eld));
3858
85c91580
VS		 3859 connector->latency_present[0] = false;
3860 connector->latency_present[1] = false;
3861 connector->video_latency[0] = 0;
3862 connector->audio_latency[0] = 0;
3863 connector->video_latency[1] = 0;
3864 connector->audio_latency[1] = 0;
3865
e9bd0b84
JN		 3866 if (!edid)
3867 return;
3868
76adaa34
WF		 3869 cea = drm_find_cea_extension(edid);
3870 if (!cea) {
3871 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
3872 return;
3873 }
3874
59f7c0fa
JB		 3875 mnl = get_monitor_name(edid, eld + 20);
3876
76adaa34
WF		 3877 eld[4] = (cea[1] << 5) | mnl;
3878 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20);
3879
3880 eld[0] = 2 << 3; /* ELD version: 2 */
3881
3882 eld[16] = edid->mfg_id[0];
3883 eld[17] = edid->mfg_id[1];
3884 eld[18] = edid->prod_code[0];
3885 eld[19] = edid->prod_code[1];
3886
9e50b9d5
VS		 3887 if (cea_revision(cea) >= 3) {
3888 int i, start, end;
3889
3890 if (cea_db_offsets(cea, &start, &end)) {
3891 start = 0;
3892 end = 0;
3893 }
3894
3895 for_each_cea_db(cea, i, start, end) {
3896 db = &cea[i];
3897 dbl = cea_db_payload_len(db);
3898
3899 switch (cea_db_tag(db)) {
7c018782
VS		 3900 int sad_count;
3901
a0ab734d
CS		 3902 case AUDIO_BLOCK:
3903 /* Audio Data Block, contains SADs */
7c018782
VS		 3904 sad_count = min(dbl / 3, 15 - total_sad_count);
3905 if (sad_count >= 1)
3906 memcpy(eld + 20 + mnl + total_sad_count * 3,
3907 &db[1], sad_count * 3);
3908 total_sad_count += sad_count;
a0ab734d
CS		 3909 break;
3910 case SPEAKER_BLOCK:
9e50b9d5
VS		 3911 /* Speaker Allocation Data Block */
3912 if (dbl >= 1)
3913 eld[7] = db[1];
a0ab734d
CS		 3914 break;
3915 case VENDOR_BLOCK:
3916 /* HDMI Vendor-Specific Data Block */
14f77fdd 3917 if (cea_db_is_hdmi_vsdb(db))
23ebf8b9 3918 drm_parse_hdmi_vsdb_audio(connector, db);
a0ab734d
CS		 3919 break;
3920 default:
3921 break;
3922 }
76adaa34 3923 }
9e50b9d5 3924 }
7c018782 3925 eld[5] |= total_sad_count << 4;
76adaa34 3926
8deba626
JN		 3927 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
3928 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3929 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
3930 else
3931 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
3932
938fd8aa
JN		 3933 eld[DRM_ELD_BASELINE_ELD_LEN] =
3934 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
3935
3936 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
7c018782 3937 drm_eld_size(eld), total_sad_count);
76adaa34
WF		 3938}
3939EXPORT_SYMBOL(drm_edid_to_eld);
3940
fe214163
RM		 3941/**
3942 * drm_edid_to_sad - extracts SADs from EDID
3943 * @edid: EDID to parse
3944 * @sads: pointer that will be set to the extracted SADs
3945 *
3946 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
fe214163 3947 *
db6cf833
TR		 3948 * Note: The returned pointer needs to be freed using kfree().
3949 *
3950 * Return: The number of found SADs or negative number on error.
fe214163
RM		 3951 */
3952int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
3953{
3954 int count = 0;
3955 int i, start, end, dbl;
3956 u8 *cea;
3957
3958 cea = drm_find_cea_extension(edid);
3959 if (!cea) {
3960 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3961 return -ENOENT;
3962 }
3963
3964 if (cea_revision(cea) < 3) {
3965 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3966 return -ENOTSUPP;
3967 }
3968
3969 if (cea_db_offsets(cea, &start, &end)) {
3970 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3971 return -EPROTO;
3972 }
3973
3974 for_each_cea_db(cea, i, start, end) {
3975 u8 *db = &cea[i];
3976
3977 if (cea_db_tag(db) == AUDIO_BLOCK) {
3978 int j;
3979 dbl = cea_db_payload_len(db);
3980
3981 count = dbl / 3; /* SAD is 3B */
3982 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
3983 if (!*sads)
3984 return -ENOMEM;
3985 for (j = 0; j < count; j++) {
3986 u8 *sad = &db[1 + j * 3];
3987
3988 (*sads)[j].format = (sad[0] & 0x78) >> 3;
3989 (*sads)[j].channels = sad[0] & 0x7;
3990 (*sads)[j].freq = sad[1] & 0x7F;
3991 (*sads)[j].byte2 = sad[2];
3992 }
3993 break;
3994 }
3995 }
3996
3997 return count;
3998}
3999EXPORT_SYMBOL(drm_edid_to_sad);
4000
d105f476
AD		 4001/**
4002 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
4003 * @edid: EDID to parse
4004 * @sadb: pointer to the speaker block
4005 *
4006 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
d105f476 4007 *
db6cf833
TR		 4008 * Note: The returned pointer needs to be freed using kfree().
4009 *
4010 * Return: The number of found Speaker Allocation Blocks or negative number on
4011 * error.
d105f476
AD		 4012 */
4013int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
4014{
4015 int count = 0;
4016 int i, start, end, dbl;
4017 const u8 *cea;
4018
4019 cea = drm_find_cea_extension(edid);
4020 if (!cea) {
4021 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4022 return -ENOENT;
4023 }
4024
4025 if (cea_revision(cea) < 3) {
4026 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4027 return -ENOTSUPP;
4028 }
4029
4030 if (cea_db_offsets(cea, &start, &end)) {
4031 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4032 return -EPROTO;
4033 }
4034
4035 for_each_cea_db(cea, i, start, end) {
4036 const u8 *db = &cea[i];
4037
4038 if (cea_db_tag(db) == SPEAKER_BLOCK) {
4039 dbl = cea_db_payload_len(db);
4040
4041 /* Speaker Allocation Data Block */
4042 if (dbl == 3) {
89086bca 4043 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
618e3776
AD		 4044 if (!*sadb)
4045 return -ENOMEM;
d105f476
AD		 4046 count = dbl;
4047 break;
4048 }
4049 }
4050 }
4051
4052 return count;
4053}
4054EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4055
76adaa34 4056/**
db6cf833 4057 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
76adaa34
WF		 4058 * @connector: connector associated with the HDMI/DP sink
4059 * @mode: the display mode
db6cf833
TR		 4060 *
4061 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4062 * the sink doesn't support audio or video.
76adaa34
WF		 4063 */
4064int drm_av_sync_delay(struct drm_connector *connector,
3a818d35 4065 const struct drm_display_mode *mode)
76adaa34
WF		 4066{
4067 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4068 int a, v;
4069
4070 if (!connector->latency_present[0])
4071 return 0;
4072 if (!connector->latency_present[1])
4073 i = 0;
4074
4075 a = connector->audio_latency[i];
4076 v = connector->video_latency[i];
4077
4078 /*
4079 * HDMI/DP sink doesn't support audio or video?
4080 */
4081 if (a == 255 || v == 255)
4082 return 0;
4083
4084 /*
4085 * Convert raw EDID values to millisecond.
4086 * Treat unknown latency as 0ms.
4087 */
4088 if (a)
4089 a = min(2 * (a - 1), 500);
4090 if (v)
4091 v = min(2 * (v - 1), 500);
4092
4093 return max(v - a, 0);
4094}
4095EXPORT_SYMBOL(drm_av_sync_delay);
4096
8fe9790d 4097/**
db6cf833 4098 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
8fe9790d
ZW		 4099 * @edid: monitor EDID information
4100 *
4101 * Parse the CEA extension according to CEA-861-B.
db6cf833
TR		 4102 *
4103 * Return: True if the monitor is HDMI, false if not or unknown.
8fe9790d
ZW		 4104 */
4105bool drm_detect_hdmi_monitor(struct edid *edid)
4106{
4107 u8 *edid_ext;
14f77fdd 4108 int i;
8fe9790d 4109 int start_offset, end_offset;
8fe9790d
ZW		 4110
4111 edid_ext = drm_find_cea_extension(edid);
4112 if (!edid_ext)
14f77fdd 4113 return false;
f23c20c8 4114
9e50b9d5 4115 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
14f77fdd 4116 return false;
f23c20c8
ML		 4117
4118 /*
4119 * Because HDMI identifier is in Vendor Specific Block,
4120 * search it from all data blocks of CEA extension.
4121 */
9e50b9d5 4122 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
14f77fdd
VS		 4123 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
4124 return true;
f23c20c8
ML		 4125 }
4126
14f77fdd 4127 return false;
f23c20c8
ML		 4128}
4129EXPORT_SYMBOL(drm_detect_hdmi_monitor);
4130
8fe9790d
ZW		 4131/**
4132 * drm_detect_monitor_audio - check monitor audio capability
fc66811c 4133 * @edid: EDID block to scan
8fe9790d
ZW		 4134 *
4135 * Monitor should have CEA extension block.
4136 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
4137 * audio' only. If there is any audio extension block and supported
4138 * audio format, assume at least 'basic audio' support, even if 'basic
4139 * audio' is not defined in EDID.
4140 *
db6cf833 4141 * Return: True if the monitor supports audio, false otherwise.
8fe9790d
ZW		 4142 */
4143bool drm_detect_monitor_audio(struct edid *edid)
4144{
4145 u8 *edid_ext;
4146 int i, j;
4147 bool has_audio = false;
4148 int start_offset, end_offset;
4149
4150 edid_ext = drm_find_cea_extension(edid);
4151 if (!edid_ext)
4152 goto end;
4153
4154 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
4155
4156 if (has_audio) {
4157 DRM_DEBUG_KMS("Monitor has basic audio support\n");
4158 goto end;
4159 }
4160
9e50b9d5
VS		 4161 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4162 goto end;
8fe9790d 4163
9e50b9d5
VS		 4164 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4165 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
8fe9790d 4166 has_audio = true;
9e50b9d5 4167 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
8fe9790d
ZW		 4168 DRM_DEBUG_KMS("CEA audio format %d\n",
4169 (edid_ext[i + j] >> 3) & 0xf);
4170 goto end;
4171 }
4172 }
4173end:
4174 return has_audio;
4175}
4176EXPORT_SYMBOL(drm_detect_monitor_audio);
4177
b1edd6a6
VS		 4178/**
4179 * drm_rgb_quant_range_selectable - is RGB quantization range selectable?
fc66811c 4180 * @edid: EDID block to scan
b1edd6a6
VS		 4181 *
4182 * Check whether the monitor reports the RGB quantization range selection
4183 * as supported. The AVI infoframe can then be used to inform the monitor
4184 * which quantization range (full or limited) is used.
db6cf833
TR		 4185 *
4186 * Return: True if the RGB quantization range is selectable, false otherwise.
b1edd6a6
VS		 4187 */
4188bool drm_rgb_quant_range_selectable(struct edid *edid)
4189{
4190 u8 *edid_ext;
4191 int i, start, end;
4192
4193 edid_ext = drm_find_cea_extension(edid);
4194 if (!edid_ext)
4195 return false;
4196
4197 if (cea_db_offsets(edid_ext, &start, &end))
4198 return false;
4199
4200 for_each_cea_db(edid_ext, i, start, end) {
87563fc0
SS		 4201 if (cea_db_tag(&edid_ext[i]) == USE_EXTENDED_TAG &&
4202 cea_db_payload_len(&edid_ext[i]) == 2 &&
4203 cea_db_extended_tag(&edid_ext[i]) ==
4204 EXT_VIDEO_CAPABILITY_BLOCK) {
b1edd6a6
VS		 4205 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]);
4206 return edid_ext[i + 2] & EDID_CEA_VCDB_QS;
4207 }
4208 }
4209
4210 return false;
4211}
4212EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
4213
c8127cf0
VS		 4214/**
4215 * drm_default_rgb_quant_range - default RGB quantization range
4216 * @mode: display mode
4217 *
4218 * Determine the default RGB quantization range for the mode,
4219 * as specified in CEA-861.
4220 *
4221 * Return: The default RGB quantization range for the mode
4222 */
4223enum hdmi_quantization_range
4224drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4225{
4226 /* All CEA modes other than VIC 1 use limited quantization range. */
4227 return drm_match_cea_mode(mode) > 1 ?
4228 HDMI_QUANTIZATION_RANGE_LIMITED :
4229 HDMI_QUANTIZATION_RANGE_FULL;
4230}
4231EXPORT_SYMBOL(drm_default_rgb_quant_range);
4232
e6a9a2c3
SS		 4233static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
4234 const u8 *db)
4235{
4236 u8 dc_mask;
4237 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4238
4239 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
4240 hdmi->y420_dc_modes |= dc_mask;
4241}
4242
afa1c763
SS		 4243static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
4244 const u8 *hf_vsdb)
4245{
62c58af3
SS		 4246 struct drm_display_info *display = &connector->display_info;
4247 struct drm_hdmi_info *hdmi = &display->hdmi;
afa1c763
SS		 4248
4249 if (hf_vsdb[6] & 0x80) {
4250 hdmi->scdc.supported = true;
4251 if (hf_vsdb[6] & 0x40)
4252 hdmi->scdc.read_request = true;
4253 }
62c58af3
SS		 4254
4255 /*
4256 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
4257 * And as per the spec, three factors confirm this:
4258 * * Availability of a HF-VSDB block in EDID (check)
4259 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
4260 * * SCDC support available (let's check)
4261 * Lets check it out.
4262 */
4263
4264 if (hf_vsdb[5]) {
4265 /* max clock is 5000 KHz times block value */
4266 u32 max_tmds_clock = hf_vsdb[5] * 5000;
4267 struct drm_scdc *scdc = &hdmi->scdc;
4268
4269 if (max_tmds_clock > 340000) {
4270 display->max_tmds_clock = max_tmds_clock;
4271 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4272 display->max_tmds_clock);
4273 }
4274
4275 if (scdc->supported) {
4276 scdc->scrambling.supported = true;
4277
4278 /* Few sinks support scrambling for cloks < 340M */
4279 if ((hf_vsdb[6] & 0x8))
4280 scdc->scrambling.low_rates = true;
4281 }
4282 }
e6a9a2c3
SS		 4283
4284 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
afa1c763
SS		 4285}
4286
1cea146a
VS		 4287static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
4288 const u8 *hdmi)
d0c94692 4289{
1826750f 4290 struct drm_display_info *info = &connector->display_info;
d0c94692
MK		 4291 unsigned int dc_bpc = 0;
4292
1cea146a
VS		 4293 /* HDMI supports at least 8 bpc */
4294 info->bpc = 8;
d0c94692 4295
1cea146a
VS		 4296 if (cea_db_payload_len(hdmi) < 6)
4297 return;
4298
4299 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
4300 dc_bpc = 10;
4301 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
4302 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
4303 connector->name);
4304 }
4305
4306 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
4307 dc_bpc = 12;
4308 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
4309 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
4310 connector->name);
4311 }
4312
4313 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
4314 dc_bpc = 16;
4315 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
4316 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
4317 connector->name);
4318 }
4319
4320 if (dc_bpc == 0) {
4321 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
4322 connector->name);
4323 return;
4324 }
4325
4326 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
4327 connector->name, dc_bpc);
4328 info->bpc = dc_bpc;
d0c94692
MK		 4329
4330 /*
1cea146a
VS		 4331 * Deep color support mandates RGB444 support for all video
4332 * modes and forbids YCRCB422 support for all video modes per
4333 * HDMI 1.3 spec.
d0c94692 4334 */
1cea146a 4335 info->color_formats = DRM_COLOR_FORMAT_RGB444;
d0c94692 4336
1cea146a
VS		 4337 /* YCRCB444 is optional according to spec. */
4338 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4339 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4340 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
4341 connector->name);
4342 }
d0c94692 4343
1cea146a
VS		 4344 /*
4345 * Spec says that if any deep color mode is supported at all,
4346 * then deep color 36 bit must be supported.
4347 */
4348 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
4349 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
4350 connector->name);
4351 }
4352}
d0c94692 4353
23ebf8b9
VS		 4354static void
4355drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
4356{
4357 struct drm_display_info *info = &connector->display_info;
4358 u8 len = cea_db_payload_len(db);
4359
4360 if (len >= 6)
4361 info->dvi_dual = db[6] & 1;
4362 if (len >= 7)
4363 info->max_tmds_clock = db[7] * 5000;
4364
4365 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
4366 "max TMDS clock %d kHz\n",
4367 info->dvi_dual,
4368 info->max_tmds_clock);
4369
4370 drm_parse_hdmi_deep_color_info(connector, db);
4371}
4372
1cea146a 4373static void drm_parse_cea_ext(struct drm_connector *connector,
4b4df570 4374 const struct edid *edid)
1cea146a
VS		 4375{
4376 struct drm_display_info *info = &connector->display_info;
4377 const u8 *edid_ext;
4378 int i, start, end;
d0c94692 4379
1cea146a
VS		 4380 edid_ext = drm_find_cea_extension(edid);
4381 if (!edid_ext)
4382 return;
d0c94692 4383
1cea146a 4384 info->cea_rev = edid_ext[1];
d0c94692 4385
1cea146a
VS		 4386 /* The existence of a CEA block should imply RGB support */
4387 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4388 if (edid_ext[3] & EDID_CEA_YCRCB444)
4389 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4390 if (edid_ext[3] & EDID_CEA_YCRCB422)
4391 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4392
4393 if (cea_db_offsets(edid_ext, &start, &end))
4394 return;
4395
4396 for_each_cea_db(edid_ext, i, start, end) {
4397 const u8 *db = &edid_ext[i];
4398
23ebf8b9
VS		 4399 if (cea_db_is_hdmi_vsdb(db))
4400 drm_parse_hdmi_vsdb_video(connector, db);
afa1c763
SS		 4401 if (cea_db_is_hdmi_forum_vsdb(db))
4402 drm_parse_hdmi_forum_vsdb(connector, db);
832d4f2f
SS		 4403 if (cea_db_is_y420cmdb(db))
4404 drm_parse_y420cmdb_bitmap(connector, db);
1cea146a 4405 }
d0c94692
MK		 4406}
4407
4b4df570
KP		 4408/* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
4409 * all of the values which would have been set from EDID
4410 */
4411void
4412drm_reset_display_info(struct drm_connector *connector)
3b11228b 4413{
1826750f 4414 struct drm_display_info *info = &connector->display_info;
ebec9a7b 4415
4b4df570
KP		 4416 info->width_mm = 0;
4417 info->height_mm = 0;
4418
4419 info->bpc = 0;
4420 info->color_formats = 0;
4421 info->cea_rev = 0;
4422 info->max_tmds_clock = 0;
4423 info->dvi_dual = false;
d82e1ce7 4424 memset(&info->hdmi, 0, sizeof(info->hdmi));
4b4df570
KP		 4425
4426 info->non_desktop = 0;
4427}
4428EXPORT_SYMBOL_GPL(drm_reset_display_info);
4429
4430u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
4431{
4432 struct drm_display_info *info = &connector->display_info;
4433
4434 u32 quirks = edid_get_quirks(edid);
4435
d82e1ce7
VS		 4436 drm_reset_display_info(connector);
4437
3b11228b
JB		 4438 info->width_mm = edid->width_cm * 10;
4439 info->height_mm = edid->height_cm * 10;
4440
66660d4c
DA		 4441 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
4442
4b4df570
KP		 4443 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
4444
a988bc72 4445 if (edid->revision < 3)
4b4df570 4446 return quirks;
3b11228b
JB		 4447
4448 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
4b4df570 4449 return quirks;
3b11228b 4450
1cea146a 4451 drm_parse_cea_ext(connector, edid);
d0c94692 4452
210a021d
MK		 4453 /*
4454 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
4455 *
4456 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
4457 * tells us to assume 8 bpc color depth if the EDID doesn't have
4458 * extensions which tell otherwise.
4459 */
4460 if ((info->bpc == 0) && (edid->revision < 4) &&
4461 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) {
4462 info->bpc = 8;
4463 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
4464 connector->name, info->bpc);
4465 }
4466
a988bc72
LPC		 4467 /* Only defined for 1.4 with digital displays */
4468 if (edid->revision < 4)
4b4df570 4469 return quirks;
a988bc72 4470
3b11228b
JB		 4471 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
4472 case DRM_EDID_DIGITAL_DEPTH_6:
4473 info->bpc = 6;
4474 break;
4475 case DRM_EDID_DIGITAL_DEPTH_8:
4476 info->bpc = 8;
4477 break;
4478 case DRM_EDID_DIGITAL_DEPTH_10:
4479 info->bpc = 10;
4480 break;
4481 case DRM_EDID_DIGITAL_DEPTH_12:
4482 info->bpc = 12;
4483 break;
4484 case DRM_EDID_DIGITAL_DEPTH_14:
4485 info->bpc = 14;
4486 break;
4487 case DRM_EDID_DIGITAL_DEPTH_16:
4488 info->bpc = 16;
4489 break;
4490 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
4491 default:
4492 info->bpc = 0;
4493 break;
4494 }
da05a5a7 4495
d0c94692 4496 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
25933820 4497 connector->name, info->bpc);
d0c94692 4498
a988bc72 4499 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
ee58808d
LPC		 4500 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
4501 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4502 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
4503 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4b4df570 4504 return quirks;
3b11228b 4505}
4b4df570 4506EXPORT_SYMBOL_GPL(drm_add_display_info);
3b11228b 4507
c9729177
DA		 4508static int validate_displayid(u8 *displayid, int length, int idx)
4509{
4510 int i;
4511 u8 csum = 0;
4512 struct displayid_hdr *base;
4513
4514 base = (struct displayid_hdr *)&displayid[idx];
4515
4516 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
4517 base->rev, base->bytes, base->prod_id, base->ext_count);
4518
4519 if (base->bytes + 5 > length - idx)
4520 return -EINVAL;
4521 for (i = idx; i <= base->bytes + 5; i++) {
4522 csum += displayid[i];
4523 }
4524 if (csum) {
813a7878 4525 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum);
c9729177
DA		 4526 return -EINVAL;
4527 }
4528 return 0;
4529}
4530
a39ed680
DA		 4531static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
4532 struct displayid_detailed_timings_1 *timings)
4533{
4534 struct drm_display_mode *mode;
4535 unsigned pixel_clock = (timings->pixel_clock[0] |
4536 (timings->pixel_clock[1] << 8) |
4537 (timings->pixel_clock[2] << 16));
4538 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
4539 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
4540 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
4541 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
4542 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
4543 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
4544 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
4545 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
4546 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
4547 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
4548 mode = drm_mode_create(dev);
4549 if (!mode)
4550 return NULL;
4551
4552 mode->clock = pixel_clock * 10;
4553 mode->hdisplay = hactive;
4554 mode->hsync_start = mode->hdisplay + hsync;
4555 mode->hsync_end = mode->hsync_start + hsync_width;
4556 mode->htotal = mode->hdisplay + hblank;
4557
4558 mode->vdisplay = vactive;
4559 mode->vsync_start = mode->vdisplay + vsync;
4560 mode->vsync_end = mode->vsync_start + vsync_width;
4561 mode->vtotal = mode->vdisplay + vblank;
4562
4563 mode->flags = 0;
4564 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4565 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4566 mode->type = DRM_MODE_TYPE_DRIVER;
4567
4568 if (timings->flags & 0x80)
4569 mode->type |= DRM_MODE_TYPE_PREFERRED;
4570 mode->vrefresh = drm_mode_vrefresh(mode);
4571 drm_mode_set_name(mode);
4572
4573 return mode;
4574}
4575
4576static int add_displayid_detailed_1_modes(struct drm_connector *connector,
4577 struct displayid_block *block)
4578{
4579 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
4580 int i;
4581 int num_timings;
4582 struct drm_display_mode *newmode;
4583 int num_modes = 0;
4584 /* blocks must be multiple of 20 bytes length */
4585 if (block->num_bytes % 20)
4586 return 0;
4587
4588 num_timings = block->num_bytes / 20;
4589 for (i = 0; i < num_timings; i++) {
4590 struct displayid_detailed_timings_1 *timings = &det->timings[i];
4591
4592 newmode = drm_mode_displayid_detailed(connector->dev, timings);
4593 if (!newmode)
4594 continue;
4595
4596 drm_mode_probed_add(connector, newmode);
4597 num_modes++;
4598 }
4599 return num_modes;
4600}
4601
4602static int add_displayid_detailed_modes(struct drm_connector *connector,
4603 struct edid *edid)
4604{
4605 u8 *displayid;
4606 int ret;
4607 int idx = 1;
4608 int length = EDID_LENGTH;
4609 struct displayid_block *block;
4610 int num_modes = 0;
4611
4612 displayid = drm_find_displayid_extension(edid);
4613 if (!displayid)
4614 return 0;
4615
4616 ret = validate_displayid(displayid, length, idx);
4617 if (ret)
4618 return 0;
4619
4620 idx += sizeof(struct displayid_hdr);
4621 while (block = (struct displayid_block *)&displayid[idx],
4622 idx + sizeof(struct displayid_block) <= length &&
4623 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
4624 block->num_bytes > 0) {
4625 idx += block->num_bytes + sizeof(struct displayid_block);
4626 switch (block->tag) {
4627 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4628 num_modes += add_displayid_detailed_1_modes(connector, block);
4629 break;
4630 }
4631 }
4632 return num_modes;
4633}
4634
f453ba04
DA		 4635/**
4636 * drm_add_edid_modes - add modes from EDID data, if available
4637 * @connector: connector we're probing
db6cf833 4638 * @edid: EDID data
f453ba04 4639 *
b3c6c8bf
DV		 4640 * Add the specified modes to the connector's mode list. Also fills out the
4641 * &drm_display_info structure in @connector with any information which can be
4642 * derived from the edid.
f453ba04 4643 *
db6cf833 4644 * Return: The number of modes added or 0 if we couldn't find any.
f453ba04
DA		 4645 */
4646int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
4647{
4648 int num_modes = 0;
4649 u32 quirks;
4650
4651 if (edid == NULL) {
4652 return 0;
4653 }
3c537889 4654 if (!drm_edid_is_valid(edid)) {
dcdb1674 4655 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
25933820 4656 connector->name);
f453ba04
DA		 4657 return 0;
4658 }
4659
0f0f8708
SS		 4660 /*
4661 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
4662 * To avoid multiple parsing of same block, lets parse that map
4663 * from sink info, before parsing CEA modes.
4664 */
4b4df570 4665 quirks = drm_add_display_info(connector, edid);
0f0f8708 4666
c867df70
AJ		 4667 /*
4668 * EDID spec says modes should be preferred in this order:
4669 * - preferred detailed mode
4670 * - other detailed modes from base block
4671 * - detailed modes from extension blocks
4672 * - CVT 3-byte code modes
4673 * - standard timing codes
4674 * - established timing codes
4675 * - modes inferred from GTF or CVT range information
4676 *
13931579 4677 * We get this pretty much right.
c867df70
AJ		 4678 *
4679 * XXX order for additional mode types in extension blocks?
4680 */
13931579
AJ		 4681 num_modes += add_detailed_modes(connector, edid, quirks);
4682 num_modes += add_cvt_modes(connector, edid);
c867df70
AJ		 4683 num_modes += add_standard_modes(connector, edid);
4684 num_modes += add_established_modes(connector, edid);
54ac76f8 4685 num_modes += add_cea_modes(connector, edid);
e6e79209 4686 num_modes += add_alternate_cea_modes(connector, edid);
a39ed680 4687 num_modes += add_displayid_detailed_modes(connector, edid);
4d53dc0c
VS		 4688 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
4689 num_modes += add_inferred_modes(connector, edid);
f453ba04
DA		 4690
4691 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
4692 edid_fixup_preferred(connector, quirks);
4693
e10aec65
MK		 4694 if (quirks & EDID_QUIRK_FORCE_6BPC)
4695 connector->display_info.bpc = 6;
4696
49d45a31
RM		 4697 if (quirks & EDID_QUIRK_FORCE_8BPC)
4698 connector->display_info.bpc = 8;
4699
e345da82
MK		 4700 if (quirks & EDID_QUIRK_FORCE_10BPC)
4701 connector->display_info.bpc = 10;
4702
bc5b9641
MK		 4703 if (quirks & EDID_QUIRK_FORCE_12BPC)
4704 connector->display_info.bpc = 12;
4705
f453ba04
DA		 4706 return num_modes;
4707}
4708EXPORT_SYMBOL(drm_add_edid_modes);
f0fda0a4
ZY		 4709
4710/**
4711 * drm_add_modes_noedid - add modes for the connectors without EDID
4712 * @connector: connector we're probing
4713 * @hdisplay: the horizontal display limit
4714 * @vdisplay: the vertical display limit
4715 *
4716 * Add the specified modes to the connector's mode list. Only when the
4717 * hdisplay/vdisplay is not beyond the given limit, it will be added.
4718 *
db6cf833 4719 * Return: The number of modes added or 0 if we couldn't find any.
f0fda0a4
ZY		 4720 */
4721int drm_add_modes_noedid(struct drm_connector *connector,
4722 int hdisplay, int vdisplay)
4723{
4724 int i, count, num_modes = 0;
b1f559ec 4725 struct drm_display_mode *mode;
f0fda0a4
ZY		 4726 struct drm_device *dev = connector->dev;
4727
fbb40b28 4728 count = ARRAY_SIZE(drm_dmt_modes);
f0fda0a4
ZY		 4729 if (hdisplay < 0)
4730 hdisplay = 0;
4731 if (vdisplay < 0)
4732 vdisplay = 0;
4733
4734 for (i = 0; i < count; i++) {
b1f559ec 4735 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
f0fda0a4
ZY		 4736 if (hdisplay && vdisplay) {
4737 /*
4738 * Only when two are valid, they will be used to check
4739 * whether the mode should be added to the mode list of
4740 * the connector.
4741 */
4742 if (ptr->hdisplay > hdisplay ||
4743 ptr->vdisplay > vdisplay)
4744 continue;
4745 }
f985dedb
AJ		 4746 if (drm_mode_vrefresh(ptr) > 61)
4747 continue;
f0fda0a4
ZY		 4748 mode = drm_mode_duplicate(dev, ptr);
4749 if (mode) {
4750 drm_mode_probed_add(connector, mode);
4751 num_modes++;
4752 }
4753 }
4754 return num_modes;
4755}
4756EXPORT_SYMBOL(drm_add_modes_noedid);
10a85120 4757
db6cf833
TR		 4758/**
4759 * drm_set_preferred_mode - Sets the preferred mode of a connector
4760 * @connector: connector whose mode list should be processed
4761 * @hpref: horizontal resolution of preferred mode
4762 * @vpref: vertical resolution of preferred mode
4763 *
4764 * Marks a mode as preferred if it matches the resolution specified by @hpref
4765 * and @vpref.
4766 */
3cf70daf
GH		 4767void drm_set_preferred_mode(struct drm_connector *connector,
4768 int hpref, int vpref)
4769{
4770 struct drm_display_mode *mode;
4771
4772 list_for_each_entry(mode, &connector->probed_modes, head) {
db6cf833 4773 if (mode->hdisplay == hpref &&
9d3de138 4774 mode->vdisplay == vpref)
3cf70daf
GH		 4775 mode->type |= DRM_MODE_TYPE_PREFERRED;
4776 }
4777}
4778EXPORT_SYMBOL(drm_set_preferred_mode);
4779
10a85120
TR		 4780/**
4781 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
4782 * data from a DRM display mode
4783 * @frame: HDMI AVI infoframe
4784 * @mode: DRM display mode
0c1f528c 4785 * @is_hdmi2_sink: Sink is HDMI 2.0 compliant
10a85120 4786 *
db6cf833 4787 * Return: 0 on success or a negative error code on failure.
10a85120
TR		 4788 */
4789int
4790drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
0c1f528c
SS		 4791 const struct drm_display_mode *mode,
4792 bool is_hdmi2_sink)
10a85120
TR		 4793{
4794 int err;
4795
4796 if (!frame || !mode)
4797 return -EINVAL;
4798
4799 err = hdmi_avi_infoframe_init(frame);
4800 if (err < 0)
4801 return err;
4802
bf02db99
DL		 4803 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
4804 frame->pixel_repeat = 1;
4805
10a85120 4806 frame->video_code = drm_match_cea_mode(mode);
10a85120 4807
0c1f528c
SS		 4808 /*
4809 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
4810 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
4811 * have to make sure we dont break HDMI 1.4 sinks.
4812 */
4813 if (!is_hdmi2_sink && frame->video_code > 64)
4814 frame->video_code = 0;
4815
4816 /*
4817 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
4818 * we should send its VIC in vendor infoframes, else send the
4819 * VIC in AVI infoframes. Lets check if this mode is present in
4820 * HDMI 1.4b 4K modes
4821 */
4822 if (frame->video_code) {
4823 u8 vendor_if_vic = drm_match_hdmi_mode(mode);
4824 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK;
4825
4826 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d)
4827 frame->video_code = 0;
4828 }
4829
10a85120 4830 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
0967e6a5 4831
69ab6d35
VK		 4832 /*
4833 * Populate picture aspect ratio from either
4834 * user input (if specified) or from the CEA mode list.
4835 */
4836 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 ||
4837 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9)
4838 frame->picture_aspect = mode->picture_aspect_ratio;
4839 else if (frame->video_code > 0)
0967e6a5
VK		 4840 frame->picture_aspect = drm_get_cea_aspect_ratio(
4841 frame->video_code);
4842
10a85120 4843 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
24d01805 4844 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
10a85120
TR		 4845
4846 return 0;
4847}
4848EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
83dd0008 4849
a2ce26f8
VS		 4850/**
4851 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
4852 * quantization range information
4853 * @frame: HDMI AVI infoframe
779c4c28 4854 * @mode: DRM display mode
a2ce26f8
VS		 4855 * @rgb_quant_range: RGB quantization range (Q)
4856 * @rgb_quant_range_selectable: Sink support selectable RGB quantization range (QS)
4857 */
4858void
4859drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
779c4c28 4860 const struct drm_display_mode *mode,
a2ce26f8 4861 enum hdmi_quantization_range rgb_quant_range,
9271c0ca
VS		 4862 bool rgb_quant_range_selectable,
4863 bool is_hdmi2_sink)
a2ce26f8
VS		 4864{
4865 /*
4866 * CEA-861:
4867 * "A Source shall not send a non-zero Q value that does not correspond
4868 * to the default RGB Quantization Range for the transmitted Picture
4869 * unless the Sink indicates support for the Q bit in a Video
4870 * Capabilities Data Block."
779c4c28
VS		 4871 *
4872 * HDMI 2.0 recommends sending non-zero Q when it does match the
4873 * default RGB quantization range for the mode, even when QS=0.
a2ce26f8 4874 */
779c4c28
VS		 4875 if (rgb_quant_range_selectable ||
4876 rgb_quant_range == drm_default_rgb_quant_range(mode))
a2ce26f8
VS		 4877 frame->quantization_range = rgb_quant_range;
4878 else
4879 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
fcc8a22c
VS		 4880
4881 /*
4882 * CEA-861-F:
4883 * "When transmitting any RGB colorimetry, the Source should set the
4884 * YQ-field to match the RGB Quantization Range being transmitted
4885 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
4886 * set YQ=1) and the Sink shall ignore the YQ-field."
9271c0ca
VS		 4887 *
4888 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
4889 * by non-zero YQ when receiving RGB. There doesn't seem to be any
4890 * good way to tell which version of CEA-861 the sink supports, so
4891 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
4892 * on on CEA-861-F.
fcc8a22c 4893 */
9271c0ca
VS		 4894 if (!is_hdmi2_sink ||
4895 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
fcc8a22c
VS		 4896 frame->ycc_quantization_range =
4897 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
4898 else
4899 frame->ycc_quantization_range =
4900 HDMI_YCC_QUANTIZATION_RANGE_FULL;
a2ce26f8
VS		 4901}
4902EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
4903
4eed4a0a
DL		 4904static enum hdmi_3d_structure
4905s3d_structure_from_display_mode(const struct drm_display_mode *mode)
4906{
4907 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
4908
4909 switch (layout) {
4910 case DRM_MODE_FLAG_3D_FRAME_PACKING:
4911 return HDMI_3D_STRUCTURE_FRAME_PACKING;
4912 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
4913 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
4914 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
4915 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
4916 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
4917 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
4918 case DRM_MODE_FLAG_3D_L_DEPTH:
4919 return HDMI_3D_STRUCTURE_L_DEPTH;
4920 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
4921 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
4922 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
4923 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
4924 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
4925 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
4926 default:
4927 return HDMI_3D_STRUCTURE_INVALID;
4928 }
4929}
4930
83dd0008
LD		 4931/**
4932 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
4933 * data from a DRM display mode
4934 * @frame: HDMI vendor infoframe
4935 * @mode: DRM display mode
4936 *
4937 * Note that there's is a need to send HDMI vendor infoframes only when using a
4938 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
4939 * function will return -EINVAL, error that can be safely ignored.
4940 *
db6cf833 4941 * Return: 0 on success or a negative error code on failure.
83dd0008
LD		 4942 */
4943int
4944drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
4945 const struct drm_display_mode *mode)
4946{
4947 int err;
4eed4a0a 4948 u32 s3d_flags;
83dd0008
LD		 4949 u8 vic;
4950
4951 if (!frame || !mode)
4952 return -EINVAL;
4953
4954 vic = drm_match_hdmi_mode(mode);
4eed4a0a
DL		 4955 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
4956
4957 if (!vic && !s3d_flags)
4958 return -EINVAL;
4959
4960 if (vic && s3d_flags)
83dd0008
LD		 4961 return -EINVAL;
4962
4963 err = hdmi_vendor_infoframe_init(frame);
4964 if (err < 0)
4965 return err;
4966
4eed4a0a
DL		 4967 if (vic)
4968 frame->vic = vic;
4969 else
4970 frame->s3d_struct = s3d_structure_from_display_mode(mode);
83dd0008
LD		 4971
4972 return 0;
4973}
4974EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
40d9b043 4975
5e546cd5
DA		 4976static int drm_parse_tiled_block(struct drm_connector *connector,
4977 struct displayid_block *block)
4978{
4979 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
4980 u16 w, h;
4981 u8 tile_v_loc, tile_h_loc;
4982 u8 num_v_tile, num_h_tile;
4983 struct drm_tile_group *tg;
4984
4985 w = tile->tile_size[0] | tile->tile_size[1] << 8;
4986 h = tile->tile_size[2] | tile->tile_size[3] << 8;
4987
4988 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
4989 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
4990 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
4991 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
4992
4993 connector->has_tile = true;
4994 if (tile->tile_cap & 0x80)
4995 connector->tile_is_single_monitor = true;
4996
4997 connector->num_h_tile = num_h_tile + 1;
4998 connector->num_v_tile = num_v_tile + 1;
4999 connector->tile_h_loc = tile_h_loc;
5000 connector->tile_v_loc = tile_v_loc;
5001 connector->tile_h_size = w + 1;
5002 connector->tile_v_size = h + 1;
5003
5004 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
5005 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
5006 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
5007 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
5008 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
5009
5010 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
5011 if (!tg) {
5012 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5013 }
5014 if (!tg)
5015 return -ENOMEM;
5016
5017 if (connector->tile_group != tg) {
5018 /* if we haven't got a pointer,
5019 take the reference, drop ref to old tile group */
5020 if (connector->tile_group) {
5021 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5022 }
5023 connector->tile_group = tg;
5024 } else
5025 /* if same tile group, then release the ref we just took. */
5026 drm_mode_put_tile_group(connector->dev, tg);
5027 return 0;
5028}
5029
40d9b043
DA		 5030static int drm_parse_display_id(struct drm_connector *connector,
5031 u8 *displayid, int length,
5032 bool is_edid_extension)
5033{
5034 /* if this is an EDID extension the first byte will be 0x70 */
5035 int idx = 0;
40d9b043 5036 struct displayid_block *block;
5e546cd5 5037 int ret;
40d9b043
DA		 5038
5039 if (is_edid_extension)
5040 idx = 1;
5041
c9729177
DA		 5042 ret = validate_displayid(displayid, length, idx);
5043 if (ret)
5044 return ret;
40d9b043 5045
3a4a2ea3
TB		 5046 idx += sizeof(struct displayid_hdr);
5047 while (block = (struct displayid_block *)&displayid[idx],
5048 idx + sizeof(struct displayid_block) <= length &&
5049 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
5050 block->num_bytes > 0) {
5051 idx += block->num_bytes + sizeof(struct displayid_block);
5052 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
5053 block->tag, block->rev, block->num_bytes);
5054
5055 switch (block->tag) {
5056 case DATA_BLOCK_TILED_DISPLAY:
5057 ret = drm_parse_tiled_block(connector, block);
5058 if (ret)
5059 return ret;
5060 break;
a39ed680
DA		 5061 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
5062 /* handled in mode gathering code. */
5063 break;
3a4a2ea3
TB		 5064 default:
5065 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
5066 break;
5067 }
40d9b043
DA		 5068 }
5069 return 0;
5070}
5071
5072static void drm_get_displayid(struct drm_connector *connector,
5073 struct edid *edid)
5074{
5075 void *displayid = NULL;
5076 int ret;
5077 connector->has_tile = false;
5078 displayid = drm_find_displayid_extension(edid);
5079 if (!displayid) {
5080 /* drop reference to any tile group we had */
5081 goto out_drop_ref;
5082 }
5083
5084 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
5085 if (ret < 0)
5086 goto out_drop_ref;
5087 if (!connector->has_tile)
5088 goto out_drop_ref;
5089 return;
5090out_drop_ref:
5091 if (connector->tile_group) {
5092 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5093 connector->tile_group = NULL;
5094 }
5095 return;
5096}
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