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drm: fsl-dcu: use vblank hooks in struct drm_crtc_funcs
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / drm_edid.c
CommitLineData
f453ba04
DA		 1/*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
61e57a8d 5 * Copyright 2010 Red Hat, Inc.
f453ba04
DA		 6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30#include <linux/kernel.h>
5a0e3ad6 31#include <linux/slab.h>
10a85120 32#include <linux/hdmi.h>
f453ba04 33#include <linux/i2c.h>
47819ba2 34#include <linux/module.h>
5cb8eaa2 35#include <linux/vga_switcheroo.h>
760285e7
DH		 36#include <drm/drmP.h>
37#include <drm/drm_edid.h>
9338203c 38#include <drm/drm_encoder.h>
40d9b043 39#include <drm/drm_displayid.h>
f453ba04 40
969218fe
TI		 41#include "drm_crtc_internal.h"
42
13931579
AJ		 43#define version_greater(edid, maj, min) \
44 (((edid)->version > (maj)) || \
45 ((edid)->version == (maj) && (edid)->revision > (min)))
f453ba04 46
d1ff6409
AJ		 47#define EDID_EST_TIMINGS 16
48#define EDID_STD_TIMINGS 8
49#define EDID_DETAILED_TIMINGS 4
f453ba04
DA		 50
51/*
52 * EDID blocks out in the wild have a variety of bugs, try to collect
53 * them here (note that userspace may work around broken monitors first,
54 * but fixes should make their way here so that the kernel "just works"
55 * on as many displays as possible).
56 */
57
58/* First detailed mode wrong, use largest 60Hz mode */
59#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
60/* Reported 135MHz pixel clock is too high, needs adjustment */
61#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
62/* Prefer the largest mode at 75 Hz */
63#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
64/* Detail timing is in cm not mm */
65#define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
66/* Detailed timing descriptors have bogus size values, so just take the
67 * maximum size and use that.
68 */
69#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
70/* Monitor forgot to set the first detailed is preferred bit. */
71#define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
72/* use +hsync +vsync for detailed mode */
73#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
bc42aabc
AJ		 74/* Force reduced-blanking timings for detailed modes */
75#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
49d45a31
RM		 76/* Force 8bpc */
77#define EDID_QUIRK_FORCE_8BPC (1 << 8)
bc5b9641
MK		 78/* Force 12bpc */
79#define EDID_QUIRK_FORCE_12BPC (1 << 9)
e10aec65
MK		 80/* Force 6bpc */
81#define EDID_QUIRK_FORCE_6BPC (1 << 10)
3c537889 82
13931579
AJ		 83struct detailed_mode_closure {
84 struct drm_connector *connector;
85 struct edid *edid;
86 bool preferred;
87 u32 quirks;
88 int modes;
89};
f453ba04 90
5c61259e
ZY		 91#define LEVEL_DMT 0
92#define LEVEL_GTF 1
7a374350
AJ		 93#define LEVEL_GTF2 2
94#define LEVEL_CVT 3
5c61259e 95
23c4cfbd 96static const struct edid_quirk {
c51a3fd6 97 char vendor[4];
f453ba04
DA		 98 int product_id;
99 u32 quirks;
100} edid_quirk_list[] = {
101 /* Acer AL1706 */
102 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
103 /* Acer F51 */
104 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
105 /* Unknown Acer */
106 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
107
e10aec65
MK		 108 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
109 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
110
f453ba04
DA		 111 /* Belinea 10 15 55 */
112 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
113 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
114
115 /* Envision Peripherals, Inc. EN-7100e */
116 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
ba1163de
AJ		 117 /* Envision EN2028 */
118 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
f453ba04
DA		 119
120 /* Funai Electronics PM36B */
121 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
122 EDID_QUIRK_DETAILED_IN_CM },
123
124 /* LG Philips LCD LP154W01-A5 */
125 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
126 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
127
128 /* Philips 107p5 CRT */
129 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
130
131 /* Proview AY765C */
132 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
133
134 /* Samsung SyncMaster 205BW. Note: irony */
135 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
136 /* Samsung SyncMaster 22[5-6]BW */
137 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
138 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
bc42aabc 139
bc5b9641
MK		 140 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
141 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
142
bc42aabc
AJ		 143 /* ViewSonic VA2026w */
144 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
118bdbd8
AD		 145
146 /* Medion MD 30217 PG */
147 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
49d45a31
RM		 148
149 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
150 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
f453ba04
DA		 151};
152
a6b21831
TR		 153/*
154 * Autogenerated from the DMT spec.
155 * This table is copied from xfree86/modes/xf86EdidModes.c.
156 */
157static const struct drm_display_mode drm_dmt_modes[] = {
24b856b1 158 /* 0x01 - 640x350@85Hz */
a6b21831
TR		 159 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
160 736, 832, 0, 350, 382, 385, 445, 0,
161 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 162 /* 0x02 - 640x400@85Hz */
a6b21831
TR		 163 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
164 736, 832, 0, 400, 401, 404, 445, 0,
165 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 166 /* 0x03 - 720x400@85Hz */
a6b21831
TR		 167 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
168 828, 936, 0, 400, 401, 404, 446, 0,
169 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 170 /* 0x04 - 640x480@60Hz */
a6b21831 171 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
fcf22d05 172 752, 800, 0, 480, 490, 492, 525, 0,
a6b21831 173 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 174 /* 0x05 - 640x480@72Hz */
a6b21831
TR		 175 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
176 704, 832, 0, 480, 489, 492, 520, 0,
177 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 178 /* 0x06 - 640x480@75Hz */
a6b21831
TR		 179 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
180 720, 840, 0, 480, 481, 484, 500, 0,
181 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 182 /* 0x07 - 640x480@85Hz */
a6b21831
TR		 183 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
184 752, 832, 0, 480, 481, 484, 509, 0,
185 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 186 /* 0x08 - 800x600@56Hz */
a6b21831
TR		 187 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
188 896, 1024, 0, 600, 601, 603, 625, 0,
189 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 190 /* 0x09 - 800x600@60Hz */
a6b21831
TR		 191 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
192 968, 1056, 0, 600, 601, 605, 628, 0,
193 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 194 /* 0x0a - 800x600@72Hz */
a6b21831
TR		 195 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
196 976, 1040, 0, 600, 637, 643, 666, 0,
197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 198 /* 0x0b - 800x600@75Hz */
a6b21831
TR		 199 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
200 896, 1056, 0, 600, 601, 604, 625, 0,
201 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 202 /* 0x0c - 800x600@85Hz */
a6b21831
TR		 203 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
204 896, 1048, 0, 600, 601, 604, 631, 0,
205 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 206 /* 0x0d - 800x600@120Hz RB */
a6b21831
TR		 207 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
208 880, 960, 0, 600, 603, 607, 636, 0,
209 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 210 /* 0x0e - 848x480@60Hz */
a6b21831
TR		 211 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
212 976, 1088, 0, 480, 486, 494, 517, 0,
213 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 214 /* 0x0f - 1024x768@43Hz, interlace */
a6b21831 215 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
735b100f 216 1208, 1264, 0, 768, 768, 776, 817, 0,
a6b21831 217 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
fcf22d05 218 DRM_MODE_FLAG_INTERLACE) },
24b856b1 219 /* 0x10 - 1024x768@60Hz */
a6b21831
TR		 220 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
221 1184, 1344, 0, 768, 771, 777, 806, 0,
222 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 223 /* 0x11 - 1024x768@70Hz */
a6b21831
TR		 224 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
225 1184, 1328, 0, 768, 771, 777, 806, 0,
226 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 227 /* 0x12 - 1024x768@75Hz */
a6b21831
TR		 228 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
229 1136, 1312, 0, 768, 769, 772, 800, 0,
230 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 231 /* 0x13 - 1024x768@85Hz */
a6b21831
TR		 232 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
233 1168, 1376, 0, 768, 769, 772, 808, 0,
234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 235 /* 0x14 - 1024x768@120Hz RB */
a6b21831
TR		 236 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
237 1104, 1184, 0, 768, 771, 775, 813, 0,
238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 239 /* 0x15 - 1152x864@75Hz */
a6b21831
TR		 240 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
241 1344, 1600, 0, 864, 865, 868, 900, 0,
242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
bfcd74d2
VS		 243 /* 0x55 - 1280x720@60Hz */
244 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
245 1430, 1650, 0, 720, 725, 730, 750, 0,
246 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 247 /* 0x16 - 1280x768@60Hz RB */
a6b21831
TR		 248 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
249 1360, 1440, 0, 768, 771, 778, 790, 0,
250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 251 /* 0x17 - 1280x768@60Hz */
a6b21831
TR		 252 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
253 1472, 1664, 0, 768, 771, 778, 798, 0,
254 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 255 /* 0x18 - 1280x768@75Hz */
a6b21831
TR		 256 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
257 1488, 1696, 0, 768, 771, 778, 805, 0,
fcf22d05 258 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 259 /* 0x19 - 1280x768@85Hz */
a6b21831
TR		 260 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
261 1496, 1712, 0, 768, 771, 778, 809, 0,
262 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 263 /* 0x1a - 1280x768@120Hz RB */
a6b21831
TR		 264 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
265 1360, 1440, 0, 768, 771, 778, 813, 0,
266 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 267 /* 0x1b - 1280x800@60Hz RB */
a6b21831
TR		 268 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
269 1360, 1440, 0, 800, 803, 809, 823, 0,
270 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 271 /* 0x1c - 1280x800@60Hz */
a6b21831
TR		 272 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
273 1480, 1680, 0, 800, 803, 809, 831, 0,
fcf22d05 274 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 275 /* 0x1d - 1280x800@75Hz */
a6b21831
TR		 276 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
277 1488, 1696, 0, 800, 803, 809, 838, 0,
278 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 279 /* 0x1e - 1280x800@85Hz */
a6b21831
TR		 280 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
281 1496, 1712, 0, 800, 803, 809, 843, 0,
282 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 283 /* 0x1f - 1280x800@120Hz RB */
a6b21831
TR		 284 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
285 1360, 1440, 0, 800, 803, 809, 847, 0,
286 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 287 /* 0x20 - 1280x960@60Hz */
a6b21831
TR		 288 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
289 1488, 1800, 0, 960, 961, 964, 1000, 0,
290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 291 /* 0x21 - 1280x960@85Hz */
a6b21831
TR		 292 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
293 1504, 1728, 0, 960, 961, 964, 1011, 0,
294 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 295 /* 0x22 - 1280x960@120Hz RB */
a6b21831
TR		 296 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
297 1360, 1440, 0, 960, 963, 967, 1017, 0,
298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 299 /* 0x23 - 1280x1024@60Hz */
a6b21831
TR		 300 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
301 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 303 /* 0x24 - 1280x1024@75Hz */
a6b21831
TR		 304 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
305 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
306 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 307 /* 0x25 - 1280x1024@85Hz */
a6b21831
TR		 308 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
309 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 311 /* 0x26 - 1280x1024@120Hz RB */
a6b21831
TR		 312 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
313 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
314 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 315 /* 0x27 - 1360x768@60Hz */
a6b21831
TR		 316 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
317 1536, 1792, 0, 768, 771, 777, 795, 0,
318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 319 /* 0x28 - 1360x768@120Hz RB */
a6b21831
TR		 320 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
321 1440, 1520, 0, 768, 771, 776, 813, 0,
322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 323 /* 0x51 - 1366x768@60Hz */
324 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
325 1579, 1792, 0, 768, 771, 774, 798, 0,
326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
327 /* 0x56 - 1366x768@60Hz */
328 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
329 1436, 1500, 0, 768, 769, 772, 800, 0,
330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 331 /* 0x29 - 1400x1050@60Hz RB */
a6b21831
TR		 332 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
333 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
334 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 335 /* 0x2a - 1400x1050@60Hz */
a6b21831
TR		 336 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
337 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
338 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 339 /* 0x2b - 1400x1050@75Hz */
a6b21831
TR		 340 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
341 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
342 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 343 /* 0x2c - 1400x1050@85Hz */
a6b21831
TR		 344 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
345 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
346 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 347 /* 0x2d - 1400x1050@120Hz RB */
a6b21831
TR		 348 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
349 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 351 /* 0x2e - 1440x900@60Hz RB */
a6b21831
TR		 352 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
353 1520, 1600, 0, 900, 903, 909, 926, 0,
354 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 355 /* 0x2f - 1440x900@60Hz */
a6b21831
TR		 356 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
357 1672, 1904, 0, 900, 903, 909, 934, 0,
358 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 359 /* 0x30 - 1440x900@75Hz */
a6b21831
TR		 360 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
361 1688, 1936, 0, 900, 903, 909, 942, 0,
362 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 363 /* 0x31 - 1440x900@85Hz */
a6b21831
TR		 364 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
365 1696, 1952, 0, 900, 903, 909, 948, 0,
366 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 367 /* 0x32 - 1440x900@120Hz RB */
a6b21831
TR		 368 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
369 1520, 1600, 0, 900, 903, 909, 953, 0,
370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 371 /* 0x53 - 1600x900@60Hz */
372 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
373 1704, 1800, 0, 900, 901, 904, 1000, 0,
374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 375 /* 0x33 - 1600x1200@60Hz */
a6b21831
TR		 376 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
377 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 379 /* 0x34 - 1600x1200@65Hz */
a6b21831
TR		 380 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
381 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
382 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 383 /* 0x35 - 1600x1200@70Hz */
a6b21831
TR		 384 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
385 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
386 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 387 /* 0x36 - 1600x1200@75Hz */
a6b21831
TR		 388 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
389 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 391 /* 0x37 - 1600x1200@85Hz */
a6b21831
TR		 392 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
393 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
394 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 395 /* 0x38 - 1600x1200@120Hz RB */
a6b21831
TR		 396 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
397 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 399 /* 0x39 - 1680x1050@60Hz RB */
a6b21831
TR		 400 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
401 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
402 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 403 /* 0x3a - 1680x1050@60Hz */
a6b21831
TR		 404 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
405 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
406 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 407 /* 0x3b - 1680x1050@75Hz */
a6b21831
TR		 408 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
409 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
410 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 411 /* 0x3c - 1680x1050@85Hz */
a6b21831
TR		 412 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
413 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
414 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 415 /* 0x3d - 1680x1050@120Hz RB */
a6b21831
TR		 416 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
417 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
418 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 419 /* 0x3e - 1792x1344@60Hz */
a6b21831
TR		 420 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
421 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
422 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 423 /* 0x3f - 1792x1344@75Hz */
a6b21831
TR		 424 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
425 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
426 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 427 /* 0x40 - 1792x1344@120Hz RB */
a6b21831
TR		 428 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
429 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
430 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 431 /* 0x41 - 1856x1392@60Hz */
a6b21831
TR		 432 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
433 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
434 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 435 /* 0x42 - 1856x1392@75Hz */
a6b21831 436 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
fcf22d05 437 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
a6b21831 438 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 439 /* 0x43 - 1856x1392@120Hz RB */
a6b21831
TR		 440 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
441 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
442 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 443 /* 0x52 - 1920x1080@60Hz */
444 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
445 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
446 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 447 /* 0x44 - 1920x1200@60Hz RB */
a6b21831
TR		 448 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
449 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
450 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 451 /* 0x45 - 1920x1200@60Hz */
a6b21831
TR		 452 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
453 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
454 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 455 /* 0x46 - 1920x1200@75Hz */
a6b21831
TR		 456 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
457 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
458 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 459 /* 0x47 - 1920x1200@85Hz */
a6b21831
TR		 460 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
461 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
462 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 463 /* 0x48 - 1920x1200@120Hz RB */
a6b21831
TR		 464 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
465 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 467 /* 0x49 - 1920x1440@60Hz */
a6b21831
TR		 468 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
469 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
470 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 471 /* 0x4a - 1920x1440@75Hz */
a6b21831
TR		 472 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
473 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
474 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 475 /* 0x4b - 1920x1440@120Hz RB */
a6b21831
TR		 476 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
477 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 479 /* 0x54 - 2048x1152@60Hz */
480 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
481 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
482 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 483 /* 0x4c - 2560x1600@60Hz RB */
a6b21831
TR		 484 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
485 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
24b856b1 487 /* 0x4d - 2560x1600@60Hz */
a6b21831
TR		 488 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
489 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
490 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 491 /* 0x4e - 2560x1600@75Hz */
a6b21831
TR		 492 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
493 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
494 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 495 /* 0x4f - 2560x1600@85Hz */
a6b21831
TR		 496 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
497 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
498 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
24b856b1 499 /* 0x50 - 2560x1600@120Hz RB */
a6b21831
TR		 500 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
501 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
502 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
bfcd74d2
VS		 503 /* 0x57 - 4096x2160@60Hz RB */
504 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
505 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
506 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
507 /* 0x58 - 4096x2160@59.94Hz RB */
508 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
509 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
a6b21831
TR		 511};
512
e7bfa5c4
VS		 513/*
514 * These more or less come from the DMT spec. The 720x400 modes are
515 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
516 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
517 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
518 * mode.
519 *
520 * The DMT modes have been fact-checked; the rest are mild guesses.
521 */
a6b21831
TR		 522static const struct drm_display_mode edid_est_modes[] = {
523 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
524 968, 1056, 0, 600, 601, 605, 628, 0,
525 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
526 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
527 896, 1024, 0, 600, 601, 603, 625, 0,
528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
529 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
530 720, 840, 0, 480, 481, 484, 500, 0,
531 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
532 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
87707cfd 533 704, 832, 0, 480, 489, 492, 520, 0,
a6b21831
TR		 534 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
535 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
536 768, 864, 0, 480, 483, 486, 525, 0,
537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
87707cfd 538 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
a6b21831
TR		 539 752, 800, 0, 480, 490, 492, 525, 0,
540 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
541 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
542 846, 900, 0, 400, 421, 423, 449, 0,
543 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
544 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
545 846, 900, 0, 400, 412, 414, 449, 0,
546 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
547 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
548 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
87707cfd 550 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
a6b21831
TR		 551 1136, 1312, 0, 768, 769, 772, 800, 0,
552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
553 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
554 1184, 1328, 0, 768, 771, 777, 806, 0,
555 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
556 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
557 1184, 1344, 0, 768, 771, 777, 806, 0,
558 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
559 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
560 1208, 1264, 0, 768, 768, 776, 817, 0,
561 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
562 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
563 928, 1152, 0, 624, 625, 628, 667, 0,
564 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
565 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
566 896, 1056, 0, 600, 601, 604, 625, 0,
567 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
568 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
569 976, 1040, 0, 600, 637, 643, 666, 0,
570 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
571 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
572 1344, 1600, 0, 864, 865, 868, 900, 0,
573 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
574};
575
576struct minimode {
577 short w;
578 short h;
579 short r;
580 short rb;
581};
582
583static const struct minimode est3_modes[] = {
584 /* byte 6 */
585 { 640, 350, 85, 0 },
586 { 640, 400, 85, 0 },
587 { 720, 400, 85, 0 },
588 { 640, 480, 85, 0 },
589 { 848, 480, 60, 0 },
590 { 800, 600, 85, 0 },
591 { 1024, 768, 85, 0 },
592 { 1152, 864, 75, 0 },
593 /* byte 7 */
594 { 1280, 768, 60, 1 },
595 { 1280, 768, 60, 0 },
596 { 1280, 768, 75, 0 },
597 { 1280, 768, 85, 0 },
598 { 1280, 960, 60, 0 },
599 { 1280, 960, 85, 0 },
600 { 1280, 1024, 60, 0 },
601 { 1280, 1024, 85, 0 },
602 /* byte 8 */
603 { 1360, 768, 60, 0 },
604 { 1440, 900, 60, 1 },
605 { 1440, 900, 60, 0 },
606 { 1440, 900, 75, 0 },
607 { 1440, 900, 85, 0 },
608 { 1400, 1050, 60, 1 },
609 { 1400, 1050, 60, 0 },
610 { 1400, 1050, 75, 0 },
611 /* byte 9 */
612 { 1400, 1050, 85, 0 },
613 { 1680, 1050, 60, 1 },
614 { 1680, 1050, 60, 0 },
615 { 1680, 1050, 75, 0 },
616 { 1680, 1050, 85, 0 },
617 { 1600, 1200, 60, 0 },
618 { 1600, 1200, 65, 0 },
619 { 1600, 1200, 70, 0 },
620 /* byte 10 */
621 { 1600, 1200, 75, 0 },
622 { 1600, 1200, 85, 0 },
623 { 1792, 1344, 60, 0 },
c068b32a 624 { 1792, 1344, 75, 0 },
a6b21831
TR		 625 { 1856, 1392, 60, 0 },
626 { 1856, 1392, 75, 0 },
627 { 1920, 1200, 60, 1 },
628 { 1920, 1200, 60, 0 },
629 /* byte 11 */
630 { 1920, 1200, 75, 0 },
631 { 1920, 1200, 85, 0 },
632 { 1920, 1440, 60, 0 },
633 { 1920, 1440, 75, 0 },
634};
635
636static const struct minimode extra_modes[] = {
637 { 1024, 576, 60, 0 },
638 { 1366, 768, 60, 0 },
639 { 1600, 900, 60, 0 },
640 { 1680, 945, 60, 0 },
641 { 1920, 1080, 60, 0 },
642 { 2048, 1152, 60, 0 },
643 { 2048, 1536, 60, 0 },
644};
645
646/*
647 * Probably taken from CEA-861 spec.
648 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
d9278b4c
JN		 649 *
650 * Index using the VIC.
a6b21831
TR		 651 */
652static const struct drm_display_mode edid_cea_modes[] = {
d9278b4c
JN		 653 /* 0 - dummy, VICs start at 1 */
654 { },
a6b21831
TR		 655 /* 1 - 640x480@60Hz */
656 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
657 752, 800, 0, 480, 490, 492, 525, 0,
ee7925bb 658 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 659 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 660 /* 2 - 720x480@60Hz */
661 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
662 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 663 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 664 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 665 /* 3 - 720x480@60Hz */
666 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
667 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 668 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 669 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 670 /* 4 - 1280x720@60Hz */
671 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
672 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 673 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 674 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 675 /* 5 - 1920x1080i@60Hz */
676 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
677 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
678 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
ee7925bb 679 DRM_MODE_FLAG_INTERLACE),
985e5dc2 680 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 681 /* 6 - 720(1440)x480i@60Hz */
682 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
683 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 684 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 685 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 686 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 687 /* 7 - 720(1440)x480i@60Hz */
688 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
689 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 690 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 691 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 692 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 693 /* 8 - 720(1440)x240@60Hz */
694 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
695 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 696 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 697 DRM_MODE_FLAG_DBLCLK),
985e5dc2 698 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 699 /* 9 - 720(1440)x240@60Hz */
700 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
701 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 702 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 703 DRM_MODE_FLAG_DBLCLK),
985e5dc2 704 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 705 /* 10 - 2880x480i@60Hz */
706 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
707 3204, 3432, 0, 480, 488, 494, 525, 0,
708 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 709 DRM_MODE_FLAG_INTERLACE),
985e5dc2 710 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 711 /* 11 - 2880x480i@60Hz */
712 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
713 3204, 3432, 0, 480, 488, 494, 525, 0,
714 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 715 DRM_MODE_FLAG_INTERLACE),
985e5dc2 716 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 717 /* 12 - 2880x240@60Hz */
718 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
719 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 720 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 721 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 722 /* 13 - 2880x240@60Hz */
723 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
724 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 725 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 726 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 727 /* 14 - 1440x480@60Hz */
728 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
729 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 730 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 731 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 732 /* 15 - 1440x480@60Hz */
733 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
734 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 735 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 736 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 737 /* 16 - 1920x1080@60Hz */
738 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
739 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 740 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 741 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 742 /* 17 - 720x576@50Hz */
743 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
744 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 745 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 746 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 747 /* 18 - 720x576@50Hz */
748 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
749 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 750 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 751 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 752 /* 19 - 1280x720@50Hz */
753 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
754 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 755 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 756 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 757 /* 20 - 1920x1080i@50Hz */
758 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
759 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
760 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
ee7925bb 761 DRM_MODE_FLAG_INTERLACE),
985e5dc2 762 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 763 /* 21 - 720(1440)x576i@50Hz */
764 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
765 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 766 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 767 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 768 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 769 /* 22 - 720(1440)x576i@50Hz */
770 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
771 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 772 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 773 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 774 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 775 /* 23 - 720(1440)x288@50Hz */
776 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
777 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 778 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 779 DRM_MODE_FLAG_DBLCLK),
985e5dc2 780 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 781 /* 24 - 720(1440)x288@50Hz */
782 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
783 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 784 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 785 DRM_MODE_FLAG_DBLCLK),
985e5dc2 786 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 787 /* 25 - 2880x576i@50Hz */
788 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
789 3180, 3456, 0, 576, 580, 586, 625, 0,
790 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 791 DRM_MODE_FLAG_INTERLACE),
985e5dc2 792 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 793 /* 26 - 2880x576i@50Hz */
794 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
795 3180, 3456, 0, 576, 580, 586, 625, 0,
796 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 797 DRM_MODE_FLAG_INTERLACE),
985e5dc2 798 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 799 /* 27 - 2880x288@50Hz */
800 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
801 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 802 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 803 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 804 /* 28 - 2880x288@50Hz */
805 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
806 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 807 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 808 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 809 /* 29 - 1440x576@50Hz */
810 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
811 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 812 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 813 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 814 /* 30 - 1440x576@50Hz */
815 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
816 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 817 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 818 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 819 /* 31 - 1920x1080@50Hz */
820 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
821 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 822 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 823 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 824 /* 32 - 1920x1080@24Hz */
825 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
826 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 827 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 828 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 829 /* 33 - 1920x1080@25Hz */
830 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
831 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 832 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 833 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 834 /* 34 - 1920x1080@30Hz */
835 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
836 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 837 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 838 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 839 /* 35 - 2880x480@60Hz */
840 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
841 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 842 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 843 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 844 /* 36 - 2880x480@60Hz */
845 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
846 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 847 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 848 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 849 /* 37 - 2880x576@50Hz */
850 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
851 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 852 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 853 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 854 /* 38 - 2880x576@50Hz */
855 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
856 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 857 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 858 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 859 /* 39 - 1920x1080i@50Hz */
860 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
861 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
862 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 863 DRM_MODE_FLAG_INTERLACE),
985e5dc2 864 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 865 /* 40 - 1920x1080i@100Hz */
866 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
867 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
868 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
ee7925bb 869 DRM_MODE_FLAG_INTERLACE),
985e5dc2 870 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 871 /* 41 - 1280x720@100Hz */
872 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
873 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 874 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 875 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 876 /* 42 - 720x576@100Hz */
877 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
878 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 879 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 880 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 881 /* 43 - 720x576@100Hz */
882 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
883 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 884 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 885 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 886 /* 44 - 720(1440)x576i@100Hz */
887 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
888 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 889 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
5a11f7f8 890 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 891 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 892 /* 45 - 720(1440)x576i@100Hz */
893 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
894 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 895 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
5a11f7f8 896 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 897 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 898 /* 46 - 1920x1080i@120Hz */
899 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
900 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
901 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
ee7925bb 902 DRM_MODE_FLAG_INTERLACE),
985e5dc2 903 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 904 /* 47 - 1280x720@120Hz */
905 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
906 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 907 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 908 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 909 /* 48 - 720x480@120Hz */
910 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
911 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 912 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 913 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 914 /* 49 - 720x480@120Hz */
915 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
916 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 917 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 918 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 919 /* 50 - 720(1440)x480i@120Hz */
920 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
921 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 922 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 923 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 924 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 925 /* 51 - 720(1440)x480i@120Hz */
926 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
927 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 928 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 929 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 930 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 931 /* 52 - 720x576@200Hz */
932 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
933 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 934 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 935 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 936 /* 53 - 720x576@200Hz */
937 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
938 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 939 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 940 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 941 /* 54 - 720(1440)x576i@200Hz */
942 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
943 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 944 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 945 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 946 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 947 /* 55 - 720(1440)x576i@200Hz */
948 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
949 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 950 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 951 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 952 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 953 /* 56 - 720x480@240Hz */
954 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
955 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 956 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 957 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 958 /* 57 - 720x480@240Hz */
959 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
960 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 961 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 962 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
e587803c 963 /* 58 - 720(1440)x480i@240Hz */
fb01d280
CT		 964 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
965 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 966 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 967 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 968 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
e587803c 969 /* 59 - 720(1440)x480i@240Hz */
fb01d280
CT		 970 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
971 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 972 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 973 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 974 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 975 /* 60 - 1280x720@24Hz */
976 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
977 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 978 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 979 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 980 /* 61 - 1280x720@25Hz */
981 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
982 3740, 3960, 0, 720, 725, 730, 750, 0,
ee7925bb 983 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 984 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 985 /* 62 - 1280x720@30Hz */
986 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
987 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 988 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 989 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 990 /* 63 - 1920x1080@120Hz */
991 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
992 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 993 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 994 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 995 /* 64 - 1920x1080@100Hz */
996 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
8f0e4907 997 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 998 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 999 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 1000};
1001
7ebe1963 1002/*
d9278b4c 1003 * HDMI 1.4 4k modes. Index using the VIC.
7ebe1963
LD		 1004 */
1005static const struct drm_display_mode edid_4k_modes[] = {
d9278b4c
JN		 1006 /* 0 - dummy, VICs start at 1 */
1007 { },
7ebe1963
LD		 1008 /* 1 - 3840x2160@30Hz */
1009 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1010 3840, 4016, 4104, 4400, 0,
1011 2160, 2168, 2178, 2250, 0,
1012 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1013 .vrefresh = 30, },
1014 /* 2 - 3840x2160@25Hz */
1015 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1016 3840, 4896, 4984, 5280, 0,
1017 2160, 2168, 2178, 2250, 0,
1018 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1019 .vrefresh = 25, },
1020 /* 3 - 3840x2160@24Hz */
1021 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1022 3840, 5116, 5204, 5500, 0,
1023 2160, 2168, 2178, 2250, 0,
1024 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1025 .vrefresh = 24, },
1026 /* 4 - 4096x2160@24Hz (SMPTE) */
1027 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1028 4096, 5116, 5204, 5500, 0,
1029 2160, 2168, 2178, 2250, 0,
1030 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1031 .vrefresh = 24, },
1032};
1033
61e57a8d 1034/*** DDC fetch and block validation ***/
f453ba04 1035
083ae056
AJ		 1036static const u8 edid_header[] = {
1037 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1038};
f453ba04 1039
db6cf833
TR		 1040/**
1041 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1042 * @raw_edid: pointer to raw base EDID block
1043 *
1044 * Sanity check the header of the base EDID block.
1045 *
1046 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
051963d4
TR		 1047 */
1048int drm_edid_header_is_valid(const u8 *raw_edid)
1049{
1050 int i, score = 0;
1051
1052 for (i = 0; i < sizeof(edid_header); i++)
1053 if (raw_edid[i] == edid_header[i])
1054 score++;
1055
1056 return score;
1057}
1058EXPORT_SYMBOL(drm_edid_header_is_valid);
1059
47819ba2
AJ		 1060static int edid_fixup __read_mostly = 6;
1061module_param_named(edid_fixup, edid_fixup, int, 0400);
1062MODULE_PARM_DESC(edid_fixup,
1063 "Minimum number of valid EDID header bytes (0-8, default 6)");
051963d4 1064
40d9b043
DA		 1065static void drm_get_displayid(struct drm_connector *connector,
1066 struct edid *edid);
da9df2f4 1067
c465bbc8
SB		 1068static int drm_edid_block_checksum(const u8 *raw_edid)
1069{
1070 int i;
1071 u8 csum = 0;
1072 for (i = 0; i < EDID_LENGTH; i++)
1073 csum += raw_edid[i];
1074
1075 return csum;
1076}
1077
d6885d65
SB		 1078static bool drm_edid_is_zero(const u8 *in_edid, int length)
1079{
1080 if (memchr_inv(in_edid, 0, length))
1081 return false;
1082
1083 return true;
1084}
1085
db6cf833
TR		 1086/**
1087 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1088 * @raw_edid: pointer to raw EDID block
1089 * @block: type of block to validate (0 for base, extension otherwise)
1090 * @print_bad_edid: if true, dump bad EDID blocks to the console
6ba2bd3d 1091 * @edid_corrupt: if true, the header or checksum is invalid
db6cf833
TR		 1092 *
1093 * Validate a base or extension EDID block and optionally dump bad blocks to
1094 * the console.
1095 *
1096 * Return: True if the block is valid, false otherwise.
f453ba04 1097 */
6ba2bd3d
TP		 1098bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1099 bool *edid_corrupt)
f453ba04 1100{
c465bbc8 1101 u8 csum;
61e57a8d 1102 struct edid *edid = (struct edid *)raw_edid;
f453ba04 1103
fe2ef780
SWK		 1104 if (WARN_ON(!raw_edid))
1105 return false;
1106
47819ba2
AJ		 1107 if (edid_fixup > 8 || edid_fixup < 0)
1108 edid_fixup = 6;
1109
f89ec8a4 1110 if (block == 0) {
051963d4 1111 int score = drm_edid_header_is_valid(raw_edid);
6ba2bd3d
TP		 1112 if (score == 8) {
1113 if (edid_corrupt)
ac6f2e29 1114 *edid_corrupt = false;
6ba2bd3d
TP		 1115 } else if (score >= edid_fixup) {
1116 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1117 * The corrupt flag needs to be set here otherwise, the
1118 * fix-up code here will correct the problem, the
1119 * checksum is correct and the test fails
1120 */
1121 if (edid_corrupt)
ac6f2e29 1122 *edid_corrupt = true;
61e57a8d
AJ		 1123 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1124 memcpy(raw_edid, edid_header, sizeof(edid_header));
1125 } else {
6ba2bd3d 1126 if (edid_corrupt)
ac6f2e29 1127 *edid_corrupt = true;
61e57a8d
AJ		 1128 goto bad;
1129 }
1130 }
f453ba04 1131
c465bbc8 1132 csum = drm_edid_block_checksum(raw_edid);
f453ba04 1133 if (csum) {
0b2443ed
JG		 1134 if (print_bad_edid) {
1135 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum);
1136 }
4a638b4e 1137
6ba2bd3d 1138 if (edid_corrupt)
ac6f2e29 1139 *edid_corrupt = true;
6ba2bd3d 1140
4a638b4e
AJ		 1141 /* allow CEA to slide through, switches mangle this */
1142 if (raw_edid[0] != 0x02)
1143 goto bad;
f453ba04
DA		 1144 }
1145
61e57a8d
AJ		 1146 /* per-block-type checks */
1147 switch (raw_edid[0]) {
1148 case 0: /* base */
1149 if (edid->version != 1) {
1150 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version);
1151 goto bad;
1152 }
862b89c0 1153
61e57a8d
AJ		 1154 if (edid->revision > 4)
1155 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1156 break;
862b89c0 1157
61e57a8d
AJ		 1158 default:
1159 break;
1160 }
47ee4ccf 1161
fe2ef780 1162 return true;
f453ba04
DA		 1163
1164bad:
fe2ef780 1165 if (print_bad_edid) {
da4c07b7
SB		 1166 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1167 printk(KERN_ERR "EDID block is all zeroes\n");
1168 } else {
1169 printk(KERN_ERR "Raw EDID:\n");
1170 print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1,
0aff47f2 1171 raw_edid, EDID_LENGTH, false);
da4c07b7 1172 }
f453ba04 1173 }
fe2ef780 1174 return false;
f453ba04 1175}
da0df92b 1176EXPORT_SYMBOL(drm_edid_block_valid);
61e57a8d
AJ		 1177
1178/**
1179 * drm_edid_is_valid - sanity check EDID data
1180 * @edid: EDID data
1181 *
1182 * Sanity-check an entire EDID record (including extensions)
db6cf833
TR		 1183 *
1184 * Return: True if the EDID data is valid, false otherwise.
61e57a8d
AJ		 1185 */
1186bool drm_edid_is_valid(struct edid *edid)
1187{
1188 int i;
1189 u8 *raw = (u8 *)edid;
1190
1191 if (!edid)
1192 return false;
1193
1194 for (i = 0; i <= edid->extensions; i++)
6ba2bd3d 1195 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
61e57a8d
AJ		 1196 return false;
1197
1198 return true;
1199}
3c537889 1200EXPORT_SYMBOL(drm_edid_is_valid);
f453ba04 1201
61e57a8d
AJ		 1202#define DDC_SEGMENT_ADDR 0x30
1203/**
db6cf833 1204 * drm_do_probe_ddc_edid() - get EDID information via I2C
7c58e87e 1205 * @data: I2C device adapter
fc66811c
DV		 1206 * @buf: EDID data buffer to be filled
1207 * @block: 128 byte EDID block to start fetching from
1208 * @len: EDID data buffer length to fetch
1209 *
db6cf833 1210 * Try to fetch EDID information by calling I2C driver functions.
61e57a8d 1211 *
db6cf833 1212 * Return: 0 on success or -1 on failure.
61e57a8d
AJ		 1213 */
1214static int
18df89fe 1215drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
61e57a8d 1216{
18df89fe 1217 struct i2c_adapter *adapter = data;
61e57a8d 1218 unsigned char start = block * EDID_LENGTH;
cd004b3f
S		 1219 unsigned char segment = block >> 1;
1220 unsigned char xfers = segment ? 3 : 2;
4819d2e4
CW		 1221 int ret, retries = 5;
1222
db6cf833
TR		 1223 /*
1224 * The core I2C driver will automatically retry the transfer if the
4819d2e4
CW		 1225 * adapter reports EAGAIN. However, we find that bit-banging transfers
1226 * are susceptible to errors under a heavily loaded machine and
1227 * generate spurious NAKs and timeouts. Retrying the transfer
1228 * of the individual block a few times seems to overcome this.
1229 */
1230 do {
1231 struct i2c_msg msgs[] = {
1232 {
cd004b3f
S		 1233 .addr = DDC_SEGMENT_ADDR,
1234 .flags = 0,
1235 .len = 1,
1236 .buf = &segment,
1237 }, {
4819d2e4
CW		 1238 .addr = DDC_ADDR,
1239 .flags = 0,
1240 .len = 1,
1241 .buf = &start,
1242 }, {
1243 .addr = DDC_ADDR,
1244 .flags = I2C_M_RD,
1245 .len = len,
1246 .buf = buf,
1247 }
1248 };
cd004b3f 1249
db6cf833
TR		 1250 /*
1251 * Avoid sending the segment addr to not upset non-compliant
1252 * DDC monitors.
1253 */
cd004b3f
S		 1254 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1255
9292f37e
ED		 1256 if (ret == -ENXIO) {
1257 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1258 adapter->name);
1259 break;
1260 }
cd004b3f 1261 } while (ret != xfers && --retries);
4819d2e4 1262
cd004b3f 1263 return ret == xfers ? 0 : -1;
61e57a8d
AJ		 1264}
1265
14544d09
CW		 1266static void connector_bad_edid(struct drm_connector *connector,
1267 u8 *edid, int num_blocks)
1268{
1269 int i;
1270
1271 if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS))
1272 return;
1273
1274 dev_warn(connector->dev->dev,
1275 "%s: EDID is invalid:\n",
1276 connector->name);
1277 for (i = 0; i < num_blocks; i++) {
1278 u8 *block = edid + i * EDID_LENGTH;
1279 char prefix[20];
1280
1281 if (drm_edid_is_zero(block, EDID_LENGTH))
1282 sprintf(prefix, "\t[%02x] ZERO ", i);
1283 else if (!drm_edid_block_valid(block, i, false, NULL))
1284 sprintf(prefix, "\t[%02x] BAD ", i);
1285 else
1286 sprintf(prefix, "\t[%02x] GOOD ", i);
1287
1288 print_hex_dump(KERN_WARNING,
1289 prefix, DUMP_PREFIX_NONE, 16, 1,
1290 block, EDID_LENGTH, false);
1291 }
1292}
1293
18df89fe
LPC		 1294/**
1295 * drm_do_get_edid - get EDID data using a custom EDID block read function
1296 * @connector: connector we're probing
1297 * @get_edid_block: EDID block read function
1298 * @data: private data passed to the block read function
1299 *
1300 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1301 * exposes a different interface to read EDID blocks this function can be used
1302 * to get EDID data using a custom block read function.
1303 *
1304 * As in the general case the DDC bus is accessible by the kernel at the I2C
1305 * level, drivers must make all reasonable efforts to expose it as an I2C
1306 * adapter and use drm_get_edid() instead of abusing this function.
1307 *
1308 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1309 */
1310struct edid *drm_do_get_edid(struct drm_connector *connector,
1311 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1312 size_t len),
1313 void *data)
61e57a8d 1314{
0ea75e23 1315 int i, j = 0, valid_extensions = 0;
f14f3686 1316 u8 *edid, *new;
61e57a8d 1317
f14f3686 1318 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
61e57a8d
AJ		 1319 return NULL;
1320
1321 /* base block fetch */
1322 for (i = 0; i < 4; i++) {
f14f3686 1323 if (get_edid_block(data, edid, 0, EDID_LENGTH))
61e57a8d 1324 goto out;
14544d09 1325 if (drm_edid_block_valid(edid, 0, false,
6ba2bd3d 1326 &connector->edid_corrupt))
61e57a8d 1327 break;
f14f3686 1328 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
4a9a8b71
DA		 1329 connector->null_edid_counter++;
1330 goto carp;
1331 }
61e57a8d
AJ		 1332 }
1333 if (i == 4)
1334 goto carp;
1335
1336 /* if there's no extensions, we're done */
14544d09
CW		 1337 valid_extensions = edid[0x7e];
1338 if (valid_extensions == 0)
f14f3686 1339 return (struct edid *)edid;
61e57a8d 1340
14544d09 1341 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
61e57a8d
AJ		 1342 if (!new)
1343 goto out;
f14f3686 1344 edid = new;
61e57a8d 1345
f14f3686 1346 for (j = 1; j <= edid[0x7e]; j++) {
14544d09 1347 u8 *block = edid + j * EDID_LENGTH;
a28187cc 1348
61e57a8d 1349 for (i = 0; i < 4; i++) {
a28187cc 1350 if (get_edid_block(data, block, j, EDID_LENGTH))
61e57a8d 1351 goto out;
14544d09 1352 if (drm_edid_block_valid(block, j, false, NULL))
61e57a8d
AJ		 1353 break;
1354 }
f934ec8c 1355
14544d09
CW		 1356 if (i == 4)
1357 valid_extensions--;
0ea75e23
ST		 1358 }
1359
f14f3686 1360 if (valid_extensions != edid[0x7e]) {
14544d09
CW		 1361 u8 *base;
1362
1363 connector_bad_edid(connector, edid, edid[0x7e] + 1);
1364
f14f3686
CW		 1365 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
1366 edid[0x7e] = valid_extensions;
14544d09
CW		 1367
1368 new = kmalloc((valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
0ea75e23
ST		 1369 if (!new)
1370 goto out;
14544d09
CW		 1371
1372 base = new;
1373 for (i = 0; i <= edid[0x7e]; i++) {
1374 u8 *block = edid + i * EDID_LENGTH;
1375
1376 if (!drm_edid_block_valid(block, i, false, NULL))
1377 continue;
1378
1379 memcpy(base, block, EDID_LENGTH);
1380 base += EDID_LENGTH;
1381 }
1382
1383 kfree(edid);
f14f3686 1384 edid = new;
61e57a8d
AJ		 1385 }
1386
f14f3686 1387 return (struct edid *)edid;
61e57a8d
AJ		 1388
1389carp:
14544d09 1390 connector_bad_edid(connector, edid, 1);
61e57a8d 1391out:
f14f3686 1392 kfree(edid);
61e57a8d
AJ		 1393 return NULL;
1394}
18df89fe 1395EXPORT_SYMBOL_GPL(drm_do_get_edid);
61e57a8d
AJ		 1396
1397/**
db6cf833
TR		 1398 * drm_probe_ddc() - probe DDC presence
1399 * @adapter: I2C adapter to probe
fc66811c 1400 *
db6cf833 1401 * Return: True on success, false on failure.
61e57a8d 1402 */
fbff4690 1403bool
61e57a8d
AJ		 1404drm_probe_ddc(struct i2c_adapter *adapter)
1405{
1406 unsigned char out;
1407
1408 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1409}
fbff4690 1410EXPORT_SYMBOL(drm_probe_ddc);
61e57a8d
AJ		 1411
1412/**
1413 * drm_get_edid - get EDID data, if available
1414 * @connector: connector we're probing
db6cf833 1415 * @adapter: I2C adapter to use for DDC
61e57a8d 1416 *
db6cf833 1417 * Poke the given I2C channel to grab EDID data if possible. If found,
61e57a8d
AJ		 1418 * attach it to the connector.
1419 *
db6cf833 1420 * Return: Pointer to valid EDID or NULL if we couldn't find any.
61e57a8d
AJ		 1421 */
1422struct edid *drm_get_edid(struct drm_connector *connector,
1423 struct i2c_adapter *adapter)
1424{
40d9b043
DA		 1425 struct edid *edid;
1426
18df89fe
LPC		 1427 if (!drm_probe_ddc(adapter))
1428 return NULL;
61e57a8d 1429
40d9b043
DA		 1430 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
1431 if (edid)
1432 drm_get_displayid(connector, edid);
1433 return edid;
61e57a8d
AJ		 1434}
1435EXPORT_SYMBOL(drm_get_edid);
1436
5cb8eaa2
LW		 1437/**
1438 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
1439 * @connector: connector we're probing
1440 * @adapter: I2C adapter to use for DDC
1441 *
1442 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
1443 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
1444 * switch DDC to the GPU which is retrieving EDID.
1445 *
1446 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
1447 */
1448struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
1449 struct i2c_adapter *adapter)
1450{
1451 struct pci_dev *pdev = connector->dev->pdev;
1452 struct edid *edid;
1453
1454 vga_switcheroo_lock_ddc(pdev);
1455 edid = drm_get_edid(connector, adapter);
1456 vga_switcheroo_unlock_ddc(pdev);
1457
1458 return edid;
1459}
1460EXPORT_SYMBOL(drm_get_edid_switcheroo);
1461
51f8da59
JN		 1462/**
1463 * drm_edid_duplicate - duplicate an EDID and the extensions
1464 * @edid: EDID to duplicate
1465 *
db6cf833 1466 * Return: Pointer to duplicated EDID or NULL on allocation failure.
51f8da59
JN		 1467 */
1468struct edid *drm_edid_duplicate(const struct edid *edid)
1469{
1470 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1471}
1472EXPORT_SYMBOL(drm_edid_duplicate);
1473
61e57a8d
AJ		 1474/*** EDID parsing ***/
1475
f453ba04
DA		 1476/**
1477 * edid_vendor - match a string against EDID's obfuscated vendor field
1478 * @edid: EDID to match
1479 * @vendor: vendor string
1480 *
1481 * Returns true if @vendor is in @edid, false otherwise
1482 */
23c4cfbd 1483static bool edid_vendor(struct edid *edid, const char *vendor)
f453ba04
DA		 1484{
1485 char edid_vendor[3];
1486
1487 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1488 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1489 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
16456c87 1490 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
f453ba04
DA		 1491
1492 return !strncmp(edid_vendor, vendor, 3);
1493}
1494
1495/**
1496 * edid_get_quirks - return quirk flags for a given EDID
1497 * @edid: EDID to process
1498 *
1499 * This tells subsequent routines what fixes they need to apply.
1500 */
1501static u32 edid_get_quirks(struct edid *edid)
1502{
23c4cfbd 1503 const struct edid_quirk *quirk;
f453ba04
DA		 1504 int i;
1505
1506 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1507 quirk = &edid_quirk_list[i];
1508
1509 if (edid_vendor(edid, quirk->vendor) &&
1510 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1511 return quirk->quirks;
1512 }
1513
1514 return 0;
1515}
1516
1517#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
339d202c 1518#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
f453ba04 1519
f453ba04
DA		 1520/**
1521 * edid_fixup_preferred - set preferred modes based on quirk list
1522 * @connector: has mode list to fix up
1523 * @quirks: quirks list
1524 *
1525 * Walk the mode list for @connector, clearing the preferred status
1526 * on existing modes and setting it anew for the right mode ala @quirks.
1527 */
1528static void edid_fixup_preferred(struct drm_connector *connector,
1529 u32 quirks)
1530{
1531 struct drm_display_mode *t, *cur_mode, *preferred_mode;
f890607b 1532 int target_refresh = 0;
339d202c 1533 int cur_vrefresh, preferred_vrefresh;
f453ba04
DA		 1534
1535 if (list_empty(&connector->probed_modes))
1536 return;
1537
1538 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1539 target_refresh = 60;
1540 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1541 target_refresh = 75;
1542
1543 preferred_mode = list_first_entry(&connector->probed_modes,
1544 struct drm_display_mode, head);
1545
1546 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1547 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1548
1549 if (cur_mode == preferred_mode)
1550 continue;
1551
1552 /* Largest mode is preferred */
1553 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1554 preferred_mode = cur_mode;
1555
339d202c
AD		 1556 cur_vrefresh = cur_mode->vrefresh ?
1557 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1558 preferred_vrefresh = preferred_mode->vrefresh ?
1559 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
f453ba04
DA		 1560 /* At a given size, try to get closest to target refresh */
1561 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
339d202c
AD		 1562 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1563 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
f453ba04
DA		 1564 preferred_mode = cur_mode;
1565 }
1566 }
1567
1568 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1569}
1570
f6e252ba
AJ		 1571static bool
1572mode_is_rb(const struct drm_display_mode *mode)
1573{
1574 return (mode->htotal - mode->hdisplay == 160) &&
1575 (mode->hsync_end - mode->hdisplay == 80) &&
1576 (mode->hsync_end - mode->hsync_start == 32) &&
1577 (mode->vsync_start - mode->vdisplay == 3);
1578}
1579
33c7531d
AJ		 1580/*
1581 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1582 * @dev: Device to duplicate against
1583 * @hsize: Mode width
1584 * @vsize: Mode height
1585 * @fresh: Mode refresh rate
f6e252ba 1586 * @rb: Mode reduced-blanking-ness
33c7531d
AJ		 1587 *
1588 * Walk the DMT mode list looking for a match for the given parameters.
db6cf833
TR		 1589 *
1590 * Return: A newly allocated copy of the mode, or NULL if not found.
33c7531d 1591 */
1d42bbc8 1592struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
f6e252ba
AJ		 1593 int hsize, int vsize, int fresh,
1594 bool rb)
559ee21d 1595{
07a5e632 1596 int i;
559ee21d 1597
a6b21831 1598 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
b1f559ec 1599 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
f8b46a05
AJ		 1600 if (hsize != ptr->hdisplay)
1601 continue;
1602 if (vsize != ptr->vdisplay)
1603 continue;
1604 if (fresh != drm_mode_vrefresh(ptr))
1605 continue;
f6e252ba
AJ		 1606 if (rb != mode_is_rb(ptr))
1607 continue;
f8b46a05
AJ		 1608
1609 return drm_mode_duplicate(dev, ptr);
559ee21d 1610 }
f8b46a05
AJ		 1611
1612 return NULL;
559ee21d 1613}
1d42bbc8 1614EXPORT_SYMBOL(drm_mode_find_dmt);
23425cae 1615
d1ff6409
AJ		 1616typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1617
4d76a221
AJ		 1618static void
1619cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1620{
1621 int i, n = 0;
4966b2a9 1622 u8 d = ext[0x02];
4d76a221
AJ		 1623 u8 *det_base = ext + d;
1624
4966b2a9 1625 n = (127 - d) / 18;
4d76a221
AJ		 1626 for (i = 0; i < n; i++)
1627 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1628}
1629
cbba98f8
AJ		 1630static void
1631vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1632{
1633 unsigned int i, n = min((int)ext[0x02], 6);
1634 u8 *det_base = ext + 5;
1635
1636 if (ext[0x01] != 1)
1637 return; /* unknown version */
1638
1639 for (i = 0; i < n; i++)
1640 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1641}
1642
d1ff6409
AJ		 1643static void
1644drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1645{
1646 int i;
1647 struct edid *edid = (struct edid *)raw_edid;
1648
1649 if (edid == NULL)
1650 return;
1651
1652 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1653 cb(&(edid->detailed_timings[i]), closure);
1654
4d76a221
AJ		 1655 for (i = 1; i <= raw_edid[0x7e]; i++) {
1656 u8 *ext = raw_edid + (i * EDID_LENGTH);
1657 switch (*ext) {
1658 case CEA_EXT:
1659 cea_for_each_detailed_block(ext, cb, closure);
1660 break;
cbba98f8
AJ		 1661 case VTB_EXT:
1662 vtb_for_each_detailed_block(ext, cb, closure);
1663 break;
4d76a221
AJ		 1664 default:
1665 break;
1666 }
1667 }
d1ff6409
AJ		 1668}
1669
1670static void
1671is_rb(struct detailed_timing *t, void *data)
1672{
1673 u8 *r = (u8 *)t;
1674 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
1675 if (r[15] & 0x10)
1676 *(bool *)data = true;
1677}
1678
1679/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
1680static bool
1681drm_monitor_supports_rb(struct edid *edid)
1682{
1683 if (edid->revision >= 4) {
b196a498 1684 bool ret = false;
d1ff6409
AJ		 1685 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
1686 return ret;
1687 }
1688
1689 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
1690}
1691
7a374350
AJ		 1692static void
1693find_gtf2(struct detailed_timing *t, void *data)
1694{
1695 u8 *r = (u8 *)t;
1696 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
1697 *(u8 **)data = r;
1698}
1699
1700/* Secondary GTF curve kicks in above some break frequency */
1701static int
1702drm_gtf2_hbreak(struct edid *edid)
1703{
1704 u8 *r = NULL;
1705 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1706 return r ? (r[12] * 2) : 0;
1707}
1708
1709static int
1710drm_gtf2_2c(struct edid *edid)
1711{
1712 u8 *r = NULL;
1713 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1714 return r ? r[13] : 0;
1715}
1716
1717static int
1718drm_gtf2_m(struct edid *edid)
1719{
1720 u8 *r = NULL;
1721 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1722 return r ? (r[15] << 8) + r[14] : 0;
1723}
1724
1725static int
1726drm_gtf2_k(struct edid *edid)
1727{
1728 u8 *r = NULL;
1729 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1730 return r ? r[16] : 0;
1731}
1732
1733static int
1734drm_gtf2_2j(struct edid *edid)
1735{
1736 u8 *r = NULL;
1737 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1738 return r ? r[17] : 0;
1739}
1740
1741/**
1742 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
1743 * @edid: EDID block to scan
1744 */
1745static int standard_timing_level(struct edid *edid)
1746{
1747 if (edid->revision >= 2) {
1748 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
1749 return LEVEL_CVT;
1750 if (drm_gtf2_hbreak(edid))
1751 return LEVEL_GTF2;
1752 return LEVEL_GTF;
1753 }
1754 return LEVEL_DMT;
1755}
1756
23425cae
AJ		 1757/*
1758 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
1759 * monitors fill with ascii space (0x20) instead.
1760 */
1761static int
1762bad_std_timing(u8 a, u8 b)
1763{
1764 return (a == 0x00 && b == 0x00) ||
1765 (a == 0x01 && b == 0x01) ||
1766 (a == 0x20 && b == 0x20);
1767}
1768
f453ba04
DA		 1769/**
1770 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
fc66811c
DV		 1771 * @connector: connector of for the EDID block
1772 * @edid: EDID block to scan
f453ba04
DA		 1773 * @t: standard timing params
1774 *
1775 * Take the standard timing params (in this case width, aspect, and refresh)
5c61259e 1776 * and convert them into a real mode using CVT/GTF/DMT.
f453ba04 1777 */
7ca6adb3 1778static struct drm_display_mode *
7a374350 1779drm_mode_std(struct drm_connector *connector, struct edid *edid,
464fdeca 1780 struct std_timing *t)
f453ba04 1781{
7ca6adb3
AJ		 1782 struct drm_device *dev = connector->dev;
1783 struct drm_display_mode *m, *mode = NULL;
5c61259e
ZY		 1784 int hsize, vsize;
1785 int vrefresh_rate;
0454beab
MD		 1786 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
1787 >> EDID_TIMING_ASPECT_SHIFT;
5c61259e
ZY		 1788 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
1789 >> EDID_TIMING_VFREQ_SHIFT;
7a374350 1790 int timing_level = standard_timing_level(edid);
5c61259e 1791
23425cae
AJ		 1792 if (bad_std_timing(t->hsize, t->vfreq_aspect))
1793 return NULL;
1794
5c61259e
ZY		 1795 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
1796 hsize = t->hsize * 8 + 248;
1797 /* vrefresh_rate = vfreq + 60 */
1798 vrefresh_rate = vfreq + 60;
1799 /* the vdisplay is calculated based on the aspect ratio */
f066a17d 1800 if (aspect_ratio == 0) {
464fdeca 1801 if (edid->revision < 3)
f066a17d
AJ		 1802 vsize = hsize;
1803 else
1804 vsize = (hsize * 10) / 16;
1805 } else if (aspect_ratio == 1)
f453ba04 1806 vsize = (hsize * 3) / 4;
0454beab 1807 else if (aspect_ratio == 2)
f453ba04
DA		 1808 vsize = (hsize * 4) / 5;
1809 else
1810 vsize = (hsize * 9) / 16;
a0910c8e
AJ		 1811
1812 /* HDTV hack, part 1 */
1813 if (vrefresh_rate == 60 &&
1814 ((hsize == 1360 && vsize == 765) ||
1815 (hsize == 1368 && vsize == 769))) {
1816 hsize = 1366;
1817 vsize = 768;
1818 }
1819
7ca6adb3
AJ		 1820 /*
1821 * If this connector already has a mode for this size and refresh
1822 * rate (because it came from detailed or CVT info), use that
1823 * instead. This way we don't have to guess at interlace or
1824 * reduced blanking.
1825 */
522032da 1826 list_for_each_entry(m, &connector->probed_modes, head)
7ca6adb3
AJ		 1827 if (m->hdisplay == hsize && m->vdisplay == vsize &&
1828 drm_mode_vrefresh(m) == vrefresh_rate)
1829 return NULL;
1830
a0910c8e
AJ		 1831 /* HDTV hack, part 2 */
1832 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
1833 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
d50ba256 1834 false);
559ee21d 1835 mode->hdisplay = 1366;
a4967de6
AJ		 1836 mode->hsync_start = mode->hsync_start - 1;
1837 mode->hsync_end = mode->hsync_end - 1;
559ee21d
ZY		 1838 return mode;
1839 }
a0910c8e 1840
559ee21d 1841 /* check whether it can be found in default mode table */
f6e252ba
AJ		 1842 if (drm_monitor_supports_rb(edid)) {
1843 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
1844 true);
1845 if (mode)
1846 return mode;
1847 }
1848 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
559ee21d
ZY		 1849 if (mode)
1850 return mode;
1851
f6e252ba 1852 /* okay, generate it */
5c61259e
ZY		 1853 switch (timing_level) {
1854 case LEVEL_DMT:
5c61259e
ZY		 1855 break;
1856 case LEVEL_GTF:
1857 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
1858 break;
7a374350
AJ		 1859 case LEVEL_GTF2:
1860 /*
1861 * This is potentially wrong if there's ever a monitor with
1862 * more than one ranges section, each claiming a different
1863 * secondary GTF curve. Please don't do that.
1864 */
1865 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
fc48f169
TI		 1866 if (!mode)
1867 return NULL;
7a374350 1868 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
aefd330e 1869 drm_mode_destroy(dev, mode);
7a374350
AJ		 1870 mode = drm_gtf_mode_complex(dev, hsize, vsize,
1871 vrefresh_rate, 0, 0,
1872 drm_gtf2_m(edid),
1873 drm_gtf2_2c(edid),
1874 drm_gtf2_k(edid),
1875 drm_gtf2_2j(edid));
1876 }
1877 break;
5c61259e 1878 case LEVEL_CVT:
d50ba256
DA		 1879 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
1880 false);
5c61259e
ZY		 1881 break;
1882 }
f453ba04
DA		 1883 return mode;
1884}
1885
b58db2c6
AJ		 1886/*
1887 * EDID is delightfully ambiguous about how interlaced modes are to be
1888 * encoded. Our internal representation is of frame height, but some
1889 * HDTV detailed timings are encoded as field height.
1890 *
1891 * The format list here is from CEA, in frame size. Technically we
1892 * should be checking refresh rate too. Whatever.
1893 */
1894static void
1895drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
1896 struct detailed_pixel_timing *pt)
1897{
1898 int i;
1899 static const struct {
1900 int w, h;
1901 } cea_interlaced[] = {
1902 { 1920, 1080 },
1903 { 720, 480 },
1904 { 1440, 480 },
1905 { 2880, 480 },
1906 { 720, 576 },
1907 { 1440, 576 },
1908 { 2880, 576 },
1909 };
b58db2c6
AJ		 1910
1911 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
1912 return;
1913
3c581411 1914 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
b58db2c6
AJ		 1915 if ((mode->hdisplay == cea_interlaced[i].w) &&
1916 (mode->vdisplay == cea_interlaced[i].h / 2)) {
1917 mode->vdisplay *= 2;
1918 mode->vsync_start *= 2;
1919 mode->vsync_end *= 2;
1920 mode->vtotal *= 2;
1921 mode->vtotal |= 1;
1922 }
1923 }
1924
1925 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1926}
1927
f453ba04
DA		 1928/**
1929 * drm_mode_detailed - create a new mode from an EDID detailed timing section
1930 * @dev: DRM device (needed to create new mode)
1931 * @edid: EDID block
1932 * @timing: EDID detailed timing info
1933 * @quirks: quirks to apply
1934 *
1935 * An EDID detailed timing block contains enough info for us to create and
1936 * return a new struct drm_display_mode.
1937 */
1938static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
1939 struct edid *edid,
1940 struct detailed_timing *timing,
1941 u32 quirks)
1942{
1943 struct drm_display_mode *mode;
1944 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
0454beab
MD		 1945 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
1946 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
1947 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
1948 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
e14cbee4
MD		 1949 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
1950 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
16dad1d7 1951 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
e14cbee4 1952 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
f453ba04 1953
fc438966 1954 /* ignore tiny modes */
0454beab 1955 if (hactive < 64 || vactive < 64)
fc438966
AJ		 1956 return NULL;
1957
0454beab 1958 if (pt->misc & DRM_EDID_PT_STEREO) {
c7d015f3 1959 DRM_DEBUG_KMS("stereo mode not supported\n");
f453ba04
DA		 1960 return NULL;
1961 }
0454beab 1962 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
c7d015f3 1963 DRM_DEBUG_KMS("composite sync not supported\n");
f453ba04
DA		 1964 }
1965
fcb45611
ZY		 1966 /* it is incorrect if hsync/vsync width is zero */
1967 if (!hsync_pulse_width || !vsync_pulse_width) {
1968 DRM_DEBUG_KMS("Incorrect Detailed timing. "
1969 "Wrong Hsync/Vsync pulse width\n");
1970 return NULL;
1971 }
bc42aabc
AJ		 1972
1973 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
1974 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
1975 if (!mode)
1976 return NULL;
1977
1978 goto set_size;
1979 }
1980
f453ba04
DA		 1981 mode = drm_mode_create(dev);
1982 if (!mode)
1983 return NULL;
1984
f453ba04 1985 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
0454beab
MD		 1986 timing->pixel_clock = cpu_to_le16(1088);
1987
1988 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
1989
1990 mode->hdisplay = hactive;
1991 mode->hsync_start = mode->hdisplay + hsync_offset;
1992 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
1993 mode->htotal = mode->hdisplay + hblank;
1994
1995 mode->vdisplay = vactive;
1996 mode->vsync_start = mode->vdisplay + vsync_offset;
1997 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
1998 mode->vtotal = mode->vdisplay + vblank;
f453ba04 1999
7064fef5
JB		 2000 /* Some EDIDs have bogus h/vtotal values */
2001 if (mode->hsync_end > mode->htotal)
2002 mode->htotal = mode->hsync_end + 1;
2003 if (mode->vsync_end > mode->vtotal)
2004 mode->vtotal = mode->vsync_end + 1;
2005
b58db2c6 2006 drm_mode_do_interlace_quirk(mode, pt);
f453ba04
DA		 2007
2008 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
0454beab 2009 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
f453ba04
DA		 2010 }
2011
0454beab
MD		 2012 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2013 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2014 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2015 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
f453ba04 2016
bc42aabc 2017set_size:
e14cbee4
MD		 2018 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2019 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
f453ba04
DA		 2020
2021 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2022 mode->width_mm *= 10;
2023 mode->height_mm *= 10;
2024 }
2025
2026 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2027 mode->width_mm = edid->width_cm * 10;
2028 mode->height_mm = edid->height_cm * 10;
2029 }
2030
bc42aabc 2031 mode->type = DRM_MODE_TYPE_DRIVER;
c19b3b0f 2032 mode->vrefresh = drm_mode_vrefresh(mode);
bc42aabc
AJ		 2033 drm_mode_set_name(mode);
2034
f453ba04
DA		 2035 return mode;
2036}
2037
b17e52ef 2038static bool
b1f559ec
CW		 2039mode_in_hsync_range(const struct drm_display_mode *mode,
2040 struct edid *edid, u8 *t)
b17e52ef
AJ		 2041{
2042 int hsync, hmin, hmax;
2043
2044 hmin = t[7];
2045 if (edid->revision >= 4)
2046 hmin += ((t[4] & 0x04) ? 255 : 0);
2047 hmax = t[8];
2048 if (edid->revision >= 4)
2049 hmax += ((t[4] & 0x08) ? 255 : 0);
07a5e632 2050 hsync = drm_mode_hsync(mode);
07a5e632 2051
b17e52ef
AJ		 2052 return (hsync <= hmax && hsync >= hmin);
2053}
2054
2055static bool
b1f559ec
CW		 2056mode_in_vsync_range(const struct drm_display_mode *mode,
2057 struct edid *edid, u8 *t)
b17e52ef
AJ		 2058{
2059 int vsync, vmin, vmax;
2060
2061 vmin = t[5];
2062 if (edid->revision >= 4)
2063 vmin += ((t[4] & 0x01) ? 255 : 0);
2064 vmax = t[6];
2065 if (edid->revision >= 4)
2066 vmax += ((t[4] & 0x02) ? 255 : 0);
2067 vsync = drm_mode_vrefresh(mode);
2068
2069 return (vsync <= vmax && vsync >= vmin);
2070}
2071
2072static u32
2073range_pixel_clock(struct edid *edid, u8 *t)
2074{
2075 /* unspecified */
2076 if (t[9] == 0 || t[9] == 255)
2077 return 0;
2078
2079 /* 1.4 with CVT support gives us real precision, yay */
2080 if (edid->revision >= 4 && t[10] == 0x04)
2081 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2082
2083 /* 1.3 is pathetic, so fuzz up a bit */
2084 return t[9] * 10000 + 5001;
2085}
2086
b17e52ef 2087static bool
b1f559ec 2088mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
b17e52ef
AJ		 2089 struct detailed_timing *timing)
2090{
2091 u32 max_clock;
2092 u8 *t = (u8 *)timing;
2093
2094 if (!mode_in_hsync_range(mode, edid, t))
07a5e632
AJ		 2095 return false;
2096
b17e52ef 2097 if (!mode_in_vsync_range(mode, edid, t))
07a5e632
AJ		 2098 return false;
2099
b17e52ef 2100 if ((max_clock = range_pixel_clock(edid, t)))
07a5e632
AJ		 2101 if (mode->clock > max_clock)
2102 return false;
b17e52ef
AJ		 2103
2104 /* 1.4 max horizontal check */
2105 if (edid->revision >= 4 && t[10] == 0x04)
2106 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2107 return false;
2108
2109 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2110 return false;
07a5e632
AJ		 2111
2112 return true;
2113}
2114
7b668ebe
TI		 2115static bool valid_inferred_mode(const struct drm_connector *connector,
2116 const struct drm_display_mode *mode)
2117{
85f8fcd6 2118 const struct drm_display_mode *m;
7b668ebe
TI		 2119 bool ok = false;
2120
2121 list_for_each_entry(m, &connector->probed_modes, head) {
2122 if (mode->hdisplay == m->hdisplay &&
2123 mode->vdisplay == m->vdisplay &&
2124 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2125 return false; /* duplicated */
2126 if (mode->hdisplay <= m->hdisplay &&
2127 mode->vdisplay <= m->vdisplay)
2128 ok = true;
2129 }
2130 return ok;
2131}
2132
b17e52ef 2133static int
cd4cd3de 2134drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
b17e52ef 2135 struct detailed_timing *timing)
07a5e632
AJ		 2136{
2137 int i, modes = 0;
2138 struct drm_display_mode *newmode;
2139 struct drm_device *dev = connector->dev;
2140
a6b21831 2141 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
7b668ebe
TI		 2142 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2143 valid_inferred_mode(connector, drm_dmt_modes + i)) {
07a5e632
AJ		 2144 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2145 if (newmode) {
2146 drm_mode_probed_add(connector, newmode);
2147 modes++;
2148 }
2149 }
2150 }
2151
2152 return modes;
2153}
2154
c09dedb7
TI		 2155/* fix up 1366x768 mode from 1368x768;
2156 * GFT/CVT can't express 1366 width which isn't dividable by 8
2157 */
969218fe 2158void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
c09dedb7
TI		 2159{
2160 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2161 mode->hdisplay = 1366;
2162 mode->hsync_start--;
2163 mode->hsync_end--;
2164 drm_mode_set_name(mode);
2165 }
2166}
2167
b309bd37
AJ		 2168static int
2169drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2170 struct detailed_timing *timing)
2171{
2172 int i, modes = 0;
2173 struct drm_display_mode *newmode;
2174 struct drm_device *dev = connector->dev;
2175
a6b21831 2176 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37
AJ		 2177 const struct minimode *m = &extra_modes[i];
2178 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
fc48f169
TI		 2179 if (!newmode)
2180 return modes;
b309bd37 2181
969218fe 2182 drm_mode_fixup_1366x768(newmode);
7b668ebe
TI		 2183 if (!mode_in_range(newmode, edid, timing) ||
2184 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 2185 drm_mode_destroy(dev, newmode);
2186 continue;
2187 }
2188
2189 drm_mode_probed_add(connector, newmode);
2190 modes++;
2191 }
2192
2193 return modes;
2194}
2195
2196static int
2197drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2198 struct detailed_timing *timing)
2199{
2200 int i, modes = 0;
2201 struct drm_display_mode *newmode;
2202 struct drm_device *dev = connector->dev;
2203 bool rb = drm_monitor_supports_rb(edid);
2204
a6b21831 2205 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37
AJ		 2206 const struct minimode *m = &extra_modes[i];
2207 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
fc48f169
TI		 2208 if (!newmode)
2209 return modes;
b309bd37 2210
969218fe 2211 drm_mode_fixup_1366x768(newmode);
7b668ebe
TI		 2212 if (!mode_in_range(newmode, edid, timing) ||
2213 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 2214 drm_mode_destroy(dev, newmode);
2215 continue;
2216 }
2217
2218 drm_mode_probed_add(connector, newmode);
2219 modes++;
2220 }
2221
2222 return modes;
2223}
2224
13931579
AJ		 2225static void
2226do_inferred_modes(struct detailed_timing *timing, void *c)
9340d8cf 2227{
13931579
AJ		 2228 struct detailed_mode_closure *closure = c;
2229 struct detailed_non_pixel *data = &timing->data.other_data;
b309bd37 2230 struct detailed_data_monitor_range *range = &data->data.range;
9340d8cf 2231
cb21aafe
AJ		 2232 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2233 return;
2234
2235 closure->modes += drm_dmt_modes_for_range(closure->connector,
2236 closure->edid,
2237 timing);
b309bd37
AJ		 2238
2239 if (!version_greater(closure->edid, 1, 1))
2240 return; /* GTF not defined yet */
2241
2242 switch (range->flags) {
2243 case 0x02: /* secondary gtf, XXX could do more */
2244 case 0x00: /* default gtf */
2245 closure->modes += drm_gtf_modes_for_range(closure->connector,
2246 closure->edid,
2247 timing);
2248 break;
2249 case 0x04: /* cvt, only in 1.4+ */
2250 if (!version_greater(closure->edid, 1, 3))
2251 break;
2252
2253 closure->modes += drm_cvt_modes_for_range(closure->connector,
2254 closure->edid,
2255 timing);
2256 break;
2257 case 0x01: /* just the ranges, no formula */
2258 default:
2259 break;
2260 }
13931579 2261}
69da3015 2262
13931579
AJ		 2263static int
2264add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2265{
2266 struct detailed_mode_closure closure = {
d456ea2e
JL		 2267 .connector = connector,
2268 .edid = edid,
13931579 2269 };
9340d8cf 2270
13931579
AJ		 2271 if (version_greater(edid, 1, 0))
2272 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2273 &closure);
9340d8cf 2274
13931579 2275 return closure.modes;
9340d8cf
AJ		 2276}
2277
2255be14
AJ		 2278static int
2279drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2280{
2281 int i, j, m, modes = 0;
2282 struct drm_display_mode *mode;
f3a32d74 2283 u8 *est = ((u8 *)timing) + 6;
2255be14
AJ		 2284
2285 for (i = 0; i < 6; i++) {
891a7469 2286 for (j = 7; j >= 0; j--) {
2255be14 2287 m = (i * 8) + (7 - j);
3c581411 2288 if (m >= ARRAY_SIZE(est3_modes))
2255be14
AJ		 2289 break;
2290 if (est[i] & (1 << j)) {
1d42bbc8
DA		 2291 mode = drm_mode_find_dmt(connector->dev,
2292 est3_modes[m].w,
2293 est3_modes[m].h,
f6e252ba
AJ		 2294 est3_modes[m].r,
2295 est3_modes[m].rb);
2255be14
AJ		 2296 if (mode) {
2297 drm_mode_probed_add(connector, mode);
2298 modes++;
2299 }
2300 }
2301 }
2302 }
2303
2304 return modes;
2305}
2306
13931579
AJ		 2307static void
2308do_established_modes(struct detailed_timing *timing, void *c)
9cf00977 2309{
13931579 2310 struct detailed_mode_closure *closure = c;
9cf00977 2311 struct detailed_non_pixel *data = &timing->data.other_data;
9cf00977 2312
13931579
AJ		 2313 if (data->type == EDID_DETAIL_EST_TIMINGS)
2314 closure->modes += drm_est3_modes(closure->connector, timing);
2315}
9cf00977 2316
13931579
AJ		 2317/**
2318 * add_established_modes - get est. modes from EDID and add them
db6cf833 2319 * @connector: connector to add mode(s) to
13931579
AJ		 2320 * @edid: EDID block to scan
2321 *
2322 * Each EDID block contains a bitmap of the supported "established modes" list
2323 * (defined above). Tease them out and add them to the global modes list.
2324 */
2325static int
2326add_established_modes(struct drm_connector *connector, struct edid *edid)
2327{
2328 struct drm_device *dev = connector->dev;
2329 unsigned long est_bits = edid->established_timings.t1 |
2330 (edid->established_timings.t2 << 8) |
2331 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2332 int i, modes = 0;
2333 struct detailed_mode_closure closure = {
d456ea2e
JL		 2334 .connector = connector,
2335 .edid = edid,
13931579 2336 };
9cf00977 2337
13931579
AJ		 2338 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2339 if (est_bits & (1<<i)) {
2340 struct drm_display_mode *newmode;
2341 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2342 if (newmode) {
2343 drm_mode_probed_add(connector, newmode);
2344 modes++;
2345 }
2346 }
9cf00977
AJ		 2347 }
2348
13931579
AJ		 2349 if (version_greater(edid, 1, 0))
2350 drm_for_each_detailed_block((u8 *)edid,
2351 do_established_modes, &closure);
2352
2353 return modes + closure.modes;
2354}
2355
2356static void
2357do_standard_modes(struct detailed_timing *timing, void *c)
2358{
2359 struct detailed_mode_closure *closure = c;
2360 struct detailed_non_pixel *data = &timing->data.other_data;
2361 struct drm_connector *connector = closure->connector;
2362 struct edid *edid = closure->edid;
2363
2364 if (data->type == EDID_DETAIL_STD_MODES) {
2365 int i;
9cf00977
AJ		 2366 for (i = 0; i < 6; i++) {
2367 struct std_timing *std;
2368 struct drm_display_mode *newmode;
2369
2370 std = &data->data.timings[i];
464fdeca 2371 newmode = drm_mode_std(connector, edid, std);
9cf00977
AJ		 2372 if (newmode) {
2373 drm_mode_probed_add(connector, newmode);
13931579 2374 closure->modes++;
9cf00977
AJ		 2375 }
2376 }
9cf00977 2377 }
9cf00977
AJ		 2378}
2379
f453ba04 2380/**
13931579 2381 * add_standard_modes - get std. modes from EDID and add them
db6cf833 2382 * @connector: connector to add mode(s) to
f453ba04 2383 * @edid: EDID block to scan
f453ba04 2384 *
13931579
AJ		 2385 * Standard modes can be calculated using the appropriate standard (DMT,
2386 * GTF or CVT. Grab them from @edid and add them to the list.
f453ba04 2387 */
13931579
AJ		 2388static int
2389add_standard_modes(struct drm_connector *connector, struct edid *edid)
f453ba04 2390{
9cf00977 2391 int i, modes = 0;
13931579 2392 struct detailed_mode_closure closure = {
d456ea2e
JL		 2393 .connector = connector,
2394 .edid = edid,
13931579
AJ		 2395 };
2396
2397 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2398 struct drm_display_mode *newmode;
2399
2400 newmode = drm_mode_std(connector, edid,
464fdeca 2401 &edid->standard_timings[i]);
13931579
AJ		 2402 if (newmode) {
2403 drm_mode_probed_add(connector, newmode);
2404 modes++;
2405 }
2406 }
2407
2408 if (version_greater(edid, 1, 0))
2409 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2410 &closure);
2411
2412 /* XXX should also look for standard codes in VTB blocks */
2413
2414 return modes + closure.modes;
2415}
f453ba04 2416
13931579
AJ		 2417static int drm_cvt_modes(struct drm_connector *connector,
2418 struct detailed_timing *timing)
2419{
2420 int i, j, modes = 0;
2421 struct drm_display_mode *newmode;
2422 struct drm_device *dev = connector->dev;
2423 struct cvt_timing *cvt;
2424 const int rates[] = { 60, 85, 75, 60, 50 };
2425 const u8 empty[3] = { 0, 0, 0 };
a327f6b8 2426
13931579
AJ		 2427 for (i = 0; i < 4; i++) {
2428 int uninitialized_var(width), height;
2429 cvt = &(timing->data.other_data.data.cvt[i]);
f453ba04 2430
13931579 2431 if (!memcmp(cvt->code, empty, 3))
9cf00977 2432 continue;
f453ba04 2433
13931579
AJ		 2434 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2435 switch (cvt->code[1] & 0x0c) {
2436 case 0x00:
2437 width = height * 4 / 3;
2438 break;
2439 case 0x04:
2440 width = height * 16 / 9;
2441 break;
2442 case 0x08:
2443 width = height * 16 / 10;
2444 break;
2445 case 0x0c:
2446 width = height * 15 / 9;
2447 break;
2448 }
2449
2450 for (j = 1; j < 5; j++) {
2451 if (cvt->code[2] & (1 << j)) {
2452 newmode = drm_cvt_mode(dev, width, height,
2453 rates[j], j == 0,
2454 false, false);
2455 if (newmode) {
2456 drm_mode_probed_add(connector, newmode);
2457 modes++;
2458 }
2459 }
2460 }
f453ba04
DA		 2461 }
2462
2463 return modes;
2464}
9cf00977 2465
13931579
AJ		 2466static void
2467do_cvt_mode(struct detailed_timing *timing, void *c)
882f0219 2468{
13931579
AJ		 2469 struct detailed_mode_closure *closure = c;
2470 struct detailed_non_pixel *data = &timing->data.other_data;
882f0219 2471
13931579
AJ		 2472 if (data->type == EDID_DETAIL_CVT_3BYTE)
2473 closure->modes += drm_cvt_modes(closure->connector, timing);
2474}
882f0219 2475
13931579
AJ		 2476static int
2477add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2478{
2479 struct detailed_mode_closure closure = {
d456ea2e
JL		 2480 .connector = connector,
2481 .edid = edid,
13931579 2482 };
882f0219 2483
13931579
AJ		 2484 if (version_greater(edid, 1, 2))
2485 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
882f0219 2486
13931579 2487 /* XXX should also look for CVT codes in VTB blocks */
882f0219 2488
13931579
AJ		 2489 return closure.modes;
2490}
2491
fa3a7340
VS		 2492static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
2493
13931579
AJ		 2494static void
2495do_detailed_mode(struct detailed_timing *timing, void *c)
2496{
2497 struct detailed_mode_closure *closure = c;
2498 struct drm_display_mode *newmode;
2499
2500 if (timing->pixel_clock) {
2501 newmode = drm_mode_detailed(closure->connector->dev,
2502 closure->edid, timing,
2503 closure->quirks);
2504 if (!newmode)
2505 return;
2506
2507 if (closure->preferred)
2508 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2509
fa3a7340
VS		 2510 /*
2511 * Detailed modes are limited to 10kHz pixel clock resolution,
2512 * so fix up anything that looks like CEA/HDMI mode, but the clock
2513 * is just slightly off.
2514 */
2515 fixup_detailed_cea_mode_clock(newmode);
2516
13931579
AJ		 2517 drm_mode_probed_add(closure->connector, newmode);
2518 closure->modes++;
2519 closure->preferred = 0;
882f0219 2520 }
13931579 2521}
882f0219 2522
13931579
AJ		 2523/*
2524 * add_detailed_modes - Add modes from detailed timings
2525 * @connector: attached connector
2526 * @edid: EDID block to scan
2527 * @quirks: quirks to apply
2528 */
2529static int
2530add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2531 u32 quirks)
2532{
2533 struct detailed_mode_closure closure = {
d456ea2e
JL		 2534 .connector = connector,
2535 .edid = edid,
2536 .preferred = 1,
2537 .quirks = quirks,
13931579
AJ		 2538 };
2539
2540 if (closure.preferred && !version_greater(edid, 1, 3))
2541 closure.preferred =
2542 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2543
2544 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2545
2546 return closure.modes;
882f0219 2547}
f453ba04 2548
8fe9790d 2549#define AUDIO_BLOCK 0x01
54ac76f8 2550#define VIDEO_BLOCK 0x02
f23c20c8 2551#define VENDOR_BLOCK 0x03
76adaa34 2552#define SPEAKER_BLOCK 0x04
b1edd6a6 2553#define VIDEO_CAPABILITY_BLOCK 0x07
8fe9790d 2554#define EDID_BASIC_AUDIO (1 << 6)
a988bc72
LPC		 2555#define EDID_CEA_YCRCB444 (1 << 5)
2556#define EDID_CEA_YCRCB422 (1 << 4)
b1edd6a6 2557#define EDID_CEA_VCDB_QS (1 << 6)
8fe9790d 2558
d4e4a31d 2559/*
8fe9790d 2560 * Search EDID for CEA extension block.
f23c20c8 2561 */
40d9b043 2562static u8 *drm_find_edid_extension(struct edid *edid, int ext_id)
f23c20c8 2563{
8fe9790d
ZW		 2564 u8 *edid_ext = NULL;
2565 int i;
f23c20c8
ML		 2566
2567 /* No EDID or EDID extensions */
2568 if (edid == NULL || edid->extensions == 0)
8fe9790d 2569 return NULL;
f23c20c8 2570
f23c20c8 2571 /* Find CEA extension */
7466f4cc 2572 for (i = 0; i < edid->extensions; i++) {
8fe9790d 2573 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
40d9b043 2574 if (edid_ext[0] == ext_id)
f23c20c8
ML		 2575 break;
2576 }
2577
7466f4cc 2578 if (i == edid->extensions)
8fe9790d
ZW		 2579 return NULL;
2580
2581 return edid_ext;
2582}
2583
40d9b043
DA		 2584static u8 *drm_find_cea_extension(struct edid *edid)
2585{
2586 return drm_find_edid_extension(edid, CEA_EXT);
2587}
2588
2589static u8 *drm_find_displayid_extension(struct edid *edid)
2590{
2591 return drm_find_edid_extension(edid, DISPLAYID_EXT);
2592}
2593
e6e79209
VS		 2594/*
2595 * Calculate the alternate clock for the CEA mode
2596 * (60Hz vs. 59.94Hz etc.)
2597 */
2598static unsigned int
2599cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2600{
2601 unsigned int clock = cea_mode->clock;
2602
2603 if (cea_mode->vrefresh % 6 != 0)
2604 return clock;
2605
2606 /*
2607 * edid_cea_modes contains the 59.94Hz
2608 * variant for 240 and 480 line modes,
2609 * and the 60Hz variant otherwise.
2610 */
2611 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
9afd808c 2612 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
e6e79209 2613 else
9afd808c 2614 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
e6e79209
VS		 2615
2616 return clock;
2617}
2618
c45a4e46
VS		 2619static bool
2620cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
2621{
2622 /*
2623 * For certain VICs the spec allows the vertical
2624 * front porch to vary by one or two lines.
2625 *
2626 * cea_modes[] stores the variant with the shortest
2627 * vertical front porch. We can adjust the mode to
2628 * get the other variants by simply increasing the
2629 * vertical front porch length.
2630 */
2631 BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 ||
2632 edid_cea_modes[9].vtotal != 262 ||
2633 edid_cea_modes[12].vtotal != 262 ||
2634 edid_cea_modes[13].vtotal != 262 ||
2635 edid_cea_modes[23].vtotal != 312 ||
2636 edid_cea_modes[24].vtotal != 312 ||
2637 edid_cea_modes[27].vtotal != 312 ||
2638 edid_cea_modes[28].vtotal != 312);
2639
2640 if (((vic == 8 || vic == 9 ||
2641 vic == 12 || vic == 13) && mode->vtotal < 263) ||
2642 ((vic == 23 || vic == 24 ||
2643 vic == 27 || vic == 28) && mode->vtotal < 314)) {
2644 mode->vsync_start++;
2645 mode->vsync_end++;
2646 mode->vtotal++;
2647
2648 return true;
2649 }
2650
2651 return false;
2652}
2653
4c6bcf44
VS		 2654static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
2655 unsigned int clock_tolerance)
2656{
d9278b4c 2657 u8 vic;
4c6bcf44
VS		 2658
2659 if (!to_match->clock)
2660 return 0;
2661
d9278b4c 2662 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
c45a4e46 2663 struct drm_display_mode cea_mode = edid_cea_modes[vic];
4c6bcf44
VS		 2664 unsigned int clock1, clock2;
2665
2666 /* Check both 60Hz and 59.94Hz */
c45a4e46
VS		 2667 clock1 = cea_mode.clock;
2668 clock2 = cea_mode_alternate_clock(&cea_mode);
4c6bcf44
VS		 2669
2670 if (abs(to_match->clock - clock1) > clock_tolerance &&
2671 abs(to_match->clock - clock2) > clock_tolerance)
2672 continue;
2673
c45a4e46
VS		 2674 do {
2675 if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode))
2676 return vic;
2677 } while (cea_mode_alternate_timings(vic, &cea_mode));
4c6bcf44
VS		 2678 }
2679
2680 return 0;
2681}
2682
18316c8c
TR		 2683/**
2684 * drm_match_cea_mode - look for a CEA mode matching given mode
2685 * @to_match: display mode
2686 *
db6cf833 2687 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
18316c8c 2688 * mode.
a4799037 2689 */
18316c8c 2690u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
a4799037 2691{
d9278b4c 2692 u8 vic;
a4799037 2693
a90b590e
VS		 2694 if (!to_match->clock)
2695 return 0;
2696
d9278b4c 2697 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
c45a4e46 2698 struct drm_display_mode cea_mode = edid_cea_modes[vic];
a90b590e
VS		 2699 unsigned int clock1, clock2;
2700
a90b590e 2701 /* Check both 60Hz and 59.94Hz */
c45a4e46
VS		 2702 clock1 = cea_mode.clock;
2703 clock2 = cea_mode_alternate_clock(&cea_mode);
a4799037 2704
c45a4e46
VS		 2705 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
2706 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
2707 continue;
2708
2709 do {
2710 if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode))
2711 return vic;
2712 } while (cea_mode_alternate_timings(vic, &cea_mode));
a4799037 2713 }
c45a4e46 2714
a4799037
SM		 2715 return 0;
2716}
2717EXPORT_SYMBOL(drm_match_cea_mode);
2718
d9278b4c
JN		 2719static bool drm_valid_cea_vic(u8 vic)
2720{
2721 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
2722}
2723
0967e6a5
VK		 2724/**
2725 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
2726 * the input VIC from the CEA mode list
2727 * @video_code: ID given to each of the CEA modes
2728 *
2729 * Returns picture aspect ratio
2730 */
2731enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
2732{
d9278b4c 2733 return edid_cea_modes[video_code].picture_aspect_ratio;
0967e6a5
VK		 2734}
2735EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
2736
3f2f6533
LD		 2737/*
2738 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
2739 * specific block).
2740 *
2741 * It's almost like cea_mode_alternate_clock(), we just need to add an
2742 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
2743 * one.
2744 */
2745static unsigned int
2746hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
2747{
2748 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
2749 return hdmi_mode->clock;
2750
2751 return cea_mode_alternate_clock(hdmi_mode);
2752}
2753
4c6bcf44
VS		 2754static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
2755 unsigned int clock_tolerance)
2756{
d9278b4c 2757 u8 vic;
4c6bcf44
VS		 2758
2759 if (!to_match->clock)
2760 return 0;
2761
d9278b4c
JN		 2762 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
2763 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4c6bcf44
VS		 2764 unsigned int clock1, clock2;
2765
2766 /* Make sure to also match alternate clocks */
2767 clock1 = hdmi_mode->clock;
2768 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
2769
2770 if (abs(to_match->clock - clock1) > clock_tolerance &&
2771 abs(to_match->clock - clock2) > clock_tolerance)
2772 continue;
2773
2774 if (drm_mode_equal_no_clocks(to_match, hdmi_mode))
d9278b4c 2775 return vic;
4c6bcf44
VS		 2776 }
2777
2778 return 0;
2779}
2780
3f2f6533
LD		 2781/*
2782 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
2783 * @to_match: display mode
2784 *
2785 * An HDMI mode is one defined in the HDMI vendor specific block.
2786 *
2787 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
2788 */
2789static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
2790{
d9278b4c 2791 u8 vic;
3f2f6533
LD		 2792
2793 if (!to_match->clock)
2794 return 0;
2795
d9278b4c
JN		 2796 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
2797 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3f2f6533
LD		 2798 unsigned int clock1, clock2;
2799
2800 /* Make sure to also match alternate clocks */
2801 clock1 = hdmi_mode->clock;
2802 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
2803
2804 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
2805 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
f2ecf2e3 2806 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode))
d9278b4c 2807 return vic;
3f2f6533
LD		 2808 }
2809 return 0;
2810}
2811
d9278b4c
JN		 2812static bool drm_valid_hdmi_vic(u8 vic)
2813{
2814 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
2815}
2816
e6e79209
VS		 2817static int
2818add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
2819{
2820 struct drm_device *dev = connector->dev;
2821 struct drm_display_mode *mode, *tmp;
2822 LIST_HEAD(list);
2823 int modes = 0;
2824
2825 /* Don't add CEA modes if the CEA extension block is missing */
2826 if (!drm_find_cea_extension(edid))
2827 return 0;
2828
2829 /*
2830 * Go through all probed modes and create a new mode
2831 * with the alternate clock for certain CEA modes.
2832 */
2833 list_for_each_entry(mode, &connector->probed_modes, head) {
3f2f6533 2834 const struct drm_display_mode *cea_mode = NULL;
e6e79209 2835 struct drm_display_mode *newmode;
d9278b4c 2836 u8 vic = drm_match_cea_mode(mode);
e6e79209
VS		 2837 unsigned int clock1, clock2;
2838
d9278b4c
JN		 2839 if (drm_valid_cea_vic(vic)) {
2840 cea_mode = &edid_cea_modes[vic];
3f2f6533
LD		 2841 clock2 = cea_mode_alternate_clock(cea_mode);
2842 } else {
d9278b4c
JN		 2843 vic = drm_match_hdmi_mode(mode);
2844 if (drm_valid_hdmi_vic(vic)) {
2845 cea_mode = &edid_4k_modes[vic];
3f2f6533
LD		 2846 clock2 = hdmi_mode_alternate_clock(cea_mode);
2847 }
2848 }
e6e79209 2849
3f2f6533
LD		 2850 if (!cea_mode)
2851 continue;
e6e79209
VS		 2852
2853 clock1 = cea_mode->clock;
e6e79209
VS		 2854
2855 if (clock1 == clock2)
2856 continue;
2857
2858 if (mode->clock != clock1 && mode->clock != clock2)
2859 continue;
2860
2861 newmode = drm_mode_duplicate(dev, cea_mode);
2862 if (!newmode)
2863 continue;
2864
27130212
DL		 2865 /* Carry over the stereo flags */
2866 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
2867
e6e79209
VS		 2868 /*
2869 * The current mode could be either variant. Make
2870 * sure to pick the "other" clock for the new mode.
2871 */
2872 if (mode->clock != clock1)
2873 newmode->clock = clock1;
2874 else
2875 newmode->clock = clock2;
2876
2877 list_add_tail(&newmode->head, &list);
2878 }
2879
2880 list_for_each_entry_safe(mode, tmp, &list, head) {
2881 list_del(&mode->head);
2882 drm_mode_probed_add(connector, mode);
2883 modes++;
2884 }
2885
2886 return modes;
2887}
a4799037 2888
aff04ace
TW		 2889static struct drm_display_mode *
2890drm_display_mode_from_vic_index(struct drm_connector *connector,
2891 const u8 *video_db, u8 video_len,
2892 u8 video_index)
54ac76f8
CS		 2893{
2894 struct drm_device *dev = connector->dev;
aff04ace 2895 struct drm_display_mode *newmode;
d9278b4c 2896 u8 vic;
54ac76f8 2897
aff04ace
TW		 2898 if (video_db == NULL || video_index >= video_len)
2899 return NULL;
2900
2901 /* CEA modes are numbered 1..127 */
d9278b4c
JN		 2902 vic = (video_db[video_index] & 127);
2903 if (!drm_valid_cea_vic(vic))
aff04ace
TW		 2904 return NULL;
2905
d9278b4c 2906 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
409bbf1e
DL		 2907 if (!newmode)
2908 return NULL;
2909
aff04ace
TW		 2910 newmode->vrefresh = 0;
2911
2912 return newmode;
2913}
2914
2915static int
2916do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
2917{
2918 int i, modes = 0;
2919
2920 for (i = 0; i < len; i++) {
2921 struct drm_display_mode *mode;
2922 mode = drm_display_mode_from_vic_index(connector, db, len, i);
2923 if (mode) {
2924 drm_mode_probed_add(connector, mode);
2925 modes++;
54ac76f8
CS		 2926 }
2927 }
2928
2929 return modes;
2930}
2931
c858cfca
DL		 2932struct stereo_mandatory_mode {
2933 int width, height, vrefresh;
2934 unsigned int flags;
2935};
2936
2937static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
f7e121b7
DL		 2938 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2939 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
c858cfca
DL		 2940 { 1920, 1080, 50,
2941 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
2942 { 1920, 1080, 60,
2943 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
f7e121b7
DL		 2944 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2945 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
2946 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2947 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
c858cfca
DL		 2948};
2949
2950static bool
2951stereo_match_mandatory(const struct drm_display_mode *mode,
2952 const struct stereo_mandatory_mode *stereo_mode)
2953{
2954 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
2955
2956 return mode->hdisplay == stereo_mode->width &&
2957 mode->vdisplay == stereo_mode->height &&
2958 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
2959 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
2960}
2961
c858cfca
DL		 2962static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
2963{
2964 struct drm_device *dev = connector->dev;
2965 const struct drm_display_mode *mode;
2966 struct list_head stereo_modes;
f7e121b7 2967 int modes = 0, i;
c858cfca
DL		 2968
2969 INIT_LIST_HEAD(&stereo_modes);
2970
2971 list_for_each_entry(mode, &connector->probed_modes, head) {
f7e121b7
DL		 2972 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
2973 const struct stereo_mandatory_mode *mandatory;
c858cfca
DL		 2974 struct drm_display_mode *new_mode;
2975
f7e121b7
DL		 2976 if (!stereo_match_mandatory(mode,
2977 &stereo_mandatory_modes[i]))
2978 continue;
c858cfca 2979
f7e121b7 2980 mandatory = &stereo_mandatory_modes[i];
c858cfca
DL		 2981 new_mode = drm_mode_duplicate(dev, mode);
2982 if (!new_mode)
2983 continue;
2984
f7e121b7 2985 new_mode->flags |= mandatory->flags;
c858cfca
DL		 2986 list_add_tail(&new_mode->head, &stereo_modes);
2987 modes++;
f7e121b7 2988 }
c858cfca
DL		 2989 }
2990
2991 list_splice_tail(&stereo_modes, &connector->probed_modes);
2992
2993 return modes;
2994}
2995
1deee8d7
DL		 2996static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
2997{
2998 struct drm_device *dev = connector->dev;
2999 struct drm_display_mode *newmode;
3000
d9278b4c 3001 if (!drm_valid_hdmi_vic(vic)) {
1deee8d7
DL		 3002 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3003 return 0;
3004 }
3005
3006 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3007 if (!newmode)
3008 return 0;
3009
3010 drm_mode_probed_add(connector, newmode);
3011
3012 return 1;
3013}
3014
fbf46025
TW		 3015static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3016 const u8 *video_db, u8 video_len, u8 video_index)
3017{
fbf46025
TW		 3018 struct drm_display_mode *newmode;
3019 int modes = 0;
fbf46025
TW		 3020
3021 if (structure & (1 << 0)) {
aff04ace
TW		 3022 newmode = drm_display_mode_from_vic_index(connector, video_db,
3023 video_len,
3024 video_index);
fbf46025
TW		 3025 if (newmode) {
3026 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3027 drm_mode_probed_add(connector, newmode);
3028 modes++;
3029 }
3030 }
3031 if (structure & (1 << 6)) {
aff04ace
TW		 3032 newmode = drm_display_mode_from_vic_index(connector, video_db,
3033 video_len,
3034 video_index);
fbf46025
TW		 3035 if (newmode) {
3036 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3037 drm_mode_probed_add(connector, newmode);
3038 modes++;
3039 }
3040 }
3041 if (structure & (1 << 8)) {
aff04ace
TW		 3042 newmode = drm_display_mode_from_vic_index(connector, video_db,
3043 video_len,
3044 video_index);
fbf46025 3045 if (newmode) {
89570eeb 3046 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
fbf46025
TW		 3047 drm_mode_probed_add(connector, newmode);
3048 modes++;
3049 }
3050 }
3051
3052 return modes;
3053}
3054
7ebe1963
LD		 3055/*
3056 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3057 * @connector: connector corresponding to the HDMI sink
3058 * @db: start of the CEA vendor specific block
3059 * @len: length of the CEA block payload, ie. one can access up to db[len]
3060 *
c858cfca
DL		 3061 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3062 * also adds the stereo 3d modes when applicable.
7ebe1963
LD		 3063 */
3064static int
fbf46025
TW		 3065do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3066 const u8 *video_db, u8 video_len)
7ebe1963 3067{
0e5083aa 3068 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
fbf46025
TW		 3069 u8 vic_len, hdmi_3d_len = 0;
3070 u16 mask;
3071 u16 structure_all;
7ebe1963
LD		 3072
3073 if (len < 8)
3074 goto out;
3075
3076 /* no HDMI_Video_Present */
3077 if (!(db[8] & (1 << 5)))
3078 goto out;
3079
3080 /* Latency_Fields_Present */
3081 if (db[8] & (1 << 7))
3082 offset += 2;
3083
3084 /* I_Latency_Fields_Present */
3085 if (db[8] & (1 << 6))
3086 offset += 2;
3087
3088 /* the declared length is not long enough for the 2 first bytes
3089 * of additional video format capabilities */
c858cfca 3090 if (len < (8 + offset + 2))
7ebe1963
LD		 3091 goto out;
3092
c858cfca
DL		 3093 /* 3D_Present */
3094 offset++;
fbf46025 3095 if (db[8 + offset] & (1 << 7)) {
c858cfca
DL		 3096 modes += add_hdmi_mandatory_stereo_modes(connector);
3097
fbf46025
TW		 3098 /* 3D_Multi_present */
3099 multi_present = (db[8 + offset] & 0x60) >> 5;
3100 }
3101
c858cfca 3102 offset++;
7ebe1963 3103 vic_len = db[8 + offset] >> 5;
fbf46025 3104 hdmi_3d_len = db[8 + offset] & 0x1f;
7ebe1963
LD		 3105
3106 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
7ebe1963
LD		 3107 u8 vic;
3108
3109 vic = db[9 + offset + i];
1deee8d7 3110 modes += add_hdmi_mode(connector, vic);
7ebe1963 3111 }
fbf46025
TW		 3112 offset += 1 + vic_len;
3113
0e5083aa
TW		 3114 if (multi_present == 1)
3115 multi_len = 2;
3116 else if (multi_present == 2)
3117 multi_len = 4;
3118 else
3119 multi_len = 0;
fbf46025 3120
0e5083aa 3121 if (len < (8 + offset + hdmi_3d_len - 1))
fbf46025
TW		 3122 goto out;
3123
0e5083aa 3124 if (hdmi_3d_len < multi_len)
fbf46025
TW		 3125 goto out;
3126
0e5083aa
TW		 3127 if (multi_present == 1 || multi_present == 2) {
3128 /* 3D_Structure_ALL */
3129 structure_all = (db[8 + offset] << 8) | db[9 + offset];
fbf46025 3130
0e5083aa
TW		 3131 /* check if 3D_MASK is present */
3132 if (multi_present == 2)
3133 mask = (db[10 + offset] << 8) | db[11 + offset];
3134 else
3135 mask = 0xffff;
3136
3137 for (i = 0; i < 16; i++) {
3138 if (mask & (1 << i))
3139 modes += add_3d_struct_modes(connector,
3140 structure_all,
3141 video_db,
3142 video_len, i);
3143 }
3144 }
3145
3146 offset += multi_len;
3147
3148 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3149 int vic_index;
3150 struct drm_display_mode *newmode = NULL;
3151 unsigned int newflag = 0;
3152 bool detail_present;
3153
3154 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3155
3156 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3157 break;
3158
3159 /* 2D_VIC_order_X */
3160 vic_index = db[8 + offset + i] >> 4;
3161
3162 /* 3D_Structure_X */
3163 switch (db[8 + offset + i] & 0x0f) {
3164 case 0:
3165 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3166 break;
3167 case 6:
3168 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3169 break;
3170 case 8:
3171 /* 3D_Detail_X */
3172 if ((db[9 + offset + i] >> 4) == 1)
3173 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3174 break;
3175 }
3176
3177 if (newflag != 0) {
3178 newmode = drm_display_mode_from_vic_index(connector,
3179 video_db,
3180 video_len,
3181 vic_index);
3182
3183 if (newmode) {
3184 newmode->flags |= newflag;
3185 drm_mode_probed_add(connector, newmode);
3186 modes++;
3187 }
3188 }
3189
3190 if (detail_present)
3191 i++;
fbf46025 3192 }
7ebe1963
LD		 3193
3194out:
3195 return modes;
3196}
3197
9e50b9d5
VS		 3198static int
3199cea_db_payload_len(const u8 *db)
3200{
3201 return db[0] & 0x1f;
3202}
3203
3204static int
3205cea_db_tag(const u8 *db)
3206{
3207 return db[0] >> 5;
3208}
3209
3210static int
3211cea_revision(const u8 *cea)
3212{
3213 return cea[1];
3214}
3215
3216static int
3217cea_db_offsets(const u8 *cea, int *start, int *end)
3218{
3219 /* Data block offset in CEA extension block */
3220 *start = 4;
3221 *end = cea[2];
3222 if (*end == 0)
3223 *end = 127;
3224 if (*end < 4 || *end > 127)
3225 return -ERANGE;
3226 return 0;
3227}
3228
7ebe1963
LD		 3229static bool cea_db_is_hdmi_vsdb(const u8 *db)
3230{
3231 int hdmi_id;
3232
3233 if (cea_db_tag(db) != VENDOR_BLOCK)
3234 return false;
3235
3236 if (cea_db_payload_len(db) < 5)
3237 return false;
3238
3239 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3240
6cb3b7f1 3241 return hdmi_id == HDMI_IEEE_OUI;
7ebe1963
LD		 3242}
3243
9e50b9d5
VS		 3244#define for_each_cea_db(cea, i, start, end) \
3245 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3246
54ac76f8
CS		 3247static int
3248add_cea_modes(struct drm_connector *connector, struct edid *edid)
3249{
13ac3f55 3250 const u8 *cea = drm_find_cea_extension(edid);
fbf46025
TW		 3251 const u8 *db, *hdmi = NULL, *video = NULL;
3252 u8 dbl, hdmi_len, video_len = 0;
54ac76f8
CS		 3253 int modes = 0;
3254
9e50b9d5
VS		 3255 if (cea && cea_revision(cea) >= 3) {
3256 int i, start, end;
3257
3258 if (cea_db_offsets(cea, &start, &end))
3259 return 0;
3260
3261 for_each_cea_db(cea, i, start, end) {
3262 db = &cea[i];
3263 dbl = cea_db_payload_len(db);
3264
fbf46025
TW		 3265 if (cea_db_tag(db) == VIDEO_BLOCK) {
3266 video = db + 1;
3267 video_len = dbl;
3268 modes += do_cea_modes(connector, video, dbl);
3269 }
c858cfca
DL		 3270 else if (cea_db_is_hdmi_vsdb(db)) {
3271 hdmi = db;
3272 hdmi_len = dbl;
3273 }
54ac76f8
CS		 3274 }
3275 }
3276
c858cfca
DL		 3277 /*
3278 * We parse the HDMI VSDB after having added the cea modes as we will
3279 * be patching their flags when the sink supports stereo 3D.
3280 */
3281 if (hdmi)
fbf46025
TW		 3282 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
3283 video_len);
c858cfca 3284
54ac76f8
CS		 3285 return modes;
3286}
3287
fa3a7340
VS		 3288static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
3289{
3290 const struct drm_display_mode *cea_mode;
3291 int clock1, clock2, clock;
d9278b4c 3292 u8 vic;
fa3a7340
VS		 3293 const char *type;
3294
4c6bcf44
VS		 3295 /*
3296 * allow 5kHz clock difference either way to account for
3297 * the 10kHz clock resolution limit of detailed timings.
3298 */
d9278b4c
JN		 3299 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
3300 if (drm_valid_cea_vic(vic)) {
fa3a7340 3301 type = "CEA";
d9278b4c 3302 cea_mode = &edid_cea_modes[vic];
fa3a7340
VS		 3303 clock1 = cea_mode->clock;
3304 clock2 = cea_mode_alternate_clock(cea_mode);
3305 } else {
d9278b4c
JN		 3306 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
3307 if (drm_valid_hdmi_vic(vic)) {
fa3a7340 3308 type = "HDMI";
d9278b4c 3309 cea_mode = &edid_4k_modes[vic];
fa3a7340
VS		 3310 clock1 = cea_mode->clock;
3311 clock2 = hdmi_mode_alternate_clock(cea_mode);
3312 } else {
3313 return;
3314 }
3315 }
3316
3317 /* pick whichever is closest */
3318 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
3319 clock = clock1;
3320 else
3321 clock = clock2;
3322
3323 if (mode->clock == clock)
3324 return;
3325
3326 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
d9278b4c 3327 type, vic, mode->clock, clock);
fa3a7340
VS		 3328 mode->clock = clock;
3329}
3330
76adaa34 3331static void
23ebf8b9 3332drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
76adaa34 3333{
8504072a 3334 u8 len = cea_db_payload_len(db);
76adaa34 3335
23ebf8b9 3336 if (len >= 6)
8504072a 3337 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */
8504072a
VS		 3338 if (len >= 8) {
3339 connector->latency_present[0] = db[8] >> 7;
3340 connector->latency_present[1] = (db[8] >> 6) & 1;
3341 }
3342 if (len >= 9)
3343 connector->video_latency[0] = db[9];
3344 if (len >= 10)
3345 connector->audio_latency[0] = db[10];
3346 if (len >= 11)
3347 connector->video_latency[1] = db[11];
3348 if (len >= 12)
3349 connector->audio_latency[1] = db[12];
76adaa34 3350
23ebf8b9
VS		 3351 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
3352 "video latency %d %d, "
3353 "audio latency %d %d\n",
3354 connector->latency_present[0],
3355 connector->latency_present[1],
3356 connector->video_latency[0],
3357 connector->video_latency[1],
3358 connector->audio_latency[0],
3359 connector->audio_latency[1]);
76adaa34
WF		 3360}
3361
3362static void
3363monitor_name(struct detailed_timing *t, void *data)
3364{
3365 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
3366 *(u8 **)data = t->data.other_data.data.str.str;
14f77fdd
VS		 3367}
3368
59f7c0fa
JB		 3369static int get_monitor_name(struct edid *edid, char name[13])
3370{
3371 char *edid_name = NULL;
3372 int mnl;
3373
3374 if (!edid || !name)
3375 return 0;
3376
3377 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
3378 for (mnl = 0; edid_name && mnl < 13; mnl++) {
3379 if (edid_name[mnl] == 0x0a)
3380 break;
3381
3382 name[mnl] = edid_name[mnl];
3383 }
3384
3385 return mnl;
3386}
3387
3388/**
3389 * drm_edid_get_monitor_name - fetch the monitor name from the edid
3390 * @edid: monitor EDID information
3391 * @name: pointer to a character array to hold the name of the monitor
3392 * @bufsize: The size of the name buffer (should be at least 14 chars.)
3393 *
3394 */
3395void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
3396{
3397 int name_length;
3398 char buf[13];
3399
3400 if (bufsize <= 0)
3401 return;
3402
3403 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
3404 memcpy(name, buf, name_length);
3405 name[name_length] = '\0';
3406}
3407EXPORT_SYMBOL(drm_edid_get_monitor_name);
3408
76adaa34
WF		 3409/**
3410 * drm_edid_to_eld - build ELD from EDID
3411 * @connector: connector corresponding to the HDMI/DP sink
3412 * @edid: EDID to parse
3413 *
db6cf833
TR		 3414 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
3415 * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to
3416 * fill in.
76adaa34
WF		 3417 */
3418void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
3419{
3420 uint8_t *eld = connector->eld;
3421 u8 *cea;
76adaa34 3422 u8 *db;
7c018782 3423 int total_sad_count = 0;
76adaa34
WF		 3424 int mnl;
3425 int dbl;
3426
3427 memset(eld, 0, sizeof(connector->eld));
3428
85c91580
VS		 3429 connector->latency_present[0] = false;
3430 connector->latency_present[1] = false;
3431 connector->video_latency[0] = 0;
3432 connector->audio_latency[0] = 0;
3433 connector->video_latency[1] = 0;
3434 connector->audio_latency[1] = 0;
3435
76adaa34
WF		 3436 cea = drm_find_cea_extension(edid);
3437 if (!cea) {
3438 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
3439 return;
3440 }
3441
59f7c0fa
JB		 3442 mnl = get_monitor_name(edid, eld + 20);
3443
76adaa34
WF		 3444 eld[4] = (cea[1] << 5) | mnl;
3445 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20);
3446
3447 eld[0] = 2 << 3; /* ELD version: 2 */
3448
3449 eld[16] = edid->mfg_id[0];
3450 eld[17] = edid->mfg_id[1];
3451 eld[18] = edid->prod_code[0];
3452 eld[19] = edid->prod_code[1];
3453
9e50b9d5
VS		 3454 if (cea_revision(cea) >= 3) {
3455 int i, start, end;
3456
3457 if (cea_db_offsets(cea, &start, &end)) {
3458 start = 0;
3459 end = 0;
3460 }
3461
3462 for_each_cea_db(cea, i, start, end) {
3463 db = &cea[i];
3464 dbl = cea_db_payload_len(db);
3465
3466 switch (cea_db_tag(db)) {
7c018782
VS		 3467 int sad_count;
3468
a0ab734d
CS		 3469 case AUDIO_BLOCK:
3470 /* Audio Data Block, contains SADs */
7c018782
VS		 3471 sad_count = min(dbl / 3, 15 - total_sad_count);
3472 if (sad_count >= 1)
3473 memcpy(eld + 20 + mnl + total_sad_count * 3,
3474 &db[1], sad_count * 3);
3475 total_sad_count += sad_count;
a0ab734d
CS		 3476 break;
3477 case SPEAKER_BLOCK:
9e50b9d5
VS		 3478 /* Speaker Allocation Data Block */
3479 if (dbl >= 1)
3480 eld[7] = db[1];
a0ab734d
CS		 3481 break;
3482 case VENDOR_BLOCK:
3483 /* HDMI Vendor-Specific Data Block */
14f77fdd 3484 if (cea_db_is_hdmi_vsdb(db))
23ebf8b9 3485 drm_parse_hdmi_vsdb_audio(connector, db);
a0ab734d
CS		 3486 break;
3487 default:
3488 break;
3489 }
76adaa34 3490 }
9e50b9d5 3491 }
7c018782 3492 eld[5] |= total_sad_count << 4;
76adaa34 3493
938fd8aa
JN		 3494 eld[DRM_ELD_BASELINE_ELD_LEN] =
3495 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
3496
3497 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
7c018782 3498 drm_eld_size(eld), total_sad_count);
76adaa34
WF		 3499}
3500EXPORT_SYMBOL(drm_edid_to_eld);
3501
fe214163
RM		 3502/**
3503 * drm_edid_to_sad - extracts SADs from EDID
3504 * @edid: EDID to parse
3505 * @sads: pointer that will be set to the extracted SADs
3506 *
3507 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
fe214163 3508 *
db6cf833
TR		 3509 * Note: The returned pointer needs to be freed using kfree().
3510 *
3511 * Return: The number of found SADs or negative number on error.
fe214163
RM		 3512 */
3513int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
3514{
3515 int count = 0;
3516 int i, start, end, dbl;
3517 u8 *cea;
3518
3519 cea = drm_find_cea_extension(edid);
3520 if (!cea) {
3521 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3522 return -ENOENT;
3523 }
3524
3525 if (cea_revision(cea) < 3) {
3526 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3527 return -ENOTSUPP;
3528 }
3529
3530 if (cea_db_offsets(cea, &start, &end)) {
3531 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3532 return -EPROTO;
3533 }
3534
3535 for_each_cea_db(cea, i, start, end) {
3536 u8 *db = &cea[i];
3537
3538 if (cea_db_tag(db) == AUDIO_BLOCK) {
3539 int j;
3540 dbl = cea_db_payload_len(db);
3541
3542 count = dbl / 3; /* SAD is 3B */
3543 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
3544 if (!*sads)
3545 return -ENOMEM;
3546 for (j = 0; j < count; j++) {
3547 u8 *sad = &db[1 + j * 3];
3548
3549 (*sads)[j].format = (sad[0] & 0x78) >> 3;
3550 (*sads)[j].channels = sad[0] & 0x7;
3551 (*sads)[j].freq = sad[1] & 0x7F;
3552 (*sads)[j].byte2 = sad[2];
3553 }
3554 break;
3555 }
3556 }
3557
3558 return count;
3559}
3560EXPORT_SYMBOL(drm_edid_to_sad);
3561
d105f476
AD		 3562/**
3563 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
3564 * @edid: EDID to parse
3565 * @sadb: pointer to the speaker block
3566 *
3567 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
d105f476 3568 *
db6cf833
TR		 3569 * Note: The returned pointer needs to be freed using kfree().
3570 *
3571 * Return: The number of found Speaker Allocation Blocks or negative number on
3572 * error.
d105f476
AD		 3573 */
3574int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
3575{
3576 int count = 0;
3577 int i, start, end, dbl;
3578 const u8 *cea;
3579
3580 cea = drm_find_cea_extension(edid);
3581 if (!cea) {
3582 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3583 return -ENOENT;
3584 }
3585
3586 if (cea_revision(cea) < 3) {
3587 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3588 return -ENOTSUPP;
3589 }
3590
3591 if (cea_db_offsets(cea, &start, &end)) {
3592 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3593 return -EPROTO;
3594 }
3595
3596 for_each_cea_db(cea, i, start, end) {
3597 const u8 *db = &cea[i];
3598
3599 if (cea_db_tag(db) == SPEAKER_BLOCK) {
3600 dbl = cea_db_payload_len(db);
3601
3602 /* Speaker Allocation Data Block */
3603 if (dbl == 3) {
89086bca 3604 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
618e3776
AD		 3605 if (!*sadb)
3606 return -ENOMEM;
d105f476
AD		 3607 count = dbl;
3608 break;
3609 }
3610 }
3611 }
3612
3613 return count;
3614}
3615EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
3616
76adaa34 3617/**
db6cf833 3618 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
76adaa34
WF		 3619 * @connector: connector associated with the HDMI/DP sink
3620 * @mode: the display mode
db6cf833
TR		 3621 *
3622 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
3623 * the sink doesn't support audio or video.
76adaa34
WF		 3624 */
3625int drm_av_sync_delay(struct drm_connector *connector,
3a818d35 3626 const struct drm_display_mode *mode)
76adaa34
WF		 3627{
3628 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
3629 int a, v;
3630
3631 if (!connector->latency_present[0])
3632 return 0;
3633 if (!connector->latency_present[1])
3634 i = 0;
3635
3636 a = connector->audio_latency[i];
3637 v = connector->video_latency[i];
3638
3639 /*
3640 * HDMI/DP sink doesn't support audio or video?
3641 */
3642 if (a == 255 || v == 255)
3643 return 0;
3644
3645 /*
3646 * Convert raw EDID values to millisecond.
3647 * Treat unknown latency as 0ms.
3648 */
3649 if (a)
3650 a = min(2 * (a - 1), 500);
3651 if (v)
3652 v = min(2 * (v - 1), 500);
3653
3654 return max(v - a, 0);
3655}
3656EXPORT_SYMBOL(drm_av_sync_delay);
3657
8fe9790d 3658/**
db6cf833 3659 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
8fe9790d
ZW		 3660 * @edid: monitor EDID information
3661 *
3662 * Parse the CEA extension according to CEA-861-B.
db6cf833
TR		 3663 *
3664 * Return: True if the monitor is HDMI, false if not or unknown.
8fe9790d
ZW		 3665 */
3666bool drm_detect_hdmi_monitor(struct edid *edid)
3667{
3668 u8 *edid_ext;
14f77fdd 3669 int i;
8fe9790d 3670 int start_offset, end_offset;
8fe9790d
ZW		 3671
3672 edid_ext = drm_find_cea_extension(edid);
3673 if (!edid_ext)
14f77fdd 3674 return false;
f23c20c8 3675
9e50b9d5 3676 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
14f77fdd 3677 return false;
f23c20c8
ML		 3678
3679 /*
3680 * Because HDMI identifier is in Vendor Specific Block,
3681 * search it from all data blocks of CEA extension.
3682 */
9e50b9d5 3683 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
14f77fdd
VS		 3684 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
3685 return true;
f23c20c8
ML		 3686 }
3687
14f77fdd 3688 return false;
f23c20c8
ML		 3689}
3690EXPORT_SYMBOL(drm_detect_hdmi_monitor);
3691
8fe9790d
ZW		 3692/**
3693 * drm_detect_monitor_audio - check monitor audio capability
fc66811c 3694 * @edid: EDID block to scan
8fe9790d
ZW		 3695 *
3696 * Monitor should have CEA extension block.
3697 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
3698 * audio' only. If there is any audio extension block and supported
3699 * audio format, assume at least 'basic audio' support, even if 'basic
3700 * audio' is not defined in EDID.
3701 *
db6cf833 3702 * Return: True if the monitor supports audio, false otherwise.
8fe9790d
ZW		 3703 */
3704bool drm_detect_monitor_audio(struct edid *edid)
3705{
3706 u8 *edid_ext;
3707 int i, j;
3708 bool has_audio = false;
3709 int start_offset, end_offset;
3710
3711 edid_ext = drm_find_cea_extension(edid);
3712 if (!edid_ext)
3713 goto end;
3714
3715 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
3716
3717 if (has_audio) {
3718 DRM_DEBUG_KMS("Monitor has basic audio support\n");
3719 goto end;
3720 }
3721
9e50b9d5
VS		 3722 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3723 goto end;
8fe9790d 3724
9e50b9d5
VS		 3725 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3726 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
8fe9790d 3727 has_audio = true;
9e50b9d5 3728 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
8fe9790d
ZW		 3729 DRM_DEBUG_KMS("CEA audio format %d\n",
3730 (edid_ext[i + j] >> 3) & 0xf);
3731 goto end;
3732 }
3733 }
3734end:
3735 return has_audio;
3736}
3737EXPORT_SYMBOL(drm_detect_monitor_audio);
3738
b1edd6a6
VS		 3739/**
3740 * drm_rgb_quant_range_selectable - is RGB quantization range selectable?
fc66811c 3741 * @edid: EDID block to scan
b1edd6a6
VS		 3742 *
3743 * Check whether the monitor reports the RGB quantization range selection
3744 * as supported. The AVI infoframe can then be used to inform the monitor
3745 * which quantization range (full or limited) is used.
db6cf833
TR		 3746 *
3747 * Return: True if the RGB quantization range is selectable, false otherwise.
b1edd6a6
VS		 3748 */
3749bool drm_rgb_quant_range_selectable(struct edid *edid)
3750{
3751 u8 *edid_ext;
3752 int i, start, end;
3753
3754 edid_ext = drm_find_cea_extension(edid);
3755 if (!edid_ext)
3756 return false;
3757
3758 if (cea_db_offsets(edid_ext, &start, &end))
3759 return false;
3760
3761 for_each_cea_db(edid_ext, i, start, end) {
3762 if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK &&
3763 cea_db_payload_len(&edid_ext[i]) == 2) {
3764 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]);
3765 return edid_ext[i + 2] & EDID_CEA_VCDB_QS;
3766 }
3767 }
3768
3769 return false;
3770}
3771EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
3772
c8127cf0
VS		 3773/**
3774 * drm_default_rgb_quant_range - default RGB quantization range
3775 * @mode: display mode
3776 *
3777 * Determine the default RGB quantization range for the mode,
3778 * as specified in CEA-861.
3779 *
3780 * Return: The default RGB quantization range for the mode
3781 */
3782enum hdmi_quantization_range
3783drm_default_rgb_quant_range(const struct drm_display_mode *mode)
3784{
3785 /* All CEA modes other than VIC 1 use limited quantization range. */
3786 return drm_match_cea_mode(mode) > 1 ?
3787 HDMI_QUANTIZATION_RANGE_LIMITED :
3788 HDMI_QUANTIZATION_RANGE_FULL;
3789}
3790EXPORT_SYMBOL(drm_default_rgb_quant_range);
3791
1cea146a
VS		 3792static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
3793 const u8 *hdmi)
d0c94692 3794{
1826750f 3795 struct drm_display_info *info = &connector->display_info;
d0c94692
MK		 3796 unsigned int dc_bpc = 0;
3797
1cea146a
VS		 3798 /* HDMI supports at least 8 bpc */
3799 info->bpc = 8;
d0c94692 3800
1cea146a
VS		 3801 if (cea_db_payload_len(hdmi) < 6)
3802 return;
3803
3804 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
3805 dc_bpc = 10;
3806 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
3807 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
3808 connector->name);
3809 }
3810
3811 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
3812 dc_bpc = 12;
3813 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
3814 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
3815 connector->name);
3816 }
3817
3818 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
3819 dc_bpc = 16;
3820 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
3821 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
3822 connector->name);
3823 }
3824
3825 if (dc_bpc == 0) {
3826 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
3827 connector->name);
3828 return;
3829 }
3830
3831 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
3832 connector->name, dc_bpc);
3833 info->bpc = dc_bpc;
d0c94692
MK		 3834
3835 /*
1cea146a
VS		 3836 * Deep color support mandates RGB444 support for all video
3837 * modes and forbids YCRCB422 support for all video modes per
3838 * HDMI 1.3 spec.
d0c94692 3839 */
1cea146a 3840 info->color_formats = DRM_COLOR_FORMAT_RGB444;
d0c94692 3841
1cea146a
VS		 3842 /* YCRCB444 is optional according to spec. */
3843 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
3844 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3845 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
3846 connector->name);
3847 }
d0c94692 3848
1cea146a
VS		 3849 /*
3850 * Spec says that if any deep color mode is supported at all,
3851 * then deep color 36 bit must be supported.
3852 */
3853 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
3854 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
3855 connector->name);
3856 }
3857}
d0c94692 3858
23ebf8b9
VS		 3859static void
3860drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
3861{
3862 struct drm_display_info *info = &connector->display_info;
3863 u8 len = cea_db_payload_len(db);
3864
3865 if (len >= 6)
3866 info->dvi_dual = db[6] & 1;
3867 if (len >= 7)
3868 info->max_tmds_clock = db[7] * 5000;
3869
3870 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
3871 "max TMDS clock %d kHz\n",
3872 info->dvi_dual,
3873 info->max_tmds_clock);
3874
3875 drm_parse_hdmi_deep_color_info(connector, db);
3876}
3877
1cea146a
VS		 3878static void drm_parse_cea_ext(struct drm_connector *connector,
3879 struct edid *edid)
3880{
3881 struct drm_display_info *info = &connector->display_info;
3882 const u8 *edid_ext;
3883 int i, start, end;
d0c94692 3884
1cea146a
VS		 3885 edid_ext = drm_find_cea_extension(edid);
3886 if (!edid_ext)
3887 return;
d0c94692 3888
1cea146a 3889 info->cea_rev = edid_ext[1];
d0c94692 3890
1cea146a
VS		 3891 /* The existence of a CEA block should imply RGB support */
3892 info->color_formats = DRM_COLOR_FORMAT_RGB444;
3893 if (edid_ext[3] & EDID_CEA_YCRCB444)
3894 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3895 if (edid_ext[3] & EDID_CEA_YCRCB422)
3896 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
3897
3898 if (cea_db_offsets(edid_ext, &start, &end))
3899 return;
3900
3901 for_each_cea_db(edid_ext, i, start, end) {
3902 const u8 *db = &edid_ext[i];
3903
23ebf8b9
VS		 3904 if (cea_db_is_hdmi_vsdb(db))
3905 drm_parse_hdmi_vsdb_video(connector, db);
1cea146a 3906 }
d0c94692
MK		 3907}
3908
1cea146a
VS		 3909static void drm_add_display_info(struct drm_connector *connector,
3910 struct edid *edid)
3b11228b 3911{
1826750f 3912 struct drm_display_info *info = &connector->display_info;
ebec9a7b 3913
3b11228b
JB		 3914 info->width_mm = edid->width_cm * 10;
3915 info->height_mm = edid->height_cm * 10;
3916
3917 /* driver figures it out in this case */
3918 info->bpc = 0;
da05a5a7 3919 info->color_formats = 0;
011acce2 3920 info->cea_rev = 0;
23ebf8b9
VS		 3921 info->max_tmds_clock = 0;
3922 info->dvi_dual = false;
3b11228b 3923
a988bc72 3924 if (edid->revision < 3)
3b11228b
JB		 3925 return;
3926
3927 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
3928 return;
3929
1cea146a 3930 drm_parse_cea_ext(connector, edid);
d0c94692 3931
210a021d
MK		 3932 /*
3933 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
3934 *
3935 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
3936 * tells us to assume 8 bpc color depth if the EDID doesn't have
3937 * extensions which tell otherwise.
3938 */
3939 if ((info->bpc == 0) && (edid->revision < 4) &&
3940 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) {
3941 info->bpc = 8;
3942 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
3943 connector->name, info->bpc);
3944 }
3945
a988bc72
LPC		 3946 /* Only defined for 1.4 with digital displays */
3947 if (edid->revision < 4)
3948 return;
3949
3b11228b
JB		 3950 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
3951 case DRM_EDID_DIGITAL_DEPTH_6:
3952 info->bpc = 6;
3953 break;
3954 case DRM_EDID_DIGITAL_DEPTH_8:
3955 info->bpc = 8;
3956 break;
3957 case DRM_EDID_DIGITAL_DEPTH_10:
3958 info->bpc = 10;
3959 break;
3960 case DRM_EDID_DIGITAL_DEPTH_12:
3961 info->bpc = 12;
3962 break;
3963 case DRM_EDID_DIGITAL_DEPTH_14:
3964 info->bpc = 14;
3965 break;
3966 case DRM_EDID_DIGITAL_DEPTH_16:
3967 info->bpc = 16;
3968 break;
3969 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
3970 default:
3971 info->bpc = 0;
3972 break;
3973 }
da05a5a7 3974
d0c94692 3975 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
25933820 3976 connector->name, info->bpc);
d0c94692 3977
a988bc72 3978 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
ee58808d
LPC		 3979 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
3980 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3981 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
3982 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
3b11228b
JB		 3983}
3984
c9729177
DA		 3985static int validate_displayid(u8 *displayid, int length, int idx)
3986{
3987 int i;
3988 u8 csum = 0;
3989 struct displayid_hdr *base;
3990
3991 base = (struct displayid_hdr *)&displayid[idx];
3992
3993 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
3994 base->rev, base->bytes, base->prod_id, base->ext_count);
3995
3996 if (base->bytes + 5 > length - idx)
3997 return -EINVAL;
3998 for (i = idx; i <= base->bytes + 5; i++) {
3999 csum += displayid[i];
4000 }
4001 if (csum) {
4002 DRM_ERROR("DisplayID checksum invalid, remainder is %d\n", csum);
4003 return -EINVAL;
4004 }
4005 return 0;
4006}
4007
a39ed680
DA		 4008static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
4009 struct displayid_detailed_timings_1 *timings)
4010{
4011 struct drm_display_mode *mode;
4012 unsigned pixel_clock = (timings->pixel_clock[0] |
4013 (timings->pixel_clock[1] << 8) |
4014 (timings->pixel_clock[2] << 16));
4015 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
4016 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
4017 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
4018 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
4019 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
4020 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
4021 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
4022 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
4023 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
4024 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
4025 mode = drm_mode_create(dev);
4026 if (!mode)
4027 return NULL;
4028
4029 mode->clock = pixel_clock * 10;
4030 mode->hdisplay = hactive;
4031 mode->hsync_start = mode->hdisplay + hsync;
4032 mode->hsync_end = mode->hsync_start + hsync_width;
4033 mode->htotal = mode->hdisplay + hblank;
4034
4035 mode->vdisplay = vactive;
4036 mode->vsync_start = mode->vdisplay + vsync;
4037 mode->vsync_end = mode->vsync_start + vsync_width;
4038 mode->vtotal = mode->vdisplay + vblank;
4039
4040 mode->flags = 0;
4041 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4042 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4043 mode->type = DRM_MODE_TYPE_DRIVER;
4044
4045 if (timings->flags & 0x80)
4046 mode->type |= DRM_MODE_TYPE_PREFERRED;
4047 mode->vrefresh = drm_mode_vrefresh(mode);
4048 drm_mode_set_name(mode);
4049
4050 return mode;
4051}
4052
4053static int add_displayid_detailed_1_modes(struct drm_connector *connector,
4054 struct displayid_block *block)
4055{
4056 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
4057 int i;
4058 int num_timings;
4059 struct drm_display_mode *newmode;
4060 int num_modes = 0;
4061 /* blocks must be multiple of 20 bytes length */
4062 if (block->num_bytes % 20)
4063 return 0;
4064
4065 num_timings = block->num_bytes / 20;
4066 for (i = 0; i < num_timings; i++) {
4067 struct displayid_detailed_timings_1 *timings = &det->timings[i];
4068
4069 newmode = drm_mode_displayid_detailed(connector->dev, timings);
4070 if (!newmode)
4071 continue;
4072
4073 drm_mode_probed_add(connector, newmode);
4074 num_modes++;
4075 }
4076 return num_modes;
4077}
4078
4079static int add_displayid_detailed_modes(struct drm_connector *connector,
4080 struct edid *edid)
4081{
4082 u8 *displayid;
4083 int ret;
4084 int idx = 1;
4085 int length = EDID_LENGTH;
4086 struct displayid_block *block;
4087 int num_modes = 0;
4088
4089 displayid = drm_find_displayid_extension(edid);
4090 if (!displayid)
4091 return 0;
4092
4093 ret = validate_displayid(displayid, length, idx);
4094 if (ret)
4095 return 0;
4096
4097 idx += sizeof(struct displayid_hdr);
4098 while (block = (struct displayid_block *)&displayid[idx],
4099 idx + sizeof(struct displayid_block) <= length &&
4100 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
4101 block->num_bytes > 0) {
4102 idx += block->num_bytes + sizeof(struct displayid_block);
4103 switch (block->tag) {
4104 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4105 num_modes += add_displayid_detailed_1_modes(connector, block);
4106 break;
4107 }
4108 }
4109 return num_modes;
4110}
4111
f453ba04
DA		 4112/**
4113 * drm_add_edid_modes - add modes from EDID data, if available
4114 * @connector: connector we're probing
db6cf833 4115 * @edid: EDID data
f453ba04 4116 *
b3c6c8bf
DV		 4117 * Add the specified modes to the connector's mode list. Also fills out the
4118 * &drm_display_info structure in @connector with any information which can be
4119 * derived from the edid.
f453ba04 4120 *
db6cf833 4121 * Return: The number of modes added or 0 if we couldn't find any.
f453ba04
DA		 4122 */
4123int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
4124{
4125 int num_modes = 0;
4126 u32 quirks;
4127
4128 if (edid == NULL) {
4129 return 0;
4130 }
3c537889 4131 if (!drm_edid_is_valid(edid)) {
dcdb1674 4132 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
25933820 4133 connector->name);
f453ba04
DA		 4134 return 0;
4135 }
4136
4137 quirks = edid_get_quirks(edid);
4138
c867df70
AJ		 4139 /*
4140 * EDID spec says modes should be preferred in this order:
4141 * - preferred detailed mode
4142 * - other detailed modes from base block
4143 * - detailed modes from extension blocks
4144 * - CVT 3-byte code modes
4145 * - standard timing codes
4146 * - established timing codes
4147 * - modes inferred from GTF or CVT range information
4148 *
13931579 4149 * We get this pretty much right.
c867df70
AJ		 4150 *
4151 * XXX order for additional mode types in extension blocks?
4152 */
13931579
AJ		 4153 num_modes += add_detailed_modes(connector, edid, quirks);
4154 num_modes += add_cvt_modes(connector, edid);
c867df70
AJ		 4155 num_modes += add_standard_modes(connector, edid);
4156 num_modes += add_established_modes(connector, edid);
54ac76f8 4157 num_modes += add_cea_modes(connector, edid);
e6e79209 4158 num_modes += add_alternate_cea_modes(connector, edid);
a39ed680 4159 num_modes += add_displayid_detailed_modes(connector, edid);
4d53dc0c
VS		 4160 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
4161 num_modes += add_inferred_modes(connector, edid);
f453ba04
DA		 4162
4163 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
4164 edid_fixup_preferred(connector, quirks);
4165
1cea146a 4166 drm_add_display_info(connector, edid);
f453ba04 4167
e10aec65
MK		 4168 if (quirks & EDID_QUIRK_FORCE_6BPC)
4169 connector->display_info.bpc = 6;
4170
49d45a31
RM		 4171 if (quirks & EDID_QUIRK_FORCE_8BPC)
4172 connector->display_info.bpc = 8;
4173
bc5b9641
MK		 4174 if (quirks & EDID_QUIRK_FORCE_12BPC)
4175 connector->display_info.bpc = 12;
4176
f453ba04
DA		 4177 return num_modes;
4178}
4179EXPORT_SYMBOL(drm_add_edid_modes);
f0fda0a4
ZY		 4180
4181/**
4182 * drm_add_modes_noedid - add modes for the connectors without EDID
4183 * @connector: connector we're probing
4184 * @hdisplay: the horizontal display limit
4185 * @vdisplay: the vertical display limit
4186 *
4187 * Add the specified modes to the connector's mode list. Only when the
4188 * hdisplay/vdisplay is not beyond the given limit, it will be added.
4189 *
db6cf833 4190 * Return: The number of modes added or 0 if we couldn't find any.
f0fda0a4
ZY		 4191 */
4192int drm_add_modes_noedid(struct drm_connector *connector,
4193 int hdisplay, int vdisplay)
4194{
4195 int i, count, num_modes = 0;
b1f559ec 4196 struct drm_display_mode *mode;
f0fda0a4
ZY		 4197 struct drm_device *dev = connector->dev;
4198
fbb40b28 4199 count = ARRAY_SIZE(drm_dmt_modes);
f0fda0a4
ZY		 4200 if (hdisplay < 0)
4201 hdisplay = 0;
4202 if (vdisplay < 0)
4203 vdisplay = 0;
4204
4205 for (i = 0; i < count; i++) {
b1f559ec 4206 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
f0fda0a4
ZY		 4207 if (hdisplay && vdisplay) {
4208 /*
4209 * Only when two are valid, they will be used to check
4210 * whether the mode should be added to the mode list of
4211 * the connector.
4212 */
4213 if (ptr->hdisplay > hdisplay ||
4214 ptr->vdisplay > vdisplay)
4215 continue;
4216 }
f985dedb
AJ		 4217 if (drm_mode_vrefresh(ptr) > 61)
4218 continue;
f0fda0a4
ZY		 4219 mode = drm_mode_duplicate(dev, ptr);
4220 if (mode) {
4221 drm_mode_probed_add(connector, mode);
4222 num_modes++;
4223 }
4224 }
4225 return num_modes;
4226}
4227EXPORT_SYMBOL(drm_add_modes_noedid);
10a85120 4228
db6cf833
TR		 4229/**
4230 * drm_set_preferred_mode - Sets the preferred mode of a connector
4231 * @connector: connector whose mode list should be processed
4232 * @hpref: horizontal resolution of preferred mode
4233 * @vpref: vertical resolution of preferred mode
4234 *
4235 * Marks a mode as preferred if it matches the resolution specified by @hpref
4236 * and @vpref.
4237 */
3cf70daf
GH		 4238void drm_set_preferred_mode(struct drm_connector *connector,
4239 int hpref, int vpref)
4240{
4241 struct drm_display_mode *mode;
4242
4243 list_for_each_entry(mode, &connector->probed_modes, head) {
db6cf833 4244 if (mode->hdisplay == hpref &&
9d3de138 4245 mode->vdisplay == vpref)
3cf70daf
GH		 4246 mode->type |= DRM_MODE_TYPE_PREFERRED;
4247 }
4248}
4249EXPORT_SYMBOL(drm_set_preferred_mode);
4250
10a85120
TR		 4251/**
4252 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
4253 * data from a DRM display mode
4254 * @frame: HDMI AVI infoframe
4255 * @mode: DRM display mode
4256 *
db6cf833 4257 * Return: 0 on success or a negative error code on failure.
10a85120
TR		 4258 */
4259int
4260drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
4261 const struct drm_display_mode *mode)
4262{
4263 int err;
4264
4265 if (!frame || !mode)
4266 return -EINVAL;
4267
4268 err = hdmi_avi_infoframe_init(frame);
4269 if (err < 0)
4270 return err;
4271
bf02db99
DL		 4272 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
4273 frame->pixel_repeat = 1;
4274
10a85120 4275 frame->video_code = drm_match_cea_mode(mode);
10a85120
TR		 4276
4277 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
0967e6a5 4278
69ab6d35
VK		 4279 /*
4280 * Populate picture aspect ratio from either
4281 * user input (if specified) or from the CEA mode list.
4282 */
4283 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 ||
4284 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9)
4285 frame->picture_aspect = mode->picture_aspect_ratio;
4286 else if (frame->video_code > 0)
0967e6a5
VK		 4287 frame->picture_aspect = drm_get_cea_aspect_ratio(
4288 frame->video_code);
4289
10a85120 4290 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
24d01805 4291 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
10a85120
TR		 4292
4293 return 0;
4294}
4295EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
83dd0008 4296
a2ce26f8
VS		 4297/**
4298 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
4299 * quantization range information
4300 * @frame: HDMI AVI infoframe
779c4c28 4301 * @mode: DRM display mode
a2ce26f8
VS		 4302 * @rgb_quant_range: RGB quantization range (Q)
4303 * @rgb_quant_range_selectable: Sink support selectable RGB quantization range (QS)
4304 */
4305void
4306drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
779c4c28 4307 const struct drm_display_mode *mode,
a2ce26f8
VS		 4308 enum hdmi_quantization_range rgb_quant_range,
4309 bool rgb_quant_range_selectable)
4310{
4311 /*
4312 * CEA-861:
4313 * "A Source shall not send a non-zero Q value that does not correspond
4314 * to the default RGB Quantization Range for the transmitted Picture
4315 * unless the Sink indicates support for the Q bit in a Video
4316 * Capabilities Data Block."
779c4c28
VS		 4317 *
4318 * HDMI 2.0 recommends sending non-zero Q when it does match the
4319 * default RGB quantization range for the mode, even when QS=0.
a2ce26f8 4320 */
779c4c28
VS		 4321 if (rgb_quant_range_selectable ||
4322 rgb_quant_range == drm_default_rgb_quant_range(mode))
a2ce26f8
VS		 4323 frame->quantization_range = rgb_quant_range;
4324 else
4325 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
fcc8a22c
VS		 4326
4327 /*
4328 * CEA-861-F:
4329 * "When transmitting any RGB colorimetry, the Source should set the
4330 * YQ-field to match the RGB Quantization Range being transmitted
4331 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
4332 * set YQ=1) and the Sink shall ignore the YQ-field."
4333 */
4334 if (rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
4335 frame->ycc_quantization_range =
4336 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
4337 else
4338 frame->ycc_quantization_range =
4339 HDMI_YCC_QUANTIZATION_RANGE_FULL;
a2ce26f8
VS		 4340}
4341EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
4342
4eed4a0a
DL		 4343static enum hdmi_3d_structure
4344s3d_structure_from_display_mode(const struct drm_display_mode *mode)
4345{
4346 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
4347
4348 switch (layout) {
4349 case DRM_MODE_FLAG_3D_FRAME_PACKING:
4350 return HDMI_3D_STRUCTURE_FRAME_PACKING;
4351 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
4352 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
4353 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
4354 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
4355 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
4356 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
4357 case DRM_MODE_FLAG_3D_L_DEPTH:
4358 return HDMI_3D_STRUCTURE_L_DEPTH;
4359 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
4360 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
4361 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
4362 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
4363 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
4364 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
4365 default:
4366 return HDMI_3D_STRUCTURE_INVALID;
4367 }
4368}
4369
83dd0008
LD		 4370/**
4371 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
4372 * data from a DRM display mode
4373 * @frame: HDMI vendor infoframe
4374 * @mode: DRM display mode
4375 *
4376 * Note that there's is a need to send HDMI vendor infoframes only when using a
4377 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
4378 * function will return -EINVAL, error that can be safely ignored.
4379 *
db6cf833 4380 * Return: 0 on success or a negative error code on failure.
83dd0008
LD		 4381 */
4382int
4383drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
4384 const struct drm_display_mode *mode)
4385{
4386 int err;
4eed4a0a 4387 u32 s3d_flags;
83dd0008
LD		 4388 u8 vic;
4389
4390 if (!frame || !mode)
4391 return -EINVAL;
4392
4393 vic = drm_match_hdmi_mode(mode);
4eed4a0a
DL		 4394 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
4395
4396 if (!vic && !s3d_flags)
4397 return -EINVAL;
4398
4399 if (vic && s3d_flags)
83dd0008
LD		 4400 return -EINVAL;
4401
4402 err = hdmi_vendor_infoframe_init(frame);
4403 if (err < 0)
4404 return err;
4405
4eed4a0a
DL		 4406 if (vic)
4407 frame->vic = vic;
4408 else
4409 frame->s3d_struct = s3d_structure_from_display_mode(mode);
83dd0008
LD		 4410
4411 return 0;
4412}
4413EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
40d9b043 4414
5e546cd5
DA		 4415static int drm_parse_tiled_block(struct drm_connector *connector,
4416 struct displayid_block *block)
4417{
4418 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
4419 u16 w, h;
4420 u8 tile_v_loc, tile_h_loc;
4421 u8 num_v_tile, num_h_tile;
4422 struct drm_tile_group *tg;
4423
4424 w = tile->tile_size[0] | tile->tile_size[1] << 8;
4425 h = tile->tile_size[2] | tile->tile_size[3] << 8;
4426
4427 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
4428 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
4429 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
4430 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
4431
4432 connector->has_tile = true;
4433 if (tile->tile_cap & 0x80)
4434 connector->tile_is_single_monitor = true;
4435
4436 connector->num_h_tile = num_h_tile + 1;
4437 connector->num_v_tile = num_v_tile + 1;
4438 connector->tile_h_loc = tile_h_loc;
4439 connector->tile_v_loc = tile_v_loc;
4440 connector->tile_h_size = w + 1;
4441 connector->tile_v_size = h + 1;
4442
4443 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
4444 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
4445 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
4446 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
4447 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
4448
4449 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
4450 if (!tg) {
4451 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
4452 }
4453 if (!tg)
4454 return -ENOMEM;
4455
4456 if (connector->tile_group != tg) {
4457 /* if we haven't got a pointer,
4458 take the reference, drop ref to old tile group */
4459 if (connector->tile_group) {
4460 drm_mode_put_tile_group(connector->dev, connector->tile_group);
4461 }
4462 connector->tile_group = tg;
4463 } else
4464 /* if same tile group, then release the ref we just took. */
4465 drm_mode_put_tile_group(connector->dev, tg);
4466 return 0;
4467}
4468
40d9b043
DA		 4469static int drm_parse_display_id(struct drm_connector *connector,
4470 u8 *displayid, int length,
4471 bool is_edid_extension)
4472{
4473 /* if this is an EDID extension the first byte will be 0x70 */
4474 int idx = 0;
40d9b043 4475 struct displayid_block *block;
5e546cd5 4476 int ret;
40d9b043
DA		 4477
4478 if (is_edid_extension)
4479 idx = 1;
4480
c9729177
DA		 4481 ret = validate_displayid(displayid, length, idx);
4482 if (ret)
4483 return ret;
40d9b043 4484
3a4a2ea3
TB		 4485 idx += sizeof(struct displayid_hdr);
4486 while (block = (struct displayid_block *)&displayid[idx],
4487 idx + sizeof(struct displayid_block) <= length &&
4488 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
4489 block->num_bytes > 0) {
4490 idx += block->num_bytes + sizeof(struct displayid_block);
4491 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
4492 block->tag, block->rev, block->num_bytes);
4493
4494 switch (block->tag) {
4495 case DATA_BLOCK_TILED_DISPLAY:
4496 ret = drm_parse_tiled_block(connector, block);
4497 if (ret)
4498 return ret;
4499 break;
a39ed680
DA		 4500 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4501 /* handled in mode gathering code. */
4502 break;
3a4a2ea3
TB		 4503 default:
4504 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
4505 break;
4506 }
40d9b043
DA		 4507 }
4508 return 0;
4509}
4510
4511static void drm_get_displayid(struct drm_connector *connector,
4512 struct edid *edid)
4513{
4514 void *displayid = NULL;
4515 int ret;
4516 connector->has_tile = false;
4517 displayid = drm_find_displayid_extension(edid);
4518 if (!displayid) {
4519 /* drop reference to any tile group we had */
4520 goto out_drop_ref;
4521 }
4522
4523 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
4524 if (ret < 0)
4525 goto out_drop_ref;
4526 if (!connector->has_tile)
4527 goto out_drop_ref;
4528 return;
4529out_drop_ref:
4530 if (connector->tile_group) {
4531 drm_mode_put_tile_group(connector->dev, connector->tile_group);
4532 connector->tile_group = NULL;
4533 }
4534 return;
4535}
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