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f453ba04 DA |
1 | /* |
2 | * Copyright (c) 2006 Luc Verhaegen (quirks list) | |
3 | * Copyright (c) 2007-2008 Intel Corporation | |
4 | * Jesse Barnes <jesse.barnes@intel.com> | |
61e57a8d | 5 | * Copyright 2010 Red Hat, Inc. |
f453ba04 DA |
6 | * |
7 | * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from | |
8 | * FB layer. | |
9 | * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> | |
10 | * | |
11 | * Permission is hereby granted, free of charge, to any person obtaining a | |
12 | * copy of this software and associated documentation files (the "Software"), | |
13 | * to deal in the Software without restriction, including without limitation | |
14 | * the rights to use, copy, modify, merge, publish, distribute, sub license, | |
15 | * and/or sell copies of the Software, and to permit persons to whom the | |
16 | * Software is furnished to do so, subject to the following conditions: | |
17 | * | |
18 | * The above copyright notice and this permission notice (including the | |
19 | * next paragraph) shall be included in all copies or substantial portions | |
20 | * of the Software. | |
21 | * | |
22 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
23 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
24 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
25 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
26 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
27 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
28 | * DEALINGS IN THE SOFTWARE. | |
29 | */ | |
30 | #include <linux/kernel.h> | |
5a0e3ad6 | 31 | #include <linux/slab.h> |
f453ba04 DA |
32 | #include <linux/i2c.h> |
33 | #include <linux/i2c-algo-bit.h> | |
34 | #include "drmP.h" | |
35 | #include "drm_edid.h" | |
36 | ||
d1ff6409 AJ |
37 | #define EDID_EST_TIMINGS 16 |
38 | #define EDID_STD_TIMINGS 8 | |
39 | #define EDID_DETAILED_TIMINGS 4 | |
f453ba04 DA |
40 | |
41 | /* | |
42 | * EDID blocks out in the wild have a variety of bugs, try to collect | |
43 | * them here (note that userspace may work around broken monitors first, | |
44 | * but fixes should make their way here so that the kernel "just works" | |
45 | * on as many displays as possible). | |
46 | */ | |
47 | ||
48 | /* First detailed mode wrong, use largest 60Hz mode */ | |
49 | #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) | |
50 | /* Reported 135MHz pixel clock is too high, needs adjustment */ | |
51 | #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) | |
52 | /* Prefer the largest mode at 75 Hz */ | |
53 | #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) | |
54 | /* Detail timing is in cm not mm */ | |
55 | #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) | |
56 | /* Detailed timing descriptors have bogus size values, so just take the | |
57 | * maximum size and use that. | |
58 | */ | |
59 | #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) | |
60 | /* Monitor forgot to set the first detailed is preferred bit. */ | |
61 | #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5) | |
62 | /* use +hsync +vsync for detailed mode */ | |
63 | #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) | |
3c537889 | 64 | |
f453ba04 | 65 | |
5c61259e ZY |
66 | #define LEVEL_DMT 0 |
67 | #define LEVEL_GTF 1 | |
7a374350 AJ |
68 | #define LEVEL_GTF2 2 |
69 | #define LEVEL_CVT 3 | |
5c61259e | 70 | |
f453ba04 DA |
71 | static struct edid_quirk { |
72 | char *vendor; | |
73 | int product_id; | |
74 | u32 quirks; | |
75 | } edid_quirk_list[] = { | |
76 | /* Acer AL1706 */ | |
77 | { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, | |
78 | /* Acer F51 */ | |
79 | { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, | |
80 | /* Unknown Acer */ | |
81 | { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, | |
82 | ||
83 | /* Belinea 10 15 55 */ | |
84 | { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, | |
85 | { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, | |
86 | ||
87 | /* Envision Peripherals, Inc. EN-7100e */ | |
88 | { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, | |
ba1163de AJ |
89 | /* Envision EN2028 */ |
90 | { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, | |
f453ba04 DA |
91 | |
92 | /* Funai Electronics PM36B */ | |
93 | { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | | |
94 | EDID_QUIRK_DETAILED_IN_CM }, | |
95 | ||
96 | /* LG Philips LCD LP154W01-A5 */ | |
97 | { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, | |
98 | { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, | |
99 | ||
100 | /* Philips 107p5 CRT */ | |
101 | { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, | |
102 | ||
103 | /* Proview AY765C */ | |
104 | { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, | |
105 | ||
106 | /* Samsung SyncMaster 205BW. Note: irony */ | |
107 | { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, | |
108 | /* Samsung SyncMaster 22[5-6]BW */ | |
109 | { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, | |
110 | { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, | |
111 | }; | |
112 | ||
61e57a8d | 113 | /*** DDC fetch and block validation ***/ |
f453ba04 | 114 | |
083ae056 AJ |
115 | static const u8 edid_header[] = { |
116 | 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 | |
117 | }; | |
f453ba04 | 118 | |
61e57a8d AJ |
119 | /* |
120 | * Sanity check the EDID block (base or extension). Return 0 if the block | |
121 | * doesn't check out, or 1 if it's valid. | |
f453ba04 | 122 | */ |
61e57a8d AJ |
123 | static bool |
124 | drm_edid_block_valid(u8 *raw_edid) | |
f453ba04 | 125 | { |
61e57a8d | 126 | int i; |
f453ba04 | 127 | u8 csum = 0; |
61e57a8d | 128 | struct edid *edid = (struct edid *)raw_edid; |
f453ba04 | 129 | |
61e57a8d AJ |
130 | if (raw_edid[0] == 0x00) { |
131 | int score = 0; | |
862b89c0 | 132 | |
61e57a8d AJ |
133 | for (i = 0; i < sizeof(edid_header); i++) |
134 | if (raw_edid[i] == edid_header[i]) | |
135 | score++; | |
136 | ||
137 | if (score == 8) ; | |
138 | else if (score >= 6) { | |
139 | DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); | |
140 | memcpy(raw_edid, edid_header, sizeof(edid_header)); | |
141 | } else { | |
142 | goto bad; | |
143 | } | |
144 | } | |
f453ba04 DA |
145 | |
146 | for (i = 0; i < EDID_LENGTH; i++) | |
147 | csum += raw_edid[i]; | |
148 | if (csum) { | |
149 | DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum); | |
4a638b4e AJ |
150 | |
151 | /* allow CEA to slide through, switches mangle this */ | |
152 | if (raw_edid[0] != 0x02) | |
153 | goto bad; | |
f453ba04 DA |
154 | } |
155 | ||
61e57a8d AJ |
156 | /* per-block-type checks */ |
157 | switch (raw_edid[0]) { | |
158 | case 0: /* base */ | |
159 | if (edid->version != 1) { | |
160 | DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version); | |
161 | goto bad; | |
162 | } | |
862b89c0 | 163 | |
61e57a8d AJ |
164 | if (edid->revision > 4) |
165 | DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); | |
166 | break; | |
862b89c0 | 167 | |
61e57a8d AJ |
168 | default: |
169 | break; | |
170 | } | |
47ee4ccf | 171 | |
f453ba04 DA |
172 | return 1; |
173 | ||
174 | bad: | |
175 | if (raw_edid) { | |
176 | DRM_ERROR("Raw EDID:\n"); | |
177 | print_hex_dump_bytes(KERN_ERR, DUMP_PREFIX_NONE, raw_edid, EDID_LENGTH); | |
178 | printk("\n"); | |
179 | } | |
180 | return 0; | |
181 | } | |
61e57a8d AJ |
182 | |
183 | /** | |
184 | * drm_edid_is_valid - sanity check EDID data | |
185 | * @edid: EDID data | |
186 | * | |
187 | * Sanity-check an entire EDID record (including extensions) | |
188 | */ | |
189 | bool drm_edid_is_valid(struct edid *edid) | |
190 | { | |
191 | int i; | |
192 | u8 *raw = (u8 *)edid; | |
193 | ||
194 | if (!edid) | |
195 | return false; | |
196 | ||
197 | for (i = 0; i <= edid->extensions; i++) | |
198 | if (!drm_edid_block_valid(raw + i * EDID_LENGTH)) | |
199 | return false; | |
200 | ||
201 | return true; | |
202 | } | |
3c537889 | 203 | EXPORT_SYMBOL(drm_edid_is_valid); |
f453ba04 | 204 | |
61e57a8d AJ |
205 | #define DDC_ADDR 0x50 |
206 | #define DDC_SEGMENT_ADDR 0x30 | |
207 | /** | |
208 | * Get EDID information via I2C. | |
209 | * | |
210 | * \param adapter : i2c device adaptor | |
211 | * \param buf : EDID data buffer to be filled | |
212 | * \param len : EDID data buffer length | |
213 | * \return 0 on success or -1 on failure. | |
214 | * | |
215 | * Try to fetch EDID information by calling i2c driver function. | |
216 | */ | |
217 | static int | |
218 | drm_do_probe_ddc_edid(struct i2c_adapter *adapter, unsigned char *buf, | |
219 | int block, int len) | |
220 | { | |
221 | unsigned char start = block * EDID_LENGTH; | |
222 | struct i2c_msg msgs[] = { | |
223 | { | |
224 | .addr = DDC_ADDR, | |
225 | .flags = 0, | |
226 | .len = 1, | |
227 | .buf = &start, | |
228 | }, { | |
229 | .addr = DDC_ADDR, | |
230 | .flags = I2C_M_RD, | |
231 | .len = len, | |
232 | .buf = buf + start, | |
233 | } | |
234 | }; | |
235 | ||
236 | if (i2c_transfer(adapter, msgs, 2) == 2) | |
237 | return 0; | |
238 | ||
239 | return -1; | |
240 | } | |
241 | ||
242 | static u8 * | |
243 | drm_do_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) | |
244 | { | |
245 | int i, j = 0; | |
246 | u8 *block, *new; | |
247 | ||
248 | if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) | |
249 | return NULL; | |
250 | ||
251 | /* base block fetch */ | |
252 | for (i = 0; i < 4; i++) { | |
253 | if (drm_do_probe_ddc_edid(adapter, block, 0, EDID_LENGTH)) | |
254 | goto out; | |
255 | if (drm_edid_block_valid(block)) | |
256 | break; | |
257 | } | |
258 | if (i == 4) | |
259 | goto carp; | |
260 | ||
261 | /* if there's no extensions, we're done */ | |
262 | if (block[0x7e] == 0) | |
263 | return block; | |
264 | ||
265 | new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL); | |
266 | if (!new) | |
267 | goto out; | |
268 | block = new; | |
269 | ||
270 | for (j = 1; j <= block[0x7e]; j++) { | |
271 | for (i = 0; i < 4; i++) { | |
272 | if (drm_do_probe_ddc_edid(adapter, block, j, | |
273 | EDID_LENGTH)) | |
274 | goto out; | |
275 | if (drm_edid_block_valid(block + j * EDID_LENGTH)) | |
276 | break; | |
277 | } | |
278 | if (i == 4) | |
279 | goto carp; | |
280 | } | |
281 | ||
282 | return block; | |
283 | ||
284 | carp: | |
dcdb1674 | 285 | dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n", |
61e57a8d AJ |
286 | drm_get_connector_name(connector), j); |
287 | ||
288 | out: | |
289 | kfree(block); | |
290 | return NULL; | |
291 | } | |
292 | ||
293 | /** | |
294 | * Probe DDC presence. | |
295 | * | |
296 | * \param adapter : i2c device adaptor | |
297 | * \return 1 on success | |
298 | */ | |
299 | static bool | |
300 | drm_probe_ddc(struct i2c_adapter *adapter) | |
301 | { | |
302 | unsigned char out; | |
303 | ||
304 | return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); | |
305 | } | |
306 | ||
307 | /** | |
308 | * drm_get_edid - get EDID data, if available | |
309 | * @connector: connector we're probing | |
310 | * @adapter: i2c adapter to use for DDC | |
311 | * | |
312 | * Poke the given i2c channel to grab EDID data if possible. If found, | |
313 | * attach it to the connector. | |
314 | * | |
315 | * Return edid data or NULL if we couldn't find any. | |
316 | */ | |
317 | struct edid *drm_get_edid(struct drm_connector *connector, | |
318 | struct i2c_adapter *adapter) | |
319 | { | |
320 | struct edid *edid = NULL; | |
321 | ||
322 | if (drm_probe_ddc(adapter)) | |
323 | edid = (struct edid *)drm_do_get_edid(connector, adapter); | |
324 | ||
325 | connector->display_info.raw_edid = (char *)edid; | |
326 | ||
327 | return edid; | |
328 | ||
329 | } | |
330 | EXPORT_SYMBOL(drm_get_edid); | |
331 | ||
332 | /*** EDID parsing ***/ | |
333 | ||
f453ba04 DA |
334 | /** |
335 | * edid_vendor - match a string against EDID's obfuscated vendor field | |
336 | * @edid: EDID to match | |
337 | * @vendor: vendor string | |
338 | * | |
339 | * Returns true if @vendor is in @edid, false otherwise | |
340 | */ | |
341 | static bool edid_vendor(struct edid *edid, char *vendor) | |
342 | { | |
343 | char edid_vendor[3]; | |
344 | ||
345 | edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; | |
346 | edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | | |
347 | ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; | |
16456c87 | 348 | edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; |
f453ba04 DA |
349 | |
350 | return !strncmp(edid_vendor, vendor, 3); | |
351 | } | |
352 | ||
353 | /** | |
354 | * edid_get_quirks - return quirk flags for a given EDID | |
355 | * @edid: EDID to process | |
356 | * | |
357 | * This tells subsequent routines what fixes they need to apply. | |
358 | */ | |
359 | static u32 edid_get_quirks(struct edid *edid) | |
360 | { | |
361 | struct edid_quirk *quirk; | |
362 | int i; | |
363 | ||
364 | for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { | |
365 | quirk = &edid_quirk_list[i]; | |
366 | ||
367 | if (edid_vendor(edid, quirk->vendor) && | |
368 | (EDID_PRODUCT_ID(edid) == quirk->product_id)) | |
369 | return quirk->quirks; | |
370 | } | |
371 | ||
372 | return 0; | |
373 | } | |
374 | ||
375 | #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) | |
376 | #define MODE_REFRESH_DIFF(m,r) (abs((m)->vrefresh - target_refresh)) | |
377 | ||
378 | ||
379 | /** | |
380 | * edid_fixup_preferred - set preferred modes based on quirk list | |
381 | * @connector: has mode list to fix up | |
382 | * @quirks: quirks list | |
383 | * | |
384 | * Walk the mode list for @connector, clearing the preferred status | |
385 | * on existing modes and setting it anew for the right mode ala @quirks. | |
386 | */ | |
387 | static void edid_fixup_preferred(struct drm_connector *connector, | |
388 | u32 quirks) | |
389 | { | |
390 | struct drm_display_mode *t, *cur_mode, *preferred_mode; | |
f890607b | 391 | int target_refresh = 0; |
f453ba04 DA |
392 | |
393 | if (list_empty(&connector->probed_modes)) | |
394 | return; | |
395 | ||
396 | if (quirks & EDID_QUIRK_PREFER_LARGE_60) | |
397 | target_refresh = 60; | |
398 | if (quirks & EDID_QUIRK_PREFER_LARGE_75) | |
399 | target_refresh = 75; | |
400 | ||
401 | preferred_mode = list_first_entry(&connector->probed_modes, | |
402 | struct drm_display_mode, head); | |
403 | ||
404 | list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { | |
405 | cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; | |
406 | ||
407 | if (cur_mode == preferred_mode) | |
408 | continue; | |
409 | ||
410 | /* Largest mode is preferred */ | |
411 | if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) | |
412 | preferred_mode = cur_mode; | |
413 | ||
414 | /* At a given size, try to get closest to target refresh */ | |
415 | if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && | |
416 | MODE_REFRESH_DIFF(cur_mode, target_refresh) < | |
417 | MODE_REFRESH_DIFF(preferred_mode, target_refresh)) { | |
418 | preferred_mode = cur_mode; | |
419 | } | |
420 | } | |
421 | ||
422 | preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
423 | } | |
424 | ||
aa9eaa1f ZY |
425 | /* |
426 | * Add the Autogenerated from the DMT spec. | |
427 | * This table is copied from xfree86/modes/xf86EdidModes.c. | |
428 | * But the mode with Reduced blank feature is deleted. | |
429 | */ | |
430 | static struct drm_display_mode drm_dmt_modes[] = { | |
431 | /* 640x350@85Hz */ | |
432 | { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, | |
433 | 736, 832, 0, 350, 382, 385, 445, 0, | |
434 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
435 | /* 640x400@85Hz */ | |
436 | { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, | |
437 | 736, 832, 0, 400, 401, 404, 445, 0, | |
438 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
439 | /* 720x400@85Hz */ | |
440 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, | |
441 | 828, 936, 0, 400, 401, 404, 446, 0, | |
442 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
443 | /* 640x480@60Hz */ | |
444 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, | |
445 | 752, 800, 0, 480, 489, 492, 525, 0, | |
446 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
447 | /* 640x480@72Hz */ | |
448 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, | |
449 | 704, 832, 0, 480, 489, 492, 520, 0, | |
450 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
451 | /* 640x480@75Hz */ | |
452 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, | |
453 | 720, 840, 0, 480, 481, 484, 500, 0, | |
454 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
455 | /* 640x480@85Hz */ | |
456 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, | |
457 | 752, 832, 0, 480, 481, 484, 509, 0, | |
458 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
459 | /* 800x600@56Hz */ | |
460 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, | |
461 | 896, 1024, 0, 600, 601, 603, 625, 0, | |
462 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
463 | /* 800x600@60Hz */ | |
464 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, | |
465 | 968, 1056, 0, 600, 601, 605, 628, 0, | |
466 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
467 | /* 800x600@72Hz */ | |
468 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, | |
469 | 976, 1040, 0, 600, 637, 643, 666, 0, | |
470 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
471 | /* 800x600@75Hz */ | |
472 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, | |
473 | 896, 1056, 0, 600, 601, 604, 625, 0, | |
474 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
475 | /* 800x600@85Hz */ | |
476 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, | |
477 | 896, 1048, 0, 600, 601, 604, 631, 0, | |
478 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
479 | /* 848x480@60Hz */ | |
480 | { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, | |
481 | 976, 1088, 0, 480, 486, 494, 517, 0, | |
482 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
483 | /* 1024x768@43Hz, interlace */ | |
484 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, | |
485 | 1208, 1264, 0, 768, 768, 772, 817, 0, | |
486 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | | |
487 | DRM_MODE_FLAG_INTERLACE) }, | |
488 | /* 1024x768@60Hz */ | |
489 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, | |
490 | 1184, 1344, 0, 768, 771, 777, 806, 0, | |
491 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
492 | /* 1024x768@70Hz */ | |
493 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, | |
494 | 1184, 1328, 0, 768, 771, 777, 806, 0, | |
495 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
496 | /* 1024x768@75Hz */ | |
497 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, | |
498 | 1136, 1312, 0, 768, 769, 772, 800, 0, | |
499 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
500 | /* 1024x768@85Hz */ | |
501 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, | |
61dd98fa | 502 | 1168, 1376, 0, 768, 769, 772, 808, 0, |
aa9eaa1f ZY |
503 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
504 | /* 1152x864@75Hz */ | |
505 | { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, | |
506 | 1344, 1600, 0, 864, 865, 868, 900, 0, | |
507 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
508 | /* 1280x768@60Hz */ | |
509 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, | |
510 | 1472, 1664, 0, 768, 771, 778, 798, 0, | |
511 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
512 | /* 1280x768@75Hz */ | |
513 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, | |
514 | 1488, 1696, 0, 768, 771, 778, 805, 0, | |
515 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
516 | /* 1280x768@85Hz */ | |
517 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, | |
518 | 1496, 1712, 0, 768, 771, 778, 809, 0, | |
519 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
520 | /* 1280x800@60Hz */ | |
521 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, | |
522 | 1480, 1680, 0, 800, 803, 809, 831, 0, | |
523 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
524 | /* 1280x800@75Hz */ | |
525 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, | |
526 | 1488, 1696, 0, 800, 803, 809, 838, 0, | |
527 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
528 | /* 1280x800@85Hz */ | |
529 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, | |
530 | 1496, 1712, 0, 800, 803, 809, 843, 0, | |
531 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
532 | /* 1280x960@60Hz */ | |
533 | { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, | |
534 | 1488, 1800, 0, 960, 961, 964, 1000, 0, | |
535 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
536 | /* 1280x960@85Hz */ | |
537 | { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, | |
538 | 1504, 1728, 0, 960, 961, 964, 1011, 0, | |
539 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
540 | /* 1280x1024@60Hz */ | |
541 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, | |
542 | 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, | |
543 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
544 | /* 1280x1024@75Hz */ | |
545 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, | |
546 | 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, | |
547 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
548 | /* 1280x1024@85Hz */ | |
549 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, | |
550 | 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, | |
551 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
552 | /* 1360x768@60Hz */ | |
553 | { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, | |
554 | 1536, 1792, 0, 768, 771, 777, 795, 0, | |
555 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
556 | /* 1440x1050@60Hz */ | |
557 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, | |
558 | 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, | |
559 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
560 | /* 1440x1050@75Hz */ | |
561 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, | |
562 | 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, | |
563 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
564 | /* 1440x1050@85Hz */ | |
565 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, | |
566 | 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, | |
567 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
568 | /* 1440x900@60Hz */ | |
569 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, | |
570 | 1672, 1904, 0, 900, 903, 909, 934, 0, | |
571 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
572 | /* 1440x900@75Hz */ | |
573 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, | |
574 | 1688, 1936, 0, 900, 903, 909, 942, 0, | |
575 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
576 | /* 1440x900@85Hz */ | |
577 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, | |
578 | 1696, 1952, 0, 900, 903, 909, 948, 0, | |
579 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
580 | /* 1600x1200@60Hz */ | |
581 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, | |
582 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, | |
583 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
584 | /* 1600x1200@65Hz */ | |
585 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, | |
586 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, | |
587 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
588 | /* 1600x1200@70Hz */ | |
589 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, | |
590 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, | |
591 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
592 | /* 1600x1200@75Hz */ | |
c43ae476 | 593 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, |
aa9eaa1f ZY |
594 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, |
595 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
596 | /* 1600x1200@85Hz */ | |
597 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, | |
598 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, | |
599 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
600 | /* 1680x1050@60Hz */ | |
601 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, | |
602 | 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, | |
603 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
604 | /* 1680x1050@75Hz */ | |
605 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, | |
606 | 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, | |
607 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
608 | /* 1680x1050@85Hz */ | |
609 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, | |
610 | 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, | |
611 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
612 | /* 1792x1344@60Hz */ | |
613 | { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, | |
614 | 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, | |
615 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
616 | /* 1729x1344@75Hz */ | |
617 | { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, | |
618 | 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, | |
619 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
620 | /* 1853x1392@60Hz */ | |
621 | { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, | |
622 | 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, | |
623 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
624 | /* 1856x1392@75Hz */ | |
625 | { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, | |
626 | 2208, 2560, 0, 1392, 1395, 1399, 1500, 0, | |
627 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
628 | /* 1920x1200@60Hz */ | |
629 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, | |
630 | 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, | |
631 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
632 | /* 1920x1200@75Hz */ | |
633 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, | |
634 | 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, | |
635 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
636 | /* 1920x1200@85Hz */ | |
637 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, | |
638 | 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, | |
639 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
640 | /* 1920x1440@60Hz */ | |
641 | { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, | |
642 | 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, | |
643 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
644 | /* 1920x1440@75Hz */ | |
645 | { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, | |
646 | 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, | |
647 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
648 | /* 2560x1600@60Hz */ | |
649 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, | |
650 | 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, | |
651 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
652 | /* 2560x1600@75HZ */ | |
653 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, | |
654 | 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, | |
655 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
656 | /* 2560x1600@85HZ */ | |
657 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, | |
658 | 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, | |
659 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
660 | }; | |
07a5e632 AJ |
661 | static const int drm_num_dmt_modes = |
662 | sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode); | |
aa9eaa1f | 663 | |
1d42bbc8 DA |
664 | struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, |
665 | int hsize, int vsize, int fresh) | |
559ee21d | 666 | { |
07a5e632 | 667 | int i; |
559ee21d ZY |
668 | struct drm_display_mode *ptr, *mode; |
669 | ||
559ee21d | 670 | mode = NULL; |
07a5e632 | 671 | for (i = 0; i < drm_num_dmt_modes; i++) { |
559ee21d ZY |
672 | ptr = &drm_dmt_modes[i]; |
673 | if (hsize == ptr->hdisplay && | |
674 | vsize == ptr->vdisplay && | |
675 | fresh == drm_mode_vrefresh(ptr)) { | |
676 | /* get the expected default mode */ | |
677 | mode = drm_mode_duplicate(dev, ptr); | |
678 | break; | |
679 | } | |
680 | } | |
681 | return mode; | |
682 | } | |
1d42bbc8 | 683 | EXPORT_SYMBOL(drm_mode_find_dmt); |
23425cae | 684 | |
d1ff6409 AJ |
685 | typedef void detailed_cb(struct detailed_timing *timing, void *closure); |
686 | ||
4d76a221 AJ |
687 | static void |
688 | cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) | |
689 | { | |
690 | int i, n = 0; | |
691 | u8 rev = ext[0x01], d = ext[0x02]; | |
692 | u8 *det_base = ext + d; | |
693 | ||
694 | switch (rev) { | |
695 | case 0: | |
696 | /* can't happen */ | |
697 | return; | |
698 | case 1: | |
699 | /* have to infer how many blocks we have, check pixel clock */ | |
700 | for (i = 0; i < 6; i++) | |
701 | if (det_base[18*i] || det_base[18*i+1]) | |
702 | n++; | |
703 | break; | |
704 | default: | |
705 | /* explicit count */ | |
706 | n = min(ext[0x03] & 0x0f, 6); | |
707 | break; | |
708 | } | |
709 | ||
710 | for (i = 0; i < n; i++) | |
711 | cb((struct detailed_timing *)(det_base + 18 * i), closure); | |
712 | } | |
713 | ||
d1ff6409 AJ |
714 | static void |
715 | drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) | |
716 | { | |
717 | int i; | |
718 | struct edid *edid = (struct edid *)raw_edid; | |
719 | ||
720 | if (edid == NULL) | |
721 | return; | |
722 | ||
723 | for (i = 0; i < EDID_DETAILED_TIMINGS; i++) | |
724 | cb(&(edid->detailed_timings[i]), closure); | |
725 | ||
4d76a221 AJ |
726 | for (i = 1; i <= raw_edid[0x7e]; i++) { |
727 | u8 *ext = raw_edid + (i * EDID_LENGTH); | |
728 | switch (*ext) { | |
729 | case CEA_EXT: | |
730 | cea_for_each_detailed_block(ext, cb, closure); | |
731 | break; | |
732 | default: | |
733 | break; | |
734 | } | |
735 | } | |
d1ff6409 AJ |
736 | } |
737 | ||
738 | static void | |
739 | is_rb(struct detailed_timing *t, void *data) | |
740 | { | |
741 | u8 *r = (u8 *)t; | |
742 | if (r[3] == EDID_DETAIL_MONITOR_RANGE) | |
743 | if (r[15] & 0x10) | |
744 | *(bool *)data = true; | |
745 | } | |
746 | ||
747 | /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ | |
748 | static bool | |
749 | drm_monitor_supports_rb(struct edid *edid) | |
750 | { | |
751 | if (edid->revision >= 4) { | |
752 | bool ret; | |
753 | drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); | |
754 | return ret; | |
755 | } | |
756 | ||
757 | return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); | |
758 | } | |
759 | ||
7a374350 AJ |
760 | static void |
761 | find_gtf2(struct detailed_timing *t, void *data) | |
762 | { | |
763 | u8 *r = (u8 *)t; | |
764 | if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) | |
765 | *(u8 **)data = r; | |
766 | } | |
767 | ||
768 | /* Secondary GTF curve kicks in above some break frequency */ | |
769 | static int | |
770 | drm_gtf2_hbreak(struct edid *edid) | |
771 | { | |
772 | u8 *r = NULL; | |
773 | drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); | |
774 | return r ? (r[12] * 2) : 0; | |
775 | } | |
776 | ||
777 | static int | |
778 | drm_gtf2_2c(struct edid *edid) | |
779 | { | |
780 | u8 *r = NULL; | |
781 | drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); | |
782 | return r ? r[13] : 0; | |
783 | } | |
784 | ||
785 | static int | |
786 | drm_gtf2_m(struct edid *edid) | |
787 | { | |
788 | u8 *r = NULL; | |
789 | drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); | |
790 | return r ? (r[15] << 8) + r[14] : 0; | |
791 | } | |
792 | ||
793 | static int | |
794 | drm_gtf2_k(struct edid *edid) | |
795 | { | |
796 | u8 *r = NULL; | |
797 | drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); | |
798 | return r ? r[16] : 0; | |
799 | } | |
800 | ||
801 | static int | |
802 | drm_gtf2_2j(struct edid *edid) | |
803 | { | |
804 | u8 *r = NULL; | |
805 | drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); | |
806 | return r ? r[17] : 0; | |
807 | } | |
808 | ||
809 | /** | |
810 | * standard_timing_level - get std. timing level(CVT/GTF/DMT) | |
811 | * @edid: EDID block to scan | |
812 | */ | |
813 | static int standard_timing_level(struct edid *edid) | |
814 | { | |
815 | if (edid->revision >= 2) { | |
816 | if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) | |
817 | return LEVEL_CVT; | |
818 | if (drm_gtf2_hbreak(edid)) | |
819 | return LEVEL_GTF2; | |
820 | return LEVEL_GTF; | |
821 | } | |
822 | return LEVEL_DMT; | |
823 | } | |
824 | ||
23425cae AJ |
825 | /* |
826 | * 0 is reserved. The spec says 0x01 fill for unused timings. Some old | |
827 | * monitors fill with ascii space (0x20) instead. | |
828 | */ | |
829 | static int | |
830 | bad_std_timing(u8 a, u8 b) | |
831 | { | |
832 | return (a == 0x00 && b == 0x00) || | |
833 | (a == 0x01 && b == 0x01) || | |
834 | (a == 0x20 && b == 0x20); | |
835 | } | |
836 | ||
f453ba04 DA |
837 | /** |
838 | * drm_mode_std - convert standard mode info (width, height, refresh) into mode | |
839 | * @t: standard timing params | |
5c61259e | 840 | * @timing_level: standard timing level |
f453ba04 DA |
841 | * |
842 | * Take the standard timing params (in this case width, aspect, and refresh) | |
5c61259e | 843 | * and convert them into a real mode using CVT/GTF/DMT. |
f453ba04 | 844 | */ |
7ca6adb3 | 845 | static struct drm_display_mode * |
7a374350 AJ |
846 | drm_mode_std(struct drm_connector *connector, struct edid *edid, |
847 | struct std_timing *t, int revision) | |
f453ba04 | 848 | { |
7ca6adb3 AJ |
849 | struct drm_device *dev = connector->dev; |
850 | struct drm_display_mode *m, *mode = NULL; | |
5c61259e ZY |
851 | int hsize, vsize; |
852 | int vrefresh_rate; | |
0454beab MD |
853 | unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) |
854 | >> EDID_TIMING_ASPECT_SHIFT; | |
5c61259e ZY |
855 | unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) |
856 | >> EDID_TIMING_VFREQ_SHIFT; | |
7a374350 | 857 | int timing_level = standard_timing_level(edid); |
5c61259e | 858 | |
23425cae AJ |
859 | if (bad_std_timing(t->hsize, t->vfreq_aspect)) |
860 | return NULL; | |
861 | ||
5c61259e ZY |
862 | /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ |
863 | hsize = t->hsize * 8 + 248; | |
864 | /* vrefresh_rate = vfreq + 60 */ | |
865 | vrefresh_rate = vfreq + 60; | |
866 | /* the vdisplay is calculated based on the aspect ratio */ | |
f066a17d AJ |
867 | if (aspect_ratio == 0) { |
868 | if (revision < 3) | |
869 | vsize = hsize; | |
870 | else | |
871 | vsize = (hsize * 10) / 16; | |
872 | } else if (aspect_ratio == 1) | |
f453ba04 | 873 | vsize = (hsize * 3) / 4; |
0454beab | 874 | else if (aspect_ratio == 2) |
f453ba04 DA |
875 | vsize = (hsize * 4) / 5; |
876 | else | |
877 | vsize = (hsize * 9) / 16; | |
a0910c8e AJ |
878 | |
879 | /* HDTV hack, part 1 */ | |
880 | if (vrefresh_rate == 60 && | |
881 | ((hsize == 1360 && vsize == 765) || | |
882 | (hsize == 1368 && vsize == 769))) { | |
883 | hsize = 1366; | |
884 | vsize = 768; | |
885 | } | |
886 | ||
7ca6adb3 AJ |
887 | /* |
888 | * If this connector already has a mode for this size and refresh | |
889 | * rate (because it came from detailed or CVT info), use that | |
890 | * instead. This way we don't have to guess at interlace or | |
891 | * reduced blanking. | |
892 | */ | |
522032da | 893 | list_for_each_entry(m, &connector->probed_modes, head) |
7ca6adb3 AJ |
894 | if (m->hdisplay == hsize && m->vdisplay == vsize && |
895 | drm_mode_vrefresh(m) == vrefresh_rate) | |
896 | return NULL; | |
897 | ||
a0910c8e AJ |
898 | /* HDTV hack, part 2 */ |
899 | if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { | |
900 | mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, | |
d50ba256 | 901 | false); |
559ee21d | 902 | mode->hdisplay = 1366; |
a4967de6 AJ |
903 | mode->hsync_start = mode->hsync_start - 1; |
904 | mode->hsync_end = mode->hsync_end - 1; | |
559ee21d ZY |
905 | return mode; |
906 | } | |
a0910c8e | 907 | |
559ee21d | 908 | /* check whether it can be found in default mode table */ |
1d42bbc8 | 909 | mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate); |
559ee21d ZY |
910 | if (mode) |
911 | return mode; | |
912 | ||
5c61259e ZY |
913 | switch (timing_level) { |
914 | case LEVEL_DMT: | |
5c61259e ZY |
915 | break; |
916 | case LEVEL_GTF: | |
917 | mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); | |
918 | break; | |
7a374350 AJ |
919 | case LEVEL_GTF2: |
920 | /* | |
921 | * This is potentially wrong if there's ever a monitor with | |
922 | * more than one ranges section, each claiming a different | |
923 | * secondary GTF curve. Please don't do that. | |
924 | */ | |
925 | mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); | |
926 | if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { | |
927 | kfree(mode); | |
928 | mode = drm_gtf_mode_complex(dev, hsize, vsize, | |
929 | vrefresh_rate, 0, 0, | |
930 | drm_gtf2_m(edid), | |
931 | drm_gtf2_2c(edid), | |
932 | drm_gtf2_k(edid), | |
933 | drm_gtf2_2j(edid)); | |
934 | } | |
935 | break; | |
5c61259e | 936 | case LEVEL_CVT: |
d50ba256 DA |
937 | mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, |
938 | false); | |
5c61259e ZY |
939 | break; |
940 | } | |
f453ba04 DA |
941 | return mode; |
942 | } | |
943 | ||
b58db2c6 AJ |
944 | /* |
945 | * EDID is delightfully ambiguous about how interlaced modes are to be | |
946 | * encoded. Our internal representation is of frame height, but some | |
947 | * HDTV detailed timings are encoded as field height. | |
948 | * | |
949 | * The format list here is from CEA, in frame size. Technically we | |
950 | * should be checking refresh rate too. Whatever. | |
951 | */ | |
952 | static void | |
953 | drm_mode_do_interlace_quirk(struct drm_display_mode *mode, | |
954 | struct detailed_pixel_timing *pt) | |
955 | { | |
956 | int i; | |
957 | static const struct { | |
958 | int w, h; | |
959 | } cea_interlaced[] = { | |
960 | { 1920, 1080 }, | |
961 | { 720, 480 }, | |
962 | { 1440, 480 }, | |
963 | { 2880, 480 }, | |
964 | { 720, 576 }, | |
965 | { 1440, 576 }, | |
966 | { 2880, 576 }, | |
967 | }; | |
968 | static const int n_sizes = | |
969 | sizeof(cea_interlaced)/sizeof(cea_interlaced[0]); | |
970 | ||
971 | if (!(pt->misc & DRM_EDID_PT_INTERLACED)) | |
972 | return; | |
973 | ||
974 | for (i = 0; i < n_sizes; i++) { | |
975 | if ((mode->hdisplay == cea_interlaced[i].w) && | |
976 | (mode->vdisplay == cea_interlaced[i].h / 2)) { | |
977 | mode->vdisplay *= 2; | |
978 | mode->vsync_start *= 2; | |
979 | mode->vsync_end *= 2; | |
980 | mode->vtotal *= 2; | |
981 | mode->vtotal |= 1; | |
982 | } | |
983 | } | |
984 | ||
985 | mode->flags |= DRM_MODE_FLAG_INTERLACE; | |
986 | } | |
987 | ||
f453ba04 DA |
988 | /** |
989 | * drm_mode_detailed - create a new mode from an EDID detailed timing section | |
990 | * @dev: DRM device (needed to create new mode) | |
991 | * @edid: EDID block | |
992 | * @timing: EDID detailed timing info | |
993 | * @quirks: quirks to apply | |
994 | * | |
995 | * An EDID detailed timing block contains enough info for us to create and | |
996 | * return a new struct drm_display_mode. | |
997 | */ | |
998 | static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, | |
999 | struct edid *edid, | |
1000 | struct detailed_timing *timing, | |
1001 | u32 quirks) | |
1002 | { | |
1003 | struct drm_display_mode *mode; | |
1004 | struct detailed_pixel_timing *pt = &timing->data.pixel_data; | |
0454beab MD |
1005 | unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; |
1006 | unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; | |
1007 | unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; | |
1008 | unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; | |
e14cbee4 MD |
1009 | unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; |
1010 | unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; | |
1011 | unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) >> 2 | pt->vsync_offset_pulse_width_lo >> 4; | |
1012 | unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); | |
f453ba04 | 1013 | |
fc438966 | 1014 | /* ignore tiny modes */ |
0454beab | 1015 | if (hactive < 64 || vactive < 64) |
fc438966 AJ |
1016 | return NULL; |
1017 | ||
0454beab | 1018 | if (pt->misc & DRM_EDID_PT_STEREO) { |
f453ba04 DA |
1019 | printk(KERN_WARNING "stereo mode not supported\n"); |
1020 | return NULL; | |
1021 | } | |
0454beab | 1022 | if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { |
79b7dcb2 | 1023 | printk(KERN_WARNING "composite sync not supported\n"); |
f453ba04 DA |
1024 | } |
1025 | ||
fcb45611 ZY |
1026 | /* it is incorrect if hsync/vsync width is zero */ |
1027 | if (!hsync_pulse_width || !vsync_pulse_width) { | |
1028 | DRM_DEBUG_KMS("Incorrect Detailed timing. " | |
1029 | "Wrong Hsync/Vsync pulse width\n"); | |
1030 | return NULL; | |
1031 | } | |
f453ba04 DA |
1032 | mode = drm_mode_create(dev); |
1033 | if (!mode) | |
1034 | return NULL; | |
1035 | ||
1036 | mode->type = DRM_MODE_TYPE_DRIVER; | |
1037 | ||
1038 | if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) | |
0454beab MD |
1039 | timing->pixel_clock = cpu_to_le16(1088); |
1040 | ||
1041 | mode->clock = le16_to_cpu(timing->pixel_clock) * 10; | |
1042 | ||
1043 | mode->hdisplay = hactive; | |
1044 | mode->hsync_start = mode->hdisplay + hsync_offset; | |
1045 | mode->hsync_end = mode->hsync_start + hsync_pulse_width; | |
1046 | mode->htotal = mode->hdisplay + hblank; | |
1047 | ||
1048 | mode->vdisplay = vactive; | |
1049 | mode->vsync_start = mode->vdisplay + vsync_offset; | |
1050 | mode->vsync_end = mode->vsync_start + vsync_pulse_width; | |
1051 | mode->vtotal = mode->vdisplay + vblank; | |
f453ba04 | 1052 | |
7064fef5 JB |
1053 | /* Some EDIDs have bogus h/vtotal values */ |
1054 | if (mode->hsync_end > mode->htotal) | |
1055 | mode->htotal = mode->hsync_end + 1; | |
1056 | if (mode->vsync_end > mode->vtotal) | |
1057 | mode->vtotal = mode->vsync_end + 1; | |
1058 | ||
b58db2c6 | 1059 | drm_mode_do_interlace_quirk(mode, pt); |
f453ba04 | 1060 | |
171fdd89 AJ |
1061 | drm_mode_set_name(mode); |
1062 | ||
f453ba04 | 1063 | if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { |
0454beab | 1064 | pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; |
f453ba04 DA |
1065 | } |
1066 | ||
0454beab MD |
1067 | mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? |
1068 | DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; | |
1069 | mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? | |
1070 | DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; | |
f453ba04 | 1071 | |
e14cbee4 MD |
1072 | mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; |
1073 | mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; | |
f453ba04 DA |
1074 | |
1075 | if (quirks & EDID_QUIRK_DETAILED_IN_CM) { | |
1076 | mode->width_mm *= 10; | |
1077 | mode->height_mm *= 10; | |
1078 | } | |
1079 | ||
1080 | if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { | |
1081 | mode->width_mm = edid->width_cm * 10; | |
1082 | mode->height_mm = edid->height_cm * 10; | |
1083 | } | |
1084 | ||
1085 | return mode; | |
1086 | } | |
1087 | ||
1088 | /* | |
1089 | * Detailed mode info for the EDID "established modes" data to use. | |
1090 | */ | |
1091 | static struct drm_display_mode edid_est_modes[] = { | |
1092 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, | |
1093 | 968, 1056, 0, 600, 601, 605, 628, 0, | |
1094 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ | |
1095 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, | |
1096 | 896, 1024, 0, 600, 601, 603, 625, 0, | |
1097 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ | |
1098 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, | |
1099 | 720, 840, 0, 480, 481, 484, 500, 0, | |
1100 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ | |
1101 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, | |
1102 | 704, 832, 0, 480, 489, 491, 520, 0, | |
1103 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ | |
1104 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, | |
1105 | 768, 864, 0, 480, 483, 486, 525, 0, | |
1106 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ | |
1107 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656, | |
1108 | 752, 800, 0, 480, 490, 492, 525, 0, | |
1109 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ | |
1110 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, | |
1111 | 846, 900, 0, 400, 421, 423, 449, 0, | |
1112 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ | |
1113 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, | |
1114 | 846, 900, 0, 400, 412, 414, 449, 0, | |
1115 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ | |
1116 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, | |
1117 | 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, | |
1118 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ | |
1119 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040, | |
1120 | 1136, 1312, 0, 768, 769, 772, 800, 0, | |
1121 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ | |
1122 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, | |
1123 | 1184, 1328, 0, 768, 771, 777, 806, 0, | |
1124 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ | |
1125 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, | |
1126 | 1184, 1344, 0, 768, 771, 777, 806, 0, | |
1127 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ | |
1128 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, | |
1129 | 1208, 1264, 0, 768, 768, 776, 817, 0, | |
1130 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ | |
1131 | { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, | |
1132 | 928, 1152, 0, 624, 625, 628, 667, 0, | |
1133 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ | |
1134 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, | |
1135 | 896, 1056, 0, 600, 601, 604, 625, 0, | |
1136 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ | |
1137 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, | |
1138 | 976, 1040, 0, 600, 637, 643, 666, 0, | |
1139 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ | |
1140 | { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, | |
1141 | 1344, 1600, 0, 864, 865, 868, 900, 0, | |
1142 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ | |
1143 | }; | |
1144 | ||
f453ba04 DA |
1145 | /** |
1146 | * add_established_modes - get est. modes from EDID and add them | |
1147 | * @edid: EDID block to scan | |
1148 | * | |
1149 | * Each EDID block contains a bitmap of the supported "established modes" list | |
1150 | * (defined above). Tease them out and add them to the global modes list. | |
1151 | */ | |
1152 | static int add_established_modes(struct drm_connector *connector, struct edid *edid) | |
1153 | { | |
1154 | struct drm_device *dev = connector->dev; | |
1155 | unsigned long est_bits = edid->established_timings.t1 | | |
1156 | (edid->established_timings.t2 << 8) | | |
1157 | ((edid->established_timings.mfg_rsvd & 0x80) << 9); | |
1158 | int i, modes = 0; | |
1159 | ||
1160 | for (i = 0; i <= EDID_EST_TIMINGS; i++) | |
1161 | if (est_bits & (1<<i)) { | |
1162 | struct drm_display_mode *newmode; | |
1163 | newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); | |
1164 | if (newmode) { | |
1165 | drm_mode_probed_add(connector, newmode); | |
1166 | modes++; | |
1167 | } | |
1168 | } | |
1169 | ||
1170 | return modes; | |
1171 | } | |
1172 | ||
1173 | /** | |
1174 | * add_standard_modes - get std. modes from EDID and add them | |
1175 | * @edid: EDID block to scan | |
1176 | * | |
1177 | * Standard modes can be calculated using the CVT standard. Grab them from | |
1178 | * @edid, calculate them, and add them to the list. | |
1179 | */ | |
1180 | static int add_standard_modes(struct drm_connector *connector, struct edid *edid) | |
1181 | { | |
f453ba04 DA |
1182 | int i, modes = 0; |
1183 | ||
1184 | for (i = 0; i < EDID_STD_TIMINGS; i++) { | |
f453ba04 DA |
1185 | struct drm_display_mode *newmode; |
1186 | ||
7a374350 AJ |
1187 | newmode = drm_mode_std(connector, edid, |
1188 | &edid->standard_timings[i], | |
1189 | edid->revision); | |
f453ba04 DA |
1190 | if (newmode) { |
1191 | drm_mode_probed_add(connector, newmode); | |
1192 | modes++; | |
1193 | } | |
1194 | } | |
1195 | ||
1196 | return modes; | |
1197 | } | |
1198 | ||
07a5e632 | 1199 | static bool |
b17e52ef | 1200 | mode_is_rb(struct drm_display_mode *mode) |
07a5e632 | 1201 | { |
b17e52ef AJ |
1202 | return (mode->htotal - mode->hdisplay == 160) && |
1203 | (mode->hsync_end - mode->hdisplay == 80) && | |
1204 | (mode->hsync_end - mode->hsync_start == 32) && | |
1205 | (mode->vsync_start - mode->vdisplay == 3); | |
1206 | } | |
07a5e632 | 1207 | |
b17e52ef AJ |
1208 | static bool |
1209 | mode_in_hsync_range(struct drm_display_mode *mode, struct edid *edid, u8 *t) | |
1210 | { | |
1211 | int hsync, hmin, hmax; | |
1212 | ||
1213 | hmin = t[7]; | |
1214 | if (edid->revision >= 4) | |
1215 | hmin += ((t[4] & 0x04) ? 255 : 0); | |
1216 | hmax = t[8]; | |
1217 | if (edid->revision >= 4) | |
1218 | hmax += ((t[4] & 0x08) ? 255 : 0); | |
07a5e632 | 1219 | hsync = drm_mode_hsync(mode); |
07a5e632 | 1220 | |
b17e52ef AJ |
1221 | return (hsync <= hmax && hsync >= hmin); |
1222 | } | |
1223 | ||
1224 | static bool | |
1225 | mode_in_vsync_range(struct drm_display_mode *mode, struct edid *edid, u8 *t) | |
1226 | { | |
1227 | int vsync, vmin, vmax; | |
1228 | ||
1229 | vmin = t[5]; | |
1230 | if (edid->revision >= 4) | |
1231 | vmin += ((t[4] & 0x01) ? 255 : 0); | |
1232 | vmax = t[6]; | |
1233 | if (edid->revision >= 4) | |
1234 | vmax += ((t[4] & 0x02) ? 255 : 0); | |
1235 | vsync = drm_mode_vrefresh(mode); | |
1236 | ||
1237 | return (vsync <= vmax && vsync >= vmin); | |
1238 | } | |
1239 | ||
1240 | static u32 | |
1241 | range_pixel_clock(struct edid *edid, u8 *t) | |
1242 | { | |
1243 | /* unspecified */ | |
1244 | if (t[9] == 0 || t[9] == 255) | |
1245 | return 0; | |
1246 | ||
1247 | /* 1.4 with CVT support gives us real precision, yay */ | |
1248 | if (edid->revision >= 4 && t[10] == 0x04) | |
1249 | return (t[9] * 10000) - ((t[12] >> 2) * 250); | |
1250 | ||
1251 | /* 1.3 is pathetic, so fuzz up a bit */ | |
1252 | return t[9] * 10000 + 5001; | |
1253 | } | |
1254 | ||
b17e52ef AJ |
1255 | static bool |
1256 | mode_in_range(struct drm_display_mode *mode, struct edid *edid, | |
1257 | struct detailed_timing *timing) | |
1258 | { | |
1259 | u32 max_clock; | |
1260 | u8 *t = (u8 *)timing; | |
1261 | ||
1262 | if (!mode_in_hsync_range(mode, edid, t)) | |
07a5e632 AJ |
1263 | return false; |
1264 | ||
b17e52ef | 1265 | if (!mode_in_vsync_range(mode, edid, t)) |
07a5e632 AJ |
1266 | return false; |
1267 | ||
b17e52ef | 1268 | if ((max_clock = range_pixel_clock(edid, t))) |
07a5e632 AJ |
1269 | if (mode->clock > max_clock) |
1270 | return false; | |
b17e52ef AJ |
1271 | |
1272 | /* 1.4 max horizontal check */ | |
1273 | if (edid->revision >= 4 && t[10] == 0x04) | |
1274 | if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) | |
1275 | return false; | |
1276 | ||
1277 | if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) | |
1278 | return false; | |
07a5e632 AJ |
1279 | |
1280 | return true; | |
1281 | } | |
1282 | ||
1283 | /* | |
1284 | * XXX If drm_dmt_modes ever regrows the CVT-R modes (and it will) this will | |
1285 | * need to account for them. | |
1286 | */ | |
b17e52ef AJ |
1287 | static int |
1288 | drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, | |
1289 | struct detailed_timing *timing) | |
07a5e632 AJ |
1290 | { |
1291 | int i, modes = 0; | |
1292 | struct drm_display_mode *newmode; | |
1293 | struct drm_device *dev = connector->dev; | |
1294 | ||
1295 | for (i = 0; i < drm_num_dmt_modes; i++) { | |
b17e52ef | 1296 | if (mode_in_range(drm_dmt_modes + i, edid, timing)) { |
07a5e632 AJ |
1297 | newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); |
1298 | if (newmode) { | |
1299 | drm_mode_probed_add(connector, newmode); | |
1300 | modes++; | |
1301 | } | |
1302 | } | |
1303 | } | |
1304 | ||
1305 | return modes; | |
1306 | } | |
1307 | ||
9340d8cf AJ |
1308 | static int drm_cvt_modes(struct drm_connector *connector, |
1309 | struct detailed_timing *timing) | |
1310 | { | |
1311 | int i, j, modes = 0; | |
1312 | struct drm_display_mode *newmode; | |
1313 | struct drm_device *dev = connector->dev; | |
1314 | struct cvt_timing *cvt; | |
1315 | const int rates[] = { 60, 85, 75, 60, 50 }; | |
69da3015 | 1316 | const u8 empty[3] = { 0, 0, 0 }; |
9340d8cf AJ |
1317 | |
1318 | for (i = 0; i < 4; i++) { | |
29ebdf92 | 1319 | int uninitialized_var(width), height; |
9340d8cf AJ |
1320 | cvt = &(timing->data.other_data.data.cvt[i]); |
1321 | ||
69da3015 AJ |
1322 | if (!memcmp(cvt->code, empty, 3)) |
1323 | continue; | |
1324 | ||
8e10ee9a AJ |
1325 | height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; |
1326 | switch (cvt->code[1] & 0x0c) { | |
9340d8cf AJ |
1327 | case 0x00: |
1328 | width = height * 4 / 3; | |
1329 | break; | |
8e10ee9a | 1330 | case 0x04: |
9340d8cf AJ |
1331 | width = height * 16 / 9; |
1332 | break; | |
8e10ee9a | 1333 | case 0x08: |
9340d8cf AJ |
1334 | width = height * 16 / 10; |
1335 | break; | |
8e10ee9a | 1336 | case 0x0c: |
9340d8cf AJ |
1337 | width = height * 15 / 9; |
1338 | break; | |
1339 | } | |
1340 | ||
1341 | for (j = 1; j < 5; j++) { | |
1342 | if (cvt->code[2] & (1 << j)) { | |
1343 | newmode = drm_cvt_mode(dev, width, height, | |
1344 | rates[j], j == 0, | |
1345 | false, false); | |
1346 | if (newmode) { | |
1347 | drm_mode_probed_add(connector, newmode); | |
1348 | modes++; | |
1349 | } | |
1350 | } | |
1351 | } | |
1352 | } | |
1353 | ||
1354 | return modes; | |
1355 | } | |
1356 | ||
2255be14 AJ |
1357 | static const struct { |
1358 | short w; | |
1359 | short h; | |
1360 | short r; | |
1361 | short rb; | |
1362 | } est3_modes[] = { | |
1363 | /* byte 6 */ | |
1364 | { 640, 350, 85, 0 }, | |
1365 | { 640, 400, 85, 0 }, | |
1366 | { 720, 400, 85, 0 }, | |
1367 | { 640, 480, 85, 0 }, | |
1368 | { 848, 480, 60, 0 }, | |
1369 | { 800, 600, 85, 0 }, | |
1370 | { 1024, 768, 85, 0 }, | |
1371 | { 1152, 864, 75, 0 }, | |
1372 | /* byte 7 */ | |
1373 | { 1280, 768, 60, 1 }, | |
1374 | { 1280, 768, 60, 0 }, | |
1375 | { 1280, 768, 75, 0 }, | |
1376 | { 1280, 768, 85, 0 }, | |
1377 | { 1280, 960, 60, 0 }, | |
1378 | { 1280, 960, 85, 0 }, | |
1379 | { 1280, 1024, 60, 0 }, | |
1380 | { 1280, 1024, 85, 0 }, | |
1381 | /* byte 8 */ | |
1382 | { 1360, 768, 60, 0 }, | |
1383 | { 1440, 900, 60, 1 }, | |
1384 | { 1440, 900, 60, 0 }, | |
1385 | { 1440, 900, 75, 0 }, | |
1386 | { 1440, 900, 85, 0 }, | |
1387 | { 1400, 1050, 60, 1 }, | |
1388 | { 1400, 1050, 60, 0 }, | |
1389 | { 1400, 1050, 75, 0 }, | |
1390 | /* byte 9 */ | |
1391 | { 1400, 1050, 85, 0 }, | |
1392 | { 1680, 1050, 60, 1 }, | |
1393 | { 1680, 1050, 60, 0 }, | |
1394 | { 1680, 1050, 75, 0 }, | |
1395 | { 1680, 1050, 85, 0 }, | |
1396 | { 1600, 1200, 60, 0 }, | |
1397 | { 1600, 1200, 65, 0 }, | |
1398 | { 1600, 1200, 70, 0 }, | |
1399 | /* byte 10 */ | |
1400 | { 1600, 1200, 75, 0 }, | |
1401 | { 1600, 1200, 85, 0 }, | |
1402 | { 1792, 1344, 60, 0 }, | |
1403 | { 1792, 1344, 85, 0 }, | |
1404 | { 1856, 1392, 60, 0 }, | |
1405 | { 1856, 1392, 75, 0 }, | |
1406 | { 1920, 1200, 60, 1 }, | |
1407 | { 1920, 1200, 60, 0 }, | |
1408 | /* byte 11 */ | |
1409 | { 1920, 1200, 75, 0 }, | |
1410 | { 1920, 1200, 85, 0 }, | |
1411 | { 1920, 1440, 60, 0 }, | |
1412 | { 1920, 1440, 75, 0 }, | |
1413 | }; | |
1414 | static const int num_est3_modes = sizeof(est3_modes) / sizeof(est3_modes[0]); | |
1415 | ||
1416 | static int | |
1417 | drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) | |
1418 | { | |
1419 | int i, j, m, modes = 0; | |
1420 | struct drm_display_mode *mode; | |
1421 | u8 *est = ((u8 *)timing) + 5; | |
1422 | ||
1423 | for (i = 0; i < 6; i++) { | |
1424 | for (j = 7; j > 0; j--) { | |
1425 | m = (i * 8) + (7 - j); | |
0ddfa7d5 | 1426 | if (m >= num_est3_modes) |
2255be14 AJ |
1427 | break; |
1428 | if (est[i] & (1 << j)) { | |
1d42bbc8 DA |
1429 | mode = drm_mode_find_dmt(connector->dev, |
1430 | est3_modes[m].w, | |
1431 | est3_modes[m].h, | |
1432 | est3_modes[m].r | |
1433 | /*, est3_modes[m].rb */); | |
2255be14 AJ |
1434 | if (mode) { |
1435 | drm_mode_probed_add(connector, mode); | |
1436 | modes++; | |
1437 | } | |
1438 | } | |
1439 | } | |
1440 | } | |
1441 | ||
1442 | return modes; | |
1443 | } | |
1444 | ||
9cf00977 AJ |
1445 | static int add_detailed_modes(struct drm_connector *connector, |
1446 | struct detailed_timing *timing, | |
1447 | struct edid *edid, u32 quirks, int preferred) | |
1448 | { | |
1449 | int i, modes = 0; | |
1450 | struct detailed_non_pixel *data = &timing->data.other_data; | |
07a5e632 | 1451 | int gtf = (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF); |
9cf00977 AJ |
1452 | struct drm_display_mode *newmode; |
1453 | struct drm_device *dev = connector->dev; | |
1454 | ||
1455 | if (timing->pixel_clock) { | |
1456 | newmode = drm_mode_detailed(dev, edid, timing, quirks); | |
1457 | if (!newmode) | |
1458 | return 0; | |
1459 | ||
1460 | if (preferred) | |
1461 | newmode->type |= DRM_MODE_TYPE_PREFERRED; | |
1462 | ||
1463 | drm_mode_probed_add(connector, newmode); | |
1464 | return 1; | |
1465 | } | |
1466 | ||
1467 | /* other timing types */ | |
1468 | switch (data->type) { | |
1469 | case EDID_DETAIL_MONITOR_RANGE: | |
07a5e632 | 1470 | if (gtf) |
b17e52ef AJ |
1471 | modes += drm_gtf_modes_for_range(connector, edid, |
1472 | timing); | |
9cf00977 AJ |
1473 | break; |
1474 | case EDID_DETAIL_STD_MODES: | |
1475 | /* Six modes per detailed section */ | |
1476 | for (i = 0; i < 6; i++) { | |
1477 | struct std_timing *std; | |
1478 | struct drm_display_mode *newmode; | |
1479 | ||
1480 | std = &data->data.timings[i]; | |
7a374350 AJ |
1481 | newmode = drm_mode_std(connector, edid, std, |
1482 | edid->revision); | |
9cf00977 AJ |
1483 | if (newmode) { |
1484 | drm_mode_probed_add(connector, newmode); | |
1485 | modes++; | |
1486 | } | |
1487 | } | |
1488 | break; | |
9340d8cf AJ |
1489 | case EDID_DETAIL_CVT_3BYTE: |
1490 | modes += drm_cvt_modes(connector, timing); | |
1491 | break; | |
2255be14 AJ |
1492 | case EDID_DETAIL_EST_TIMINGS: |
1493 | modes += drm_est3_modes(connector, timing); | |
1494 | break; | |
9cf00977 AJ |
1495 | default: |
1496 | break; | |
1497 | } | |
1498 | ||
1499 | return modes; | |
1500 | } | |
1501 | ||
f453ba04 | 1502 | /** |
9cf00977 | 1503 | * add_detailed_info - get detailed mode info from EDID data |
f453ba04 DA |
1504 | * @connector: attached connector |
1505 | * @edid: EDID block to scan | |
1506 | * @quirks: quirks to apply | |
1507 | * | |
1508 | * Some of the detailed timing sections may contain mode information. Grab | |
1509 | * it and add it to the list. | |
1510 | */ | |
1511 | static int add_detailed_info(struct drm_connector *connector, | |
1512 | struct edid *edid, u32 quirks) | |
1513 | { | |
9cf00977 | 1514 | int i, modes = 0; |
f453ba04 DA |
1515 | |
1516 | for (i = 0; i < EDID_DETAILED_TIMINGS; i++) { | |
1517 | struct detailed_timing *timing = &edid->detailed_timings[i]; | |
a327f6b8 AJ |
1518 | int preferred = (i == 0); |
1519 | ||
1520 | if (preferred && edid->version == 1 && edid->revision < 4) | |
1521 | preferred = (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); | |
f453ba04 | 1522 | |
9cf00977 AJ |
1523 | /* In 1.0, only timings are allowed */ |
1524 | if (!timing->pixel_clock && edid->version == 1 && | |
1525 | edid->revision == 0) | |
1526 | continue; | |
f453ba04 | 1527 | |
9cf00977 AJ |
1528 | modes += add_detailed_modes(connector, timing, edid, quirks, |
1529 | preferred); | |
f453ba04 DA |
1530 | } |
1531 | ||
1532 | return modes; | |
1533 | } | |
9cf00977 | 1534 | |
882f0219 ZY |
1535 | /** |
1536 | * add_detailed_mode_eedid - get detailed mode info from addtional timing | |
1537 | * EDID block | |
1538 | * @connector: attached connector | |
1539 | * @edid: EDID block to scan(It is only to get addtional timing EDID block) | |
1540 | * @quirks: quirks to apply | |
1541 | * | |
1542 | * Some of the detailed timing sections may contain mode information. Grab | |
1543 | * it and add it to the list. | |
1544 | */ | |
1545 | static int add_detailed_info_eedid(struct drm_connector *connector, | |
1546 | struct edid *edid, u32 quirks) | |
1547 | { | |
9cf00977 | 1548 | int i, modes = 0; |
882f0219 ZY |
1549 | char *edid_ext = NULL; |
1550 | struct detailed_timing *timing; | |
882f0219 | 1551 | int start_offset, end_offset; |
882f0219 | 1552 | |
59d8aff6 | 1553 | if (edid->version == 1 && edid->revision < 3) |
882f0219 | 1554 | return 0; |
59d8aff6 | 1555 | if (!edid->extensions) |
882f0219 | 1556 | return 0; |
882f0219 ZY |
1557 | |
1558 | /* Find CEA extension */ | |
7466f4cc | 1559 | for (i = 0; i < edid->extensions; i++) { |
882f0219 | 1560 | edid_ext = (char *)edid + EDID_LENGTH * (i + 1); |
882f0219 ZY |
1561 | if (edid_ext[0] == 0x02) |
1562 | break; | |
1563 | } | |
1564 | ||
59d8aff6 | 1565 | if (i == edid->extensions) |
882f0219 | 1566 | return 0; |
882f0219 ZY |
1567 | |
1568 | /* Get the start offset of detailed timing block */ | |
1569 | start_offset = edid_ext[2]; | |
1570 | if (start_offset == 0) { | |
1571 | /* If the start_offset is zero, it means that neither detailed | |
1572 | * info nor data block exist. In such case it is also | |
1573 | * unnecessary to parse the detailed timing info. | |
1574 | */ | |
1575 | return 0; | |
1576 | } | |
1577 | ||
882f0219 ZY |
1578 | end_offset = EDID_LENGTH; |
1579 | end_offset -= sizeof(struct detailed_timing); | |
1580 | for (i = start_offset; i < end_offset; | |
1581 | i += sizeof(struct detailed_timing)) { | |
1582 | timing = (struct detailed_timing *)(edid_ext + i); | |
9cf00977 | 1583 | modes += add_detailed_modes(connector, timing, edid, quirks, 0); |
882f0219 ZY |
1584 | } |
1585 | ||
1586 | return modes; | |
1587 | } | |
f453ba04 | 1588 | |
f23c20c8 ML |
1589 | #define HDMI_IDENTIFIER 0x000C03 |
1590 | #define VENDOR_BLOCK 0x03 | |
1591 | /** | |
1592 | * drm_detect_hdmi_monitor - detect whether monitor is hdmi. | |
1593 | * @edid: monitor EDID information | |
1594 | * | |
1595 | * Parse the CEA extension according to CEA-861-B. | |
1596 | * Return true if HDMI, false if not or unknown. | |
1597 | */ | |
1598 | bool drm_detect_hdmi_monitor(struct edid *edid) | |
1599 | { | |
1600 | char *edid_ext = NULL; | |
7466f4cc | 1601 | int i, hdmi_id; |
f23c20c8 ML |
1602 | int start_offset, end_offset; |
1603 | bool is_hdmi = false; | |
1604 | ||
1605 | /* No EDID or EDID extensions */ | |
1606 | if (edid == NULL || edid->extensions == 0) | |
1607 | goto end; | |
1608 | ||
f23c20c8 | 1609 | /* Find CEA extension */ |
7466f4cc | 1610 | for (i = 0; i < edid->extensions; i++) { |
f23c20c8 ML |
1611 | edid_ext = (char *)edid + EDID_LENGTH * (i + 1); |
1612 | /* This block is CEA extension */ | |
1613 | if (edid_ext[0] == 0x02) | |
1614 | break; | |
1615 | } | |
1616 | ||
7466f4cc | 1617 | if (i == edid->extensions) |
f23c20c8 ML |
1618 | goto end; |
1619 | ||
1620 | /* Data block offset in CEA extension block */ | |
1621 | start_offset = 4; | |
1622 | end_offset = edid_ext[2]; | |
1623 | ||
1624 | /* | |
1625 | * Because HDMI identifier is in Vendor Specific Block, | |
1626 | * search it from all data blocks of CEA extension. | |
1627 | */ | |
1628 | for (i = start_offset; i < end_offset; | |
1629 | /* Increased by data block len */ | |
1630 | i += ((edid_ext[i] & 0x1f) + 1)) { | |
1631 | /* Find vendor specific block */ | |
1632 | if ((edid_ext[i] >> 5) == VENDOR_BLOCK) { | |
1633 | hdmi_id = edid_ext[i + 1] | (edid_ext[i + 2] << 8) | | |
1634 | edid_ext[i + 3] << 16; | |
1635 | /* Find HDMI identifier */ | |
1636 | if (hdmi_id == HDMI_IDENTIFIER) | |
1637 | is_hdmi = true; | |
1638 | break; | |
1639 | } | |
1640 | } | |
1641 | ||
1642 | end: | |
1643 | return is_hdmi; | |
1644 | } | |
1645 | EXPORT_SYMBOL(drm_detect_hdmi_monitor); | |
1646 | ||
f453ba04 DA |
1647 | /** |
1648 | * drm_add_edid_modes - add modes from EDID data, if available | |
1649 | * @connector: connector we're probing | |
1650 | * @edid: edid data | |
1651 | * | |
1652 | * Add the specified modes to the connector's mode list. | |
1653 | * | |
1654 | * Return number of modes added or 0 if we couldn't find any. | |
1655 | */ | |
1656 | int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) | |
1657 | { | |
1658 | int num_modes = 0; | |
1659 | u32 quirks; | |
1660 | ||
1661 | if (edid == NULL) { | |
1662 | return 0; | |
1663 | } | |
3c537889 | 1664 | if (!drm_edid_is_valid(edid)) { |
dcdb1674 | 1665 | dev_warn(connector->dev->dev, "%s: EDID invalid.\n", |
f453ba04 DA |
1666 | drm_get_connector_name(connector)); |
1667 | return 0; | |
1668 | } | |
1669 | ||
1670 | quirks = edid_get_quirks(edid); | |
1671 | ||
c867df70 AJ |
1672 | /* |
1673 | * EDID spec says modes should be preferred in this order: | |
1674 | * - preferred detailed mode | |
1675 | * - other detailed modes from base block | |
1676 | * - detailed modes from extension blocks | |
1677 | * - CVT 3-byte code modes | |
1678 | * - standard timing codes | |
1679 | * - established timing codes | |
1680 | * - modes inferred from GTF or CVT range information | |
1681 | * | |
1682 | * We don't quite implement this yet, but we're close. | |
1683 | * | |
1684 | * XXX order for additional mode types in extension blocks? | |
1685 | */ | |
f453ba04 | 1686 | num_modes += add_detailed_info(connector, edid, quirks); |
882f0219 | 1687 | num_modes += add_detailed_info_eedid(connector, edid, quirks); |
c867df70 AJ |
1688 | num_modes += add_standard_modes(connector, edid); |
1689 | num_modes += add_established_modes(connector, edid); | |
f453ba04 DA |
1690 | |
1691 | if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) | |
1692 | edid_fixup_preferred(connector, quirks); | |
1693 | ||
f453ba04 DA |
1694 | connector->display_info.width_mm = edid->width_cm * 10; |
1695 | connector->display_info.height_mm = edid->height_cm * 10; | |
f453ba04 DA |
1696 | |
1697 | return num_modes; | |
1698 | } | |
1699 | EXPORT_SYMBOL(drm_add_edid_modes); | |
f0fda0a4 ZY |
1700 | |
1701 | /** | |
1702 | * drm_add_modes_noedid - add modes for the connectors without EDID | |
1703 | * @connector: connector we're probing | |
1704 | * @hdisplay: the horizontal display limit | |
1705 | * @vdisplay: the vertical display limit | |
1706 | * | |
1707 | * Add the specified modes to the connector's mode list. Only when the | |
1708 | * hdisplay/vdisplay is not beyond the given limit, it will be added. | |
1709 | * | |
1710 | * Return number of modes added or 0 if we couldn't find any. | |
1711 | */ | |
1712 | int drm_add_modes_noedid(struct drm_connector *connector, | |
1713 | int hdisplay, int vdisplay) | |
1714 | { | |
1715 | int i, count, num_modes = 0; | |
1716 | struct drm_display_mode *mode, *ptr; | |
1717 | struct drm_device *dev = connector->dev; | |
1718 | ||
1719 | count = sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode); | |
1720 | if (hdisplay < 0) | |
1721 | hdisplay = 0; | |
1722 | if (vdisplay < 0) | |
1723 | vdisplay = 0; | |
1724 | ||
1725 | for (i = 0; i < count; i++) { | |
1726 | ptr = &drm_dmt_modes[i]; | |
1727 | if (hdisplay && vdisplay) { | |
1728 | /* | |
1729 | * Only when two are valid, they will be used to check | |
1730 | * whether the mode should be added to the mode list of | |
1731 | * the connector. | |
1732 | */ | |
1733 | if (ptr->hdisplay > hdisplay || | |
1734 | ptr->vdisplay > vdisplay) | |
1735 | continue; | |
1736 | } | |
f985dedb AJ |
1737 | if (drm_mode_vrefresh(ptr) > 61) |
1738 | continue; | |
f0fda0a4 ZY |
1739 | mode = drm_mode_duplicate(dev, ptr); |
1740 | if (mode) { | |
1741 | drm_mode_probed_add(connector, mode); | |
1742 | num_modes++; | |
1743 | } | |
1744 | } | |
1745 | return num_modes; | |
1746 | } | |
1747 | EXPORT_SYMBOL(drm_add_modes_noedid); |