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drm/edid: Strengthen the algorithm for standard mode codes
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / drm_edid.c
CommitLineData
f453ba04
DA		 1/*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
61e57a8d 5 * Copyright 2010 Red Hat, Inc.
f453ba04
DA		 6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30#include <linux/kernel.h>
31#include <linux/i2c.h>
32#include <linux/i2c-algo-bit.h>
33#include "drmP.h"
34#include "drm_edid.h"
35
d1ff6409
AJ		 36#define EDID_EST_TIMINGS 16
37#define EDID_STD_TIMINGS 8
38#define EDID_DETAILED_TIMINGS 4
39
f453ba04
DA		 40/*
41 * EDID blocks out in the wild have a variety of bugs, try to collect
42 * them here (note that userspace may work around broken monitors first,
43 * but fixes should make their way here so that the kernel "just works"
44 * on as many displays as possible).
45 */
46
47/* First detailed mode wrong, use largest 60Hz mode */
48#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
49/* Reported 135MHz pixel clock is too high, needs adjustment */
50#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
51/* Prefer the largest mode at 75 Hz */
52#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
53/* Detail timing is in cm not mm */
54#define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
55/* Detailed timing descriptors have bogus size values, so just take the
56 * maximum size and use that.
57 */
58#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
59/* Monitor forgot to set the first detailed is preferred bit. */
60#define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
61/* use +hsync +vsync for detailed mode */
62#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
3c537889 63
f453ba04 64
5c61259e
ZY		 65#define LEVEL_DMT 0
66#define LEVEL_GTF 1
67#define LEVEL_CVT 2
68
f453ba04
DA		 69static struct edid_quirk {
70 char *vendor;
71 int product_id;
72 u32 quirks;
73} edid_quirk_list[] = {
74 /* Acer AL1706 */
75 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
76 /* Acer F51 */
77 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
78 /* Unknown Acer */
79 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
80
81 /* Belinea 10 15 55 */
82 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
83 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
84
85 /* Envision Peripherals, Inc. EN-7100e */
86 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
87
88 /* Funai Electronics PM36B */
89 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
90 EDID_QUIRK_DETAILED_IN_CM },
91
92 /* LG Philips LCD LP154W01-A5 */
93 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
94 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
95
96 /* Philips 107p5 CRT */
97 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
98
99 /* Proview AY765C */
100 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
101
102 /* Samsung SyncMaster 205BW. Note: irony */
103 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
104 /* Samsung SyncMaster 22[5-6]BW */
105 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
106 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
107};
108
61e57a8d 109/*** DDC fetch and block validation ***/
f453ba04 110
083ae056
AJ		 111static const u8 edid_header[] = {
112 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
113};
f453ba04 114
61e57a8d
AJ		 115/*
116 * Sanity check the EDID block (base or extension). Return 0 if the block
117 * doesn't check out, or 1 if it's valid.
f453ba04 118 */
61e57a8d
AJ		 119static bool
120drm_edid_block_valid(u8 *raw_edid)
f453ba04 121{
61e57a8d 122 int i;
f453ba04 123 u8 csum = 0;
61e57a8d 124 struct edid *edid = (struct edid *)raw_edid;
f453ba04 125
61e57a8d
AJ		 126 if (raw_edid[0] == 0x00) {
127 int score = 0;
862b89c0 128
61e57a8d
AJ		 129 for (i = 0; i < sizeof(edid_header); i++)
130 if (raw_edid[i] == edid_header[i])
131 score++;
132
133 if (score == 8) ;
134 else if (score >= 6) {
135 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
136 memcpy(raw_edid, edid_header, sizeof(edid_header));
137 } else {
138 goto bad;
139 }
140 }
f453ba04
DA		 141
142 for (i = 0; i < EDID_LENGTH; i++)
143 csum += raw_edid[i];
144 if (csum) {
145 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum);
146 goto bad;
147 }
148
61e57a8d
AJ		 149 /* per-block-type checks */
150 switch (raw_edid[0]) {
151 case 0: /* base */
152 if (edid->version != 1) {
153 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version);
154 goto bad;
155 }
862b89c0 156
61e57a8d
AJ		 157 if (edid->revision > 4)
158 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
159 break;
160
161 default:
162 break;
163 }
47ee4ccf 164
f453ba04
DA		 165 return 1;
166
167bad:
168 if (raw_edid) {
169 DRM_ERROR("Raw EDID:\n");
170 print_hex_dump_bytes(KERN_ERR, DUMP_PREFIX_NONE, raw_edid, EDID_LENGTH);
171 printk("\n");
172 }
173 return 0;
174}
61e57a8d
AJ		 175
176/**
177 * drm_edid_is_valid - sanity check EDID data
178 * @edid: EDID data
179 *
180 * Sanity-check an entire EDID record (including extensions)
181 */
182bool drm_edid_is_valid(struct edid *edid)
183{
184 int i;
185 u8 *raw = (u8 *)edid;
186
187 if (!edid)
188 return false;
189
190 for (i = 0; i <= edid->extensions; i++)
191 if (!drm_edid_block_valid(raw + i * EDID_LENGTH))
192 return false;
193
194 return true;
195}
3c537889 196EXPORT_SYMBOL(drm_edid_is_valid);
f453ba04 197
61e57a8d
AJ		 198#define DDC_ADDR 0x50
199#define DDC_SEGMENT_ADDR 0x30
200/**
201 * Get EDID information via I2C.
202 *
203 * \param adapter : i2c device adaptor
204 * \param buf : EDID data buffer to be filled
205 * \param len : EDID data buffer length
206 * \return 0 on success or -1 on failure.
207 *
208 * Try to fetch EDID information by calling i2c driver function.
209 */
210static int
211drm_do_probe_ddc_edid(struct i2c_adapter *adapter, unsigned char *buf,
212 int block, int len)
213{
214 unsigned char start = block * EDID_LENGTH;
215 struct i2c_msg msgs[] = {
216 {
217 .addr = DDC_ADDR,
218 .flags = 0,
219 .len = 1,
220 .buf = &start,
221 }, {
222 .addr = DDC_ADDR,
223 .flags = I2C_M_RD,
224 .len = len,
225 .buf = buf + start,
226 }
227 };
228
229 if (i2c_transfer(adapter, msgs, 2) == 2)
230 return 0;
231
232 return -1;
233}
234
235static u8 *
236drm_do_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
237{
238 int i, j = 0;
239 u8 *block, *new;
240
241 if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
242 return NULL;
243
244 /* base block fetch */
245 for (i = 0; i < 4; i++) {
246 if (drm_do_probe_ddc_edid(adapter, block, 0, EDID_LENGTH))
247 goto out;
248 if (drm_edid_block_valid(block))
249 break;
250 }
251 if (i == 4)
252 goto carp;
253
254 /* if there's no extensions, we're done */
255 if (block[0x7e] == 0)
256 return block;
257
258 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL);
259 if (!new)
260 goto out;
261 block = new;
262
263 for (j = 1; j <= block[0x7e]; j++) {
264 for (i = 0; i < 4; i++) {
265 if (drm_do_probe_ddc_edid(adapter, block, j,
266 EDID_LENGTH))
267 goto out;
268 if (drm_edid_block_valid(block + j * EDID_LENGTH))
269 break;
270 }
271 if (i == 4)
272 goto carp;
273 }
274
275 return block;
276
277carp:
278 dev_warn(&connector->dev->pdev->dev, "%s: EDID block %d invalid.\n",
279 drm_get_connector_name(connector), j);
280
281out:
282 kfree(block);
283 return NULL;
284}
285
286/**
287 * Probe DDC presence.
288 *
289 * \param adapter : i2c device adaptor
290 * \return 1 on success
291 */
292static bool
293drm_probe_ddc(struct i2c_adapter *adapter)
294{
295 unsigned char out;
296
297 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
298}
299
300/**
301 * drm_get_edid - get EDID data, if available
302 * @connector: connector we're probing
303 * @adapter: i2c adapter to use for DDC
304 *
305 * Poke the given i2c channel to grab EDID data if possible. If found,
306 * attach it to the connector.
307 *
308 * Return edid data or NULL if we couldn't find any.
309 */
310struct edid *drm_get_edid(struct drm_connector *connector,
311 struct i2c_adapter *adapter)
312{
313 struct edid *edid = NULL;
314
315 if (drm_probe_ddc(adapter))
316 edid = (struct edid *)drm_do_get_edid(connector, adapter);
317
318 connector->display_info.raw_edid = (char *)edid;
319
320 return edid;
321
322}
323EXPORT_SYMBOL(drm_get_edid);
324
325/*** EDID parsing ***/
326
f453ba04
DA		 327/**
328 * edid_vendor - match a string against EDID's obfuscated vendor field
329 * @edid: EDID to match
330 * @vendor: vendor string
331 *
332 * Returns true if @vendor is in @edid, false otherwise
333 */
334static bool edid_vendor(struct edid *edid, char *vendor)
335{
336 char edid_vendor[3];
337
338 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
339 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
340 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
16456c87 341 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
f453ba04
DA		 342
343 return !strncmp(edid_vendor, vendor, 3);
344}
345
346/**
347 * edid_get_quirks - return quirk flags for a given EDID
348 * @edid: EDID to process
349 *
350 * This tells subsequent routines what fixes they need to apply.
351 */
352static u32 edid_get_quirks(struct edid *edid)
353{
354 struct edid_quirk *quirk;
355 int i;
356
357 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
358 quirk = &edid_quirk_list[i];
359
360 if (edid_vendor(edid, quirk->vendor) &&
361 (EDID_PRODUCT_ID(edid) == quirk->product_id))
362 return quirk->quirks;
363 }
364
365 return 0;
366}
367
368#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
369#define MODE_REFRESH_DIFF(m,r) (abs((m)->vrefresh - target_refresh))
370
371
372/**
373 * edid_fixup_preferred - set preferred modes based on quirk list
374 * @connector: has mode list to fix up
375 * @quirks: quirks list
376 *
377 * Walk the mode list for @connector, clearing the preferred status
378 * on existing modes and setting it anew for the right mode ala @quirks.
379 */
380static void edid_fixup_preferred(struct drm_connector *connector,
381 u32 quirks)
382{
383 struct drm_display_mode *t, *cur_mode, *preferred_mode;
f890607b 384 int target_refresh = 0;
f453ba04
DA		 385
386 if (list_empty(&connector->probed_modes))
387 return;
388
389 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
390 target_refresh = 60;
391 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
392 target_refresh = 75;
393
394 preferred_mode = list_first_entry(&connector->probed_modes,
395 struct drm_display_mode, head);
396
397 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
398 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
399
400 if (cur_mode == preferred_mode)
401 continue;
402
403 /* Largest mode is preferred */
404 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
405 preferred_mode = cur_mode;
406
407 /* At a given size, try to get closest to target refresh */
408 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
409 MODE_REFRESH_DIFF(cur_mode, target_refresh) <
410 MODE_REFRESH_DIFF(preferred_mode, target_refresh)) {
411 preferred_mode = cur_mode;
412 }
413 }
414
415 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
416}
417
aa9eaa1f
ZY		 418/*
419 * Add the Autogenerated from the DMT spec.
420 * This table is copied from xfree86/modes/xf86EdidModes.c.
421 * But the mode with Reduced blank feature is deleted.
422 */
423static struct drm_display_mode drm_dmt_modes[] = {
424 /* 640x350@85Hz */
425 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
426 736, 832, 0, 350, 382, 385, 445, 0,
427 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
428 /* 640x400@85Hz */
429 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
430 736, 832, 0, 400, 401, 404, 445, 0,
431 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
432 /* 720x400@85Hz */
433 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
434 828, 936, 0, 400, 401, 404, 446, 0,
435 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
436 /* 640x480@60Hz */
437 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
438 752, 800, 0, 480, 489, 492, 525, 0,
439 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
440 /* 640x480@72Hz */
441 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
442 704, 832, 0, 480, 489, 492, 520, 0,
443 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
444 /* 640x480@75Hz */
445 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
446 720, 840, 0, 480, 481, 484, 500, 0,
447 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
448 /* 640x480@85Hz */
449 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
450 752, 832, 0, 480, 481, 484, 509, 0,
451 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
452 /* 800x600@56Hz */
453 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
454 896, 1024, 0, 600, 601, 603, 625, 0,
455 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
456 /* 800x600@60Hz */
457 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
458 968, 1056, 0, 600, 601, 605, 628, 0,
459 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
460 /* 800x600@72Hz */
461 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
462 976, 1040, 0, 600, 637, 643, 666, 0,
463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
464 /* 800x600@75Hz */
465 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
466 896, 1056, 0, 600, 601, 604, 625, 0,
467 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
468 /* 800x600@85Hz */
469 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
470 896, 1048, 0, 600, 601, 604, 631, 0,
471 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
472 /* 848x480@60Hz */
473 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
474 976, 1088, 0, 480, 486, 494, 517, 0,
475 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
476 /* 1024x768@43Hz, interlace */
477 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
478 1208, 1264, 0, 768, 768, 772, 817, 0,
479 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
480 DRM_MODE_FLAG_INTERLACE) },
481 /* 1024x768@60Hz */
482 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
483 1184, 1344, 0, 768, 771, 777, 806, 0,
484 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
485 /* 1024x768@70Hz */
486 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
487 1184, 1328, 0, 768, 771, 777, 806, 0,
488 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
489 /* 1024x768@75Hz */
490 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
491 1136, 1312, 0, 768, 769, 772, 800, 0,
492 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
493 /* 1024x768@85Hz */
494 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
495 1072, 1376, 0, 768, 769, 772, 808, 0,
496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
497 /* 1152x864@75Hz */
498 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
499 1344, 1600, 0, 864, 865, 868, 900, 0,
500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
501 /* 1280x768@60Hz */
502 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
503 1472, 1664, 0, 768, 771, 778, 798, 0,
504 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
505 /* 1280x768@75Hz */
506 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
507 1488, 1696, 0, 768, 771, 778, 805, 0,
508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
509 /* 1280x768@85Hz */
510 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
511 1496, 1712, 0, 768, 771, 778, 809, 0,
512 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
513 /* 1280x800@60Hz */
514 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
515 1480, 1680, 0, 800, 803, 809, 831, 0,
516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
517 /* 1280x800@75Hz */
518 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
519 1488, 1696, 0, 800, 803, 809, 838, 0,
520 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
521 /* 1280x800@85Hz */
522 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
523 1496, 1712, 0, 800, 803, 809, 843, 0,
524 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
525 /* 1280x960@60Hz */
526 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
527 1488, 1800, 0, 960, 961, 964, 1000, 0,
528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
529 /* 1280x960@85Hz */
530 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
531 1504, 1728, 0, 960, 961, 964, 1011, 0,
532 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
533 /* 1280x1024@60Hz */
534 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
535 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
536 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
537 /* 1280x1024@75Hz */
538 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
539 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
540 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
541 /* 1280x1024@85Hz */
542 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
543 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
544 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
545 /* 1360x768@60Hz */
546 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
547 1536, 1792, 0, 768, 771, 777, 795, 0,
548 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
549 /* 1440x1050@60Hz */
550 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
551 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
552 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
553 /* 1440x1050@75Hz */
554 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
555 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
556 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
557 /* 1440x1050@85Hz */
558 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
559 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
560 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
561 /* 1440x900@60Hz */
562 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
563 1672, 1904, 0, 900, 903, 909, 934, 0,
564 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
565 /* 1440x900@75Hz */
566 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
567 1688, 1936, 0, 900, 903, 909, 942, 0,
568 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
569 /* 1440x900@85Hz */
570 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
571 1696, 1952, 0, 900, 903, 909, 948, 0,
572 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
573 /* 1600x1200@60Hz */
574 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
575 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
576 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
577 /* 1600x1200@65Hz */
578 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
579 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
580 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
581 /* 1600x1200@70Hz */
582 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
583 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
584 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
585 /* 1600x1200@75Hz */
586 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 2025000, 1600, 1664,
587 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
588 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
589 /* 1600x1200@85Hz */
590 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
591 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
592 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
593 /* 1680x1050@60Hz */
594 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
595 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
596 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
597 /* 1680x1050@75Hz */
598 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
599 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
600 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
601 /* 1680x1050@85Hz */
602 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
603 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
604 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
605 /* 1792x1344@60Hz */
606 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
607 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
608 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
609 /* 1729x1344@75Hz */
610 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
611 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
612 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
613 /* 1853x1392@60Hz */
614 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
615 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
616 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
617 /* 1856x1392@75Hz */
618 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
619 2208, 2560, 0, 1392, 1395, 1399, 1500, 0,
620 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
621 /* 1920x1200@60Hz */
622 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
623 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
624 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
625 /* 1920x1200@75Hz */
626 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
627 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
628 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
629 /* 1920x1200@85Hz */
630 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
631 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
632 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
633 /* 1920x1440@60Hz */
634 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
635 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
636 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
637 /* 1920x1440@75Hz */
638 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
639 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
640 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
641 /* 2560x1600@60Hz */
642 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
643 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
644 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
645 /* 2560x1600@75HZ */
646 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
647 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
648 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
649 /* 2560x1600@85HZ */
650 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
651 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
652 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
653};
07a5e632
AJ		 654static const int drm_num_dmt_modes =
655 sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode);
aa9eaa1f 656
559ee21d
ZY		 657static struct drm_display_mode *drm_find_dmt(struct drm_device *dev,
658 int hsize, int vsize, int fresh)
659{
07a5e632 660 int i;
559ee21d
ZY		 661 struct drm_display_mode *ptr, *mode;
662
559ee21d 663 mode = NULL;
07a5e632 664 for (i = 0; i < drm_num_dmt_modes; i++) {
559ee21d
ZY		 665 ptr = &drm_dmt_modes[i];
666 if (hsize == ptr->hdisplay &&
667 vsize == ptr->vdisplay &&
668 fresh == drm_mode_vrefresh(ptr)) {
669 /* get the expected default mode */
670 mode = drm_mode_duplicate(dev, ptr);
671 break;
672 }
673 }
674 return mode;
675}
23425cae 676
d1ff6409
AJ		 677typedef void detailed_cb(struct detailed_timing *timing, void *closure);
678
679static void
680drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
681{
682 int i;
683 struct edid *edid = (struct edid *)raw_edid;
684
685 if (edid == NULL)
686 return;
687
688 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
689 cb(&(edid->detailed_timings[i]), closure);
690
691 /* XXX extension block walk */
692}
693
694static void
695is_rb(struct detailed_timing *t, void *data)
696{
697 u8 *r = (u8 *)t;
698 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
699 if (r[15] & 0x10)
700 *(bool *)data = true;
701}
702
703/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
704static bool
705drm_monitor_supports_rb(struct edid *edid)
706{
707 if (edid->revision >= 4) {
708 bool ret;
709 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
710 return ret;
711 }
712
713 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
714}
715
23425cae
AJ		 716/*
717 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
718 * monitors fill with ascii space (0x20) instead.
719 */
720static int
721bad_std_timing(u8 a, u8 b)
722{
723 return (a == 0x00 && b == 0x00) ||
724 (a == 0x01 && b == 0x01) ||
725 (a == 0x20 && b == 0x20);
726}
727
f453ba04
DA		 728/**
729 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
730 * @t: standard timing params
5c61259e 731 * @timing_level: standard timing level
f453ba04
DA		 732 *
733 * Take the standard timing params (in this case width, aspect, and refresh)
5c61259e 734 * and convert them into a real mode using CVT/GTF/DMT.
f453ba04 735 */
7ca6adb3
AJ		 736static struct drm_display_mode *
737drm_mode_std(struct drm_connector *connector, struct std_timing *t,
738 int revision, int timing_level)
f453ba04 739{
7ca6adb3
AJ		 740 struct drm_device *dev = connector->dev;
741 struct drm_display_mode *m, *mode = NULL;
5c61259e
ZY		 742 int hsize, vsize;
743 int vrefresh_rate;
0454beab
MD		 744 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
745 >> EDID_TIMING_ASPECT_SHIFT;
5c61259e
ZY		 746 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
747 >> EDID_TIMING_VFREQ_SHIFT;
748
23425cae
AJ		 749 if (bad_std_timing(t->hsize, t->vfreq_aspect))
750 return NULL;
751
5c61259e
ZY		 752 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
753 hsize = t->hsize * 8 + 248;
754 /* vrefresh_rate = vfreq + 60 */
755 vrefresh_rate = vfreq + 60;
756 /* the vdisplay is calculated based on the aspect ratio */
f066a17d
AJ		 757 if (aspect_ratio == 0) {
758 if (revision < 3)
759 vsize = hsize;
760 else
761 vsize = (hsize * 10) / 16;
762 } else if (aspect_ratio == 1)
f453ba04 763 vsize = (hsize * 3) / 4;
0454beab 764 else if (aspect_ratio == 2)
f453ba04
DA		 765 vsize = (hsize * 4) / 5;
766 else
767 vsize = (hsize * 9) / 16;
a0910c8e
AJ		 768
769 /* HDTV hack, part 1 */
770 if (vrefresh_rate == 60 &&
771 ((hsize == 1360 && vsize == 765) ||
772 (hsize == 1368 && vsize == 769))) {
773 hsize = 1366;
774 vsize = 768;
775 }
776
7ca6adb3
AJ		 777 /*
778 * If this connector already has a mode for this size and refresh
779 * rate (because it came from detailed or CVT info), use that
780 * instead. This way we don't have to guess at interlace or
781 * reduced blanking.
782 */
783 list_for_each_entry(m, &connector->modes, head)
784 if (m->hdisplay == hsize && m->vdisplay == vsize &&
785 drm_mode_vrefresh(m) == vrefresh_rate)
786 return NULL;
787
a0910c8e
AJ		 788 /* HDTV hack, part 2 */
789 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
790 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
d50ba256 791 false);
559ee21d
ZY		 792 mode->hdisplay = 1366;
793 mode->vsync_start = mode->vsync_start - 1;
794 mode->vsync_end = mode->vsync_end - 1;
795 return mode;
796 }
a0910c8e 797
559ee21d
ZY		 798 /* check whether it can be found in default mode table */
799 mode = drm_find_dmt(dev, hsize, vsize, vrefresh_rate);
800 if (mode)
801 return mode;
802
5c61259e
ZY		 803 switch (timing_level) {
804 case LEVEL_DMT:
5c61259e
ZY		 805 break;
806 case LEVEL_GTF:
807 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
808 break;
809 case LEVEL_CVT:
d50ba256
DA		 810 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
811 false);
5c61259e
ZY		 812 break;
813 }
f453ba04
DA		 814 return mode;
815}
816
b58db2c6
AJ		 817/*
818 * EDID is delightfully ambiguous about how interlaced modes are to be
819 * encoded. Our internal representation is of frame height, but some
820 * HDTV detailed timings are encoded as field height.
821 *
822 * The format list here is from CEA, in frame size. Technically we
823 * should be checking refresh rate too. Whatever.
824 */
825static void
826drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
827 struct detailed_pixel_timing *pt)
828{
829 int i;
830 static const struct {
831 int w, h;
832 } cea_interlaced[] = {
833 { 1920, 1080 },
834 { 720, 480 },
835 { 1440, 480 },
836 { 2880, 480 },
837 { 720, 576 },
838 { 1440, 576 },
839 { 2880, 576 },
840 };
841 static const int n_sizes =
842 sizeof(cea_interlaced)/sizeof(cea_interlaced[0]);
843
844 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
845 return;
846
847 for (i = 0; i < n_sizes; i++) {
848 if ((mode->hdisplay == cea_interlaced[i].w) &&
849 (mode->vdisplay == cea_interlaced[i].h / 2)) {
850 mode->vdisplay *= 2;
851 mode->vsync_start *= 2;
852 mode->vsync_end *= 2;
853 mode->vtotal *= 2;
854 mode->vtotal |= 1;
855 }
856 }
857
858 mode->flags |= DRM_MODE_FLAG_INTERLACE;
859}
860
f453ba04
DA		 861/**
862 * drm_mode_detailed - create a new mode from an EDID detailed timing section
863 * @dev: DRM device (needed to create new mode)
864 * @edid: EDID block
865 * @timing: EDID detailed timing info
866 * @quirks: quirks to apply
867 *
868 * An EDID detailed timing block contains enough info for us to create and
869 * return a new struct drm_display_mode.
870 */
871static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
872 struct edid *edid,
873 struct detailed_timing *timing,
874 u32 quirks)
875{
876 struct drm_display_mode *mode;
877 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
0454beab
MD		 878 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
879 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
880 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
881 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
e14cbee4
MD		 882 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
883 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
884 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) >> 2 | pt->vsync_offset_pulse_width_lo >> 4;
885 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
f453ba04 886
fc438966 887 /* ignore tiny modes */
0454beab 888 if (hactive < 64 || vactive < 64)
fc438966
AJ		 889 return NULL;
890
0454beab 891 if (pt->misc & DRM_EDID_PT_STEREO) {
f453ba04
DA		 892 printk(KERN_WARNING "stereo mode not supported\n");
893 return NULL;
894 }
0454beab 895 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
79b7dcb2 896 printk(KERN_WARNING "composite sync not supported\n");
f453ba04
DA		 897 }
898
fcb45611
ZY		 899 /* it is incorrect if hsync/vsync width is zero */
900 if (!hsync_pulse_width || !vsync_pulse_width) {
901 DRM_DEBUG_KMS("Incorrect Detailed timing. "
902 "Wrong Hsync/Vsync pulse width\n");
903 return NULL;
904 }
f453ba04
DA		 905 mode = drm_mode_create(dev);
906 if (!mode)
907 return NULL;
908
909 mode->type = DRM_MODE_TYPE_DRIVER;
910
911 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
0454beab
MD		 912 timing->pixel_clock = cpu_to_le16(1088);
913
914 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
915
916 mode->hdisplay = hactive;
917 mode->hsync_start = mode->hdisplay + hsync_offset;
918 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
919 mode->htotal = mode->hdisplay + hblank;
920
921 mode->vdisplay = vactive;
922 mode->vsync_start = mode->vdisplay + vsync_offset;
923 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
924 mode->vtotal = mode->vdisplay + vblank;
f453ba04 925
7064fef5
JB		 926 /* Some EDIDs have bogus h/vtotal values */
927 if (mode->hsync_end > mode->htotal)
928 mode->htotal = mode->hsync_end + 1;
929 if (mode->vsync_end > mode->vtotal)
930 mode->vtotal = mode->vsync_end + 1;
931
f453ba04
DA		 932 drm_mode_set_name(mode);
933
b58db2c6 934 drm_mode_do_interlace_quirk(mode, pt);
f453ba04
DA		 935
936 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
0454beab 937 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
f453ba04
DA		 938 }
939
0454beab
MD		 940 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
941 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
942 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
943 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
f453ba04 944
e14cbee4
MD		 945 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
946 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
f453ba04
DA		 947
948 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
949 mode->width_mm *= 10;
950 mode->height_mm *= 10;
951 }
952
953 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
954 mode->width_mm = edid->width_cm * 10;
955 mode->height_mm = edid->height_cm * 10;
956 }
957
958 return mode;
959}
960
961/*
962 * Detailed mode info for the EDID "established modes" data to use.
963 */
964static struct drm_display_mode edid_est_modes[] = {
965 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
966 968, 1056, 0, 600, 601, 605, 628, 0,
967 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
968 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
969 896, 1024, 0, 600, 601, 603, 625, 0,
970 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
971 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
972 720, 840, 0, 480, 481, 484, 500, 0,
973 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
974 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
975 704, 832, 0, 480, 489, 491, 520, 0,
976 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
977 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
978 768, 864, 0, 480, 483, 486, 525, 0,
979 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
980 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656,
981 752, 800, 0, 480, 490, 492, 525, 0,
982 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
983 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
984 846, 900, 0, 400, 421, 423, 449, 0,
985 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
986 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
987 846, 900, 0, 400, 412, 414, 449, 0,
988 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
989 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
990 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
991 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
992 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040,
993 1136, 1312, 0, 768, 769, 772, 800, 0,
994 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
995 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
996 1184, 1328, 0, 768, 771, 777, 806, 0,
997 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
998 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
999 1184, 1344, 0, 768, 771, 777, 806, 0,
1000 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
1001 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
1002 1208, 1264, 0, 768, 768, 776, 817, 0,
1003 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
1004 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
1005 928, 1152, 0, 624, 625, 628, 667, 0,
1006 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
1007 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
1008 896, 1056, 0, 600, 601, 604, 625, 0,
1009 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
1010 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
1011 976, 1040, 0, 600, 637, 643, 666, 0,
1012 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
1013 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
1014 1344, 1600, 0, 864, 865, 868, 900, 0,
1015 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
1016};
1017
f453ba04
DA		 1018/**
1019 * add_established_modes - get est. modes from EDID and add them
1020 * @edid: EDID block to scan
1021 *
1022 * Each EDID block contains a bitmap of the supported "established modes" list
1023 * (defined above). Tease them out and add them to the global modes list.
1024 */
1025static int add_established_modes(struct drm_connector *connector, struct edid *edid)
1026{
1027 struct drm_device *dev = connector->dev;
1028 unsigned long est_bits = edid->established_timings.t1 |
1029 (edid->established_timings.t2 << 8) |
1030 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
1031 int i, modes = 0;
1032
1033 for (i = 0; i <= EDID_EST_TIMINGS; i++)
1034 if (est_bits & (1<<i)) {
1035 struct drm_display_mode *newmode;
1036 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
1037 if (newmode) {
1038 drm_mode_probed_add(connector, newmode);
1039 modes++;
1040 }
1041 }
1042
1043 return modes;
1044}
5c61259e
ZY		 1045/**
1046 * stanard_timing_level - get std. timing level(CVT/GTF/DMT)
1047 * @edid: EDID block to scan
1048 */
1049static int standard_timing_level(struct edid *edid)
1050{
1051 if (edid->revision >= 2) {
1052 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
1053 return LEVEL_CVT;
1054 return LEVEL_GTF;
1055 }
1056 return LEVEL_DMT;
1057}
f453ba04
DA		 1058
1059/**
1060 * add_standard_modes - get std. modes from EDID and add them
1061 * @edid: EDID block to scan
1062 *
1063 * Standard modes can be calculated using the CVT standard. Grab them from
1064 * @edid, calculate them, and add them to the list.
1065 */
1066static int add_standard_modes(struct drm_connector *connector, struct edid *edid)
1067{
f453ba04 1068 int i, modes = 0;
5c61259e
ZY		 1069 int timing_level;
1070
1071 timing_level = standard_timing_level(edid);
f453ba04
DA		 1072
1073 for (i = 0; i < EDID_STD_TIMINGS; i++) {
f453ba04
DA		 1074 struct drm_display_mode *newmode;
1075
7ca6adb3 1076 newmode = drm_mode_std(connector, &edid->standard_timings[i],
f066a17d 1077 edid->revision, timing_level);
f453ba04
DA		 1078 if (newmode) {
1079 drm_mode_probed_add(connector, newmode);
1080 modes++;
1081 }
1082 }
1083
1084 return modes;
1085}
1086
07a5e632 1087static bool
b17e52ef 1088mode_is_rb(struct drm_display_mode *mode)
07a5e632 1089{
b17e52ef
AJ		 1090 return (mode->htotal - mode->hdisplay == 160) &&
1091 (mode->hsync_end - mode->hdisplay == 80) &&
1092 (mode->hsync_end - mode->hsync_start == 32) &&
1093 (mode->vsync_start - mode->vdisplay == 3);
1094}
07a5e632 1095
b17e52ef
AJ		 1096static bool
1097mode_in_hsync_range(struct drm_display_mode *mode, struct edid *edid, u8 *t)
1098{
1099 int hsync, hmin, hmax;
1100
1101 hmin = t[7];
1102 if (edid->revision >= 4)
1103 hmin += ((t[4] & 0x04) ? 255 : 0);
1104 hmax = t[8];
1105 if (edid->revision >= 4)
1106 hmax += ((t[4] & 0x08) ? 255 : 0);
07a5e632 1107 hsync = drm_mode_hsync(mode);
07a5e632 1108
b17e52ef
AJ		 1109 return (hsync <= hmax && hsync >= hmin);
1110}
1111
1112static bool
1113mode_in_vsync_range(struct drm_display_mode *mode, struct edid *edid, u8 *t)
1114{
1115 int vsync, vmin, vmax;
1116
1117 vmin = t[5];
1118 if (edid->revision >= 4)
1119 vmin += ((t[4] & 0x01) ? 255 : 0);
1120 vmax = t[6];
1121 if (edid->revision >= 4)
1122 vmax += ((t[4] & 0x02) ? 255 : 0);
1123 vsync = drm_mode_vrefresh(mode);
1124
1125 return (vsync <= vmax && vsync >= vmin);
1126}
1127
1128static u32
1129range_pixel_clock(struct edid *edid, u8 *t)
1130{
1131 /* unspecified */
1132 if (t[9] == 0 || t[9] == 255)
1133 return 0;
1134
1135 /* 1.4 with CVT support gives us real precision, yay */
1136 if (edid->revision >= 4 && t[10] == 0x04)
1137 return (t[9] * 10000) - ((t[12] >> 2) * 250);
1138
1139 /* 1.3 is pathetic, so fuzz up a bit */
1140 return t[9] * 10000 + 5001;
1141}
1142
1143/*
1144 * XXX fix this for GTF secondary curve formula
1145 */
1146static bool
1147mode_in_range(struct drm_display_mode *mode, struct edid *edid,
1148 struct detailed_timing *timing)
1149{
1150 u32 max_clock;
1151 u8 *t = (u8 *)timing;
1152
1153 if (!mode_in_hsync_range(mode, edid, t))
07a5e632
AJ		 1154 return false;
1155
b17e52ef 1156 if (!mode_in_vsync_range(mode, edid, t))
07a5e632
AJ		 1157 return false;
1158
b17e52ef 1159 if ((max_clock = range_pixel_clock(edid, t)))
07a5e632
AJ		 1160 if (mode->clock > max_clock)
1161 return false;
b17e52ef
AJ		 1162
1163 /* 1.4 max horizontal check */
1164 if (edid->revision >= 4 && t[10] == 0x04)
1165 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
1166 return false;
1167
1168 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
1169 return false;
07a5e632
AJ		 1170
1171 return true;
1172}
1173
1174/*
1175 * XXX If drm_dmt_modes ever regrows the CVT-R modes (and it will) this will
1176 * need to account for them.
1177 */
b17e52ef
AJ		 1178static int
1179drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
1180 struct detailed_timing *timing)
07a5e632
AJ		 1181{
1182 int i, modes = 0;
1183 struct drm_display_mode *newmode;
1184 struct drm_device *dev = connector->dev;
1185
1186 for (i = 0; i < drm_num_dmt_modes; i++) {
b17e52ef 1187 if (mode_in_range(drm_dmt_modes + i, edid, timing)) {
07a5e632
AJ		 1188 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
1189 if (newmode) {
1190 drm_mode_probed_add(connector, newmode);
1191 modes++;
1192 }
1193 }
1194 }
1195
1196 return modes;
1197}
1198
9340d8cf
AJ		 1199static int drm_cvt_modes(struct drm_connector *connector,
1200 struct detailed_timing *timing)
1201{
1202 int i, j, modes = 0;
1203 struct drm_display_mode *newmode;
1204 struct drm_device *dev = connector->dev;
1205 struct cvt_timing *cvt;
1206 const int rates[] = { 60, 85, 75, 60, 50 };
69da3015 1207 const u8 empty[3] = { 0, 0, 0 };
9340d8cf
AJ		 1208
1209 for (i = 0; i < 4; i++) {
29ebdf92 1210 int uninitialized_var(width), height;
9340d8cf
AJ		 1211 cvt = &(timing->data.other_data.data.cvt[i]);
1212
69da3015
AJ		 1213 if (!memcmp(cvt->code, empty, 3))
1214 continue;
1215
8e10ee9a
AJ		 1216 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
1217 switch (cvt->code[1] & 0x0c) {
9340d8cf
AJ		 1218 case 0x00:
1219 width = height * 4 / 3;
1220 break;
8e10ee9a 1221 case 0x04:
9340d8cf
AJ		 1222 width = height * 16 / 9;
1223 break;
8e10ee9a 1224 case 0x08:
9340d8cf
AJ		 1225 width = height * 16 / 10;
1226 break;
8e10ee9a 1227 case 0x0c:
9340d8cf
AJ		 1228 width = height * 15 / 9;
1229 break;
1230 }
1231
1232 for (j = 1; j < 5; j++) {
1233 if (cvt->code[2] & (1 << j)) {
1234 newmode = drm_cvt_mode(dev, width, height,
1235 rates[j], j == 0,
1236 false, false);
1237 if (newmode) {
1238 drm_mode_probed_add(connector, newmode);
1239 modes++;
1240 }
1241 }
1242 }
1243 }
1244
1245 return modes;
1246}
1247
2255be14
AJ		 1248static const struct {
1249 short w;
1250 short h;
1251 short r;
1252 short rb;
1253} est3_modes[] = {
1254 /* byte 6 */
1255 { 640, 350, 85, 0 },
1256 { 640, 400, 85, 0 },
1257 { 720, 400, 85, 0 },
1258 { 640, 480, 85, 0 },
1259 { 848, 480, 60, 0 },
1260 { 800, 600, 85, 0 },
1261 { 1024, 768, 85, 0 },
1262 { 1152, 864, 75, 0 },
1263 /* byte 7 */
1264 { 1280, 768, 60, 1 },
1265 { 1280, 768, 60, 0 },
1266 { 1280, 768, 75, 0 },
1267 { 1280, 768, 85, 0 },
1268 { 1280, 960, 60, 0 },
1269 { 1280, 960, 85, 0 },
1270 { 1280, 1024, 60, 0 },
1271 { 1280, 1024, 85, 0 },
1272 /* byte 8 */
1273 { 1360, 768, 60, 0 },
1274 { 1440, 900, 60, 1 },
1275 { 1440, 900, 60, 0 },
1276 { 1440, 900, 75, 0 },
1277 { 1440, 900, 85, 0 },
1278 { 1400, 1050, 60, 1 },
1279 { 1400, 1050, 60, 0 },
1280 { 1400, 1050, 75, 0 },
1281 /* byte 9 */
1282 { 1400, 1050, 85, 0 },
1283 { 1680, 1050, 60, 1 },
1284 { 1680, 1050, 60, 0 },
1285 { 1680, 1050, 75, 0 },
1286 { 1680, 1050, 85, 0 },
1287 { 1600, 1200, 60, 0 },
1288 { 1600, 1200, 65, 0 },
1289 { 1600, 1200, 70, 0 },
1290 /* byte 10 */
1291 { 1600, 1200, 75, 0 },
1292 { 1600, 1200, 85, 0 },
1293 { 1792, 1344, 60, 0 },
1294 { 1792, 1344, 85, 0 },
1295 { 1856, 1392, 60, 0 },
1296 { 1856, 1392, 75, 0 },
1297 { 1920, 1200, 60, 1 },
1298 { 1920, 1200, 60, 0 },
1299 /* byte 11 */
1300 { 1920, 1200, 75, 0 },
1301 { 1920, 1200, 85, 0 },
1302 { 1920, 1440, 60, 0 },
1303 { 1920, 1440, 75, 0 },
1304};
1305static const int num_est3_modes = sizeof(est3_modes) / sizeof(est3_modes[0]);
1306
1307static int
1308drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
1309{
1310 int i, j, m, modes = 0;
1311 struct drm_display_mode *mode;
1312 u8 *est = ((u8 *)timing) + 5;
1313
1314 for (i = 0; i < 6; i++) {
1315 for (j = 7; j > 0; j--) {
1316 m = (i * 8) + (7 - j);
1317 if (m > num_est3_modes)
1318 break;
1319 if (est[i] & (1 << j)) {
1320 mode = drm_find_dmt(connector->dev,
1321 est3_modes[m].w,
1322 est3_modes[m].h,
1323 est3_modes[m].r
1324 /*, est3_modes[m].rb */);
1325 if (mode) {
1326 drm_mode_probed_add(connector, mode);
1327 modes++;
1328 }
1329 }
1330 }
1331 }
1332
1333 return modes;
1334}
1335
9cf00977
AJ		 1336static int add_detailed_modes(struct drm_connector *connector,
1337 struct detailed_timing *timing,
1338 struct edid *edid, u32 quirks, int preferred)
1339{
1340 int i, modes = 0;
1341 struct detailed_non_pixel *data = &timing->data.other_data;
1342 int timing_level = standard_timing_level(edid);
07a5e632 1343 int gtf = (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF);
9cf00977
AJ		 1344 struct drm_display_mode *newmode;
1345 struct drm_device *dev = connector->dev;
1346
1347 if (timing->pixel_clock) {
1348 newmode = drm_mode_detailed(dev, edid, timing, quirks);
1349 if (!newmode)
1350 return 0;
1351
1352 if (preferred)
1353 newmode->type |= DRM_MODE_TYPE_PREFERRED;
1354
1355 drm_mode_probed_add(connector, newmode);
1356 return 1;
1357 }
1358
1359 /* other timing types */
1360 switch (data->type) {
1361 case EDID_DETAIL_MONITOR_RANGE:
07a5e632 1362 if (gtf)
b17e52ef
AJ		 1363 modes += drm_gtf_modes_for_range(connector, edid,
1364 timing);
9cf00977
AJ		 1365 break;
1366 case EDID_DETAIL_STD_MODES:
1367 /* Six modes per detailed section */
1368 for (i = 0; i < 6; i++) {
1369 struct std_timing *std;
1370 struct drm_display_mode *newmode;
1371
1372 std = &data->data.timings[i];
7ca6adb3 1373 newmode = drm_mode_std(connector, std, edid->revision,
9cf00977
AJ		 1374 timing_level);
1375 if (newmode) {
1376 drm_mode_probed_add(connector, newmode);
1377 modes++;
1378 }
1379 }
1380 break;
9340d8cf
AJ		 1381 case EDID_DETAIL_CVT_3BYTE:
1382 modes += drm_cvt_modes(connector, timing);
1383 break;
2255be14
AJ		 1384 case EDID_DETAIL_EST_TIMINGS:
1385 modes += drm_est3_modes(connector, timing);
1386 break;
9cf00977
AJ		 1387 default:
1388 break;
1389 }
1390
1391 return modes;
1392}
1393
f453ba04 1394/**
9cf00977 1395 * add_detailed_info - get detailed mode info from EDID data
f453ba04
DA		 1396 * @connector: attached connector
1397 * @edid: EDID block to scan
1398 * @quirks: quirks to apply
1399 *
1400 * Some of the detailed timing sections may contain mode information. Grab
1401 * it and add it to the list.
1402 */
1403static int add_detailed_info(struct drm_connector *connector,
1404 struct edid *edid, u32 quirks)
1405{
9cf00977 1406 int i, modes = 0;
f453ba04
DA		 1407
1408 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) {
1409 struct detailed_timing *timing = &edid->detailed_timings[i];
a327f6b8
AJ		 1410 int preferred = (i == 0);
1411
1412 if (preferred && edid->version == 1 && edid->revision < 4)
1413 preferred = (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
f453ba04 1414
9cf00977
AJ		 1415 /* In 1.0, only timings are allowed */
1416 if (!timing->pixel_clock && edid->version == 1 &&
1417 edid->revision == 0)
1418 continue;
f453ba04 1419
9cf00977
AJ		 1420 modes += add_detailed_modes(connector, timing, edid, quirks,
1421 preferred);
f453ba04
DA		 1422 }
1423
1424 return modes;
1425}
9cf00977 1426
882f0219
ZY		 1427/**
1428 * add_detailed_mode_eedid - get detailed mode info from addtional timing
1429 * EDID block
1430 * @connector: attached connector
1431 * @edid: EDID block to scan(It is only to get addtional timing EDID block)
1432 * @quirks: quirks to apply
1433 *
1434 * Some of the detailed timing sections may contain mode information. Grab
1435 * it and add it to the list.
1436 */
1437static int add_detailed_info_eedid(struct drm_connector *connector,
1438 struct edid *edid, u32 quirks)
1439{
9cf00977 1440 int i, modes = 0;
882f0219
ZY		 1441 char *edid_ext = NULL;
1442 struct detailed_timing *timing;
882f0219
ZY		 1443 int start_offset, end_offset;
1444 int timing_level;
1445
59d8aff6 1446 if (edid->version == 1 && edid->revision < 3)
882f0219 1447 return 0;
59d8aff6 1448 if (!edid->extensions)
882f0219 1449 return 0;
882f0219 1450
882f0219 1451 /* Find CEA extension */
7466f4cc 1452 for (i = 0; i < edid->extensions; i++) {
882f0219 1453 edid_ext = (char *)edid + EDID_LENGTH * (i + 1);
882f0219
ZY		 1454 if (edid_ext[0] == 0x02)
1455 break;
1456 }
1457
59d8aff6 1458 if (i == edid->extensions)
882f0219 1459 return 0;
882f0219
ZY		 1460
1461 /* Get the start offset of detailed timing block */
1462 start_offset = edid_ext[2];
1463 if (start_offset == 0) {
1464 /* If the start_offset is zero, it means that neither detailed
1465 * info nor data block exist. In such case it is also
1466 * unnecessary to parse the detailed timing info.
1467 */
1468 return 0;
1469 }
1470
1471 timing_level = standard_timing_level(edid);
1472 end_offset = EDID_LENGTH;
1473 end_offset -= sizeof(struct detailed_timing);
1474 for (i = start_offset; i < end_offset;
1475 i += sizeof(struct detailed_timing)) {
1476 timing = (struct detailed_timing *)(edid_ext + i);
9cf00977 1477 modes += add_detailed_modes(connector, timing, edid, quirks, 0);
882f0219
ZY		 1478 }
1479
1480 return modes;
1481}
f453ba04 1482
f23c20c8
ML		 1483#define HDMI_IDENTIFIER 0x000C03
1484#define VENDOR_BLOCK 0x03
1485/**
1486 * drm_detect_hdmi_monitor - detect whether monitor is hdmi.
1487 * @edid: monitor EDID information
1488 *
1489 * Parse the CEA extension according to CEA-861-B.
1490 * Return true if HDMI, false if not or unknown.
1491 */
1492bool drm_detect_hdmi_monitor(struct edid *edid)
1493{
1494 char *edid_ext = NULL;
7466f4cc 1495 int i, hdmi_id;
f23c20c8
ML		 1496 int start_offset, end_offset;
1497 bool is_hdmi = false;
1498
1499 /* No EDID or EDID extensions */
1500 if (edid == NULL || edid->extensions == 0)
1501 goto end;
1502
f23c20c8 1503 /* Find CEA extension */
7466f4cc 1504 for (i = 0; i < edid->extensions; i++) {
f23c20c8
ML		 1505 edid_ext = (char *)edid + EDID_LENGTH * (i + 1);
1506 /* This block is CEA extension */
1507 if (edid_ext[0] == 0x02)
1508 break;
1509 }
1510
7466f4cc 1511 if (i == edid->extensions)
f23c20c8
ML		 1512 goto end;
1513
1514 /* Data block offset in CEA extension block */
1515 start_offset = 4;
1516 end_offset = edid_ext[2];
1517
1518 /*
1519 * Because HDMI identifier is in Vendor Specific Block,
1520 * search it from all data blocks of CEA extension.
1521 */
1522 for (i = start_offset; i < end_offset;
1523 /* Increased by data block len */
1524 i += ((edid_ext[i] & 0x1f) + 1)) {
1525 /* Find vendor specific block */
1526 if ((edid_ext[i] >> 5) == VENDOR_BLOCK) {
1527 hdmi_id = edid_ext[i + 1] | (edid_ext[i + 2] << 8) |
1528 edid_ext[i + 3] << 16;
1529 /* Find HDMI identifier */
1530 if (hdmi_id == HDMI_IDENTIFIER)
1531 is_hdmi = true;
1532 break;
1533 }
1534 }
1535
1536end:
1537 return is_hdmi;
1538}
1539EXPORT_SYMBOL(drm_detect_hdmi_monitor);
1540
f453ba04
DA		 1541/**
1542 * drm_add_edid_modes - add modes from EDID data, if available
1543 * @connector: connector we're probing
1544 * @edid: edid data
1545 *
1546 * Add the specified modes to the connector's mode list.
1547 *
1548 * Return number of modes added or 0 if we couldn't find any.
1549 */
1550int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
1551{
1552 int num_modes = 0;
1553 u32 quirks;
1554
1555 if (edid == NULL) {
1556 return 0;
1557 }
3c537889 1558 if (!drm_edid_is_valid(edid)) {
f453ba04
DA		 1559 dev_warn(&connector->dev->pdev->dev, "%s: EDID invalid.\n",
1560 drm_get_connector_name(connector));
1561 return 0;
1562 }
1563
1564 quirks = edid_get_quirks(edid);
1565
c867df70
AJ		 1566 /*
1567 * EDID spec says modes should be preferred in this order:
1568 * - preferred detailed mode
1569 * - other detailed modes from base block
1570 * - detailed modes from extension blocks
1571 * - CVT 3-byte code modes
1572 * - standard timing codes
1573 * - established timing codes
1574 * - modes inferred from GTF or CVT range information
1575 *
1576 * We don't quite implement this yet, but we're close.
1577 *
1578 * XXX order for additional mode types in extension blocks?
1579 */
f453ba04 1580 num_modes += add_detailed_info(connector, edid, quirks);
882f0219 1581 num_modes += add_detailed_info_eedid(connector, edid, quirks);
c867df70
AJ		 1582 num_modes += add_standard_modes(connector, edid);
1583 num_modes += add_established_modes(connector, edid);
f453ba04
DA		 1584
1585 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
1586 edid_fixup_preferred(connector, quirks);
1587
0454beab
MD		 1588 connector->display_info.serration_vsync = (edid->input & DRM_EDID_INPUT_SERRATION_VSYNC) ? 1 : 0;
1589 connector->display_info.sync_on_green = (edid->input & DRM_EDID_INPUT_SYNC_ON_GREEN) ? 1 : 0;
1590 connector->display_info.composite_sync = (edid->input & DRM_EDID_INPUT_COMPOSITE_SYNC) ? 1 : 0;
1591 connector->display_info.separate_syncs = (edid->input & DRM_EDID_INPUT_SEPARATE_SYNCS) ? 1 : 0;
1592 connector->display_info.blank_to_black = (edid->input & DRM_EDID_INPUT_BLANK_TO_BLACK) ? 1 : 0;
1593 connector->display_info.video_level = (edid->input & DRM_EDID_INPUT_VIDEO_LEVEL) >> 5;
1594 connector->display_info.digital = (edid->input & DRM_EDID_INPUT_DIGITAL) ? 1 : 0;
f453ba04
DA		 1595 connector->display_info.width_mm = edid->width_cm * 10;
1596 connector->display_info.height_mm = edid->height_cm * 10;
1597 connector->display_info.gamma = edid->gamma;
0454beab
MD		 1598 connector->display_info.gtf_supported = (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) ? 1 : 0;
1599 connector->display_info.standard_color = (edid->features & DRM_EDID_FEATURE_STANDARD_COLOR) ? 1 : 0;
1600 connector->display_info.display_type = (edid->features & DRM_EDID_FEATURE_DISPLAY_TYPE) >> 3;
1601 connector->display_info.active_off_supported = (edid->features & DRM_EDID_FEATURE_PM_ACTIVE_OFF) ? 1 : 0;
1602 connector->display_info.suspend_supported = (edid->features & DRM_EDID_FEATURE_PM_SUSPEND) ? 1 : 0;
1603 connector->display_info.standby_supported = (edid->features & DRM_EDID_FEATURE_PM_STANDBY) ? 1 : 0;
f453ba04
DA		 1604 connector->display_info.gamma = edid->gamma;
1605
1606 return num_modes;
1607}
1608EXPORT_SYMBOL(drm_add_edid_modes);
f0fda0a4
ZY		 1609
1610/**
1611 * drm_add_modes_noedid - add modes for the connectors without EDID
1612 * @connector: connector we're probing
1613 * @hdisplay: the horizontal display limit
1614 * @vdisplay: the vertical display limit
1615 *
1616 * Add the specified modes to the connector's mode list. Only when the
1617 * hdisplay/vdisplay is not beyond the given limit, it will be added.
1618 *
1619 * Return number of modes added or 0 if we couldn't find any.
1620 */
1621int drm_add_modes_noedid(struct drm_connector *connector,
1622 int hdisplay, int vdisplay)
1623{
1624 int i, count, num_modes = 0;
1625 struct drm_display_mode *mode, *ptr;
1626 struct drm_device *dev = connector->dev;
1627
1628 count = sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode);
1629 if (hdisplay < 0)
1630 hdisplay = 0;
1631 if (vdisplay < 0)
1632 vdisplay = 0;
1633
1634 for (i = 0; i < count; i++) {
1635 ptr = &drm_dmt_modes[i];
1636 if (hdisplay && vdisplay) {
1637 /*
1638 * Only when two are valid, they will be used to check
1639 * whether the mode should be added to the mode list of
1640 * the connector.
1641 */
1642 if (ptr->hdisplay > hdisplay ||
1643 ptr->vdisplay > vdisplay)
1644 continue;
1645 }
f985dedb
AJ		 1646 if (drm_mode_vrefresh(ptr) > 61)
1647 continue;
f0fda0a4
ZY		 1648 mode = drm_mode_duplicate(dev, ptr);
1649 if (mode) {
1650 drm_mode_probed_add(connector, mode);
1651 num_modes++;
1652 }
1653 }
1654 return num_modes;
1655}
1656EXPORT_SYMBOL(drm_add_modes_noedid);
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