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f453ba04 DA |
1 | /* |
2 | * Copyright (c) 2006 Luc Verhaegen (quirks list) | |
3 | * Copyright (c) 2007-2008 Intel Corporation | |
4 | * Jesse Barnes <jesse.barnes@intel.com> | |
61e57a8d | 5 | * Copyright 2010 Red Hat, Inc. |
f453ba04 DA |
6 | * |
7 | * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from | |
8 | * FB layer. | |
9 | * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> | |
10 | * | |
11 | * Permission is hereby granted, free of charge, to any person obtaining a | |
12 | * copy of this software and associated documentation files (the "Software"), | |
13 | * to deal in the Software without restriction, including without limitation | |
14 | * the rights to use, copy, modify, merge, publish, distribute, sub license, | |
15 | * and/or sell copies of the Software, and to permit persons to whom the | |
16 | * Software is furnished to do so, subject to the following conditions: | |
17 | * | |
18 | * The above copyright notice and this permission notice (including the | |
19 | * next paragraph) shall be included in all copies or substantial portions | |
20 | * of the Software. | |
21 | * | |
22 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
23 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
24 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
25 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
26 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
27 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
28 | * DEALINGS IN THE SOFTWARE. | |
29 | */ | |
30 | #include <linux/kernel.h> | |
5a0e3ad6 | 31 | #include <linux/slab.h> |
10a85120 | 32 | #include <linux/hdmi.h> |
f453ba04 | 33 | #include <linux/i2c.h> |
47819ba2 | 34 | #include <linux/module.h> |
760285e7 DH |
35 | #include <drm/drmP.h> |
36 | #include <drm/drm_edid.h> | |
f453ba04 | 37 | |
13931579 AJ |
38 | #define version_greater(edid, maj, min) \ |
39 | (((edid)->version > (maj)) || \ | |
40 | ((edid)->version == (maj) && (edid)->revision > (min))) | |
f453ba04 | 41 | |
d1ff6409 AJ |
42 | #define EDID_EST_TIMINGS 16 |
43 | #define EDID_STD_TIMINGS 8 | |
44 | #define EDID_DETAILED_TIMINGS 4 | |
f453ba04 DA |
45 | |
46 | /* | |
47 | * EDID blocks out in the wild have a variety of bugs, try to collect | |
48 | * them here (note that userspace may work around broken monitors first, | |
49 | * but fixes should make their way here so that the kernel "just works" | |
50 | * on as many displays as possible). | |
51 | */ | |
52 | ||
53 | /* First detailed mode wrong, use largest 60Hz mode */ | |
54 | #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) | |
55 | /* Reported 135MHz pixel clock is too high, needs adjustment */ | |
56 | #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) | |
57 | /* Prefer the largest mode at 75 Hz */ | |
58 | #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) | |
59 | /* Detail timing is in cm not mm */ | |
60 | #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) | |
61 | /* Detailed timing descriptors have bogus size values, so just take the | |
62 | * maximum size and use that. | |
63 | */ | |
64 | #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) | |
65 | /* Monitor forgot to set the first detailed is preferred bit. */ | |
66 | #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5) | |
67 | /* use +hsync +vsync for detailed mode */ | |
68 | #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) | |
bc42aabc AJ |
69 | /* Force reduced-blanking timings for detailed modes */ |
70 | #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) | |
49d45a31 RM |
71 | /* Force 8bpc */ |
72 | #define EDID_QUIRK_FORCE_8BPC (1 << 8) | |
3c537889 | 73 | |
13931579 AJ |
74 | struct detailed_mode_closure { |
75 | struct drm_connector *connector; | |
76 | struct edid *edid; | |
77 | bool preferred; | |
78 | u32 quirks; | |
79 | int modes; | |
80 | }; | |
f453ba04 | 81 | |
5c61259e ZY |
82 | #define LEVEL_DMT 0 |
83 | #define LEVEL_GTF 1 | |
7a374350 AJ |
84 | #define LEVEL_GTF2 2 |
85 | #define LEVEL_CVT 3 | |
5c61259e | 86 | |
f453ba04 | 87 | static struct edid_quirk { |
c51a3fd6 | 88 | char vendor[4]; |
f453ba04 DA |
89 | int product_id; |
90 | u32 quirks; | |
91 | } edid_quirk_list[] = { | |
92 | /* Acer AL1706 */ | |
93 | { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, | |
94 | /* Acer F51 */ | |
95 | { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, | |
96 | /* Unknown Acer */ | |
97 | { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, | |
98 | ||
99 | /* Belinea 10 15 55 */ | |
100 | { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, | |
101 | { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, | |
102 | ||
103 | /* Envision Peripherals, Inc. EN-7100e */ | |
104 | { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, | |
ba1163de AJ |
105 | /* Envision EN2028 */ |
106 | { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, | |
f453ba04 DA |
107 | |
108 | /* Funai Electronics PM36B */ | |
109 | { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | | |
110 | EDID_QUIRK_DETAILED_IN_CM }, | |
111 | ||
112 | /* LG Philips LCD LP154W01-A5 */ | |
113 | { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, | |
114 | { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, | |
115 | ||
116 | /* Philips 107p5 CRT */ | |
117 | { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, | |
118 | ||
119 | /* Proview AY765C */ | |
120 | { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, | |
121 | ||
122 | /* Samsung SyncMaster 205BW. Note: irony */ | |
123 | { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, | |
124 | /* Samsung SyncMaster 22[5-6]BW */ | |
125 | { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, | |
126 | { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, | |
bc42aabc AJ |
127 | |
128 | /* ViewSonic VA2026w */ | |
129 | { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, | |
118bdbd8 AD |
130 | |
131 | /* Medion MD 30217 PG */ | |
132 | { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, | |
49d45a31 RM |
133 | |
134 | /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ | |
135 | { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, | |
f453ba04 DA |
136 | }; |
137 | ||
a6b21831 TR |
138 | /* |
139 | * Autogenerated from the DMT spec. | |
140 | * This table is copied from xfree86/modes/xf86EdidModes.c. | |
141 | */ | |
142 | static const struct drm_display_mode drm_dmt_modes[] = { | |
143 | /* 640x350@85Hz */ | |
144 | { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, | |
145 | 736, 832, 0, 350, 382, 385, 445, 0, | |
146 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
147 | /* 640x400@85Hz */ | |
148 | { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, | |
149 | 736, 832, 0, 400, 401, 404, 445, 0, | |
150 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
151 | /* 720x400@85Hz */ | |
152 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, | |
153 | 828, 936, 0, 400, 401, 404, 446, 0, | |
154 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
155 | /* 640x480@60Hz */ | |
156 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, | |
157 | 752, 800, 0, 480, 489, 492, 525, 0, | |
158 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
159 | /* 640x480@72Hz */ | |
160 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, | |
161 | 704, 832, 0, 480, 489, 492, 520, 0, | |
162 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
163 | /* 640x480@75Hz */ | |
164 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, | |
165 | 720, 840, 0, 480, 481, 484, 500, 0, | |
166 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
167 | /* 640x480@85Hz */ | |
168 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, | |
169 | 752, 832, 0, 480, 481, 484, 509, 0, | |
170 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
171 | /* 800x600@56Hz */ | |
172 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, | |
173 | 896, 1024, 0, 600, 601, 603, 625, 0, | |
174 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
175 | /* 800x600@60Hz */ | |
176 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, | |
177 | 968, 1056, 0, 600, 601, 605, 628, 0, | |
178 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
179 | /* 800x600@72Hz */ | |
180 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, | |
181 | 976, 1040, 0, 600, 637, 643, 666, 0, | |
182 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
183 | /* 800x600@75Hz */ | |
184 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, | |
185 | 896, 1056, 0, 600, 601, 604, 625, 0, | |
186 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
187 | /* 800x600@85Hz */ | |
188 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, | |
189 | 896, 1048, 0, 600, 601, 604, 631, 0, | |
190 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
191 | /* 800x600@120Hz RB */ | |
192 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, | |
193 | 880, 960, 0, 600, 603, 607, 636, 0, | |
194 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
195 | /* 848x480@60Hz */ | |
196 | { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, | |
197 | 976, 1088, 0, 480, 486, 494, 517, 0, | |
198 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
199 | /* 1024x768@43Hz, interlace */ | |
200 | { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, | |
201 | 1208, 1264, 0, 768, 768, 772, 817, 0, | |
202 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | | |
203 | DRM_MODE_FLAG_INTERLACE) }, | |
204 | /* 1024x768@60Hz */ | |
205 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, | |
206 | 1184, 1344, 0, 768, 771, 777, 806, 0, | |
207 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
208 | /* 1024x768@70Hz */ | |
209 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, | |
210 | 1184, 1328, 0, 768, 771, 777, 806, 0, | |
211 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
212 | /* 1024x768@75Hz */ | |
213 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, | |
214 | 1136, 1312, 0, 768, 769, 772, 800, 0, | |
215 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
216 | /* 1024x768@85Hz */ | |
217 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, | |
218 | 1168, 1376, 0, 768, 769, 772, 808, 0, | |
219 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
220 | /* 1024x768@120Hz RB */ | |
221 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, | |
222 | 1104, 1184, 0, 768, 771, 775, 813, 0, | |
223 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
224 | /* 1152x864@75Hz */ | |
225 | { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, | |
226 | 1344, 1600, 0, 864, 865, 868, 900, 0, | |
227 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
228 | /* 1280x768@60Hz RB */ | |
229 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, | |
230 | 1360, 1440, 0, 768, 771, 778, 790, 0, | |
231 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
232 | /* 1280x768@60Hz */ | |
233 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, | |
234 | 1472, 1664, 0, 768, 771, 778, 798, 0, | |
235 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
236 | /* 1280x768@75Hz */ | |
237 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, | |
238 | 1488, 1696, 0, 768, 771, 778, 805, 0, | |
239 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
240 | /* 1280x768@85Hz */ | |
241 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, | |
242 | 1496, 1712, 0, 768, 771, 778, 809, 0, | |
243 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
244 | /* 1280x768@120Hz RB */ | |
245 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, | |
246 | 1360, 1440, 0, 768, 771, 778, 813, 0, | |
247 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
248 | /* 1280x800@60Hz RB */ | |
249 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, | |
250 | 1360, 1440, 0, 800, 803, 809, 823, 0, | |
251 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
252 | /* 1280x800@60Hz */ | |
253 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, | |
254 | 1480, 1680, 0, 800, 803, 809, 831, 0, | |
255 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
256 | /* 1280x800@75Hz */ | |
257 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, | |
258 | 1488, 1696, 0, 800, 803, 809, 838, 0, | |
259 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
260 | /* 1280x800@85Hz */ | |
261 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, | |
262 | 1496, 1712, 0, 800, 803, 809, 843, 0, | |
263 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
264 | /* 1280x800@120Hz RB */ | |
265 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, | |
266 | 1360, 1440, 0, 800, 803, 809, 847, 0, | |
267 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
268 | /* 1280x960@60Hz */ | |
269 | { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, | |
270 | 1488, 1800, 0, 960, 961, 964, 1000, 0, | |
271 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
272 | /* 1280x960@85Hz */ | |
273 | { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, | |
274 | 1504, 1728, 0, 960, 961, 964, 1011, 0, | |
275 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
276 | /* 1280x960@120Hz RB */ | |
277 | { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, | |
278 | 1360, 1440, 0, 960, 963, 967, 1017, 0, | |
279 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
280 | /* 1280x1024@60Hz */ | |
281 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, | |
282 | 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, | |
283 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
284 | /* 1280x1024@75Hz */ | |
285 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, | |
286 | 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, | |
287 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
288 | /* 1280x1024@85Hz */ | |
289 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, | |
290 | 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, | |
291 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
292 | /* 1280x1024@120Hz RB */ | |
293 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, | |
294 | 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, | |
295 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
296 | /* 1360x768@60Hz */ | |
297 | { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, | |
298 | 1536, 1792, 0, 768, 771, 777, 795, 0, | |
299 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
300 | /* 1360x768@120Hz RB */ | |
301 | { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, | |
302 | 1440, 1520, 0, 768, 771, 776, 813, 0, | |
303 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
304 | /* 1400x1050@60Hz RB */ | |
305 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, | |
306 | 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, | |
307 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
308 | /* 1400x1050@60Hz */ | |
309 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, | |
310 | 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, | |
311 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
312 | /* 1400x1050@75Hz */ | |
313 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, | |
314 | 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, | |
315 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
316 | /* 1400x1050@85Hz */ | |
317 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, | |
318 | 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, | |
319 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
320 | /* 1400x1050@120Hz RB */ | |
321 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, | |
322 | 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, | |
323 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
324 | /* 1440x900@60Hz RB */ | |
325 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, | |
326 | 1520, 1600, 0, 900, 903, 909, 926, 0, | |
327 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
328 | /* 1440x900@60Hz */ | |
329 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, | |
330 | 1672, 1904, 0, 900, 903, 909, 934, 0, | |
331 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
332 | /* 1440x900@75Hz */ | |
333 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, | |
334 | 1688, 1936, 0, 900, 903, 909, 942, 0, | |
335 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
336 | /* 1440x900@85Hz */ | |
337 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, | |
338 | 1696, 1952, 0, 900, 903, 909, 948, 0, | |
339 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
340 | /* 1440x900@120Hz RB */ | |
341 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, | |
342 | 1520, 1600, 0, 900, 903, 909, 953, 0, | |
343 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
344 | /* 1600x1200@60Hz */ | |
345 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, | |
346 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, | |
347 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
348 | /* 1600x1200@65Hz */ | |
349 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, | |
350 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, | |
351 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
352 | /* 1600x1200@70Hz */ | |
353 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, | |
354 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, | |
355 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
356 | /* 1600x1200@75Hz */ | |
357 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, | |
358 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, | |
359 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
360 | /* 1600x1200@85Hz */ | |
361 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, | |
362 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, | |
363 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
364 | /* 1600x1200@120Hz RB */ | |
365 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, | |
366 | 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, | |
367 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
368 | /* 1680x1050@60Hz RB */ | |
369 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, | |
370 | 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, | |
371 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
372 | /* 1680x1050@60Hz */ | |
373 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, | |
374 | 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, | |
375 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
376 | /* 1680x1050@75Hz */ | |
377 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, | |
378 | 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, | |
379 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
380 | /* 1680x1050@85Hz */ | |
381 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, | |
382 | 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, | |
383 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
384 | /* 1680x1050@120Hz RB */ | |
385 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, | |
386 | 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, | |
387 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
388 | /* 1792x1344@60Hz */ | |
389 | { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, | |
390 | 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, | |
391 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
392 | /* 1792x1344@75Hz */ | |
393 | { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, | |
394 | 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, | |
395 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
396 | /* 1792x1344@120Hz RB */ | |
397 | { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, | |
398 | 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, | |
399 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
400 | /* 1856x1392@60Hz */ | |
401 | { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, | |
402 | 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, | |
403 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
404 | /* 1856x1392@75Hz */ | |
405 | { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, | |
406 | 2208, 2560, 0, 1392, 1395, 1399, 1500, 0, | |
407 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
408 | /* 1856x1392@120Hz RB */ | |
409 | { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, | |
410 | 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, | |
411 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
412 | /* 1920x1200@60Hz RB */ | |
413 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, | |
414 | 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, | |
415 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
416 | /* 1920x1200@60Hz */ | |
417 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, | |
418 | 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, | |
419 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
420 | /* 1920x1200@75Hz */ | |
421 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, | |
422 | 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, | |
423 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
424 | /* 1920x1200@85Hz */ | |
425 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, | |
426 | 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, | |
427 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
428 | /* 1920x1200@120Hz RB */ | |
429 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, | |
430 | 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, | |
431 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
432 | /* 1920x1440@60Hz */ | |
433 | { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, | |
434 | 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, | |
435 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
436 | /* 1920x1440@75Hz */ | |
437 | { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, | |
438 | 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, | |
439 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
440 | /* 1920x1440@120Hz RB */ | |
441 | { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, | |
442 | 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, | |
443 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
444 | /* 2560x1600@60Hz RB */ | |
445 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, | |
446 | 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, | |
447 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
448 | /* 2560x1600@60Hz */ | |
449 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, | |
450 | 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, | |
451 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
452 | /* 2560x1600@75HZ */ | |
453 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, | |
454 | 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, | |
455 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
456 | /* 2560x1600@85HZ */ | |
457 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, | |
458 | 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, | |
459 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, | |
460 | /* 2560x1600@120Hz RB */ | |
461 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, | |
462 | 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, | |
463 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, | |
464 | }; | |
465 | ||
e7bfa5c4 VS |
466 | /* |
467 | * These more or less come from the DMT spec. The 720x400 modes are | |
468 | * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 | |
469 | * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode | |
470 | * should be 1152x870, again for the Mac, but instead we use the x864 DMT | |
471 | * mode. | |
472 | * | |
473 | * The DMT modes have been fact-checked; the rest are mild guesses. | |
474 | */ | |
a6b21831 TR |
475 | static const struct drm_display_mode edid_est_modes[] = { |
476 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, | |
477 | 968, 1056, 0, 600, 601, 605, 628, 0, | |
478 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ | |
479 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, | |
480 | 896, 1024, 0, 600, 601, 603, 625, 0, | |
481 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ | |
482 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, | |
483 | 720, 840, 0, 480, 481, 484, 500, 0, | |
484 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ | |
485 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, | |
486 | 704, 832, 0, 480, 489, 491, 520, 0, | |
487 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ | |
488 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, | |
489 | 768, 864, 0, 480, 483, 486, 525, 0, | |
490 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ | |
491 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656, | |
492 | 752, 800, 0, 480, 490, 492, 525, 0, | |
493 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ | |
494 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, | |
495 | 846, 900, 0, 400, 421, 423, 449, 0, | |
496 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ | |
497 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, | |
498 | 846, 900, 0, 400, 412, 414, 449, 0, | |
499 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ | |
500 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, | |
501 | 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, | |
502 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ | |
503 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040, | |
504 | 1136, 1312, 0, 768, 769, 772, 800, 0, | |
505 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ | |
506 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, | |
507 | 1184, 1328, 0, 768, 771, 777, 806, 0, | |
508 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ | |
509 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, | |
510 | 1184, 1344, 0, 768, 771, 777, 806, 0, | |
511 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ | |
512 | { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, | |
513 | 1208, 1264, 0, 768, 768, 776, 817, 0, | |
514 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ | |
515 | { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, | |
516 | 928, 1152, 0, 624, 625, 628, 667, 0, | |
517 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ | |
518 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, | |
519 | 896, 1056, 0, 600, 601, 604, 625, 0, | |
520 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ | |
521 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, | |
522 | 976, 1040, 0, 600, 637, 643, 666, 0, | |
523 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ | |
524 | { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, | |
525 | 1344, 1600, 0, 864, 865, 868, 900, 0, | |
526 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ | |
527 | }; | |
528 | ||
529 | struct minimode { | |
530 | short w; | |
531 | short h; | |
532 | short r; | |
533 | short rb; | |
534 | }; | |
535 | ||
536 | static const struct minimode est3_modes[] = { | |
537 | /* byte 6 */ | |
538 | { 640, 350, 85, 0 }, | |
539 | { 640, 400, 85, 0 }, | |
540 | { 720, 400, 85, 0 }, | |
541 | { 640, 480, 85, 0 }, | |
542 | { 848, 480, 60, 0 }, | |
543 | { 800, 600, 85, 0 }, | |
544 | { 1024, 768, 85, 0 }, | |
545 | { 1152, 864, 75, 0 }, | |
546 | /* byte 7 */ | |
547 | { 1280, 768, 60, 1 }, | |
548 | { 1280, 768, 60, 0 }, | |
549 | { 1280, 768, 75, 0 }, | |
550 | { 1280, 768, 85, 0 }, | |
551 | { 1280, 960, 60, 0 }, | |
552 | { 1280, 960, 85, 0 }, | |
553 | { 1280, 1024, 60, 0 }, | |
554 | { 1280, 1024, 85, 0 }, | |
555 | /* byte 8 */ | |
556 | { 1360, 768, 60, 0 }, | |
557 | { 1440, 900, 60, 1 }, | |
558 | { 1440, 900, 60, 0 }, | |
559 | { 1440, 900, 75, 0 }, | |
560 | { 1440, 900, 85, 0 }, | |
561 | { 1400, 1050, 60, 1 }, | |
562 | { 1400, 1050, 60, 0 }, | |
563 | { 1400, 1050, 75, 0 }, | |
564 | /* byte 9 */ | |
565 | { 1400, 1050, 85, 0 }, | |
566 | { 1680, 1050, 60, 1 }, | |
567 | { 1680, 1050, 60, 0 }, | |
568 | { 1680, 1050, 75, 0 }, | |
569 | { 1680, 1050, 85, 0 }, | |
570 | { 1600, 1200, 60, 0 }, | |
571 | { 1600, 1200, 65, 0 }, | |
572 | { 1600, 1200, 70, 0 }, | |
573 | /* byte 10 */ | |
574 | { 1600, 1200, 75, 0 }, | |
575 | { 1600, 1200, 85, 0 }, | |
576 | { 1792, 1344, 60, 0 }, | |
c068b32a | 577 | { 1792, 1344, 75, 0 }, |
a6b21831 TR |
578 | { 1856, 1392, 60, 0 }, |
579 | { 1856, 1392, 75, 0 }, | |
580 | { 1920, 1200, 60, 1 }, | |
581 | { 1920, 1200, 60, 0 }, | |
582 | /* byte 11 */ | |
583 | { 1920, 1200, 75, 0 }, | |
584 | { 1920, 1200, 85, 0 }, | |
585 | { 1920, 1440, 60, 0 }, | |
586 | { 1920, 1440, 75, 0 }, | |
587 | }; | |
588 | ||
589 | static const struct minimode extra_modes[] = { | |
590 | { 1024, 576, 60, 0 }, | |
591 | { 1366, 768, 60, 0 }, | |
592 | { 1600, 900, 60, 0 }, | |
593 | { 1680, 945, 60, 0 }, | |
594 | { 1920, 1080, 60, 0 }, | |
595 | { 2048, 1152, 60, 0 }, | |
596 | { 2048, 1536, 60, 0 }, | |
597 | }; | |
598 | ||
599 | /* | |
600 | * Probably taken from CEA-861 spec. | |
601 | * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. | |
602 | */ | |
603 | static const struct drm_display_mode edid_cea_modes[] = { | |
604 | /* 1 - 640x480@60Hz */ | |
605 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, | |
606 | 752, 800, 0, 480, 490, 492, 525, 0, | |
ee7925bb VS |
607 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
608 | .vrefresh = 60, }, | |
a6b21831 TR |
609 | /* 2 - 720x480@60Hz */ |
610 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, | |
611 | 798, 858, 0, 480, 489, 495, 525, 0, | |
ee7925bb VS |
612 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
613 | .vrefresh = 60, }, | |
a6b21831 TR |
614 | /* 3 - 720x480@60Hz */ |
615 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, | |
616 | 798, 858, 0, 480, 489, 495, 525, 0, | |
ee7925bb VS |
617 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
618 | .vrefresh = 60, }, | |
a6b21831 TR |
619 | /* 4 - 1280x720@60Hz */ |
620 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, | |
621 | 1430, 1650, 0, 720, 725, 730, 750, 0, | |
ee7925bb VS |
622 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
623 | .vrefresh = 60, }, | |
a6b21831 TR |
624 | /* 5 - 1920x1080i@60Hz */ |
625 | { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, | |
626 | 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, | |
627 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | | |
ee7925bb VS |
628 | DRM_MODE_FLAG_INTERLACE), |
629 | .vrefresh = 60, }, | |
a6b21831 TR |
630 | /* 6 - 1440x480i@60Hz */ |
631 | { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478, | |
632 | 1602, 1716, 0, 480, 488, 494, 525, 0, | |
633 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb VS |
634 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
635 | .vrefresh = 60, }, | |
a6b21831 TR |
636 | /* 7 - 1440x480i@60Hz */ |
637 | { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478, | |
638 | 1602, 1716, 0, 480, 488, 494, 525, 0, | |
639 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb VS |
640 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
641 | .vrefresh = 60, }, | |
a6b21831 TR |
642 | /* 8 - 1440x240@60Hz */ |
643 | { DRM_MODE("1440x240", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478, | |
644 | 1602, 1716, 0, 240, 244, 247, 262, 0, | |
645 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb VS |
646 | DRM_MODE_FLAG_DBLCLK), |
647 | .vrefresh = 60, }, | |
a6b21831 TR |
648 | /* 9 - 1440x240@60Hz */ |
649 | { DRM_MODE("1440x240", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478, | |
650 | 1602, 1716, 0, 240, 244, 247, 262, 0, | |
651 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb VS |
652 | DRM_MODE_FLAG_DBLCLK), |
653 | .vrefresh = 60, }, | |
a6b21831 TR |
654 | /* 10 - 2880x480i@60Hz */ |
655 | { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, | |
656 | 3204, 3432, 0, 480, 488, 494, 525, 0, | |
657 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb VS |
658 | DRM_MODE_FLAG_INTERLACE), |
659 | .vrefresh = 60, }, | |
a6b21831 TR |
660 | /* 11 - 2880x480i@60Hz */ |
661 | { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, | |
662 | 3204, 3432, 0, 480, 488, 494, 525, 0, | |
663 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb VS |
664 | DRM_MODE_FLAG_INTERLACE), |
665 | .vrefresh = 60, }, | |
a6b21831 TR |
666 | /* 12 - 2880x240@60Hz */ |
667 | { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, | |
668 | 3204, 3432, 0, 240, 244, 247, 262, 0, | |
ee7925bb VS |
669 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
670 | .vrefresh = 60, }, | |
a6b21831 TR |
671 | /* 13 - 2880x240@60Hz */ |
672 | { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, | |
673 | 3204, 3432, 0, 240, 244, 247, 262, 0, | |
ee7925bb VS |
674 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
675 | .vrefresh = 60, }, | |
a6b21831 TR |
676 | /* 14 - 1440x480@60Hz */ |
677 | { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, | |
678 | 1596, 1716, 0, 480, 489, 495, 525, 0, | |
ee7925bb VS |
679 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
680 | .vrefresh = 60, }, | |
a6b21831 TR |
681 | /* 15 - 1440x480@60Hz */ |
682 | { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, | |
683 | 1596, 1716, 0, 480, 489, 495, 525, 0, | |
ee7925bb VS |
684 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
685 | .vrefresh = 60, }, | |
a6b21831 TR |
686 | /* 16 - 1920x1080@60Hz */ |
687 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, | |
688 | 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, | |
ee7925bb VS |
689 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
690 | .vrefresh = 60, }, | |
a6b21831 TR |
691 | /* 17 - 720x576@50Hz */ |
692 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, | |
693 | 796, 864, 0, 576, 581, 586, 625, 0, | |
ee7925bb VS |
694 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
695 | .vrefresh = 50, }, | |
a6b21831 TR |
696 | /* 18 - 720x576@50Hz */ |
697 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, | |
698 | 796, 864, 0, 576, 581, 586, 625, 0, | |
ee7925bb VS |
699 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
700 | .vrefresh = 50, }, | |
a6b21831 TR |
701 | /* 19 - 1280x720@50Hz */ |
702 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, | |
703 | 1760, 1980, 0, 720, 725, 730, 750, 0, | |
ee7925bb VS |
704 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
705 | .vrefresh = 50, }, | |
a6b21831 TR |
706 | /* 20 - 1920x1080i@50Hz */ |
707 | { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, | |
708 | 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, | |
709 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | | |
ee7925bb VS |
710 | DRM_MODE_FLAG_INTERLACE), |
711 | .vrefresh = 50, }, | |
a6b21831 TR |
712 | /* 21 - 1440x576i@50Hz */ |
713 | { DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464, | |
714 | 1590, 1728, 0, 576, 580, 586, 625, 0, | |
715 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb VS |
716 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
717 | .vrefresh = 50, }, | |
a6b21831 TR |
718 | /* 22 - 1440x576i@50Hz */ |
719 | { DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464, | |
720 | 1590, 1728, 0, 576, 580, 586, 625, 0, | |
721 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb VS |
722 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
723 | .vrefresh = 50, }, | |
a6b21831 TR |
724 | /* 23 - 1440x288@50Hz */ |
725 | { DRM_MODE("1440x288", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464, | |
726 | 1590, 1728, 0, 288, 290, 293, 312, 0, | |
727 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb VS |
728 | DRM_MODE_FLAG_DBLCLK), |
729 | .vrefresh = 50, }, | |
a6b21831 TR |
730 | /* 24 - 1440x288@50Hz */ |
731 | { DRM_MODE("1440x288", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464, | |
732 | 1590, 1728, 0, 288, 290, 293, 312, 0, | |
733 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb VS |
734 | DRM_MODE_FLAG_DBLCLK), |
735 | .vrefresh = 50, }, | |
a6b21831 TR |
736 | /* 25 - 2880x576i@50Hz */ |
737 | { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, | |
738 | 3180, 3456, 0, 576, 580, 586, 625, 0, | |
739 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb VS |
740 | DRM_MODE_FLAG_INTERLACE), |
741 | .vrefresh = 50, }, | |
a6b21831 TR |
742 | /* 26 - 2880x576i@50Hz */ |
743 | { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, | |
744 | 3180, 3456, 0, 576, 580, 586, 625, 0, | |
745 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb VS |
746 | DRM_MODE_FLAG_INTERLACE), |
747 | .vrefresh = 50, }, | |
a6b21831 TR |
748 | /* 27 - 2880x288@50Hz */ |
749 | { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, | |
750 | 3180, 3456, 0, 288, 290, 293, 312, 0, | |
ee7925bb VS |
751 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
752 | .vrefresh = 50, }, | |
a6b21831 TR |
753 | /* 28 - 2880x288@50Hz */ |
754 | { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, | |
755 | 3180, 3456, 0, 288, 290, 293, 312, 0, | |
ee7925bb VS |
756 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
757 | .vrefresh = 50, }, | |
a6b21831 TR |
758 | /* 29 - 1440x576@50Hz */ |
759 | { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, | |
760 | 1592, 1728, 0, 576, 581, 586, 625, 0, | |
ee7925bb VS |
761 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
762 | .vrefresh = 50, }, | |
a6b21831 TR |
763 | /* 30 - 1440x576@50Hz */ |
764 | { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, | |
765 | 1592, 1728, 0, 576, 581, 586, 625, 0, | |
ee7925bb VS |
766 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
767 | .vrefresh = 50, }, | |
a6b21831 TR |
768 | /* 31 - 1920x1080@50Hz */ |
769 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, | |
770 | 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, | |
ee7925bb VS |
771 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
772 | .vrefresh = 50, }, | |
a6b21831 TR |
773 | /* 32 - 1920x1080@24Hz */ |
774 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, | |
775 | 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, | |
ee7925bb VS |
776 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
777 | .vrefresh = 24, }, | |
a6b21831 TR |
778 | /* 33 - 1920x1080@25Hz */ |
779 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, | |
780 | 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, | |
ee7925bb VS |
781 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
782 | .vrefresh = 25, }, | |
a6b21831 TR |
783 | /* 34 - 1920x1080@30Hz */ |
784 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, | |
785 | 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, | |
ee7925bb VS |
786 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
787 | .vrefresh = 30, }, | |
a6b21831 TR |
788 | /* 35 - 2880x480@60Hz */ |
789 | { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, | |
790 | 3192, 3432, 0, 480, 489, 495, 525, 0, | |
ee7925bb VS |
791 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
792 | .vrefresh = 60, }, | |
a6b21831 TR |
793 | /* 36 - 2880x480@60Hz */ |
794 | { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, | |
795 | 3192, 3432, 0, 480, 489, 495, 525, 0, | |
ee7925bb VS |
796 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
797 | .vrefresh = 60, }, | |
a6b21831 TR |
798 | /* 37 - 2880x576@50Hz */ |
799 | { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, | |
800 | 3184, 3456, 0, 576, 581, 586, 625, 0, | |
ee7925bb VS |
801 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
802 | .vrefresh = 50, }, | |
a6b21831 TR |
803 | /* 38 - 2880x576@50Hz */ |
804 | { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, | |
805 | 3184, 3456, 0, 576, 581, 586, 625, 0, | |
ee7925bb VS |
806 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
807 | .vrefresh = 50, }, | |
a6b21831 TR |
808 | /* 39 - 1920x1080i@50Hz */ |
809 | { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, | |
810 | 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, | |
811 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb VS |
812 | DRM_MODE_FLAG_INTERLACE), |
813 | .vrefresh = 50, }, | |
a6b21831 TR |
814 | /* 40 - 1920x1080i@100Hz */ |
815 | { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, | |
816 | 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, | |
817 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | | |
ee7925bb VS |
818 | DRM_MODE_FLAG_INTERLACE), |
819 | .vrefresh = 100, }, | |
a6b21831 TR |
820 | /* 41 - 1280x720@100Hz */ |
821 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, | |
822 | 1760, 1980, 0, 720, 725, 730, 750, 0, | |
ee7925bb VS |
823 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
824 | .vrefresh = 100, }, | |
a6b21831 TR |
825 | /* 42 - 720x576@100Hz */ |
826 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, | |
827 | 796, 864, 0, 576, 581, 586, 625, 0, | |
ee7925bb VS |
828 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
829 | .vrefresh = 100, }, | |
a6b21831 TR |
830 | /* 43 - 720x576@100Hz */ |
831 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, | |
832 | 796, 864, 0, 576, 581, 586, 625, 0, | |
ee7925bb VS |
833 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
834 | .vrefresh = 100, }, | |
a6b21831 TR |
835 | /* 44 - 1440x576i@100Hz */ |
836 | { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, | |
837 | 1590, 1728, 0, 576, 580, 586, 625, 0, | |
838 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb VS |
839 | DRM_MODE_FLAG_DBLCLK), |
840 | .vrefresh = 100, }, | |
a6b21831 TR |
841 | /* 45 - 1440x576i@100Hz */ |
842 | { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, | |
843 | 1590, 1728, 0, 576, 580, 586, 625, 0, | |
844 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb VS |
845 | DRM_MODE_FLAG_DBLCLK), |
846 | .vrefresh = 100, }, | |
a6b21831 TR |
847 | /* 46 - 1920x1080i@120Hz */ |
848 | { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, | |
849 | 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, | |
850 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | | |
ee7925bb VS |
851 | DRM_MODE_FLAG_INTERLACE), |
852 | .vrefresh = 120, }, | |
a6b21831 TR |
853 | /* 47 - 1280x720@120Hz */ |
854 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, | |
855 | 1430, 1650, 0, 720, 725, 730, 750, 0, | |
ee7925bb VS |
856 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
857 | .vrefresh = 120, }, | |
a6b21831 TR |
858 | /* 48 - 720x480@120Hz */ |
859 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, | |
860 | 798, 858, 0, 480, 489, 495, 525, 0, | |
ee7925bb VS |
861 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
862 | .vrefresh = 120, }, | |
a6b21831 TR |
863 | /* 49 - 720x480@120Hz */ |
864 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, | |
865 | 798, 858, 0, 480, 489, 495, 525, 0, | |
ee7925bb VS |
866 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
867 | .vrefresh = 120, }, | |
a6b21831 TR |
868 | /* 50 - 1440x480i@120Hz */ |
869 | { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1478, | |
870 | 1602, 1716, 0, 480, 488, 494, 525, 0, | |
871 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb VS |
872 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
873 | .vrefresh = 120, }, | |
a6b21831 TR |
874 | /* 51 - 1440x480i@120Hz */ |
875 | { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1478, | |
876 | 1602, 1716, 0, 480, 488, 494, 525, 0, | |
877 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb VS |
878 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
879 | .vrefresh = 120, }, | |
a6b21831 TR |
880 | /* 52 - 720x576@200Hz */ |
881 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, | |
882 | 796, 864, 0, 576, 581, 586, 625, 0, | |
ee7925bb VS |
883 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
884 | .vrefresh = 200, }, | |
a6b21831 TR |
885 | /* 53 - 720x576@200Hz */ |
886 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, | |
887 | 796, 864, 0, 576, 581, 586, 625, 0, | |
ee7925bb VS |
888 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
889 | .vrefresh = 200, }, | |
a6b21831 TR |
890 | /* 54 - 1440x576i@200Hz */ |
891 | { DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1464, | |
892 | 1590, 1728, 0, 576, 580, 586, 625, 0, | |
893 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb VS |
894 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
895 | .vrefresh = 200, }, | |
a6b21831 TR |
896 | /* 55 - 1440x576i@200Hz */ |
897 | { DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1464, | |
898 | 1590, 1728, 0, 576, 580, 586, 625, 0, | |
899 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb VS |
900 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
901 | .vrefresh = 200, }, | |
a6b21831 TR |
902 | /* 56 - 720x480@240Hz */ |
903 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, | |
904 | 798, 858, 0, 480, 489, 495, 525, 0, | |
ee7925bb VS |
905 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
906 | .vrefresh = 240, }, | |
a6b21831 TR |
907 | /* 57 - 720x480@240Hz */ |
908 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, | |
909 | 798, 858, 0, 480, 489, 495, 525, 0, | |
ee7925bb VS |
910 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), |
911 | .vrefresh = 240, }, | |
a6b21831 TR |
912 | /* 58 - 1440x480i@240 */ |
913 | { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1478, | |
914 | 1602, 1716, 0, 480, 488, 494, 525, 0, | |
915 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb VS |
916 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
917 | .vrefresh = 240, }, | |
a6b21831 TR |
918 | /* 59 - 1440x480i@240 */ |
919 | { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1478, | |
920 | 1602, 1716, 0, 480, 488, 494, 525, 0, | |
921 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | | |
ee7925bb VS |
922 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), |
923 | .vrefresh = 240, }, | |
a6b21831 TR |
924 | /* 60 - 1280x720@24Hz */ |
925 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, | |
926 | 3080, 3300, 0, 720, 725, 730, 750, 0, | |
ee7925bb VS |
927 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
928 | .vrefresh = 24, }, | |
a6b21831 TR |
929 | /* 61 - 1280x720@25Hz */ |
930 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, | |
931 | 3740, 3960, 0, 720, 725, 730, 750, 0, | |
ee7925bb VS |
932 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
933 | .vrefresh = 25, }, | |
a6b21831 TR |
934 | /* 62 - 1280x720@30Hz */ |
935 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, | |
936 | 3080, 3300, 0, 720, 725, 730, 750, 0, | |
ee7925bb VS |
937 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
938 | .vrefresh = 30, }, | |
a6b21831 TR |
939 | /* 63 - 1920x1080@120Hz */ |
940 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, | |
941 | 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, | |
ee7925bb VS |
942 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
943 | .vrefresh = 120, }, | |
a6b21831 TR |
944 | /* 64 - 1920x1080@100Hz */ |
945 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, | |
946 | 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, | |
ee7925bb VS |
947 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), |
948 | .vrefresh = 100, }, | |
a6b21831 TR |
949 | }; |
950 | ||
7ebe1963 LD |
951 | /* |
952 | * HDMI 1.4 4k modes. | |
953 | */ | |
954 | static const struct drm_display_mode edid_4k_modes[] = { | |
955 | /* 1 - 3840x2160@30Hz */ | |
956 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, | |
957 | 3840, 4016, 4104, 4400, 0, | |
958 | 2160, 2168, 2178, 2250, 0, | |
959 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
960 | .vrefresh = 30, }, | |
961 | /* 2 - 3840x2160@25Hz */ | |
962 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, | |
963 | 3840, 4896, 4984, 5280, 0, | |
964 | 2160, 2168, 2178, 2250, 0, | |
965 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
966 | .vrefresh = 25, }, | |
967 | /* 3 - 3840x2160@24Hz */ | |
968 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, | |
969 | 3840, 5116, 5204, 5500, 0, | |
970 | 2160, 2168, 2178, 2250, 0, | |
971 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
972 | .vrefresh = 24, }, | |
973 | /* 4 - 4096x2160@24Hz (SMPTE) */ | |
974 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, | |
975 | 4096, 5116, 5204, 5500, 0, | |
976 | 2160, 2168, 2178, 2250, 0, | |
977 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), | |
978 | .vrefresh = 24, }, | |
979 | }; | |
980 | ||
61e57a8d | 981 | /*** DDC fetch and block validation ***/ |
f453ba04 | 982 | |
083ae056 AJ |
983 | static const u8 edid_header[] = { |
984 | 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 | |
985 | }; | |
f453ba04 | 986 | |
051963d4 TR |
987 | /* |
988 | * Sanity check the header of the base EDID block. Return 8 if the header | |
989 | * is perfect, down to 0 if it's totally wrong. | |
990 | */ | |
991 | int drm_edid_header_is_valid(const u8 *raw_edid) | |
992 | { | |
993 | int i, score = 0; | |
994 | ||
995 | for (i = 0; i < sizeof(edid_header); i++) | |
996 | if (raw_edid[i] == edid_header[i]) | |
997 | score++; | |
998 | ||
999 | return score; | |
1000 | } | |
1001 | EXPORT_SYMBOL(drm_edid_header_is_valid); | |
1002 | ||
47819ba2 AJ |
1003 | static int edid_fixup __read_mostly = 6; |
1004 | module_param_named(edid_fixup, edid_fixup, int, 0400); | |
1005 | MODULE_PARM_DESC(edid_fixup, | |
1006 | "Minimum number of valid EDID header bytes (0-8, default 6)"); | |
051963d4 | 1007 | |
61e57a8d AJ |
1008 | /* |
1009 | * Sanity check the EDID block (base or extension). Return 0 if the block | |
1010 | * doesn't check out, or 1 if it's valid. | |
f453ba04 | 1011 | */ |
0b2443ed | 1012 | bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid) |
f453ba04 | 1013 | { |
61e57a8d | 1014 | int i; |
f453ba04 | 1015 | u8 csum = 0; |
61e57a8d | 1016 | struct edid *edid = (struct edid *)raw_edid; |
f453ba04 | 1017 | |
fe2ef780 SWK |
1018 | if (WARN_ON(!raw_edid)) |
1019 | return false; | |
1020 | ||
47819ba2 AJ |
1021 | if (edid_fixup > 8 || edid_fixup < 0) |
1022 | edid_fixup = 6; | |
1023 | ||
f89ec8a4 | 1024 | if (block == 0) { |
051963d4 | 1025 | int score = drm_edid_header_is_valid(raw_edid); |
61e57a8d | 1026 | if (score == 8) ; |
47819ba2 | 1027 | else if (score >= edid_fixup) { |
61e57a8d AJ |
1028 | DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); |
1029 | memcpy(raw_edid, edid_header, sizeof(edid_header)); | |
1030 | } else { | |
1031 | goto bad; | |
1032 | } | |
1033 | } | |
f453ba04 DA |
1034 | |
1035 | for (i = 0; i < EDID_LENGTH; i++) | |
1036 | csum += raw_edid[i]; | |
1037 | if (csum) { | |
0b2443ed JG |
1038 | if (print_bad_edid) { |
1039 | DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum); | |
1040 | } | |
4a638b4e AJ |
1041 | |
1042 | /* allow CEA to slide through, switches mangle this */ | |
1043 | if (raw_edid[0] != 0x02) | |
1044 | goto bad; | |
f453ba04 DA |
1045 | } |
1046 | ||
61e57a8d AJ |
1047 | /* per-block-type checks */ |
1048 | switch (raw_edid[0]) { | |
1049 | case 0: /* base */ | |
1050 | if (edid->version != 1) { | |
1051 | DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version); | |
1052 | goto bad; | |
1053 | } | |
862b89c0 | 1054 | |
61e57a8d AJ |
1055 | if (edid->revision > 4) |
1056 | DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); | |
1057 | break; | |
862b89c0 | 1058 | |
61e57a8d AJ |
1059 | default: |
1060 | break; | |
1061 | } | |
47ee4ccf | 1062 | |
fe2ef780 | 1063 | return true; |
f453ba04 DA |
1064 | |
1065 | bad: | |
fe2ef780 | 1066 | if (print_bad_edid) { |
f49dadb8 | 1067 | printk(KERN_ERR "Raw EDID:\n"); |
0aff47f2 TV |
1068 | print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1, |
1069 | raw_edid, EDID_LENGTH, false); | |
f453ba04 | 1070 | } |
fe2ef780 | 1071 | return false; |
f453ba04 | 1072 | } |
da0df92b | 1073 | EXPORT_SYMBOL(drm_edid_block_valid); |
61e57a8d AJ |
1074 | |
1075 | /** | |
1076 | * drm_edid_is_valid - sanity check EDID data | |
1077 | * @edid: EDID data | |
1078 | * | |
1079 | * Sanity-check an entire EDID record (including extensions) | |
1080 | */ | |
1081 | bool drm_edid_is_valid(struct edid *edid) | |
1082 | { | |
1083 | int i; | |
1084 | u8 *raw = (u8 *)edid; | |
1085 | ||
1086 | if (!edid) | |
1087 | return false; | |
1088 | ||
1089 | for (i = 0; i <= edid->extensions; i++) | |
0b2443ed | 1090 | if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true)) |
61e57a8d AJ |
1091 | return false; |
1092 | ||
1093 | return true; | |
1094 | } | |
3c537889 | 1095 | EXPORT_SYMBOL(drm_edid_is_valid); |
f453ba04 | 1096 | |
61e57a8d AJ |
1097 | #define DDC_SEGMENT_ADDR 0x30 |
1098 | /** | |
1099 | * Get EDID information via I2C. | |
1100 | * | |
1101 | * \param adapter : i2c device adaptor | |
1102 | * \param buf : EDID data buffer to be filled | |
1103 | * \param len : EDID data buffer length | |
1104 | * \return 0 on success or -1 on failure. | |
1105 | * | |
1106 | * Try to fetch EDID information by calling i2c driver function. | |
1107 | */ | |
1108 | static int | |
1109 | drm_do_probe_ddc_edid(struct i2c_adapter *adapter, unsigned char *buf, | |
1110 | int block, int len) | |
1111 | { | |
1112 | unsigned char start = block * EDID_LENGTH; | |
cd004b3f S |
1113 | unsigned char segment = block >> 1; |
1114 | unsigned char xfers = segment ? 3 : 2; | |
4819d2e4 CW |
1115 | int ret, retries = 5; |
1116 | ||
1117 | /* The core i2c driver will automatically retry the transfer if the | |
1118 | * adapter reports EAGAIN. However, we find that bit-banging transfers | |
1119 | * are susceptible to errors under a heavily loaded machine and | |
1120 | * generate spurious NAKs and timeouts. Retrying the transfer | |
1121 | * of the individual block a few times seems to overcome this. | |
1122 | */ | |
1123 | do { | |
1124 | struct i2c_msg msgs[] = { | |
1125 | { | |
cd004b3f S |
1126 | .addr = DDC_SEGMENT_ADDR, |
1127 | .flags = 0, | |
1128 | .len = 1, | |
1129 | .buf = &segment, | |
1130 | }, { | |
4819d2e4 CW |
1131 | .addr = DDC_ADDR, |
1132 | .flags = 0, | |
1133 | .len = 1, | |
1134 | .buf = &start, | |
1135 | }, { | |
1136 | .addr = DDC_ADDR, | |
1137 | .flags = I2C_M_RD, | |
1138 | .len = len, | |
1139 | .buf = buf, | |
1140 | } | |
1141 | }; | |
cd004b3f S |
1142 | |
1143 | /* | |
1144 | * Avoid sending the segment addr to not upset non-compliant ddc | |
1145 | * monitors. | |
1146 | */ | |
1147 | ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); | |
1148 | ||
9292f37e ED |
1149 | if (ret == -ENXIO) { |
1150 | DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", | |
1151 | adapter->name); | |
1152 | break; | |
1153 | } | |
cd004b3f | 1154 | } while (ret != xfers && --retries); |
4819d2e4 | 1155 | |
cd004b3f | 1156 | return ret == xfers ? 0 : -1; |
61e57a8d AJ |
1157 | } |
1158 | ||
4a9a8b71 DA |
1159 | static bool drm_edid_is_zero(u8 *in_edid, int length) |
1160 | { | |
6311803b AM |
1161 | if (memchr_inv(in_edid, 0, length)) |
1162 | return false; | |
4a9a8b71 | 1163 | |
4a9a8b71 DA |
1164 | return true; |
1165 | } | |
1166 | ||
61e57a8d AJ |
1167 | static u8 * |
1168 | drm_do_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) | |
1169 | { | |
0ea75e23 | 1170 | int i, j = 0, valid_extensions = 0; |
61e57a8d | 1171 | u8 *block, *new; |
0b2443ed | 1172 | bool print_bad_edid = !connector->bad_edid_counter || (drm_debug & DRM_UT_KMS); |
61e57a8d AJ |
1173 | |
1174 | if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) | |
1175 | return NULL; | |
1176 | ||
1177 | /* base block fetch */ | |
1178 | for (i = 0; i < 4; i++) { | |
1179 | if (drm_do_probe_ddc_edid(adapter, block, 0, EDID_LENGTH)) | |
1180 | goto out; | |
0b2443ed | 1181 | if (drm_edid_block_valid(block, 0, print_bad_edid)) |
61e57a8d | 1182 | break; |
4a9a8b71 DA |
1183 | if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) { |
1184 | connector->null_edid_counter++; | |
1185 | goto carp; | |
1186 | } | |
61e57a8d AJ |
1187 | } |
1188 | if (i == 4) | |
1189 | goto carp; | |
1190 | ||
1191 | /* if there's no extensions, we're done */ | |
1192 | if (block[0x7e] == 0) | |
1193 | return block; | |
1194 | ||
1195 | new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL); | |
1196 | if (!new) | |
1197 | goto out; | |
1198 | block = new; | |
1199 | ||
1200 | for (j = 1; j <= block[0x7e]; j++) { | |
1201 | for (i = 0; i < 4; i++) { | |
0ea75e23 ST |
1202 | if (drm_do_probe_ddc_edid(adapter, |
1203 | block + (valid_extensions + 1) * EDID_LENGTH, | |
1204 | j, EDID_LENGTH)) | |
61e57a8d | 1205 | goto out; |
0b2443ed | 1206 | if (drm_edid_block_valid(block + (valid_extensions + 1) * EDID_LENGTH, j, print_bad_edid)) { |
0ea75e23 | 1207 | valid_extensions++; |
61e57a8d | 1208 | break; |
0ea75e23 | 1209 | } |
61e57a8d | 1210 | } |
f934ec8c ML |
1211 | |
1212 | if (i == 4 && print_bad_edid) { | |
0ea75e23 ST |
1213 | dev_warn(connector->dev->dev, |
1214 | "%s: Ignoring invalid EDID block %d.\n", | |
1215 | drm_get_connector_name(connector), j); | |
f934ec8c ML |
1216 | |
1217 | connector->bad_edid_counter++; | |
1218 | } | |
0ea75e23 ST |
1219 | } |
1220 | ||
1221 | if (valid_extensions != block[0x7e]) { | |
1222 | block[EDID_LENGTH-1] += block[0x7e] - valid_extensions; | |
1223 | block[0x7e] = valid_extensions; | |
1224 | new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); | |
1225 | if (!new) | |
1226 | goto out; | |
1227 | block = new; | |
61e57a8d AJ |
1228 | } |
1229 | ||
1230 | return block; | |
1231 | ||
1232 | carp: | |
0b2443ed JG |
1233 | if (print_bad_edid) { |
1234 | dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n", | |
1235 | drm_get_connector_name(connector), j); | |
1236 | } | |
1237 | connector->bad_edid_counter++; | |
61e57a8d AJ |
1238 | |
1239 | out: | |
1240 | kfree(block); | |
1241 | return NULL; | |
1242 | } | |
1243 | ||
1244 | /** | |
1245 | * Probe DDC presence. | |
1246 | * | |
1247 | * \param adapter : i2c device adaptor | |
1248 | * \return 1 on success | |
1249 | */ | |
fbff4690 | 1250 | bool |
61e57a8d AJ |
1251 | drm_probe_ddc(struct i2c_adapter *adapter) |
1252 | { | |
1253 | unsigned char out; | |
1254 | ||
1255 | return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); | |
1256 | } | |
fbff4690 | 1257 | EXPORT_SYMBOL(drm_probe_ddc); |
61e57a8d AJ |
1258 | |
1259 | /** | |
1260 | * drm_get_edid - get EDID data, if available | |
1261 | * @connector: connector we're probing | |
1262 | * @adapter: i2c adapter to use for DDC | |
1263 | * | |
1264 | * Poke the given i2c channel to grab EDID data if possible. If found, | |
1265 | * attach it to the connector. | |
1266 | * | |
1267 | * Return edid data or NULL if we couldn't find any. | |
1268 | */ | |
1269 | struct edid *drm_get_edid(struct drm_connector *connector, | |
1270 | struct i2c_adapter *adapter) | |
1271 | { | |
1272 | struct edid *edid = NULL; | |
1273 | ||
1274 | if (drm_probe_ddc(adapter)) | |
1275 | edid = (struct edid *)drm_do_get_edid(connector, adapter); | |
1276 | ||
61e57a8d | 1277 | return edid; |
61e57a8d AJ |
1278 | } |
1279 | EXPORT_SYMBOL(drm_get_edid); | |
1280 | ||
51f8da59 JN |
1281 | /** |
1282 | * drm_edid_duplicate - duplicate an EDID and the extensions | |
1283 | * @edid: EDID to duplicate | |
1284 | * | |
1285 | * Return duplicate edid or NULL on allocation failure. | |
1286 | */ | |
1287 | struct edid *drm_edid_duplicate(const struct edid *edid) | |
1288 | { | |
1289 | return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); | |
1290 | } | |
1291 | EXPORT_SYMBOL(drm_edid_duplicate); | |
1292 | ||
61e57a8d AJ |
1293 | /*** EDID parsing ***/ |
1294 | ||
f453ba04 DA |
1295 | /** |
1296 | * edid_vendor - match a string against EDID's obfuscated vendor field | |
1297 | * @edid: EDID to match | |
1298 | * @vendor: vendor string | |
1299 | * | |
1300 | * Returns true if @vendor is in @edid, false otherwise | |
1301 | */ | |
1302 | static bool edid_vendor(struct edid *edid, char *vendor) | |
1303 | { | |
1304 | char edid_vendor[3]; | |
1305 | ||
1306 | edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; | |
1307 | edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | | |
1308 | ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; | |
16456c87 | 1309 | edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; |
f453ba04 DA |
1310 | |
1311 | return !strncmp(edid_vendor, vendor, 3); | |
1312 | } | |
1313 | ||
1314 | /** | |
1315 | * edid_get_quirks - return quirk flags for a given EDID | |
1316 | * @edid: EDID to process | |
1317 | * | |
1318 | * This tells subsequent routines what fixes they need to apply. | |
1319 | */ | |
1320 | static u32 edid_get_quirks(struct edid *edid) | |
1321 | { | |
1322 | struct edid_quirk *quirk; | |
1323 | int i; | |
1324 | ||
1325 | for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { | |
1326 | quirk = &edid_quirk_list[i]; | |
1327 | ||
1328 | if (edid_vendor(edid, quirk->vendor) && | |
1329 | (EDID_PRODUCT_ID(edid) == quirk->product_id)) | |
1330 | return quirk->quirks; | |
1331 | } | |
1332 | ||
1333 | return 0; | |
1334 | } | |
1335 | ||
1336 | #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) | |
339d202c | 1337 | #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) |
f453ba04 | 1338 | |
f453ba04 DA |
1339 | /** |
1340 | * edid_fixup_preferred - set preferred modes based on quirk list | |
1341 | * @connector: has mode list to fix up | |
1342 | * @quirks: quirks list | |
1343 | * | |
1344 | * Walk the mode list for @connector, clearing the preferred status | |
1345 | * on existing modes and setting it anew for the right mode ala @quirks. | |
1346 | */ | |
1347 | static void edid_fixup_preferred(struct drm_connector *connector, | |
1348 | u32 quirks) | |
1349 | { | |
1350 | struct drm_display_mode *t, *cur_mode, *preferred_mode; | |
f890607b | 1351 | int target_refresh = 0; |
339d202c | 1352 | int cur_vrefresh, preferred_vrefresh; |
f453ba04 DA |
1353 | |
1354 | if (list_empty(&connector->probed_modes)) | |
1355 | return; | |
1356 | ||
1357 | if (quirks & EDID_QUIRK_PREFER_LARGE_60) | |
1358 | target_refresh = 60; | |
1359 | if (quirks & EDID_QUIRK_PREFER_LARGE_75) | |
1360 | target_refresh = 75; | |
1361 | ||
1362 | preferred_mode = list_first_entry(&connector->probed_modes, | |
1363 | struct drm_display_mode, head); | |
1364 | ||
1365 | list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { | |
1366 | cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; | |
1367 | ||
1368 | if (cur_mode == preferred_mode) | |
1369 | continue; | |
1370 | ||
1371 | /* Largest mode is preferred */ | |
1372 | if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) | |
1373 | preferred_mode = cur_mode; | |
1374 | ||
339d202c AD |
1375 | cur_vrefresh = cur_mode->vrefresh ? |
1376 | cur_mode->vrefresh : drm_mode_vrefresh(cur_mode); | |
1377 | preferred_vrefresh = preferred_mode->vrefresh ? | |
1378 | preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode); | |
f453ba04 DA |
1379 | /* At a given size, try to get closest to target refresh */ |
1380 | if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && | |
339d202c AD |
1381 | MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < |
1382 | MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { | |
f453ba04 DA |
1383 | preferred_mode = cur_mode; |
1384 | } | |
1385 | } | |
1386 | ||
1387 | preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
1388 | } | |
1389 | ||
f6e252ba AJ |
1390 | static bool |
1391 | mode_is_rb(const struct drm_display_mode *mode) | |
1392 | { | |
1393 | return (mode->htotal - mode->hdisplay == 160) && | |
1394 | (mode->hsync_end - mode->hdisplay == 80) && | |
1395 | (mode->hsync_end - mode->hsync_start == 32) && | |
1396 | (mode->vsync_start - mode->vdisplay == 3); | |
1397 | } | |
1398 | ||
33c7531d AJ |
1399 | /* |
1400 | * drm_mode_find_dmt - Create a copy of a mode if present in DMT | |
1401 | * @dev: Device to duplicate against | |
1402 | * @hsize: Mode width | |
1403 | * @vsize: Mode height | |
1404 | * @fresh: Mode refresh rate | |
f6e252ba | 1405 | * @rb: Mode reduced-blanking-ness |
33c7531d AJ |
1406 | * |
1407 | * Walk the DMT mode list looking for a match for the given parameters. | |
1408 | * Return a newly allocated copy of the mode, or NULL if not found. | |
1409 | */ | |
1d42bbc8 | 1410 | struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, |
f6e252ba AJ |
1411 | int hsize, int vsize, int fresh, |
1412 | bool rb) | |
559ee21d | 1413 | { |
07a5e632 | 1414 | int i; |
559ee21d | 1415 | |
a6b21831 | 1416 | for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { |
b1f559ec | 1417 | const struct drm_display_mode *ptr = &drm_dmt_modes[i]; |
f8b46a05 AJ |
1418 | if (hsize != ptr->hdisplay) |
1419 | continue; | |
1420 | if (vsize != ptr->vdisplay) | |
1421 | continue; | |
1422 | if (fresh != drm_mode_vrefresh(ptr)) | |
1423 | continue; | |
f6e252ba AJ |
1424 | if (rb != mode_is_rb(ptr)) |
1425 | continue; | |
f8b46a05 AJ |
1426 | |
1427 | return drm_mode_duplicate(dev, ptr); | |
559ee21d | 1428 | } |
f8b46a05 AJ |
1429 | |
1430 | return NULL; | |
559ee21d | 1431 | } |
1d42bbc8 | 1432 | EXPORT_SYMBOL(drm_mode_find_dmt); |
23425cae | 1433 | |
d1ff6409 AJ |
1434 | typedef void detailed_cb(struct detailed_timing *timing, void *closure); |
1435 | ||
4d76a221 AJ |
1436 | static void |
1437 | cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) | |
1438 | { | |
1439 | int i, n = 0; | |
4966b2a9 | 1440 | u8 d = ext[0x02]; |
4d76a221 AJ |
1441 | u8 *det_base = ext + d; |
1442 | ||
4966b2a9 | 1443 | n = (127 - d) / 18; |
4d76a221 AJ |
1444 | for (i = 0; i < n; i++) |
1445 | cb((struct detailed_timing *)(det_base + 18 * i), closure); | |
1446 | } | |
1447 | ||
cbba98f8 AJ |
1448 | static void |
1449 | vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) | |
1450 | { | |
1451 | unsigned int i, n = min((int)ext[0x02], 6); | |
1452 | u8 *det_base = ext + 5; | |
1453 | ||
1454 | if (ext[0x01] != 1) | |
1455 | return; /* unknown version */ | |
1456 | ||
1457 | for (i = 0; i < n; i++) | |
1458 | cb((struct detailed_timing *)(det_base + 18 * i), closure); | |
1459 | } | |
1460 | ||
d1ff6409 AJ |
1461 | static void |
1462 | drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) | |
1463 | { | |
1464 | int i; | |
1465 | struct edid *edid = (struct edid *)raw_edid; | |
1466 | ||
1467 | if (edid == NULL) | |
1468 | return; | |
1469 | ||
1470 | for (i = 0; i < EDID_DETAILED_TIMINGS; i++) | |
1471 | cb(&(edid->detailed_timings[i]), closure); | |
1472 | ||
4d76a221 AJ |
1473 | for (i = 1; i <= raw_edid[0x7e]; i++) { |
1474 | u8 *ext = raw_edid + (i * EDID_LENGTH); | |
1475 | switch (*ext) { | |
1476 | case CEA_EXT: | |
1477 | cea_for_each_detailed_block(ext, cb, closure); | |
1478 | break; | |
cbba98f8 AJ |
1479 | case VTB_EXT: |
1480 | vtb_for_each_detailed_block(ext, cb, closure); | |
1481 | break; | |
4d76a221 AJ |
1482 | default: |
1483 | break; | |
1484 | } | |
1485 | } | |
d1ff6409 AJ |
1486 | } |
1487 | ||
1488 | static void | |
1489 | is_rb(struct detailed_timing *t, void *data) | |
1490 | { | |
1491 | u8 *r = (u8 *)t; | |
1492 | if (r[3] == EDID_DETAIL_MONITOR_RANGE) | |
1493 | if (r[15] & 0x10) | |
1494 | *(bool *)data = true; | |
1495 | } | |
1496 | ||
1497 | /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ | |
1498 | static bool | |
1499 | drm_monitor_supports_rb(struct edid *edid) | |
1500 | { | |
1501 | if (edid->revision >= 4) { | |
b196a498 | 1502 | bool ret = false; |
d1ff6409 AJ |
1503 | drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); |
1504 | return ret; | |
1505 | } | |
1506 | ||
1507 | return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); | |
1508 | } | |
1509 | ||
7a374350 AJ |
1510 | static void |
1511 | find_gtf2(struct detailed_timing *t, void *data) | |
1512 | { | |
1513 | u8 *r = (u8 *)t; | |
1514 | if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) | |
1515 | *(u8 **)data = r; | |
1516 | } | |
1517 | ||
1518 | /* Secondary GTF curve kicks in above some break frequency */ | |
1519 | static int | |
1520 | drm_gtf2_hbreak(struct edid *edid) | |
1521 | { | |
1522 | u8 *r = NULL; | |
1523 | drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); | |
1524 | return r ? (r[12] * 2) : 0; | |
1525 | } | |
1526 | ||
1527 | static int | |
1528 | drm_gtf2_2c(struct edid *edid) | |
1529 | { | |
1530 | u8 *r = NULL; | |
1531 | drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); | |
1532 | return r ? r[13] : 0; | |
1533 | } | |
1534 | ||
1535 | static int | |
1536 | drm_gtf2_m(struct edid *edid) | |
1537 | { | |
1538 | u8 *r = NULL; | |
1539 | drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); | |
1540 | return r ? (r[15] << 8) + r[14] : 0; | |
1541 | } | |
1542 | ||
1543 | static int | |
1544 | drm_gtf2_k(struct edid *edid) | |
1545 | { | |
1546 | u8 *r = NULL; | |
1547 | drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); | |
1548 | return r ? r[16] : 0; | |
1549 | } | |
1550 | ||
1551 | static int | |
1552 | drm_gtf2_2j(struct edid *edid) | |
1553 | { | |
1554 | u8 *r = NULL; | |
1555 | drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); | |
1556 | return r ? r[17] : 0; | |
1557 | } | |
1558 | ||
1559 | /** | |
1560 | * standard_timing_level - get std. timing level(CVT/GTF/DMT) | |
1561 | * @edid: EDID block to scan | |
1562 | */ | |
1563 | static int standard_timing_level(struct edid *edid) | |
1564 | { | |
1565 | if (edid->revision >= 2) { | |
1566 | if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) | |
1567 | return LEVEL_CVT; | |
1568 | if (drm_gtf2_hbreak(edid)) | |
1569 | return LEVEL_GTF2; | |
1570 | return LEVEL_GTF; | |
1571 | } | |
1572 | return LEVEL_DMT; | |
1573 | } | |
1574 | ||
23425cae AJ |
1575 | /* |
1576 | * 0 is reserved. The spec says 0x01 fill for unused timings. Some old | |
1577 | * monitors fill with ascii space (0x20) instead. | |
1578 | */ | |
1579 | static int | |
1580 | bad_std_timing(u8 a, u8 b) | |
1581 | { | |
1582 | return (a == 0x00 && b == 0x00) || | |
1583 | (a == 0x01 && b == 0x01) || | |
1584 | (a == 0x20 && b == 0x20); | |
1585 | } | |
1586 | ||
f453ba04 DA |
1587 | /** |
1588 | * drm_mode_std - convert standard mode info (width, height, refresh) into mode | |
1589 | * @t: standard timing params | |
5c61259e | 1590 | * @timing_level: standard timing level |
f453ba04 DA |
1591 | * |
1592 | * Take the standard timing params (in this case width, aspect, and refresh) | |
5c61259e | 1593 | * and convert them into a real mode using CVT/GTF/DMT. |
f453ba04 | 1594 | */ |
7ca6adb3 | 1595 | static struct drm_display_mode * |
7a374350 AJ |
1596 | drm_mode_std(struct drm_connector *connector, struct edid *edid, |
1597 | struct std_timing *t, int revision) | |
f453ba04 | 1598 | { |
7ca6adb3 AJ |
1599 | struct drm_device *dev = connector->dev; |
1600 | struct drm_display_mode *m, *mode = NULL; | |
5c61259e ZY |
1601 | int hsize, vsize; |
1602 | int vrefresh_rate; | |
0454beab MD |
1603 | unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) |
1604 | >> EDID_TIMING_ASPECT_SHIFT; | |
5c61259e ZY |
1605 | unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) |
1606 | >> EDID_TIMING_VFREQ_SHIFT; | |
7a374350 | 1607 | int timing_level = standard_timing_level(edid); |
5c61259e | 1608 | |
23425cae AJ |
1609 | if (bad_std_timing(t->hsize, t->vfreq_aspect)) |
1610 | return NULL; | |
1611 | ||
5c61259e ZY |
1612 | /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ |
1613 | hsize = t->hsize * 8 + 248; | |
1614 | /* vrefresh_rate = vfreq + 60 */ | |
1615 | vrefresh_rate = vfreq + 60; | |
1616 | /* the vdisplay is calculated based on the aspect ratio */ | |
f066a17d AJ |
1617 | if (aspect_ratio == 0) { |
1618 | if (revision < 3) | |
1619 | vsize = hsize; | |
1620 | else | |
1621 | vsize = (hsize * 10) / 16; | |
1622 | } else if (aspect_ratio == 1) | |
f453ba04 | 1623 | vsize = (hsize * 3) / 4; |
0454beab | 1624 | else if (aspect_ratio == 2) |
f453ba04 DA |
1625 | vsize = (hsize * 4) / 5; |
1626 | else | |
1627 | vsize = (hsize * 9) / 16; | |
a0910c8e AJ |
1628 | |
1629 | /* HDTV hack, part 1 */ | |
1630 | if (vrefresh_rate == 60 && | |
1631 | ((hsize == 1360 && vsize == 765) || | |
1632 | (hsize == 1368 && vsize == 769))) { | |
1633 | hsize = 1366; | |
1634 | vsize = 768; | |
1635 | } | |
1636 | ||
7ca6adb3 AJ |
1637 | /* |
1638 | * If this connector already has a mode for this size and refresh | |
1639 | * rate (because it came from detailed or CVT info), use that | |
1640 | * instead. This way we don't have to guess at interlace or | |
1641 | * reduced blanking. | |
1642 | */ | |
522032da | 1643 | list_for_each_entry(m, &connector->probed_modes, head) |
7ca6adb3 AJ |
1644 | if (m->hdisplay == hsize && m->vdisplay == vsize && |
1645 | drm_mode_vrefresh(m) == vrefresh_rate) | |
1646 | return NULL; | |
1647 | ||
a0910c8e AJ |
1648 | /* HDTV hack, part 2 */ |
1649 | if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { | |
1650 | mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, | |
d50ba256 | 1651 | false); |
559ee21d | 1652 | mode->hdisplay = 1366; |
a4967de6 AJ |
1653 | mode->hsync_start = mode->hsync_start - 1; |
1654 | mode->hsync_end = mode->hsync_end - 1; | |
559ee21d ZY |
1655 | return mode; |
1656 | } | |
a0910c8e | 1657 | |
559ee21d | 1658 | /* check whether it can be found in default mode table */ |
f6e252ba AJ |
1659 | if (drm_monitor_supports_rb(edid)) { |
1660 | mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, | |
1661 | true); | |
1662 | if (mode) | |
1663 | return mode; | |
1664 | } | |
1665 | mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); | |
559ee21d ZY |
1666 | if (mode) |
1667 | return mode; | |
1668 | ||
f6e252ba | 1669 | /* okay, generate it */ |
5c61259e ZY |
1670 | switch (timing_level) { |
1671 | case LEVEL_DMT: | |
5c61259e ZY |
1672 | break; |
1673 | case LEVEL_GTF: | |
1674 | mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); | |
1675 | break; | |
7a374350 AJ |
1676 | case LEVEL_GTF2: |
1677 | /* | |
1678 | * This is potentially wrong if there's ever a monitor with | |
1679 | * more than one ranges section, each claiming a different | |
1680 | * secondary GTF curve. Please don't do that. | |
1681 | */ | |
1682 | mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); | |
fc48f169 TI |
1683 | if (!mode) |
1684 | return NULL; | |
7a374350 | 1685 | if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { |
aefd330e | 1686 | drm_mode_destroy(dev, mode); |
7a374350 AJ |
1687 | mode = drm_gtf_mode_complex(dev, hsize, vsize, |
1688 | vrefresh_rate, 0, 0, | |
1689 | drm_gtf2_m(edid), | |
1690 | drm_gtf2_2c(edid), | |
1691 | drm_gtf2_k(edid), | |
1692 | drm_gtf2_2j(edid)); | |
1693 | } | |
1694 | break; | |
5c61259e | 1695 | case LEVEL_CVT: |
d50ba256 DA |
1696 | mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, |
1697 | false); | |
5c61259e ZY |
1698 | break; |
1699 | } | |
f453ba04 DA |
1700 | return mode; |
1701 | } | |
1702 | ||
b58db2c6 AJ |
1703 | /* |
1704 | * EDID is delightfully ambiguous about how interlaced modes are to be | |
1705 | * encoded. Our internal representation is of frame height, but some | |
1706 | * HDTV detailed timings are encoded as field height. | |
1707 | * | |
1708 | * The format list here is from CEA, in frame size. Technically we | |
1709 | * should be checking refresh rate too. Whatever. | |
1710 | */ | |
1711 | static void | |
1712 | drm_mode_do_interlace_quirk(struct drm_display_mode *mode, | |
1713 | struct detailed_pixel_timing *pt) | |
1714 | { | |
1715 | int i; | |
1716 | static const struct { | |
1717 | int w, h; | |
1718 | } cea_interlaced[] = { | |
1719 | { 1920, 1080 }, | |
1720 | { 720, 480 }, | |
1721 | { 1440, 480 }, | |
1722 | { 2880, 480 }, | |
1723 | { 720, 576 }, | |
1724 | { 1440, 576 }, | |
1725 | { 2880, 576 }, | |
1726 | }; | |
b58db2c6 AJ |
1727 | |
1728 | if (!(pt->misc & DRM_EDID_PT_INTERLACED)) | |
1729 | return; | |
1730 | ||
3c581411 | 1731 | for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { |
b58db2c6 AJ |
1732 | if ((mode->hdisplay == cea_interlaced[i].w) && |
1733 | (mode->vdisplay == cea_interlaced[i].h / 2)) { | |
1734 | mode->vdisplay *= 2; | |
1735 | mode->vsync_start *= 2; | |
1736 | mode->vsync_end *= 2; | |
1737 | mode->vtotal *= 2; | |
1738 | mode->vtotal |= 1; | |
1739 | } | |
1740 | } | |
1741 | ||
1742 | mode->flags |= DRM_MODE_FLAG_INTERLACE; | |
1743 | } | |
1744 | ||
f453ba04 DA |
1745 | /** |
1746 | * drm_mode_detailed - create a new mode from an EDID detailed timing section | |
1747 | * @dev: DRM device (needed to create new mode) | |
1748 | * @edid: EDID block | |
1749 | * @timing: EDID detailed timing info | |
1750 | * @quirks: quirks to apply | |
1751 | * | |
1752 | * An EDID detailed timing block contains enough info for us to create and | |
1753 | * return a new struct drm_display_mode. | |
1754 | */ | |
1755 | static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, | |
1756 | struct edid *edid, | |
1757 | struct detailed_timing *timing, | |
1758 | u32 quirks) | |
1759 | { | |
1760 | struct drm_display_mode *mode; | |
1761 | struct detailed_pixel_timing *pt = &timing->data.pixel_data; | |
0454beab MD |
1762 | unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; |
1763 | unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; | |
1764 | unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; | |
1765 | unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; | |
e14cbee4 MD |
1766 | unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; |
1767 | unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; | |
16dad1d7 | 1768 | unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; |
e14cbee4 | 1769 | unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); |
f453ba04 | 1770 | |
fc438966 | 1771 | /* ignore tiny modes */ |
0454beab | 1772 | if (hactive < 64 || vactive < 64) |
fc438966 AJ |
1773 | return NULL; |
1774 | ||
0454beab | 1775 | if (pt->misc & DRM_EDID_PT_STEREO) { |
c7d015f3 | 1776 | DRM_DEBUG_KMS("stereo mode not supported\n"); |
f453ba04 DA |
1777 | return NULL; |
1778 | } | |
0454beab | 1779 | if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { |
c7d015f3 | 1780 | DRM_DEBUG_KMS("composite sync not supported\n"); |
f453ba04 DA |
1781 | } |
1782 | ||
fcb45611 ZY |
1783 | /* it is incorrect if hsync/vsync width is zero */ |
1784 | if (!hsync_pulse_width || !vsync_pulse_width) { | |
1785 | DRM_DEBUG_KMS("Incorrect Detailed timing. " | |
1786 | "Wrong Hsync/Vsync pulse width\n"); | |
1787 | return NULL; | |
1788 | } | |
bc42aabc AJ |
1789 | |
1790 | if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { | |
1791 | mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); | |
1792 | if (!mode) | |
1793 | return NULL; | |
1794 | ||
1795 | goto set_size; | |
1796 | } | |
1797 | ||
f453ba04 DA |
1798 | mode = drm_mode_create(dev); |
1799 | if (!mode) | |
1800 | return NULL; | |
1801 | ||
f453ba04 | 1802 | if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) |
0454beab MD |
1803 | timing->pixel_clock = cpu_to_le16(1088); |
1804 | ||
1805 | mode->clock = le16_to_cpu(timing->pixel_clock) * 10; | |
1806 | ||
1807 | mode->hdisplay = hactive; | |
1808 | mode->hsync_start = mode->hdisplay + hsync_offset; | |
1809 | mode->hsync_end = mode->hsync_start + hsync_pulse_width; | |
1810 | mode->htotal = mode->hdisplay + hblank; | |
1811 | ||
1812 | mode->vdisplay = vactive; | |
1813 | mode->vsync_start = mode->vdisplay + vsync_offset; | |
1814 | mode->vsync_end = mode->vsync_start + vsync_pulse_width; | |
1815 | mode->vtotal = mode->vdisplay + vblank; | |
f453ba04 | 1816 | |
7064fef5 JB |
1817 | /* Some EDIDs have bogus h/vtotal values */ |
1818 | if (mode->hsync_end > mode->htotal) | |
1819 | mode->htotal = mode->hsync_end + 1; | |
1820 | if (mode->vsync_end > mode->vtotal) | |
1821 | mode->vtotal = mode->vsync_end + 1; | |
1822 | ||
b58db2c6 | 1823 | drm_mode_do_interlace_quirk(mode, pt); |
f453ba04 DA |
1824 | |
1825 | if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { | |
0454beab | 1826 | pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; |
f453ba04 DA |
1827 | } |
1828 | ||
0454beab MD |
1829 | mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? |
1830 | DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; | |
1831 | mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? | |
1832 | DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; | |
f453ba04 | 1833 | |
bc42aabc | 1834 | set_size: |
e14cbee4 MD |
1835 | mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; |
1836 | mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; | |
f453ba04 DA |
1837 | |
1838 | if (quirks & EDID_QUIRK_DETAILED_IN_CM) { | |
1839 | mode->width_mm *= 10; | |
1840 | mode->height_mm *= 10; | |
1841 | } | |
1842 | ||
1843 | if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { | |
1844 | mode->width_mm = edid->width_cm * 10; | |
1845 | mode->height_mm = edid->height_cm * 10; | |
1846 | } | |
1847 | ||
bc42aabc | 1848 | mode->type = DRM_MODE_TYPE_DRIVER; |
c19b3b0f | 1849 | mode->vrefresh = drm_mode_vrefresh(mode); |
bc42aabc AJ |
1850 | drm_mode_set_name(mode); |
1851 | ||
f453ba04 DA |
1852 | return mode; |
1853 | } | |
1854 | ||
b17e52ef | 1855 | static bool |
b1f559ec CW |
1856 | mode_in_hsync_range(const struct drm_display_mode *mode, |
1857 | struct edid *edid, u8 *t) | |
b17e52ef AJ |
1858 | { |
1859 | int hsync, hmin, hmax; | |
1860 | ||
1861 | hmin = t[7]; | |
1862 | if (edid->revision >= 4) | |
1863 | hmin += ((t[4] & 0x04) ? 255 : 0); | |
1864 | hmax = t[8]; | |
1865 | if (edid->revision >= 4) | |
1866 | hmax += ((t[4] & 0x08) ? 255 : 0); | |
07a5e632 | 1867 | hsync = drm_mode_hsync(mode); |
07a5e632 | 1868 | |
b17e52ef AJ |
1869 | return (hsync <= hmax && hsync >= hmin); |
1870 | } | |
1871 | ||
1872 | static bool | |
b1f559ec CW |
1873 | mode_in_vsync_range(const struct drm_display_mode *mode, |
1874 | struct edid *edid, u8 *t) | |
b17e52ef AJ |
1875 | { |
1876 | int vsync, vmin, vmax; | |
1877 | ||
1878 | vmin = t[5]; | |
1879 | if (edid->revision >= 4) | |
1880 | vmin += ((t[4] & 0x01) ? 255 : 0); | |
1881 | vmax = t[6]; | |
1882 | if (edid->revision >= 4) | |
1883 | vmax += ((t[4] & 0x02) ? 255 : 0); | |
1884 | vsync = drm_mode_vrefresh(mode); | |
1885 | ||
1886 | return (vsync <= vmax && vsync >= vmin); | |
1887 | } | |
1888 | ||
1889 | static u32 | |
1890 | range_pixel_clock(struct edid *edid, u8 *t) | |
1891 | { | |
1892 | /* unspecified */ | |
1893 | if (t[9] == 0 || t[9] == 255) | |
1894 | return 0; | |
1895 | ||
1896 | /* 1.4 with CVT support gives us real precision, yay */ | |
1897 | if (edid->revision >= 4 && t[10] == 0x04) | |
1898 | return (t[9] * 10000) - ((t[12] >> 2) * 250); | |
1899 | ||
1900 | /* 1.3 is pathetic, so fuzz up a bit */ | |
1901 | return t[9] * 10000 + 5001; | |
1902 | } | |
1903 | ||
b17e52ef | 1904 | static bool |
b1f559ec | 1905 | mode_in_range(const struct drm_display_mode *mode, struct edid *edid, |
b17e52ef AJ |
1906 | struct detailed_timing *timing) |
1907 | { | |
1908 | u32 max_clock; | |
1909 | u8 *t = (u8 *)timing; | |
1910 | ||
1911 | if (!mode_in_hsync_range(mode, edid, t)) | |
07a5e632 AJ |
1912 | return false; |
1913 | ||
b17e52ef | 1914 | if (!mode_in_vsync_range(mode, edid, t)) |
07a5e632 AJ |
1915 | return false; |
1916 | ||
b17e52ef | 1917 | if ((max_clock = range_pixel_clock(edid, t))) |
07a5e632 AJ |
1918 | if (mode->clock > max_clock) |
1919 | return false; | |
b17e52ef AJ |
1920 | |
1921 | /* 1.4 max horizontal check */ | |
1922 | if (edid->revision >= 4 && t[10] == 0x04) | |
1923 | if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) | |
1924 | return false; | |
1925 | ||
1926 | if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) | |
1927 | return false; | |
07a5e632 AJ |
1928 | |
1929 | return true; | |
1930 | } | |
1931 | ||
7b668ebe TI |
1932 | static bool valid_inferred_mode(const struct drm_connector *connector, |
1933 | const struct drm_display_mode *mode) | |
1934 | { | |
1935 | struct drm_display_mode *m; | |
1936 | bool ok = false; | |
1937 | ||
1938 | list_for_each_entry(m, &connector->probed_modes, head) { | |
1939 | if (mode->hdisplay == m->hdisplay && | |
1940 | mode->vdisplay == m->vdisplay && | |
1941 | drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) | |
1942 | return false; /* duplicated */ | |
1943 | if (mode->hdisplay <= m->hdisplay && | |
1944 | mode->vdisplay <= m->vdisplay) | |
1945 | ok = true; | |
1946 | } | |
1947 | return ok; | |
1948 | } | |
1949 | ||
b17e52ef | 1950 | static int |
cd4cd3de | 1951 | drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, |
b17e52ef | 1952 | struct detailed_timing *timing) |
07a5e632 AJ |
1953 | { |
1954 | int i, modes = 0; | |
1955 | struct drm_display_mode *newmode; | |
1956 | struct drm_device *dev = connector->dev; | |
1957 | ||
a6b21831 | 1958 | for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { |
7b668ebe TI |
1959 | if (mode_in_range(drm_dmt_modes + i, edid, timing) && |
1960 | valid_inferred_mode(connector, drm_dmt_modes + i)) { | |
07a5e632 AJ |
1961 | newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); |
1962 | if (newmode) { | |
1963 | drm_mode_probed_add(connector, newmode); | |
1964 | modes++; | |
1965 | } | |
1966 | } | |
1967 | } | |
1968 | ||
1969 | return modes; | |
1970 | } | |
1971 | ||
c09dedb7 TI |
1972 | /* fix up 1366x768 mode from 1368x768; |
1973 | * GFT/CVT can't express 1366 width which isn't dividable by 8 | |
1974 | */ | |
1975 | static void fixup_mode_1366x768(struct drm_display_mode *mode) | |
1976 | { | |
1977 | if (mode->hdisplay == 1368 && mode->vdisplay == 768) { | |
1978 | mode->hdisplay = 1366; | |
1979 | mode->hsync_start--; | |
1980 | mode->hsync_end--; | |
1981 | drm_mode_set_name(mode); | |
1982 | } | |
1983 | } | |
1984 | ||
b309bd37 AJ |
1985 | static int |
1986 | drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, | |
1987 | struct detailed_timing *timing) | |
1988 | { | |
1989 | int i, modes = 0; | |
1990 | struct drm_display_mode *newmode; | |
1991 | struct drm_device *dev = connector->dev; | |
1992 | ||
a6b21831 | 1993 | for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { |
b309bd37 AJ |
1994 | const struct minimode *m = &extra_modes[i]; |
1995 | newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); | |
fc48f169 TI |
1996 | if (!newmode) |
1997 | return modes; | |
b309bd37 | 1998 | |
c09dedb7 | 1999 | fixup_mode_1366x768(newmode); |
7b668ebe TI |
2000 | if (!mode_in_range(newmode, edid, timing) || |
2001 | !valid_inferred_mode(connector, newmode)) { | |
b309bd37 AJ |
2002 | drm_mode_destroy(dev, newmode); |
2003 | continue; | |
2004 | } | |
2005 | ||
2006 | drm_mode_probed_add(connector, newmode); | |
2007 | modes++; | |
2008 | } | |
2009 | ||
2010 | return modes; | |
2011 | } | |
2012 | ||
2013 | static int | |
2014 | drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, | |
2015 | struct detailed_timing *timing) | |
2016 | { | |
2017 | int i, modes = 0; | |
2018 | struct drm_display_mode *newmode; | |
2019 | struct drm_device *dev = connector->dev; | |
2020 | bool rb = drm_monitor_supports_rb(edid); | |
2021 | ||
a6b21831 | 2022 | for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { |
b309bd37 AJ |
2023 | const struct minimode *m = &extra_modes[i]; |
2024 | newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); | |
fc48f169 TI |
2025 | if (!newmode) |
2026 | return modes; | |
b309bd37 | 2027 | |
c09dedb7 | 2028 | fixup_mode_1366x768(newmode); |
7b668ebe TI |
2029 | if (!mode_in_range(newmode, edid, timing) || |
2030 | !valid_inferred_mode(connector, newmode)) { | |
b309bd37 AJ |
2031 | drm_mode_destroy(dev, newmode); |
2032 | continue; | |
2033 | } | |
2034 | ||
2035 | drm_mode_probed_add(connector, newmode); | |
2036 | modes++; | |
2037 | } | |
2038 | ||
2039 | return modes; | |
2040 | } | |
2041 | ||
13931579 AJ |
2042 | static void |
2043 | do_inferred_modes(struct detailed_timing *timing, void *c) | |
9340d8cf | 2044 | { |
13931579 AJ |
2045 | struct detailed_mode_closure *closure = c; |
2046 | struct detailed_non_pixel *data = &timing->data.other_data; | |
b309bd37 | 2047 | struct detailed_data_monitor_range *range = &data->data.range; |
9340d8cf | 2048 | |
cb21aafe AJ |
2049 | if (data->type != EDID_DETAIL_MONITOR_RANGE) |
2050 | return; | |
2051 | ||
2052 | closure->modes += drm_dmt_modes_for_range(closure->connector, | |
2053 | closure->edid, | |
2054 | timing); | |
b309bd37 AJ |
2055 | |
2056 | if (!version_greater(closure->edid, 1, 1)) | |
2057 | return; /* GTF not defined yet */ | |
2058 | ||
2059 | switch (range->flags) { | |
2060 | case 0x02: /* secondary gtf, XXX could do more */ | |
2061 | case 0x00: /* default gtf */ | |
2062 | closure->modes += drm_gtf_modes_for_range(closure->connector, | |
2063 | closure->edid, | |
2064 | timing); | |
2065 | break; | |
2066 | case 0x04: /* cvt, only in 1.4+ */ | |
2067 | if (!version_greater(closure->edid, 1, 3)) | |
2068 | break; | |
2069 | ||
2070 | closure->modes += drm_cvt_modes_for_range(closure->connector, | |
2071 | closure->edid, | |
2072 | timing); | |
2073 | break; | |
2074 | case 0x01: /* just the ranges, no formula */ | |
2075 | default: | |
2076 | break; | |
2077 | } | |
13931579 | 2078 | } |
69da3015 | 2079 | |
13931579 AJ |
2080 | static int |
2081 | add_inferred_modes(struct drm_connector *connector, struct edid *edid) | |
2082 | { | |
2083 | struct detailed_mode_closure closure = { | |
2084 | connector, edid, 0, 0, 0 | |
2085 | }; | |
9340d8cf | 2086 | |
13931579 AJ |
2087 | if (version_greater(edid, 1, 0)) |
2088 | drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, | |
2089 | &closure); | |
9340d8cf | 2090 | |
13931579 | 2091 | return closure.modes; |
9340d8cf AJ |
2092 | } |
2093 | ||
2255be14 AJ |
2094 | static int |
2095 | drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) | |
2096 | { | |
2097 | int i, j, m, modes = 0; | |
2098 | struct drm_display_mode *mode; | |
2099 | u8 *est = ((u8 *)timing) + 5; | |
2100 | ||
2101 | for (i = 0; i < 6; i++) { | |
891a7469 | 2102 | for (j = 7; j >= 0; j--) { |
2255be14 | 2103 | m = (i * 8) + (7 - j); |
3c581411 | 2104 | if (m >= ARRAY_SIZE(est3_modes)) |
2255be14 AJ |
2105 | break; |
2106 | if (est[i] & (1 << j)) { | |
1d42bbc8 DA |
2107 | mode = drm_mode_find_dmt(connector->dev, |
2108 | est3_modes[m].w, | |
2109 | est3_modes[m].h, | |
f6e252ba AJ |
2110 | est3_modes[m].r, |
2111 | est3_modes[m].rb); | |
2255be14 AJ |
2112 | if (mode) { |
2113 | drm_mode_probed_add(connector, mode); | |
2114 | modes++; | |
2115 | } | |
2116 | } | |
2117 | } | |
2118 | } | |
2119 | ||
2120 | return modes; | |
2121 | } | |
2122 | ||
13931579 AJ |
2123 | static void |
2124 | do_established_modes(struct detailed_timing *timing, void *c) | |
9cf00977 | 2125 | { |
13931579 | 2126 | struct detailed_mode_closure *closure = c; |
9cf00977 | 2127 | struct detailed_non_pixel *data = &timing->data.other_data; |
9cf00977 | 2128 | |
13931579 AJ |
2129 | if (data->type == EDID_DETAIL_EST_TIMINGS) |
2130 | closure->modes += drm_est3_modes(closure->connector, timing); | |
2131 | } | |
9cf00977 | 2132 | |
13931579 AJ |
2133 | /** |
2134 | * add_established_modes - get est. modes from EDID and add them | |
2135 | * @edid: EDID block to scan | |
2136 | * | |
2137 | * Each EDID block contains a bitmap of the supported "established modes" list | |
2138 | * (defined above). Tease them out and add them to the global modes list. | |
2139 | */ | |
2140 | static int | |
2141 | add_established_modes(struct drm_connector *connector, struct edid *edid) | |
2142 | { | |
2143 | struct drm_device *dev = connector->dev; | |
2144 | unsigned long est_bits = edid->established_timings.t1 | | |
2145 | (edid->established_timings.t2 << 8) | | |
2146 | ((edid->established_timings.mfg_rsvd & 0x80) << 9); | |
2147 | int i, modes = 0; | |
2148 | struct detailed_mode_closure closure = { | |
2149 | connector, edid, 0, 0, 0 | |
2150 | }; | |
9cf00977 | 2151 | |
13931579 AJ |
2152 | for (i = 0; i <= EDID_EST_TIMINGS; i++) { |
2153 | if (est_bits & (1<<i)) { | |
2154 | struct drm_display_mode *newmode; | |
2155 | newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); | |
2156 | if (newmode) { | |
2157 | drm_mode_probed_add(connector, newmode); | |
2158 | modes++; | |
2159 | } | |
2160 | } | |
9cf00977 AJ |
2161 | } |
2162 | ||
13931579 AJ |
2163 | if (version_greater(edid, 1, 0)) |
2164 | drm_for_each_detailed_block((u8 *)edid, | |
2165 | do_established_modes, &closure); | |
2166 | ||
2167 | return modes + closure.modes; | |
2168 | } | |
2169 | ||
2170 | static void | |
2171 | do_standard_modes(struct detailed_timing *timing, void *c) | |
2172 | { | |
2173 | struct detailed_mode_closure *closure = c; | |
2174 | struct detailed_non_pixel *data = &timing->data.other_data; | |
2175 | struct drm_connector *connector = closure->connector; | |
2176 | struct edid *edid = closure->edid; | |
2177 | ||
2178 | if (data->type == EDID_DETAIL_STD_MODES) { | |
2179 | int i; | |
9cf00977 AJ |
2180 | for (i = 0; i < 6; i++) { |
2181 | struct std_timing *std; | |
2182 | struct drm_display_mode *newmode; | |
2183 | ||
2184 | std = &data->data.timings[i]; | |
7a374350 AJ |
2185 | newmode = drm_mode_std(connector, edid, std, |
2186 | edid->revision); | |
9cf00977 AJ |
2187 | if (newmode) { |
2188 | drm_mode_probed_add(connector, newmode); | |
13931579 | 2189 | closure->modes++; |
9cf00977 AJ |
2190 | } |
2191 | } | |
9cf00977 | 2192 | } |
9cf00977 AJ |
2193 | } |
2194 | ||
f453ba04 | 2195 | /** |
13931579 | 2196 | * add_standard_modes - get std. modes from EDID and add them |
f453ba04 | 2197 | * @edid: EDID block to scan |
f453ba04 | 2198 | * |
13931579 AJ |
2199 | * Standard modes can be calculated using the appropriate standard (DMT, |
2200 | * GTF or CVT. Grab them from @edid and add them to the list. | |
f453ba04 | 2201 | */ |
13931579 AJ |
2202 | static int |
2203 | add_standard_modes(struct drm_connector *connector, struct edid *edid) | |
f453ba04 | 2204 | { |
9cf00977 | 2205 | int i, modes = 0; |
13931579 AJ |
2206 | struct detailed_mode_closure closure = { |
2207 | connector, edid, 0, 0, 0 | |
2208 | }; | |
2209 | ||
2210 | for (i = 0; i < EDID_STD_TIMINGS; i++) { | |
2211 | struct drm_display_mode *newmode; | |
2212 | ||
2213 | newmode = drm_mode_std(connector, edid, | |
2214 | &edid->standard_timings[i], | |
2215 | edid->revision); | |
2216 | if (newmode) { | |
2217 | drm_mode_probed_add(connector, newmode); | |
2218 | modes++; | |
2219 | } | |
2220 | } | |
2221 | ||
2222 | if (version_greater(edid, 1, 0)) | |
2223 | drm_for_each_detailed_block((u8 *)edid, do_standard_modes, | |
2224 | &closure); | |
2225 | ||
2226 | /* XXX should also look for standard codes in VTB blocks */ | |
2227 | ||
2228 | return modes + closure.modes; | |
2229 | } | |
f453ba04 | 2230 | |
13931579 AJ |
2231 | static int drm_cvt_modes(struct drm_connector *connector, |
2232 | struct detailed_timing *timing) | |
2233 | { | |
2234 | int i, j, modes = 0; | |
2235 | struct drm_display_mode *newmode; | |
2236 | struct drm_device *dev = connector->dev; | |
2237 | struct cvt_timing *cvt; | |
2238 | const int rates[] = { 60, 85, 75, 60, 50 }; | |
2239 | const u8 empty[3] = { 0, 0, 0 }; | |
a327f6b8 | 2240 | |
13931579 AJ |
2241 | for (i = 0; i < 4; i++) { |
2242 | int uninitialized_var(width), height; | |
2243 | cvt = &(timing->data.other_data.data.cvt[i]); | |
f453ba04 | 2244 | |
13931579 | 2245 | if (!memcmp(cvt->code, empty, 3)) |
9cf00977 | 2246 | continue; |
f453ba04 | 2247 | |
13931579 AJ |
2248 | height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; |
2249 | switch (cvt->code[1] & 0x0c) { | |
2250 | case 0x00: | |
2251 | width = height * 4 / 3; | |
2252 | break; | |
2253 | case 0x04: | |
2254 | width = height * 16 / 9; | |
2255 | break; | |
2256 | case 0x08: | |
2257 | width = height * 16 / 10; | |
2258 | break; | |
2259 | case 0x0c: | |
2260 | width = height * 15 / 9; | |
2261 | break; | |
2262 | } | |
2263 | ||
2264 | for (j = 1; j < 5; j++) { | |
2265 | if (cvt->code[2] & (1 << j)) { | |
2266 | newmode = drm_cvt_mode(dev, width, height, | |
2267 | rates[j], j == 0, | |
2268 | false, false); | |
2269 | if (newmode) { | |
2270 | drm_mode_probed_add(connector, newmode); | |
2271 | modes++; | |
2272 | } | |
2273 | } | |
2274 | } | |
f453ba04 DA |
2275 | } |
2276 | ||
2277 | return modes; | |
2278 | } | |
9cf00977 | 2279 | |
13931579 AJ |
2280 | static void |
2281 | do_cvt_mode(struct detailed_timing *timing, void *c) | |
882f0219 | 2282 | { |
13931579 AJ |
2283 | struct detailed_mode_closure *closure = c; |
2284 | struct detailed_non_pixel *data = &timing->data.other_data; | |
882f0219 | 2285 | |
13931579 AJ |
2286 | if (data->type == EDID_DETAIL_CVT_3BYTE) |
2287 | closure->modes += drm_cvt_modes(closure->connector, timing); | |
2288 | } | |
882f0219 | 2289 | |
13931579 AJ |
2290 | static int |
2291 | add_cvt_modes(struct drm_connector *connector, struct edid *edid) | |
2292 | { | |
2293 | struct detailed_mode_closure closure = { | |
2294 | connector, edid, 0, 0, 0 | |
2295 | }; | |
882f0219 | 2296 | |
13931579 AJ |
2297 | if (version_greater(edid, 1, 2)) |
2298 | drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); | |
882f0219 | 2299 | |
13931579 | 2300 | /* XXX should also look for CVT codes in VTB blocks */ |
882f0219 | 2301 | |
13931579 AJ |
2302 | return closure.modes; |
2303 | } | |
2304 | ||
2305 | static void | |
2306 | do_detailed_mode(struct detailed_timing *timing, void *c) | |
2307 | { | |
2308 | struct detailed_mode_closure *closure = c; | |
2309 | struct drm_display_mode *newmode; | |
2310 | ||
2311 | if (timing->pixel_clock) { | |
2312 | newmode = drm_mode_detailed(closure->connector->dev, | |
2313 | closure->edid, timing, | |
2314 | closure->quirks); | |
2315 | if (!newmode) | |
2316 | return; | |
2317 | ||
2318 | if (closure->preferred) | |
2319 | newmode->type |= DRM_MODE_TYPE_PREFERRED; | |
2320 | ||
2321 | drm_mode_probed_add(closure->connector, newmode); | |
2322 | closure->modes++; | |
2323 | closure->preferred = 0; | |
882f0219 | 2324 | } |
13931579 | 2325 | } |
882f0219 | 2326 | |
13931579 AJ |
2327 | /* |
2328 | * add_detailed_modes - Add modes from detailed timings | |
2329 | * @connector: attached connector | |
2330 | * @edid: EDID block to scan | |
2331 | * @quirks: quirks to apply | |
2332 | */ | |
2333 | static int | |
2334 | add_detailed_modes(struct drm_connector *connector, struct edid *edid, | |
2335 | u32 quirks) | |
2336 | { | |
2337 | struct detailed_mode_closure closure = { | |
2338 | connector, | |
2339 | edid, | |
2340 | 1, | |
2341 | quirks, | |
2342 | 0 | |
2343 | }; | |
2344 | ||
2345 | if (closure.preferred && !version_greater(edid, 1, 3)) | |
2346 | closure.preferred = | |
2347 | (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); | |
2348 | ||
2349 | drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); | |
2350 | ||
2351 | return closure.modes; | |
882f0219 | 2352 | } |
f453ba04 | 2353 | |
8fe9790d | 2354 | #define AUDIO_BLOCK 0x01 |
54ac76f8 | 2355 | #define VIDEO_BLOCK 0x02 |
f23c20c8 | 2356 | #define VENDOR_BLOCK 0x03 |
76adaa34 | 2357 | #define SPEAKER_BLOCK 0x04 |
b1edd6a6 | 2358 | #define VIDEO_CAPABILITY_BLOCK 0x07 |
8fe9790d | 2359 | #define EDID_BASIC_AUDIO (1 << 6) |
a988bc72 LPC |
2360 | #define EDID_CEA_YCRCB444 (1 << 5) |
2361 | #define EDID_CEA_YCRCB422 (1 << 4) | |
b1edd6a6 | 2362 | #define EDID_CEA_VCDB_QS (1 << 6) |
8fe9790d | 2363 | |
d4e4a31d | 2364 | /* |
8fe9790d | 2365 | * Search EDID for CEA extension block. |
f23c20c8 | 2366 | */ |
d4e4a31d | 2367 | static u8 *drm_find_cea_extension(struct edid *edid) |
f23c20c8 | 2368 | { |
8fe9790d ZW |
2369 | u8 *edid_ext = NULL; |
2370 | int i; | |
f23c20c8 ML |
2371 | |
2372 | /* No EDID or EDID extensions */ | |
2373 | if (edid == NULL || edid->extensions == 0) | |
8fe9790d | 2374 | return NULL; |
f23c20c8 | 2375 | |
f23c20c8 | 2376 | /* Find CEA extension */ |
7466f4cc | 2377 | for (i = 0; i < edid->extensions; i++) { |
8fe9790d ZW |
2378 | edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); |
2379 | if (edid_ext[0] == CEA_EXT) | |
f23c20c8 ML |
2380 | break; |
2381 | } | |
2382 | ||
7466f4cc | 2383 | if (i == edid->extensions) |
8fe9790d ZW |
2384 | return NULL; |
2385 | ||
2386 | return edid_ext; | |
2387 | } | |
2388 | ||
e6e79209 VS |
2389 | /* |
2390 | * Calculate the alternate clock for the CEA mode | |
2391 | * (60Hz vs. 59.94Hz etc.) | |
2392 | */ | |
2393 | static unsigned int | |
2394 | cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) | |
2395 | { | |
2396 | unsigned int clock = cea_mode->clock; | |
2397 | ||
2398 | if (cea_mode->vrefresh % 6 != 0) | |
2399 | return clock; | |
2400 | ||
2401 | /* | |
2402 | * edid_cea_modes contains the 59.94Hz | |
2403 | * variant for 240 and 480 line modes, | |
2404 | * and the 60Hz variant otherwise. | |
2405 | */ | |
2406 | if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) | |
2407 | clock = clock * 1001 / 1000; | |
2408 | else | |
2409 | clock = DIV_ROUND_UP(clock * 1000, 1001); | |
2410 | ||
2411 | return clock; | |
2412 | } | |
2413 | ||
18316c8c TR |
2414 | /** |
2415 | * drm_match_cea_mode - look for a CEA mode matching given mode | |
2416 | * @to_match: display mode | |
2417 | * | |
2418 | * Returns the CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 | |
2419 | * mode. | |
a4799037 | 2420 | */ |
18316c8c | 2421 | u8 drm_match_cea_mode(const struct drm_display_mode *to_match) |
a4799037 | 2422 | { |
a4799037 SM |
2423 | u8 mode; |
2424 | ||
a90b590e VS |
2425 | if (!to_match->clock) |
2426 | return 0; | |
2427 | ||
a6b21831 | 2428 | for (mode = 0; mode < ARRAY_SIZE(edid_cea_modes); mode++) { |
a90b590e VS |
2429 | const struct drm_display_mode *cea_mode = &edid_cea_modes[mode]; |
2430 | unsigned int clock1, clock2; | |
2431 | ||
a90b590e | 2432 | /* Check both 60Hz and 59.94Hz */ |
e6e79209 VS |
2433 | clock1 = cea_mode->clock; |
2434 | clock2 = cea_mode_alternate_clock(cea_mode); | |
a4799037 | 2435 | |
a90b590e VS |
2436 | if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || |
2437 | KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && | |
f2ecf2e3 | 2438 | drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode)) |
a4799037 SM |
2439 | return mode + 1; |
2440 | } | |
2441 | return 0; | |
2442 | } | |
2443 | EXPORT_SYMBOL(drm_match_cea_mode); | |
2444 | ||
3f2f6533 LD |
2445 | /* |
2446 | * Calculate the alternate clock for HDMI modes (those from the HDMI vendor | |
2447 | * specific block). | |
2448 | * | |
2449 | * It's almost like cea_mode_alternate_clock(), we just need to add an | |
2450 | * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this | |
2451 | * one. | |
2452 | */ | |
2453 | static unsigned int | |
2454 | hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) | |
2455 | { | |
2456 | if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) | |
2457 | return hdmi_mode->clock; | |
2458 | ||
2459 | return cea_mode_alternate_clock(hdmi_mode); | |
2460 | } | |
2461 | ||
2462 | /* | |
2463 | * drm_match_hdmi_mode - look for a HDMI mode matching given mode | |
2464 | * @to_match: display mode | |
2465 | * | |
2466 | * An HDMI mode is one defined in the HDMI vendor specific block. | |
2467 | * | |
2468 | * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. | |
2469 | */ | |
2470 | static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) | |
2471 | { | |
2472 | u8 mode; | |
2473 | ||
2474 | if (!to_match->clock) | |
2475 | return 0; | |
2476 | ||
2477 | for (mode = 0; mode < ARRAY_SIZE(edid_4k_modes); mode++) { | |
2478 | const struct drm_display_mode *hdmi_mode = &edid_4k_modes[mode]; | |
2479 | unsigned int clock1, clock2; | |
2480 | ||
2481 | /* Make sure to also match alternate clocks */ | |
2482 | clock1 = hdmi_mode->clock; | |
2483 | clock2 = hdmi_mode_alternate_clock(hdmi_mode); | |
2484 | ||
2485 | if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || | |
2486 | KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && | |
f2ecf2e3 | 2487 | drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode)) |
3f2f6533 LD |
2488 | return mode + 1; |
2489 | } | |
2490 | return 0; | |
2491 | } | |
2492 | ||
e6e79209 VS |
2493 | static int |
2494 | add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) | |
2495 | { | |
2496 | struct drm_device *dev = connector->dev; | |
2497 | struct drm_display_mode *mode, *tmp; | |
2498 | LIST_HEAD(list); | |
2499 | int modes = 0; | |
2500 | ||
2501 | /* Don't add CEA modes if the CEA extension block is missing */ | |
2502 | if (!drm_find_cea_extension(edid)) | |
2503 | return 0; | |
2504 | ||
2505 | /* | |
2506 | * Go through all probed modes and create a new mode | |
2507 | * with the alternate clock for certain CEA modes. | |
2508 | */ | |
2509 | list_for_each_entry(mode, &connector->probed_modes, head) { | |
3f2f6533 | 2510 | const struct drm_display_mode *cea_mode = NULL; |
e6e79209 | 2511 | struct drm_display_mode *newmode; |
3f2f6533 | 2512 | u8 mode_idx = drm_match_cea_mode(mode) - 1; |
e6e79209 VS |
2513 | unsigned int clock1, clock2; |
2514 | ||
3f2f6533 LD |
2515 | if (mode_idx < ARRAY_SIZE(edid_cea_modes)) { |
2516 | cea_mode = &edid_cea_modes[mode_idx]; | |
2517 | clock2 = cea_mode_alternate_clock(cea_mode); | |
2518 | } else { | |
2519 | mode_idx = drm_match_hdmi_mode(mode) - 1; | |
2520 | if (mode_idx < ARRAY_SIZE(edid_4k_modes)) { | |
2521 | cea_mode = &edid_4k_modes[mode_idx]; | |
2522 | clock2 = hdmi_mode_alternate_clock(cea_mode); | |
2523 | } | |
2524 | } | |
e6e79209 | 2525 | |
3f2f6533 LD |
2526 | if (!cea_mode) |
2527 | continue; | |
e6e79209 VS |
2528 | |
2529 | clock1 = cea_mode->clock; | |
e6e79209 VS |
2530 | |
2531 | if (clock1 == clock2) | |
2532 | continue; | |
2533 | ||
2534 | if (mode->clock != clock1 && mode->clock != clock2) | |
2535 | continue; | |
2536 | ||
2537 | newmode = drm_mode_duplicate(dev, cea_mode); | |
2538 | if (!newmode) | |
2539 | continue; | |
2540 | ||
27130212 DL |
2541 | /* Carry over the stereo flags */ |
2542 | newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; | |
2543 | ||
e6e79209 VS |
2544 | /* |
2545 | * The current mode could be either variant. Make | |
2546 | * sure to pick the "other" clock for the new mode. | |
2547 | */ | |
2548 | if (mode->clock != clock1) | |
2549 | newmode->clock = clock1; | |
2550 | else | |
2551 | newmode->clock = clock2; | |
2552 | ||
2553 | list_add_tail(&newmode->head, &list); | |
2554 | } | |
2555 | ||
2556 | list_for_each_entry_safe(mode, tmp, &list, head) { | |
2557 | list_del(&mode->head); | |
2558 | drm_mode_probed_add(connector, mode); | |
2559 | modes++; | |
2560 | } | |
2561 | ||
2562 | return modes; | |
2563 | } | |
a4799037 | 2564 | |
aff04ace TW |
2565 | static struct drm_display_mode * |
2566 | drm_display_mode_from_vic_index(struct drm_connector *connector, | |
2567 | const u8 *video_db, u8 video_len, | |
2568 | u8 video_index) | |
54ac76f8 CS |
2569 | { |
2570 | struct drm_device *dev = connector->dev; | |
aff04ace | 2571 | struct drm_display_mode *newmode; |
13ac3f55 | 2572 | u8 cea_mode; |
54ac76f8 | 2573 | |
aff04ace TW |
2574 | if (video_db == NULL || video_index >= video_len) |
2575 | return NULL; | |
2576 | ||
2577 | /* CEA modes are numbered 1..127 */ | |
2578 | cea_mode = (video_db[video_index] & 127) - 1; | |
2579 | if (cea_mode >= ARRAY_SIZE(edid_cea_modes)) | |
2580 | return NULL; | |
2581 | ||
2582 | newmode = drm_mode_duplicate(dev, &edid_cea_modes[cea_mode]); | |
2583 | newmode->vrefresh = 0; | |
2584 | ||
2585 | return newmode; | |
2586 | } | |
2587 | ||
2588 | static int | |
2589 | do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) | |
2590 | { | |
2591 | int i, modes = 0; | |
2592 | ||
2593 | for (i = 0; i < len; i++) { | |
2594 | struct drm_display_mode *mode; | |
2595 | mode = drm_display_mode_from_vic_index(connector, db, len, i); | |
2596 | if (mode) { | |
2597 | drm_mode_probed_add(connector, mode); | |
2598 | modes++; | |
54ac76f8 CS |
2599 | } |
2600 | } | |
2601 | ||
2602 | return modes; | |
2603 | } | |
2604 | ||
c858cfca DL |
2605 | struct stereo_mandatory_mode { |
2606 | int width, height, vrefresh; | |
2607 | unsigned int flags; | |
2608 | }; | |
2609 | ||
2610 | static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { | |
f7e121b7 DL |
2611 | { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, |
2612 | { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, | |
c858cfca DL |
2613 | { 1920, 1080, 50, |
2614 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, | |
2615 | { 1920, 1080, 60, | |
2616 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, | |
f7e121b7 DL |
2617 | { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, |
2618 | { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, | |
2619 | { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, | |
2620 | { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } | |
c858cfca DL |
2621 | }; |
2622 | ||
2623 | static bool | |
2624 | stereo_match_mandatory(const struct drm_display_mode *mode, | |
2625 | const struct stereo_mandatory_mode *stereo_mode) | |
2626 | { | |
2627 | unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; | |
2628 | ||
2629 | return mode->hdisplay == stereo_mode->width && | |
2630 | mode->vdisplay == stereo_mode->height && | |
2631 | interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && | |
2632 | drm_mode_vrefresh(mode) == stereo_mode->vrefresh; | |
2633 | } | |
2634 | ||
c858cfca DL |
2635 | static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) |
2636 | { | |
2637 | struct drm_device *dev = connector->dev; | |
2638 | const struct drm_display_mode *mode; | |
2639 | struct list_head stereo_modes; | |
f7e121b7 | 2640 | int modes = 0, i; |
c858cfca DL |
2641 | |
2642 | INIT_LIST_HEAD(&stereo_modes); | |
2643 | ||
2644 | list_for_each_entry(mode, &connector->probed_modes, head) { | |
f7e121b7 DL |
2645 | for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { |
2646 | const struct stereo_mandatory_mode *mandatory; | |
c858cfca DL |
2647 | struct drm_display_mode *new_mode; |
2648 | ||
f7e121b7 DL |
2649 | if (!stereo_match_mandatory(mode, |
2650 | &stereo_mandatory_modes[i])) | |
2651 | continue; | |
c858cfca | 2652 | |
f7e121b7 | 2653 | mandatory = &stereo_mandatory_modes[i]; |
c858cfca DL |
2654 | new_mode = drm_mode_duplicate(dev, mode); |
2655 | if (!new_mode) | |
2656 | continue; | |
2657 | ||
f7e121b7 | 2658 | new_mode->flags |= mandatory->flags; |
c858cfca DL |
2659 | list_add_tail(&new_mode->head, &stereo_modes); |
2660 | modes++; | |
f7e121b7 | 2661 | } |
c858cfca DL |
2662 | } |
2663 | ||
2664 | list_splice_tail(&stereo_modes, &connector->probed_modes); | |
2665 | ||
2666 | return modes; | |
2667 | } | |
2668 | ||
1deee8d7 DL |
2669 | static int add_hdmi_mode(struct drm_connector *connector, u8 vic) |
2670 | { | |
2671 | struct drm_device *dev = connector->dev; | |
2672 | struct drm_display_mode *newmode; | |
2673 | ||
2674 | vic--; /* VICs start at 1 */ | |
2675 | if (vic >= ARRAY_SIZE(edid_4k_modes)) { | |
2676 | DRM_ERROR("Unknown HDMI VIC: %d\n", vic); | |
2677 | return 0; | |
2678 | } | |
2679 | ||
2680 | newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); | |
2681 | if (!newmode) | |
2682 | return 0; | |
2683 | ||
2684 | drm_mode_probed_add(connector, newmode); | |
2685 | ||
2686 | return 1; | |
2687 | } | |
2688 | ||
fbf46025 TW |
2689 | static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, |
2690 | const u8 *video_db, u8 video_len, u8 video_index) | |
2691 | { | |
fbf46025 TW |
2692 | struct drm_display_mode *newmode; |
2693 | int modes = 0; | |
fbf46025 TW |
2694 | |
2695 | if (structure & (1 << 0)) { | |
aff04ace TW |
2696 | newmode = drm_display_mode_from_vic_index(connector, video_db, |
2697 | video_len, | |
2698 | video_index); | |
fbf46025 TW |
2699 | if (newmode) { |
2700 | newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; | |
2701 | drm_mode_probed_add(connector, newmode); | |
2702 | modes++; | |
2703 | } | |
2704 | } | |
2705 | if (structure & (1 << 6)) { | |
aff04ace TW |
2706 | newmode = drm_display_mode_from_vic_index(connector, video_db, |
2707 | video_len, | |
2708 | video_index); | |
fbf46025 TW |
2709 | if (newmode) { |
2710 | newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; | |
2711 | drm_mode_probed_add(connector, newmode); | |
2712 | modes++; | |
2713 | } | |
2714 | } | |
2715 | if (structure & (1 << 8)) { | |
aff04ace TW |
2716 | newmode = drm_display_mode_from_vic_index(connector, video_db, |
2717 | video_len, | |
2718 | video_index); | |
fbf46025 | 2719 | if (newmode) { |
89570eeb | 2720 | newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; |
fbf46025 TW |
2721 | drm_mode_probed_add(connector, newmode); |
2722 | modes++; | |
2723 | } | |
2724 | } | |
2725 | ||
2726 | return modes; | |
2727 | } | |
2728 | ||
7ebe1963 LD |
2729 | /* |
2730 | * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block | |
2731 | * @connector: connector corresponding to the HDMI sink | |
2732 | * @db: start of the CEA vendor specific block | |
2733 | * @len: length of the CEA block payload, ie. one can access up to db[len] | |
2734 | * | |
c858cfca DL |
2735 | * Parses the HDMI VSDB looking for modes to add to @connector. This function |
2736 | * also adds the stereo 3d modes when applicable. | |
7ebe1963 LD |
2737 | */ |
2738 | static int | |
fbf46025 TW |
2739 | do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, |
2740 | const u8 *video_db, u8 video_len) | |
7ebe1963 | 2741 | { |
fbf46025 TW |
2742 | int modes = 0, offset = 0, i, multi_present = 0; |
2743 | u8 vic_len, hdmi_3d_len = 0; | |
2744 | u16 mask; | |
2745 | u16 structure_all; | |
7ebe1963 LD |
2746 | |
2747 | if (len < 8) | |
2748 | goto out; | |
2749 | ||
2750 | /* no HDMI_Video_Present */ | |
2751 | if (!(db[8] & (1 << 5))) | |
2752 | goto out; | |
2753 | ||
2754 | /* Latency_Fields_Present */ | |
2755 | if (db[8] & (1 << 7)) | |
2756 | offset += 2; | |
2757 | ||
2758 | /* I_Latency_Fields_Present */ | |
2759 | if (db[8] & (1 << 6)) | |
2760 | offset += 2; | |
2761 | ||
2762 | /* the declared length is not long enough for the 2 first bytes | |
2763 | * of additional video format capabilities */ | |
c858cfca | 2764 | if (len < (8 + offset + 2)) |
7ebe1963 LD |
2765 | goto out; |
2766 | ||
c858cfca DL |
2767 | /* 3D_Present */ |
2768 | offset++; | |
fbf46025 | 2769 | if (db[8 + offset] & (1 << 7)) { |
c858cfca DL |
2770 | modes += add_hdmi_mandatory_stereo_modes(connector); |
2771 | ||
fbf46025 TW |
2772 | /* 3D_Multi_present */ |
2773 | multi_present = (db[8 + offset] & 0x60) >> 5; | |
2774 | } | |
2775 | ||
c858cfca | 2776 | offset++; |
7ebe1963 | 2777 | vic_len = db[8 + offset] >> 5; |
fbf46025 | 2778 | hdmi_3d_len = db[8 + offset] & 0x1f; |
7ebe1963 LD |
2779 | |
2780 | for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { | |
7ebe1963 LD |
2781 | u8 vic; |
2782 | ||
2783 | vic = db[9 + offset + i]; | |
1deee8d7 | 2784 | modes += add_hdmi_mode(connector, vic); |
7ebe1963 | 2785 | } |
fbf46025 TW |
2786 | offset += 1 + vic_len; |
2787 | ||
2788 | if (!(multi_present == 1 || multi_present == 2)) | |
2789 | goto out; | |
2790 | ||
2791 | if ((multi_present == 1 && len < (9 + offset)) || | |
2792 | (multi_present == 2 && len < (11 + offset))) | |
2793 | goto out; | |
2794 | ||
2795 | if ((multi_present == 1 && hdmi_3d_len < 2) || | |
2796 | (multi_present == 2 && hdmi_3d_len < 4)) | |
2797 | goto out; | |
2798 | ||
2799 | /* 3D_Structure_ALL */ | |
2800 | structure_all = (db[8 + offset] << 8) | db[9 + offset]; | |
2801 | ||
2802 | /* check if 3D_MASK is present */ | |
2803 | if (multi_present == 2) | |
2804 | mask = (db[10 + offset] << 8) | db[11 + offset]; | |
2805 | else | |
2806 | mask = 0xffff; | |
2807 | ||
2808 | for (i = 0; i < 16; i++) { | |
2809 | if (mask & (1 << i)) | |
2810 | modes += add_3d_struct_modes(connector, | |
2811 | structure_all, | |
2812 | video_db, | |
2813 | video_len, i); | |
2814 | } | |
7ebe1963 LD |
2815 | |
2816 | out: | |
2817 | return modes; | |
2818 | } | |
2819 | ||
9e50b9d5 VS |
2820 | static int |
2821 | cea_db_payload_len(const u8 *db) | |
2822 | { | |
2823 | return db[0] & 0x1f; | |
2824 | } | |
2825 | ||
2826 | static int | |
2827 | cea_db_tag(const u8 *db) | |
2828 | { | |
2829 | return db[0] >> 5; | |
2830 | } | |
2831 | ||
2832 | static int | |
2833 | cea_revision(const u8 *cea) | |
2834 | { | |
2835 | return cea[1]; | |
2836 | } | |
2837 | ||
2838 | static int | |
2839 | cea_db_offsets(const u8 *cea, int *start, int *end) | |
2840 | { | |
2841 | /* Data block offset in CEA extension block */ | |
2842 | *start = 4; | |
2843 | *end = cea[2]; | |
2844 | if (*end == 0) | |
2845 | *end = 127; | |
2846 | if (*end < 4 || *end > 127) | |
2847 | return -ERANGE; | |
2848 | return 0; | |
2849 | } | |
2850 | ||
7ebe1963 LD |
2851 | static bool cea_db_is_hdmi_vsdb(const u8 *db) |
2852 | { | |
2853 | int hdmi_id; | |
2854 | ||
2855 | if (cea_db_tag(db) != VENDOR_BLOCK) | |
2856 | return false; | |
2857 | ||
2858 | if (cea_db_payload_len(db) < 5) | |
2859 | return false; | |
2860 | ||
2861 | hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); | |
2862 | ||
6cb3b7f1 | 2863 | return hdmi_id == HDMI_IEEE_OUI; |
7ebe1963 LD |
2864 | } |
2865 | ||
9e50b9d5 VS |
2866 | #define for_each_cea_db(cea, i, start, end) \ |
2867 | for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) | |
2868 | ||
54ac76f8 CS |
2869 | static int |
2870 | add_cea_modes(struct drm_connector *connector, struct edid *edid) | |
2871 | { | |
13ac3f55 | 2872 | const u8 *cea = drm_find_cea_extension(edid); |
fbf46025 TW |
2873 | const u8 *db, *hdmi = NULL, *video = NULL; |
2874 | u8 dbl, hdmi_len, video_len = 0; | |
54ac76f8 CS |
2875 | int modes = 0; |
2876 | ||
9e50b9d5 VS |
2877 | if (cea && cea_revision(cea) >= 3) { |
2878 | int i, start, end; | |
2879 | ||
2880 | if (cea_db_offsets(cea, &start, &end)) | |
2881 | return 0; | |
2882 | ||
2883 | for_each_cea_db(cea, i, start, end) { | |
2884 | db = &cea[i]; | |
2885 | dbl = cea_db_payload_len(db); | |
2886 | ||
fbf46025 TW |
2887 | if (cea_db_tag(db) == VIDEO_BLOCK) { |
2888 | video = db + 1; | |
2889 | video_len = dbl; | |
2890 | modes += do_cea_modes(connector, video, dbl); | |
2891 | } | |
c858cfca DL |
2892 | else if (cea_db_is_hdmi_vsdb(db)) { |
2893 | hdmi = db; | |
2894 | hdmi_len = dbl; | |
2895 | } | |
54ac76f8 CS |
2896 | } |
2897 | } | |
2898 | ||
c858cfca DL |
2899 | /* |
2900 | * We parse the HDMI VSDB after having added the cea modes as we will | |
2901 | * be patching their flags when the sink supports stereo 3D. | |
2902 | */ | |
2903 | if (hdmi) | |
fbf46025 TW |
2904 | modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, |
2905 | video_len); | |
c858cfca | 2906 | |
54ac76f8 CS |
2907 | return modes; |
2908 | } | |
2909 | ||
76adaa34 | 2910 | static void |
8504072a | 2911 | parse_hdmi_vsdb(struct drm_connector *connector, const u8 *db) |
76adaa34 | 2912 | { |
8504072a | 2913 | u8 len = cea_db_payload_len(db); |
76adaa34 | 2914 | |
8504072a VS |
2915 | if (len >= 6) { |
2916 | connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */ | |
2917 | connector->dvi_dual = db[6] & 1; | |
2918 | } | |
2919 | if (len >= 7) | |
2920 | connector->max_tmds_clock = db[7] * 5; | |
2921 | if (len >= 8) { | |
2922 | connector->latency_present[0] = db[8] >> 7; | |
2923 | connector->latency_present[1] = (db[8] >> 6) & 1; | |
2924 | } | |
2925 | if (len >= 9) | |
2926 | connector->video_latency[0] = db[9]; | |
2927 | if (len >= 10) | |
2928 | connector->audio_latency[0] = db[10]; | |
2929 | if (len >= 11) | |
2930 | connector->video_latency[1] = db[11]; | |
2931 | if (len >= 12) | |
2932 | connector->audio_latency[1] = db[12]; | |
76adaa34 | 2933 | |
670c1ef6 | 2934 | DRM_DEBUG_KMS("HDMI: DVI dual %d, " |
76adaa34 WF |
2935 | "max TMDS clock %d, " |
2936 | "latency present %d %d, " | |
2937 | "video latency %d %d, " | |
2938 | "audio latency %d %d\n", | |
2939 | connector->dvi_dual, | |
2940 | connector->max_tmds_clock, | |
2941 | (int) connector->latency_present[0], | |
2942 | (int) connector->latency_present[1], | |
2943 | connector->video_latency[0], | |
2944 | connector->video_latency[1], | |
2945 | connector->audio_latency[0], | |
2946 | connector->audio_latency[1]); | |
2947 | } | |
2948 | ||
2949 | static void | |
2950 | monitor_name(struct detailed_timing *t, void *data) | |
2951 | { | |
2952 | if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME) | |
2953 | *(u8 **)data = t->data.other_data.data.str.str; | |
14f77fdd VS |
2954 | } |
2955 | ||
76adaa34 WF |
2956 | /** |
2957 | * drm_edid_to_eld - build ELD from EDID | |
2958 | * @connector: connector corresponding to the HDMI/DP sink | |
2959 | * @edid: EDID to parse | |
2960 | * | |
2961 | * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. | |
2962 | * Some ELD fields are left to the graphics driver caller: | |
2963 | * - Conn_Type | |
2964 | * - HDCP | |
2965 | * - Port_ID | |
2966 | */ | |
2967 | void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) | |
2968 | { | |
2969 | uint8_t *eld = connector->eld; | |
2970 | u8 *cea; | |
2971 | u8 *name; | |
2972 | u8 *db; | |
2973 | int sad_count = 0; | |
2974 | int mnl; | |
2975 | int dbl; | |
2976 | ||
2977 | memset(eld, 0, sizeof(connector->eld)); | |
2978 | ||
2979 | cea = drm_find_cea_extension(edid); | |
2980 | if (!cea) { | |
2981 | DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); | |
2982 | return; | |
2983 | } | |
2984 | ||
2985 | name = NULL; | |
2986 | drm_for_each_detailed_block((u8 *)edid, monitor_name, &name); | |
2987 | for (mnl = 0; name && mnl < 13; mnl++) { | |
2988 | if (name[mnl] == 0x0a) | |
2989 | break; | |
2990 | eld[20 + mnl] = name[mnl]; | |
2991 | } | |
2992 | eld[4] = (cea[1] << 5) | mnl; | |
2993 | DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20); | |
2994 | ||
2995 | eld[0] = 2 << 3; /* ELD version: 2 */ | |
2996 | ||
2997 | eld[16] = edid->mfg_id[0]; | |
2998 | eld[17] = edid->mfg_id[1]; | |
2999 | eld[18] = edid->prod_code[0]; | |
3000 | eld[19] = edid->prod_code[1]; | |
3001 | ||
9e50b9d5 VS |
3002 | if (cea_revision(cea) >= 3) { |
3003 | int i, start, end; | |
3004 | ||
3005 | if (cea_db_offsets(cea, &start, &end)) { | |
3006 | start = 0; | |
3007 | end = 0; | |
3008 | } | |
3009 | ||
3010 | for_each_cea_db(cea, i, start, end) { | |
3011 | db = &cea[i]; | |
3012 | dbl = cea_db_payload_len(db); | |
3013 | ||
3014 | switch (cea_db_tag(db)) { | |
a0ab734d CS |
3015 | case AUDIO_BLOCK: |
3016 | /* Audio Data Block, contains SADs */ | |
3017 | sad_count = dbl / 3; | |
9e50b9d5 VS |
3018 | if (dbl >= 1) |
3019 | memcpy(eld + 20 + mnl, &db[1], dbl); | |
a0ab734d CS |
3020 | break; |
3021 | case SPEAKER_BLOCK: | |
9e50b9d5 VS |
3022 | /* Speaker Allocation Data Block */ |
3023 | if (dbl >= 1) | |
3024 | eld[7] = db[1]; | |
a0ab734d CS |
3025 | break; |
3026 | case VENDOR_BLOCK: | |
3027 | /* HDMI Vendor-Specific Data Block */ | |
14f77fdd | 3028 | if (cea_db_is_hdmi_vsdb(db)) |
a0ab734d CS |
3029 | parse_hdmi_vsdb(connector, db); |
3030 | break; | |
3031 | default: | |
3032 | break; | |
3033 | } | |
76adaa34 | 3034 | } |
9e50b9d5 | 3035 | } |
76adaa34 WF |
3036 | eld[5] |= sad_count << 4; |
3037 | eld[2] = (20 + mnl + sad_count * 3 + 3) / 4; | |
3038 | ||
3039 | DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", (int)eld[2], sad_count); | |
3040 | } | |
3041 | EXPORT_SYMBOL(drm_edid_to_eld); | |
3042 | ||
fe214163 RM |
3043 | /** |
3044 | * drm_edid_to_sad - extracts SADs from EDID | |
3045 | * @edid: EDID to parse | |
3046 | * @sads: pointer that will be set to the extracted SADs | |
3047 | * | |
3048 | * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. | |
3049 | * Note: returned pointer needs to be kfreed | |
3050 | * | |
3051 | * Return number of found SADs or negative number on error. | |
3052 | */ | |
3053 | int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) | |
3054 | { | |
3055 | int count = 0; | |
3056 | int i, start, end, dbl; | |
3057 | u8 *cea; | |
3058 | ||
3059 | cea = drm_find_cea_extension(edid); | |
3060 | if (!cea) { | |
3061 | DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); | |
3062 | return -ENOENT; | |
3063 | } | |
3064 | ||
3065 | if (cea_revision(cea) < 3) { | |
3066 | DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); | |
3067 | return -ENOTSUPP; | |
3068 | } | |
3069 | ||
3070 | if (cea_db_offsets(cea, &start, &end)) { | |
3071 | DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); | |
3072 | return -EPROTO; | |
3073 | } | |
3074 | ||
3075 | for_each_cea_db(cea, i, start, end) { | |
3076 | u8 *db = &cea[i]; | |
3077 | ||
3078 | if (cea_db_tag(db) == AUDIO_BLOCK) { | |
3079 | int j; | |
3080 | dbl = cea_db_payload_len(db); | |
3081 | ||
3082 | count = dbl / 3; /* SAD is 3B */ | |
3083 | *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); | |
3084 | if (!*sads) | |
3085 | return -ENOMEM; | |
3086 | for (j = 0; j < count; j++) { | |
3087 | u8 *sad = &db[1 + j * 3]; | |
3088 | ||
3089 | (*sads)[j].format = (sad[0] & 0x78) >> 3; | |
3090 | (*sads)[j].channels = sad[0] & 0x7; | |
3091 | (*sads)[j].freq = sad[1] & 0x7F; | |
3092 | (*sads)[j].byte2 = sad[2]; | |
3093 | } | |
3094 | break; | |
3095 | } | |
3096 | } | |
3097 | ||
3098 | return count; | |
3099 | } | |
3100 | EXPORT_SYMBOL(drm_edid_to_sad); | |
3101 | ||
d105f476 AD |
3102 | /** |
3103 | * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID | |
3104 | * @edid: EDID to parse | |
3105 | * @sadb: pointer to the speaker block | |
3106 | * | |
3107 | * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. | |
3108 | * Note: returned pointer needs to be kfreed | |
3109 | * | |
3110 | * Return number of found Speaker Allocation Blocks or negative number on error. | |
3111 | */ | |
3112 | int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) | |
3113 | { | |
3114 | int count = 0; | |
3115 | int i, start, end, dbl; | |
3116 | const u8 *cea; | |
3117 | ||
3118 | cea = drm_find_cea_extension(edid); | |
3119 | if (!cea) { | |
3120 | DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); | |
3121 | return -ENOENT; | |
3122 | } | |
3123 | ||
3124 | if (cea_revision(cea) < 3) { | |
3125 | DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); | |
3126 | return -ENOTSUPP; | |
3127 | } | |
3128 | ||
3129 | if (cea_db_offsets(cea, &start, &end)) { | |
3130 | DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); | |
3131 | return -EPROTO; | |
3132 | } | |
3133 | ||
3134 | for_each_cea_db(cea, i, start, end) { | |
3135 | const u8 *db = &cea[i]; | |
3136 | ||
3137 | if (cea_db_tag(db) == SPEAKER_BLOCK) { | |
3138 | dbl = cea_db_payload_len(db); | |
3139 | ||
3140 | /* Speaker Allocation Data Block */ | |
3141 | if (dbl == 3) { | |
3142 | *sadb = kmalloc(dbl, GFP_KERNEL); | |
618e3776 AD |
3143 | if (!*sadb) |
3144 | return -ENOMEM; | |
d105f476 AD |
3145 | memcpy(*sadb, &db[1], dbl); |
3146 | count = dbl; | |
3147 | break; | |
3148 | } | |
3149 | } | |
3150 | } | |
3151 | ||
3152 | return count; | |
3153 | } | |
3154 | EXPORT_SYMBOL(drm_edid_to_speaker_allocation); | |
3155 | ||
76adaa34 WF |
3156 | /** |
3157 | * drm_av_sync_delay - HDMI/DP sink audio-video sync delay in millisecond | |
3158 | * @connector: connector associated with the HDMI/DP sink | |
3159 | * @mode: the display mode | |
3160 | */ | |
3161 | int drm_av_sync_delay(struct drm_connector *connector, | |
3162 | struct drm_display_mode *mode) | |
3163 | { | |
3164 | int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); | |
3165 | int a, v; | |
3166 | ||
3167 | if (!connector->latency_present[0]) | |
3168 | return 0; | |
3169 | if (!connector->latency_present[1]) | |
3170 | i = 0; | |
3171 | ||
3172 | a = connector->audio_latency[i]; | |
3173 | v = connector->video_latency[i]; | |
3174 | ||
3175 | /* | |
3176 | * HDMI/DP sink doesn't support audio or video? | |
3177 | */ | |
3178 | if (a == 255 || v == 255) | |
3179 | return 0; | |
3180 | ||
3181 | /* | |
3182 | * Convert raw EDID values to millisecond. | |
3183 | * Treat unknown latency as 0ms. | |
3184 | */ | |
3185 | if (a) | |
3186 | a = min(2 * (a - 1), 500); | |
3187 | if (v) | |
3188 | v = min(2 * (v - 1), 500); | |
3189 | ||
3190 | return max(v - a, 0); | |
3191 | } | |
3192 | EXPORT_SYMBOL(drm_av_sync_delay); | |
3193 | ||
3194 | /** | |
3195 | * drm_select_eld - select one ELD from multiple HDMI/DP sinks | |
3196 | * @encoder: the encoder just changed display mode | |
3197 | * @mode: the adjusted display mode | |
3198 | * | |
3199 | * It's possible for one encoder to be associated with multiple HDMI/DP sinks. | |
3200 | * The policy is now hard coded to simply use the first HDMI/DP sink's ELD. | |
3201 | */ | |
3202 | struct drm_connector *drm_select_eld(struct drm_encoder *encoder, | |
3203 | struct drm_display_mode *mode) | |
3204 | { | |
3205 | struct drm_connector *connector; | |
3206 | struct drm_device *dev = encoder->dev; | |
3207 | ||
3208 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) | |
3209 | if (connector->encoder == encoder && connector->eld[0]) | |
3210 | return connector; | |
3211 | ||
3212 | return NULL; | |
3213 | } | |
3214 | EXPORT_SYMBOL(drm_select_eld); | |
3215 | ||
8fe9790d ZW |
3216 | /** |
3217 | * drm_detect_hdmi_monitor - detect whether monitor is hdmi. | |
3218 | * @edid: monitor EDID information | |
3219 | * | |
3220 | * Parse the CEA extension according to CEA-861-B. | |
3221 | * Return true if HDMI, false if not or unknown. | |
3222 | */ | |
3223 | bool drm_detect_hdmi_monitor(struct edid *edid) | |
3224 | { | |
3225 | u8 *edid_ext; | |
14f77fdd | 3226 | int i; |
8fe9790d | 3227 | int start_offset, end_offset; |
8fe9790d ZW |
3228 | |
3229 | edid_ext = drm_find_cea_extension(edid); | |
3230 | if (!edid_ext) | |
14f77fdd | 3231 | return false; |
f23c20c8 | 3232 | |
9e50b9d5 | 3233 | if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) |
14f77fdd | 3234 | return false; |
f23c20c8 ML |
3235 | |
3236 | /* | |
3237 | * Because HDMI identifier is in Vendor Specific Block, | |
3238 | * search it from all data blocks of CEA extension. | |
3239 | */ | |
9e50b9d5 | 3240 | for_each_cea_db(edid_ext, i, start_offset, end_offset) { |
14f77fdd VS |
3241 | if (cea_db_is_hdmi_vsdb(&edid_ext[i])) |
3242 | return true; | |
f23c20c8 ML |
3243 | } |
3244 | ||
14f77fdd | 3245 | return false; |
f23c20c8 ML |
3246 | } |
3247 | EXPORT_SYMBOL(drm_detect_hdmi_monitor); | |
3248 | ||
8fe9790d ZW |
3249 | /** |
3250 | * drm_detect_monitor_audio - check monitor audio capability | |
3251 | * | |
3252 | * Monitor should have CEA extension block. | |
3253 | * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic | |
3254 | * audio' only. If there is any audio extension block and supported | |
3255 | * audio format, assume at least 'basic audio' support, even if 'basic | |
3256 | * audio' is not defined in EDID. | |
3257 | * | |
3258 | */ | |
3259 | bool drm_detect_monitor_audio(struct edid *edid) | |
3260 | { | |
3261 | u8 *edid_ext; | |
3262 | int i, j; | |
3263 | bool has_audio = false; | |
3264 | int start_offset, end_offset; | |
3265 | ||
3266 | edid_ext = drm_find_cea_extension(edid); | |
3267 | if (!edid_ext) | |
3268 | goto end; | |
3269 | ||
3270 | has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); | |
3271 | ||
3272 | if (has_audio) { | |
3273 | DRM_DEBUG_KMS("Monitor has basic audio support\n"); | |
3274 | goto end; | |
3275 | } | |
3276 | ||
9e50b9d5 VS |
3277 | if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) |
3278 | goto end; | |
8fe9790d | 3279 | |
9e50b9d5 VS |
3280 | for_each_cea_db(edid_ext, i, start_offset, end_offset) { |
3281 | if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { | |
8fe9790d | 3282 | has_audio = true; |
9e50b9d5 | 3283 | for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) |
8fe9790d ZW |
3284 | DRM_DEBUG_KMS("CEA audio format %d\n", |
3285 | (edid_ext[i + j] >> 3) & 0xf); | |
3286 | goto end; | |
3287 | } | |
3288 | } | |
3289 | end: | |
3290 | return has_audio; | |
3291 | } | |
3292 | EXPORT_SYMBOL(drm_detect_monitor_audio); | |
3293 | ||
b1edd6a6 VS |
3294 | /** |
3295 | * drm_rgb_quant_range_selectable - is RGB quantization range selectable? | |
3296 | * | |
3297 | * Check whether the monitor reports the RGB quantization range selection | |
3298 | * as supported. The AVI infoframe can then be used to inform the monitor | |
3299 | * which quantization range (full or limited) is used. | |
3300 | */ | |
3301 | bool drm_rgb_quant_range_selectable(struct edid *edid) | |
3302 | { | |
3303 | u8 *edid_ext; | |
3304 | int i, start, end; | |
3305 | ||
3306 | edid_ext = drm_find_cea_extension(edid); | |
3307 | if (!edid_ext) | |
3308 | return false; | |
3309 | ||
3310 | if (cea_db_offsets(edid_ext, &start, &end)) | |
3311 | return false; | |
3312 | ||
3313 | for_each_cea_db(edid_ext, i, start, end) { | |
3314 | if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK && | |
3315 | cea_db_payload_len(&edid_ext[i]) == 2) { | |
3316 | DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]); | |
3317 | return edid_ext[i + 2] & EDID_CEA_VCDB_QS; | |
3318 | } | |
3319 | } | |
3320 | ||
3321 | return false; | |
3322 | } | |
3323 | EXPORT_SYMBOL(drm_rgb_quant_range_selectable); | |
3324 | ||
3b11228b JB |
3325 | /** |
3326 | * drm_add_display_info - pull display info out if present | |
3327 | * @edid: EDID data | |
3328 | * @info: display info (attached to connector) | |
3329 | * | |
3330 | * Grab any available display info and stuff it into the drm_display_info | |
3331 | * structure that's part of the connector. Useful for tracking bpp and | |
3332 | * color spaces. | |
3333 | */ | |
3334 | static void drm_add_display_info(struct edid *edid, | |
3335 | struct drm_display_info *info) | |
3336 | { | |
ebec9a7b JB |
3337 | u8 *edid_ext; |
3338 | ||
3b11228b JB |
3339 | info->width_mm = edid->width_cm * 10; |
3340 | info->height_mm = edid->height_cm * 10; | |
3341 | ||
3342 | /* driver figures it out in this case */ | |
3343 | info->bpc = 0; | |
da05a5a7 | 3344 | info->color_formats = 0; |
3b11228b | 3345 | |
a988bc72 | 3346 | if (edid->revision < 3) |
3b11228b JB |
3347 | return; |
3348 | ||
3349 | if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) | |
3350 | return; | |
3351 | ||
a988bc72 LPC |
3352 | /* Get data from CEA blocks if present */ |
3353 | edid_ext = drm_find_cea_extension(edid); | |
3354 | if (edid_ext) { | |
3355 | info->cea_rev = edid_ext[1]; | |
3356 | ||
3357 | /* The existence of a CEA block should imply RGB support */ | |
3358 | info->color_formats = DRM_COLOR_FORMAT_RGB444; | |
3359 | if (edid_ext[3] & EDID_CEA_YCRCB444) | |
3360 | info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; | |
3361 | if (edid_ext[3] & EDID_CEA_YCRCB422) | |
3362 | info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; | |
3363 | } | |
3364 | ||
3365 | /* Only defined for 1.4 with digital displays */ | |
3366 | if (edid->revision < 4) | |
3367 | return; | |
3368 | ||
3b11228b JB |
3369 | switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { |
3370 | case DRM_EDID_DIGITAL_DEPTH_6: | |
3371 | info->bpc = 6; | |
3372 | break; | |
3373 | case DRM_EDID_DIGITAL_DEPTH_8: | |
3374 | info->bpc = 8; | |
3375 | break; | |
3376 | case DRM_EDID_DIGITAL_DEPTH_10: | |
3377 | info->bpc = 10; | |
3378 | break; | |
3379 | case DRM_EDID_DIGITAL_DEPTH_12: | |
3380 | info->bpc = 12; | |
3381 | break; | |
3382 | case DRM_EDID_DIGITAL_DEPTH_14: | |
3383 | info->bpc = 14; | |
3384 | break; | |
3385 | case DRM_EDID_DIGITAL_DEPTH_16: | |
3386 | info->bpc = 16; | |
3387 | break; | |
3388 | case DRM_EDID_DIGITAL_DEPTH_UNDEF: | |
3389 | default: | |
3390 | info->bpc = 0; | |
3391 | break; | |
3392 | } | |
da05a5a7 | 3393 | |
a988bc72 | 3394 | info->color_formats |= DRM_COLOR_FORMAT_RGB444; |
ee58808d LPC |
3395 | if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) |
3396 | info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; | |
3397 | if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) | |
3398 | info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; | |
3b11228b JB |
3399 | } |
3400 | ||
f453ba04 DA |
3401 | /** |
3402 | * drm_add_edid_modes - add modes from EDID data, if available | |
3403 | * @connector: connector we're probing | |
3404 | * @edid: edid data | |
3405 | * | |
3406 | * Add the specified modes to the connector's mode list. | |
3407 | * | |
3408 | * Return number of modes added or 0 if we couldn't find any. | |
3409 | */ | |
3410 | int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) | |
3411 | { | |
3412 | int num_modes = 0; | |
3413 | u32 quirks; | |
3414 | ||
3415 | if (edid == NULL) { | |
3416 | return 0; | |
3417 | } | |
3c537889 | 3418 | if (!drm_edid_is_valid(edid)) { |
dcdb1674 | 3419 | dev_warn(connector->dev->dev, "%s: EDID invalid.\n", |
f453ba04 DA |
3420 | drm_get_connector_name(connector)); |
3421 | return 0; | |
3422 | } | |
3423 | ||
3424 | quirks = edid_get_quirks(edid); | |
3425 | ||
c867df70 AJ |
3426 | /* |
3427 | * EDID spec says modes should be preferred in this order: | |
3428 | * - preferred detailed mode | |
3429 | * - other detailed modes from base block | |
3430 | * - detailed modes from extension blocks | |
3431 | * - CVT 3-byte code modes | |
3432 | * - standard timing codes | |
3433 | * - established timing codes | |
3434 | * - modes inferred from GTF or CVT range information | |
3435 | * | |
13931579 | 3436 | * We get this pretty much right. |
c867df70 AJ |
3437 | * |
3438 | * XXX order for additional mode types in extension blocks? | |
3439 | */ | |
13931579 AJ |
3440 | num_modes += add_detailed_modes(connector, edid, quirks); |
3441 | num_modes += add_cvt_modes(connector, edid); | |
c867df70 AJ |
3442 | num_modes += add_standard_modes(connector, edid); |
3443 | num_modes += add_established_modes(connector, edid); | |
196e077d PZ |
3444 | if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) |
3445 | num_modes += add_inferred_modes(connector, edid); | |
54ac76f8 | 3446 | num_modes += add_cea_modes(connector, edid); |
e6e79209 | 3447 | num_modes += add_alternate_cea_modes(connector, edid); |
f453ba04 DA |
3448 | |
3449 | if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) | |
3450 | edid_fixup_preferred(connector, quirks); | |
3451 | ||
3b11228b | 3452 | drm_add_display_info(edid, &connector->display_info); |
f453ba04 | 3453 | |
49d45a31 RM |
3454 | if (quirks & EDID_QUIRK_FORCE_8BPC) |
3455 | connector->display_info.bpc = 8; | |
3456 | ||
f453ba04 DA |
3457 | return num_modes; |
3458 | } | |
3459 | EXPORT_SYMBOL(drm_add_edid_modes); | |
f0fda0a4 ZY |
3460 | |
3461 | /** | |
3462 | * drm_add_modes_noedid - add modes for the connectors without EDID | |
3463 | * @connector: connector we're probing | |
3464 | * @hdisplay: the horizontal display limit | |
3465 | * @vdisplay: the vertical display limit | |
3466 | * | |
3467 | * Add the specified modes to the connector's mode list. Only when the | |
3468 | * hdisplay/vdisplay is not beyond the given limit, it will be added. | |
3469 | * | |
3470 | * Return number of modes added or 0 if we couldn't find any. | |
3471 | */ | |
3472 | int drm_add_modes_noedid(struct drm_connector *connector, | |
3473 | int hdisplay, int vdisplay) | |
3474 | { | |
3475 | int i, count, num_modes = 0; | |
b1f559ec | 3476 | struct drm_display_mode *mode; |
f0fda0a4 ZY |
3477 | struct drm_device *dev = connector->dev; |
3478 | ||
3479 | count = sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode); | |
3480 | if (hdisplay < 0) | |
3481 | hdisplay = 0; | |
3482 | if (vdisplay < 0) | |
3483 | vdisplay = 0; | |
3484 | ||
3485 | for (i = 0; i < count; i++) { | |
b1f559ec | 3486 | const struct drm_display_mode *ptr = &drm_dmt_modes[i]; |
f0fda0a4 ZY |
3487 | if (hdisplay && vdisplay) { |
3488 | /* | |
3489 | * Only when two are valid, they will be used to check | |
3490 | * whether the mode should be added to the mode list of | |
3491 | * the connector. | |
3492 | */ | |
3493 | if (ptr->hdisplay > hdisplay || | |
3494 | ptr->vdisplay > vdisplay) | |
3495 | continue; | |
3496 | } | |
f985dedb AJ |
3497 | if (drm_mode_vrefresh(ptr) > 61) |
3498 | continue; | |
f0fda0a4 ZY |
3499 | mode = drm_mode_duplicate(dev, ptr); |
3500 | if (mode) { | |
3501 | drm_mode_probed_add(connector, mode); | |
3502 | num_modes++; | |
3503 | } | |
3504 | } | |
3505 | return num_modes; | |
3506 | } | |
3507 | EXPORT_SYMBOL(drm_add_modes_noedid); | |
10a85120 | 3508 | |
3cf70daf GH |
3509 | void drm_set_preferred_mode(struct drm_connector *connector, |
3510 | int hpref, int vpref) | |
3511 | { | |
3512 | struct drm_display_mode *mode; | |
3513 | ||
3514 | list_for_each_entry(mode, &connector->probed_modes, head) { | |
3515 | if (drm_mode_width(mode) == hpref && | |
3516 | drm_mode_height(mode) == vpref) | |
3517 | mode->type |= DRM_MODE_TYPE_PREFERRED; | |
3518 | } | |
3519 | } | |
3520 | EXPORT_SYMBOL(drm_set_preferred_mode); | |
3521 | ||
10a85120 TR |
3522 | /** |
3523 | * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with | |
3524 | * data from a DRM display mode | |
3525 | * @frame: HDMI AVI infoframe | |
3526 | * @mode: DRM display mode | |
3527 | * | |
3528 | * Returns 0 on success or a negative error code on failure. | |
3529 | */ | |
3530 | int | |
3531 | drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, | |
3532 | const struct drm_display_mode *mode) | |
3533 | { | |
3534 | int err; | |
3535 | ||
3536 | if (!frame || !mode) | |
3537 | return -EINVAL; | |
3538 | ||
3539 | err = hdmi_avi_infoframe_init(frame); | |
3540 | if (err < 0) | |
3541 | return err; | |
3542 | ||
bf02db99 DL |
3543 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
3544 | frame->pixel_repeat = 1; | |
3545 | ||
10a85120 | 3546 | frame->video_code = drm_match_cea_mode(mode); |
10a85120 TR |
3547 | |
3548 | frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; | |
3549 | frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; | |
3550 | ||
3551 | return 0; | |
3552 | } | |
3553 | EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); | |
83dd0008 | 3554 | |
4eed4a0a DL |
3555 | static enum hdmi_3d_structure |
3556 | s3d_structure_from_display_mode(const struct drm_display_mode *mode) | |
3557 | { | |
3558 | u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; | |
3559 | ||
3560 | switch (layout) { | |
3561 | case DRM_MODE_FLAG_3D_FRAME_PACKING: | |
3562 | return HDMI_3D_STRUCTURE_FRAME_PACKING; | |
3563 | case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: | |
3564 | return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; | |
3565 | case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: | |
3566 | return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; | |
3567 | case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: | |
3568 | return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; | |
3569 | case DRM_MODE_FLAG_3D_L_DEPTH: | |
3570 | return HDMI_3D_STRUCTURE_L_DEPTH; | |
3571 | case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: | |
3572 | return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; | |
3573 | case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: | |
3574 | return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; | |
3575 | case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: | |
3576 | return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; | |
3577 | default: | |
3578 | return HDMI_3D_STRUCTURE_INVALID; | |
3579 | } | |
3580 | } | |
3581 | ||
83dd0008 LD |
3582 | /** |
3583 | * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with | |
3584 | * data from a DRM display mode | |
3585 | * @frame: HDMI vendor infoframe | |
3586 | * @mode: DRM display mode | |
3587 | * | |
3588 | * Note that there's is a need to send HDMI vendor infoframes only when using a | |
3589 | * 4k or stereoscopic 3D mode. So when giving any other mode as input this | |
3590 | * function will return -EINVAL, error that can be safely ignored. | |
3591 | * | |
3592 | * Returns 0 on success or a negative error code on failure. | |
3593 | */ | |
3594 | int | |
3595 | drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, | |
3596 | const struct drm_display_mode *mode) | |
3597 | { | |
3598 | int err; | |
4eed4a0a | 3599 | u32 s3d_flags; |
83dd0008 LD |
3600 | u8 vic; |
3601 | ||
3602 | if (!frame || !mode) | |
3603 | return -EINVAL; | |
3604 | ||
3605 | vic = drm_match_hdmi_mode(mode); | |
4eed4a0a DL |
3606 | s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; |
3607 | ||
3608 | if (!vic && !s3d_flags) | |
3609 | return -EINVAL; | |
3610 | ||
3611 | if (vic && s3d_flags) | |
83dd0008 LD |
3612 | return -EINVAL; |
3613 | ||
3614 | err = hdmi_vendor_infoframe_init(frame); | |
3615 | if (err < 0) | |
3616 | return err; | |
3617 | ||
4eed4a0a DL |
3618 | if (vic) |
3619 | frame->vic = vic; | |
3620 | else | |
3621 | frame->s3d_struct = s3d_structure_from_display_mode(mode); | |
83dd0008 LD |
3622 | |
3623 | return 0; | |
3624 | } | |
3625 | EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); |