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drm/edid: Fix sync polarity for secondary GTF curve
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / drm_edid.c
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f453ba04
DA		 1/*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
61e57a8d 5 * Copyright 2010 Red Hat, Inc.
f453ba04
DA		 6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30#include <linux/kernel.h>
31#include <linux/i2c.h>
32#include <linux/i2c-algo-bit.h>
33#include "drmP.h"
34#include "drm_edid.h"
35
d1ff6409
AJ		 36#define EDID_EST_TIMINGS 16
37#define EDID_STD_TIMINGS 8
38#define EDID_DETAILED_TIMINGS 4
39
f453ba04
DA		 40/*
41 * EDID blocks out in the wild have a variety of bugs, try to collect
42 * them here (note that userspace may work around broken monitors first,
43 * but fixes should make their way here so that the kernel "just works"
44 * on as many displays as possible).
45 */
46
47/* First detailed mode wrong, use largest 60Hz mode */
48#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
49/* Reported 135MHz pixel clock is too high, needs adjustment */
50#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
51/* Prefer the largest mode at 75 Hz */
52#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
53/* Detail timing is in cm not mm */
54#define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
55/* Detailed timing descriptors have bogus size values, so just take the
56 * maximum size and use that.
57 */
58#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
59/* Monitor forgot to set the first detailed is preferred bit. */
60#define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
61/* use +hsync +vsync for detailed mode */
62#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
3c537889 63
f453ba04 64
5c61259e
ZY		 65#define LEVEL_DMT 0
66#define LEVEL_GTF 1
7a374350
AJ		 67#define LEVEL_GTF2 2
68#define LEVEL_CVT 3
5c61259e 69
f453ba04
DA		 70static struct edid_quirk {
71 char *vendor;
72 int product_id;
73 u32 quirks;
74} edid_quirk_list[] = {
75 /* Acer AL1706 */
76 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
77 /* Acer F51 */
78 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
79 /* Unknown Acer */
80 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
81
82 /* Belinea 10 15 55 */
83 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
84 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
85
86 /* Envision Peripherals, Inc. EN-7100e */
87 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
88
89 /* Funai Electronics PM36B */
90 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
91 EDID_QUIRK_DETAILED_IN_CM },
92
93 /* LG Philips LCD LP154W01-A5 */
94 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
95 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
96
97 /* Philips 107p5 CRT */
98 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
99
100 /* Proview AY765C */
101 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
102
103 /* Samsung SyncMaster 205BW. Note: irony */
104 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
105 /* Samsung SyncMaster 22[5-6]BW */
106 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
107 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
108};
109
61e57a8d 110/*** DDC fetch and block validation ***/
f453ba04 111
083ae056
AJ		 112static const u8 edid_header[] = {
113 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
114};
f453ba04 115
61e57a8d
AJ		 116/*
117 * Sanity check the EDID block (base or extension). Return 0 if the block
118 * doesn't check out, or 1 if it's valid.
f453ba04 119 */
61e57a8d
AJ		 120static bool
121drm_edid_block_valid(u8 *raw_edid)
f453ba04 122{
61e57a8d 123 int i;
f453ba04 124 u8 csum = 0;
61e57a8d 125 struct edid *edid = (struct edid *)raw_edid;
f453ba04 126
61e57a8d
AJ		 127 if (raw_edid[0] == 0x00) {
128 int score = 0;
862b89c0 129
61e57a8d
AJ		 130 for (i = 0; i < sizeof(edid_header); i++)
131 if (raw_edid[i] == edid_header[i])
132 score++;
133
134 if (score == 8) ;
135 else if (score >= 6) {
136 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
137 memcpy(raw_edid, edid_header, sizeof(edid_header));
138 } else {
139 goto bad;
140 }
141 }
f453ba04
DA		 142
143 for (i = 0; i < EDID_LENGTH; i++)
144 csum += raw_edid[i];
145 if (csum) {
146 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum);
147 goto bad;
148 }
149
61e57a8d
AJ		 150 /* per-block-type checks */
151 switch (raw_edid[0]) {
152 case 0: /* base */
153 if (edid->version != 1) {
154 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version);
155 goto bad;
156 }
862b89c0 157
61e57a8d
AJ		 158 if (edid->revision > 4)
159 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
160 break;
161
162 default:
163 break;
164 }
47ee4ccf 165
f453ba04
DA		 166 return 1;
167
168bad:
169 if (raw_edid) {
170 DRM_ERROR("Raw EDID:\n");
171 print_hex_dump_bytes(KERN_ERR, DUMP_PREFIX_NONE, raw_edid, EDID_LENGTH);
172 printk("\n");
173 }
174 return 0;
175}
61e57a8d
AJ		 176
177/**
178 * drm_edid_is_valid - sanity check EDID data
179 * @edid: EDID data
180 *
181 * Sanity-check an entire EDID record (including extensions)
182 */
183bool drm_edid_is_valid(struct edid *edid)
184{
185 int i;
186 u8 *raw = (u8 *)edid;
187
188 if (!edid)
189 return false;
190
191 for (i = 0; i <= edid->extensions; i++)
192 if (!drm_edid_block_valid(raw + i * EDID_LENGTH))
193 return false;
194
195 return true;
196}
3c537889 197EXPORT_SYMBOL(drm_edid_is_valid);
f453ba04 198
61e57a8d
AJ		 199#define DDC_ADDR 0x50
200#define DDC_SEGMENT_ADDR 0x30
201/**
202 * Get EDID information via I2C.
203 *
204 * \param adapter : i2c device adaptor
205 * \param buf : EDID data buffer to be filled
206 * \param len : EDID data buffer length
207 * \return 0 on success or -1 on failure.
208 *
209 * Try to fetch EDID information by calling i2c driver function.
210 */
211static int
212drm_do_probe_ddc_edid(struct i2c_adapter *adapter, unsigned char *buf,
213 int block, int len)
214{
215 unsigned char start = block * EDID_LENGTH;
216 struct i2c_msg msgs[] = {
217 {
218 .addr = DDC_ADDR,
219 .flags = 0,
220 .len = 1,
221 .buf = &start,
222 }, {
223 .addr = DDC_ADDR,
224 .flags = I2C_M_RD,
225 .len = len,
226 .buf = buf + start,
227 }
228 };
229
230 if (i2c_transfer(adapter, msgs, 2) == 2)
231 return 0;
232
233 return -1;
234}
235
236static u8 *
237drm_do_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
238{
239 int i, j = 0;
240 u8 *block, *new;
241
242 if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
243 return NULL;
244
245 /* base block fetch */
246 for (i = 0; i < 4; i++) {
247 if (drm_do_probe_ddc_edid(adapter, block, 0, EDID_LENGTH))
248 goto out;
249 if (drm_edid_block_valid(block))
250 break;
251 }
252 if (i == 4)
253 goto carp;
254
255 /* if there's no extensions, we're done */
256 if (block[0x7e] == 0)
257 return block;
258
259 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL);
260 if (!new)
261 goto out;
262 block = new;
263
264 for (j = 1; j <= block[0x7e]; j++) {
265 for (i = 0; i < 4; i++) {
266 if (drm_do_probe_ddc_edid(adapter, block, j,
267 EDID_LENGTH))
268 goto out;
269 if (drm_edid_block_valid(block + j * EDID_LENGTH))
270 break;
271 }
272 if (i == 4)
273 goto carp;
274 }
275
276 return block;
277
278carp:
279 dev_warn(&connector->dev->pdev->dev, "%s: EDID block %d invalid.\n",
280 drm_get_connector_name(connector), j);
281
282out:
283 kfree(block);
284 return NULL;
285}
286
287/**
288 * Probe DDC presence.
289 *
290 * \param adapter : i2c device adaptor
291 * \return 1 on success
292 */
293static bool
294drm_probe_ddc(struct i2c_adapter *adapter)
295{
296 unsigned char out;
297
298 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
299}
300
301/**
302 * drm_get_edid - get EDID data, if available
303 * @connector: connector we're probing
304 * @adapter: i2c adapter to use for DDC
305 *
306 * Poke the given i2c channel to grab EDID data if possible. If found,
307 * attach it to the connector.
308 *
309 * Return edid data or NULL if we couldn't find any.
310 */
311struct edid *drm_get_edid(struct drm_connector *connector,
312 struct i2c_adapter *adapter)
313{
314 struct edid *edid = NULL;
315
316 if (drm_probe_ddc(adapter))
317 edid = (struct edid *)drm_do_get_edid(connector, adapter);
318
319 connector->display_info.raw_edid = (char *)edid;
320
321 return edid;
322
323}
324EXPORT_SYMBOL(drm_get_edid);
325
326/*** EDID parsing ***/
327
f453ba04
DA		 328/**
329 * edid_vendor - match a string against EDID's obfuscated vendor field
330 * @edid: EDID to match
331 * @vendor: vendor string
332 *
333 * Returns true if @vendor is in @edid, false otherwise
334 */
335static bool edid_vendor(struct edid *edid, char *vendor)
336{
337 char edid_vendor[3];
338
339 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
340 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
341 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
16456c87 342 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
f453ba04
DA		 343
344 return !strncmp(edid_vendor, vendor, 3);
345}
346
347/**
348 * edid_get_quirks - return quirk flags for a given EDID
349 * @edid: EDID to process
350 *
351 * This tells subsequent routines what fixes they need to apply.
352 */
353static u32 edid_get_quirks(struct edid *edid)
354{
355 struct edid_quirk *quirk;
356 int i;
357
358 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
359 quirk = &edid_quirk_list[i];
360
361 if (edid_vendor(edid, quirk->vendor) &&
362 (EDID_PRODUCT_ID(edid) == quirk->product_id))
363 return quirk->quirks;
364 }
365
366 return 0;
367}
368
369#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
370#define MODE_REFRESH_DIFF(m,r) (abs((m)->vrefresh - target_refresh))
371
372
373/**
374 * edid_fixup_preferred - set preferred modes based on quirk list
375 * @connector: has mode list to fix up
376 * @quirks: quirks list
377 *
378 * Walk the mode list for @connector, clearing the preferred status
379 * on existing modes and setting it anew for the right mode ala @quirks.
380 */
381static void edid_fixup_preferred(struct drm_connector *connector,
382 u32 quirks)
383{
384 struct drm_display_mode *t, *cur_mode, *preferred_mode;
f890607b 385 int target_refresh = 0;
f453ba04
DA		 386
387 if (list_empty(&connector->probed_modes))
388 return;
389
390 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
391 target_refresh = 60;
392 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
393 target_refresh = 75;
394
395 preferred_mode = list_first_entry(&connector->probed_modes,
396 struct drm_display_mode, head);
397
398 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
399 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
400
401 if (cur_mode == preferred_mode)
402 continue;
403
404 /* Largest mode is preferred */
405 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
406 preferred_mode = cur_mode;
407
408 /* At a given size, try to get closest to target refresh */
409 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
410 MODE_REFRESH_DIFF(cur_mode, target_refresh) <
411 MODE_REFRESH_DIFF(preferred_mode, target_refresh)) {
412 preferred_mode = cur_mode;
413 }
414 }
415
416 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
417}
418
aa9eaa1f
ZY		 419/*
420 * Add the Autogenerated from the DMT spec.
421 * This table is copied from xfree86/modes/xf86EdidModes.c.
422 * But the mode with Reduced blank feature is deleted.
423 */
424static struct drm_display_mode drm_dmt_modes[] = {
425 /* 640x350@85Hz */
426 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
427 736, 832, 0, 350, 382, 385, 445, 0,
428 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
429 /* 640x400@85Hz */
430 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
431 736, 832, 0, 400, 401, 404, 445, 0,
432 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
433 /* 720x400@85Hz */
434 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
435 828, 936, 0, 400, 401, 404, 446, 0,
436 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
437 /* 640x480@60Hz */
438 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
439 752, 800, 0, 480, 489, 492, 525, 0,
440 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
441 /* 640x480@72Hz */
442 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
443 704, 832, 0, 480, 489, 492, 520, 0,
444 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
445 /* 640x480@75Hz */
446 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
447 720, 840, 0, 480, 481, 484, 500, 0,
448 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
449 /* 640x480@85Hz */
450 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
451 752, 832, 0, 480, 481, 484, 509, 0,
452 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
453 /* 800x600@56Hz */
454 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
455 896, 1024, 0, 600, 601, 603, 625, 0,
456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
457 /* 800x600@60Hz */
458 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
459 968, 1056, 0, 600, 601, 605, 628, 0,
460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
461 /* 800x600@72Hz */
462 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
463 976, 1040, 0, 600, 637, 643, 666, 0,
464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
465 /* 800x600@75Hz */
466 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
467 896, 1056, 0, 600, 601, 604, 625, 0,
468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
469 /* 800x600@85Hz */
470 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
471 896, 1048, 0, 600, 601, 604, 631, 0,
472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
473 /* 848x480@60Hz */
474 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
475 976, 1088, 0, 480, 486, 494, 517, 0,
476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
477 /* 1024x768@43Hz, interlace */
478 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
479 1208, 1264, 0, 768, 768, 772, 817, 0,
480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
481 DRM_MODE_FLAG_INTERLACE) },
482 /* 1024x768@60Hz */
483 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
484 1184, 1344, 0, 768, 771, 777, 806, 0,
485 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
486 /* 1024x768@70Hz */
487 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
488 1184, 1328, 0, 768, 771, 777, 806, 0,
489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
490 /* 1024x768@75Hz */
491 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
492 1136, 1312, 0, 768, 769, 772, 800, 0,
493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
494 /* 1024x768@85Hz */
495 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
496 1072, 1376, 0, 768, 769, 772, 808, 0,
497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
498 /* 1152x864@75Hz */
499 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
500 1344, 1600, 0, 864, 865, 868, 900, 0,
501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
502 /* 1280x768@60Hz */
503 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
504 1472, 1664, 0, 768, 771, 778, 798, 0,
505 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
506 /* 1280x768@75Hz */
507 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
508 1488, 1696, 0, 768, 771, 778, 805, 0,
509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
510 /* 1280x768@85Hz */
511 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
512 1496, 1712, 0, 768, 771, 778, 809, 0,
513 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
514 /* 1280x800@60Hz */
515 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
516 1480, 1680, 0, 800, 803, 809, 831, 0,
517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
518 /* 1280x800@75Hz */
519 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
520 1488, 1696, 0, 800, 803, 809, 838, 0,
521 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
522 /* 1280x800@85Hz */
523 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
524 1496, 1712, 0, 800, 803, 809, 843, 0,
525 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
526 /* 1280x960@60Hz */
527 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
528 1488, 1800, 0, 960, 961, 964, 1000, 0,
529 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
530 /* 1280x960@85Hz */
531 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
532 1504, 1728, 0, 960, 961, 964, 1011, 0,
533 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
534 /* 1280x1024@60Hz */
535 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
536 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
537 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
538 /* 1280x1024@75Hz */
539 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
540 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
541 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
542 /* 1280x1024@85Hz */
543 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
544 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
545 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
546 /* 1360x768@60Hz */
547 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
548 1536, 1792, 0, 768, 771, 777, 795, 0,
549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
550 /* 1440x1050@60Hz */
551 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
552 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
553 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
554 /* 1440x1050@75Hz */
555 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
556 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
558 /* 1440x1050@85Hz */
559 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
560 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
561 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
562 /* 1440x900@60Hz */
563 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
564 1672, 1904, 0, 900, 903, 909, 934, 0,
565 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
566 /* 1440x900@75Hz */
567 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
568 1688, 1936, 0, 900, 903, 909, 942, 0,
569 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
570 /* 1440x900@85Hz */
571 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
572 1696, 1952, 0, 900, 903, 909, 948, 0,
573 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
574 /* 1600x1200@60Hz */
575 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
576 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
578 /* 1600x1200@65Hz */
579 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
580 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
581 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
582 /* 1600x1200@70Hz */
583 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
584 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
585 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
586 /* 1600x1200@75Hz */
587 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 2025000, 1600, 1664,
588 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
589 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
590 /* 1600x1200@85Hz */
591 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
592 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
593 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
594 /* 1680x1050@60Hz */
595 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
596 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
597 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
598 /* 1680x1050@75Hz */
599 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
600 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
601 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
602 /* 1680x1050@85Hz */
603 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
604 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
605 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
606 /* 1792x1344@60Hz */
607 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
608 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
609 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
610 /* 1729x1344@75Hz */
611 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
612 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
613 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
614 /* 1853x1392@60Hz */
615 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
616 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
617 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
618 /* 1856x1392@75Hz */
619 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
620 2208, 2560, 0, 1392, 1395, 1399, 1500, 0,
621 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
622 /* 1920x1200@60Hz */
623 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
624 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
625 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
626 /* 1920x1200@75Hz */
627 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
628 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
629 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
630 /* 1920x1200@85Hz */
631 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
632 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
633 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
634 /* 1920x1440@60Hz */
635 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
636 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
637 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
638 /* 1920x1440@75Hz */
639 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
640 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
641 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
642 /* 2560x1600@60Hz */
643 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
644 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
645 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
646 /* 2560x1600@75HZ */
647 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
648 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
649 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
650 /* 2560x1600@85HZ */
651 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
652 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
653 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
654};
07a5e632
AJ		 655static const int drm_num_dmt_modes =
656 sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode);
aa9eaa1f 657
559ee21d
ZY		 658static struct drm_display_mode *drm_find_dmt(struct drm_device *dev,
659 int hsize, int vsize, int fresh)
660{
07a5e632 661 int i;
559ee21d
ZY		 662 struct drm_display_mode *ptr, *mode;
663
559ee21d 664 mode = NULL;
07a5e632 665 for (i = 0; i < drm_num_dmt_modes; i++) {
559ee21d
ZY		 666 ptr = &drm_dmt_modes[i];
667 if (hsize == ptr->hdisplay &&
668 vsize == ptr->vdisplay &&
669 fresh == drm_mode_vrefresh(ptr)) {
670 /* get the expected default mode */
671 mode = drm_mode_duplicate(dev, ptr);
672 break;
673 }
674 }
675 return mode;
676}
23425cae 677
d1ff6409
AJ		 678typedef void detailed_cb(struct detailed_timing *timing, void *closure);
679
680static void
681drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
682{
683 int i;
684 struct edid *edid = (struct edid *)raw_edid;
685
686 if (edid == NULL)
687 return;
688
689 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
690 cb(&(edid->detailed_timings[i]), closure);
691
692 /* XXX extension block walk */
693}
694
695static void
696is_rb(struct detailed_timing *t, void *data)
697{
698 u8 *r = (u8 *)t;
699 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
700 if (r[15] & 0x10)
701 *(bool *)data = true;
702}
703
704/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
705static bool
706drm_monitor_supports_rb(struct edid *edid)
707{
708 if (edid->revision >= 4) {
709 bool ret;
710 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
711 return ret;
712 }
713
714 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
715}
716
7a374350
AJ		 717static void
718find_gtf2(struct detailed_timing *t, void *data)
719{
720 u8 *r = (u8 *)t;
721 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
722 *(u8 **)data = r;
723}
724
725/* Secondary GTF curve kicks in above some break frequency */
726static int
727drm_gtf2_hbreak(struct edid *edid)
728{
729 u8 *r = NULL;
730 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
731 return r ? (r[12] * 2) : 0;
732}
733
734static int
735drm_gtf2_2c(struct edid *edid)
736{
737 u8 *r = NULL;
738 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
739 return r ? r[13] : 0;
740}
741
742static int
743drm_gtf2_m(struct edid *edid)
744{
745 u8 *r = NULL;
746 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
747 return r ? (r[15] << 8) + r[14] : 0;
748}
749
750static int
751drm_gtf2_k(struct edid *edid)
752{
753 u8 *r = NULL;
754 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
755 return r ? r[16] : 0;
756}
757
758static int
759drm_gtf2_2j(struct edid *edid)
760{
761 u8 *r = NULL;
762 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
763 return r ? r[17] : 0;
764}
765
766/**
767 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
768 * @edid: EDID block to scan
769 */
770static int standard_timing_level(struct edid *edid)
771{
772 if (edid->revision >= 2) {
773 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
774 return LEVEL_CVT;
775 if (drm_gtf2_hbreak(edid))
776 return LEVEL_GTF2;
777 return LEVEL_GTF;
778 }
779 return LEVEL_DMT;
780}
781
23425cae
AJ		 782/*
783 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
784 * monitors fill with ascii space (0x20) instead.
785 */
786static int
787bad_std_timing(u8 a, u8 b)
788{
789 return (a == 0x00 && b == 0x00) ||
790 (a == 0x01 && b == 0x01) ||
791 (a == 0x20 && b == 0x20);
792}
793
f453ba04
DA		 794/**
795 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
796 * @t: standard timing params
5c61259e 797 * @timing_level: standard timing level
f453ba04
DA		 798 *
799 * Take the standard timing params (in this case width, aspect, and refresh)
5c61259e 800 * and convert them into a real mode using CVT/GTF/DMT.
f453ba04 801 */
7ca6adb3 802static struct drm_display_mode *
7a374350
AJ		 803drm_mode_std(struct drm_connector *connector, struct edid *edid,
804 struct std_timing *t, int revision)
f453ba04 805{
7ca6adb3
AJ		 806 struct drm_device *dev = connector->dev;
807 struct drm_display_mode *m, *mode = NULL;
5c61259e
ZY		 808 int hsize, vsize;
809 int vrefresh_rate;
0454beab
MD		 810 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
811 >> EDID_TIMING_ASPECT_SHIFT;
5c61259e
ZY		 812 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
813 >> EDID_TIMING_VFREQ_SHIFT;
7a374350 814 int timing_level = standard_timing_level(edid);
5c61259e 815
23425cae
AJ		 816 if (bad_std_timing(t->hsize, t->vfreq_aspect))
817 return NULL;
818
5c61259e
ZY		 819 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
820 hsize = t->hsize * 8 + 248;
821 /* vrefresh_rate = vfreq + 60 */
822 vrefresh_rate = vfreq + 60;
823 /* the vdisplay is calculated based on the aspect ratio */
f066a17d
AJ		 824 if (aspect_ratio == 0) {
825 if (revision < 3)
826 vsize = hsize;
827 else
828 vsize = (hsize * 10) / 16;
829 } else if (aspect_ratio == 1)
f453ba04 830 vsize = (hsize * 3) / 4;
0454beab 831 else if (aspect_ratio == 2)
f453ba04
DA		 832 vsize = (hsize * 4) / 5;
833 else
834 vsize = (hsize * 9) / 16;
a0910c8e
AJ		 835
836 /* HDTV hack, part 1 */
837 if (vrefresh_rate == 60 &&
838 ((hsize == 1360 && vsize == 765) ||
839 (hsize == 1368 && vsize == 769))) {
840 hsize = 1366;
841 vsize = 768;
842 }
843
7ca6adb3
AJ		 844 /*
845 * If this connector already has a mode for this size and refresh
846 * rate (because it came from detailed or CVT info), use that
847 * instead. This way we don't have to guess at interlace or
848 * reduced blanking.
849 */
850 list_for_each_entry(m, &connector->modes, head)
851 if (m->hdisplay == hsize && m->vdisplay == vsize &&
852 drm_mode_vrefresh(m) == vrefresh_rate)
853 return NULL;
854
a0910c8e
AJ		 855 /* HDTV hack, part 2 */
856 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
857 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
d50ba256 858 false);
559ee21d
ZY		 859 mode->hdisplay = 1366;
860 mode->vsync_start = mode->vsync_start - 1;
861 mode->vsync_end = mode->vsync_end - 1;
862 return mode;
863 }
a0910c8e 864
559ee21d
ZY		 865 /* check whether it can be found in default mode table */
866 mode = drm_find_dmt(dev, hsize, vsize, vrefresh_rate);
867 if (mode)
868 return mode;
869
5c61259e
ZY		 870 switch (timing_level) {
871 case LEVEL_DMT:
5c61259e
ZY		 872 break;
873 case LEVEL_GTF:
874 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
875 break;
7a374350
AJ		 876 case LEVEL_GTF2:
877 /*
878 * This is potentially wrong if there's ever a monitor with
879 * more than one ranges section, each claiming a different
880 * secondary GTF curve. Please don't do that.
881 */
882 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
883 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
884 kfree(mode);
885 mode = drm_gtf_mode_complex(dev, hsize, vsize,
886 vrefresh_rate, 0, 0,
887 drm_gtf2_m(edid),
888 drm_gtf2_2c(edid),
889 drm_gtf2_k(edid),
890 drm_gtf2_2j(edid));
891 }
892 break;
5c61259e 893 case LEVEL_CVT:
d50ba256
DA		 894 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
895 false);
5c61259e
ZY		 896 break;
897 }
f453ba04
DA		 898 return mode;
899}
900
b58db2c6
AJ		 901/*
902 * EDID is delightfully ambiguous about how interlaced modes are to be
903 * encoded. Our internal representation is of frame height, but some
904 * HDTV detailed timings are encoded as field height.
905 *
906 * The format list here is from CEA, in frame size. Technically we
907 * should be checking refresh rate too. Whatever.
908 */
909static void
910drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
911 struct detailed_pixel_timing *pt)
912{
913 int i;
914 static const struct {
915 int w, h;
916 } cea_interlaced[] = {
917 { 1920, 1080 },
918 { 720, 480 },
919 { 1440, 480 },
920 { 2880, 480 },
921 { 720, 576 },
922 { 1440, 576 },
923 { 2880, 576 },
924 };
925 static const int n_sizes =
926 sizeof(cea_interlaced)/sizeof(cea_interlaced[0]);
927
928 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
929 return;
930
931 for (i = 0; i < n_sizes; i++) {
932 if ((mode->hdisplay == cea_interlaced[i].w) &&
933 (mode->vdisplay == cea_interlaced[i].h / 2)) {
934 mode->vdisplay *= 2;
935 mode->vsync_start *= 2;
936 mode->vsync_end *= 2;
937 mode->vtotal *= 2;
938 mode->vtotal |= 1;
939 }
940 }
941
942 mode->flags |= DRM_MODE_FLAG_INTERLACE;
943}
944
f453ba04
DA		 945/**
946 * drm_mode_detailed - create a new mode from an EDID detailed timing section
947 * @dev: DRM device (needed to create new mode)
948 * @edid: EDID block
949 * @timing: EDID detailed timing info
950 * @quirks: quirks to apply
951 *
952 * An EDID detailed timing block contains enough info for us to create and
953 * return a new struct drm_display_mode.
954 */
955static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
956 struct edid *edid,
957 struct detailed_timing *timing,
958 u32 quirks)
959{
960 struct drm_display_mode *mode;
961 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
0454beab
MD		 962 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
963 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
964 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
965 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
e14cbee4
MD		 966 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
967 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
968 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) >> 2 | pt->vsync_offset_pulse_width_lo >> 4;
969 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
f453ba04 970
fc438966 971 /* ignore tiny modes */
0454beab 972 if (hactive < 64 || vactive < 64)
fc438966
AJ		 973 return NULL;
974
0454beab 975 if (pt->misc & DRM_EDID_PT_STEREO) {
f453ba04
DA		 976 printk(KERN_WARNING "stereo mode not supported\n");
977 return NULL;
978 }
0454beab 979 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
79b7dcb2 980 printk(KERN_WARNING "composite sync not supported\n");
f453ba04
DA		 981 }
982
fcb45611
ZY		 983 /* it is incorrect if hsync/vsync width is zero */
984 if (!hsync_pulse_width || !vsync_pulse_width) {
985 DRM_DEBUG_KMS("Incorrect Detailed timing. "
986 "Wrong Hsync/Vsync pulse width\n");
987 return NULL;
988 }
f453ba04
DA		 989 mode = drm_mode_create(dev);
990 if (!mode)
991 return NULL;
992
993 mode->type = DRM_MODE_TYPE_DRIVER;
994
995 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
0454beab
MD		 996 timing->pixel_clock = cpu_to_le16(1088);
997
998 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
999
1000 mode->hdisplay = hactive;
1001 mode->hsync_start = mode->hdisplay + hsync_offset;
1002 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
1003 mode->htotal = mode->hdisplay + hblank;
1004
1005 mode->vdisplay = vactive;
1006 mode->vsync_start = mode->vdisplay + vsync_offset;
1007 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
1008 mode->vtotal = mode->vdisplay + vblank;
f453ba04 1009
7064fef5
JB		 1010 /* Some EDIDs have bogus h/vtotal values */
1011 if (mode->hsync_end > mode->htotal)
1012 mode->htotal = mode->hsync_end + 1;
1013 if (mode->vsync_end > mode->vtotal)
1014 mode->vtotal = mode->vsync_end + 1;
1015
b58db2c6 1016 drm_mode_do_interlace_quirk(mode, pt);
f453ba04 1017
171fdd89
AJ		 1018 drm_mode_set_name(mode);
1019
f453ba04 1020 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
0454beab 1021 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
f453ba04
DA		 1022 }
1023
0454beab
MD		 1024 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
1025 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
1026 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
1027 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
f453ba04 1028
e14cbee4
MD		 1029 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
1030 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
f453ba04
DA		 1031
1032 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
1033 mode->width_mm *= 10;
1034 mode->height_mm *= 10;
1035 }
1036
1037 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
1038 mode->width_mm = edid->width_cm * 10;
1039 mode->height_mm = edid->height_cm * 10;
1040 }
1041
1042 return mode;
1043}
1044
1045/*
1046 * Detailed mode info for the EDID "established modes" data to use.
1047 */
1048static struct drm_display_mode edid_est_modes[] = {
1049 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
1050 968, 1056, 0, 600, 601, 605, 628, 0,
1051 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
1052 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
1053 896, 1024, 0, 600, 601, 603, 625, 0,
1054 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
1055 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
1056 720, 840, 0, 480, 481, 484, 500, 0,
1057 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
1058 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
1059 704, 832, 0, 480, 489, 491, 520, 0,
1060 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
1061 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
1062 768, 864, 0, 480, 483, 486, 525, 0,
1063 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
1064 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656,
1065 752, 800, 0, 480, 490, 492, 525, 0,
1066 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
1067 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
1068 846, 900, 0, 400, 421, 423, 449, 0,
1069 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
1070 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
1071 846, 900, 0, 400, 412, 414, 449, 0,
1072 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
1073 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
1074 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
1075 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
1076 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040,
1077 1136, 1312, 0, 768, 769, 772, 800, 0,
1078 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
1079 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
1080 1184, 1328, 0, 768, 771, 777, 806, 0,
1081 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
1082 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
1083 1184, 1344, 0, 768, 771, 777, 806, 0,
1084 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
1085 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
1086 1208, 1264, 0, 768, 768, 776, 817, 0,
1087 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
1088 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
1089 928, 1152, 0, 624, 625, 628, 667, 0,
1090 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
1091 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
1092 896, 1056, 0, 600, 601, 604, 625, 0,
1093 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
1094 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
1095 976, 1040, 0, 600, 637, 643, 666, 0,
1096 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
1097 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
1098 1344, 1600, 0, 864, 865, 868, 900, 0,
1099 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
1100};
1101
f453ba04
DA		 1102/**
1103 * add_established_modes - get est. modes from EDID and add them
1104 * @edid: EDID block to scan
1105 *
1106 * Each EDID block contains a bitmap of the supported "established modes" list
1107 * (defined above). Tease them out and add them to the global modes list.
1108 */
1109static int add_established_modes(struct drm_connector *connector, struct edid *edid)
1110{
1111 struct drm_device *dev = connector->dev;
1112 unsigned long est_bits = edid->established_timings.t1 |
1113 (edid->established_timings.t2 << 8) |
1114 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
1115 int i, modes = 0;
1116
1117 for (i = 0; i <= EDID_EST_TIMINGS; i++)
1118 if (est_bits & (1<<i)) {
1119 struct drm_display_mode *newmode;
1120 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
1121 if (newmode) {
1122 drm_mode_probed_add(connector, newmode);
1123 modes++;
1124 }
1125 }
1126
1127 return modes;
1128}
1129
1130/**
1131 * add_standard_modes - get std. modes from EDID and add them
1132 * @edid: EDID block to scan
1133 *
1134 * Standard modes can be calculated using the CVT standard. Grab them from
1135 * @edid, calculate them, and add them to the list.
1136 */
1137static int add_standard_modes(struct drm_connector *connector, struct edid *edid)
1138{
f453ba04
DA		 1139 int i, modes = 0;
1140
1141 for (i = 0; i < EDID_STD_TIMINGS; i++) {
f453ba04
DA		 1142 struct drm_display_mode *newmode;
1143
7a374350
AJ		 1144 newmode = drm_mode_std(connector, edid,
1145 &edid->standard_timings[i],
1146 edid->revision);
f453ba04
DA		 1147 if (newmode) {
1148 drm_mode_probed_add(connector, newmode);
1149 modes++;
1150 }
1151 }
1152
1153 return modes;
1154}
1155
07a5e632 1156static bool
b17e52ef 1157mode_is_rb(struct drm_display_mode *mode)
07a5e632 1158{
b17e52ef
AJ		 1159 return (mode->htotal - mode->hdisplay == 160) &&
1160 (mode->hsync_end - mode->hdisplay == 80) &&
1161 (mode->hsync_end - mode->hsync_start == 32) &&
1162 (mode->vsync_start - mode->vdisplay == 3);
1163}
07a5e632 1164
b17e52ef
AJ		 1165static bool
1166mode_in_hsync_range(struct drm_display_mode *mode, struct edid *edid, u8 *t)
1167{
1168 int hsync, hmin, hmax;
1169
1170 hmin = t[7];
1171 if (edid->revision >= 4)
1172 hmin += ((t[4] & 0x04) ? 255 : 0);
1173 hmax = t[8];
1174 if (edid->revision >= 4)
1175 hmax += ((t[4] & 0x08) ? 255 : 0);
07a5e632 1176 hsync = drm_mode_hsync(mode);
07a5e632 1177
b17e52ef
AJ		 1178 return (hsync <= hmax && hsync >= hmin);
1179}
1180
1181static bool
1182mode_in_vsync_range(struct drm_display_mode *mode, struct edid *edid, u8 *t)
1183{
1184 int vsync, vmin, vmax;
1185
1186 vmin = t[5];
1187 if (edid->revision >= 4)
1188 vmin += ((t[4] & 0x01) ? 255 : 0);
1189 vmax = t[6];
1190 if (edid->revision >= 4)
1191 vmax += ((t[4] & 0x02) ? 255 : 0);
1192 vsync = drm_mode_vrefresh(mode);
1193
1194 return (vsync <= vmax && vsync >= vmin);
1195}
1196
1197static u32
1198range_pixel_clock(struct edid *edid, u8 *t)
1199{
1200 /* unspecified */
1201 if (t[9] == 0 || t[9] == 255)
1202 return 0;
1203
1204 /* 1.4 with CVT support gives us real precision, yay */
1205 if (edid->revision >= 4 && t[10] == 0x04)
1206 return (t[9] * 10000) - ((t[12] >> 2) * 250);
1207
1208 /* 1.3 is pathetic, so fuzz up a bit */
1209 return t[9] * 10000 + 5001;
1210}
1211
b17e52ef
AJ		 1212static bool
1213mode_in_range(struct drm_display_mode *mode, struct edid *edid,
1214 struct detailed_timing *timing)
1215{
1216 u32 max_clock;
1217 u8 *t = (u8 *)timing;
1218
1219 if (!mode_in_hsync_range(mode, edid, t))
07a5e632
AJ		 1220 return false;
1221
b17e52ef 1222 if (!mode_in_vsync_range(mode, edid, t))
07a5e632
AJ		 1223 return false;
1224
b17e52ef 1225 if ((max_clock = range_pixel_clock(edid, t)))
07a5e632
AJ		 1226 if (mode->clock > max_clock)
1227 return false;
b17e52ef
AJ		 1228
1229 /* 1.4 max horizontal check */
1230 if (edid->revision >= 4 && t[10] == 0x04)
1231 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
1232 return false;
1233
1234 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
1235 return false;
07a5e632
AJ		 1236
1237 return true;
1238}
1239
1240/*
1241 * XXX If drm_dmt_modes ever regrows the CVT-R modes (and it will) this will
1242 * need to account for them.
1243 */
b17e52ef
AJ		 1244static int
1245drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
1246 struct detailed_timing *timing)
07a5e632
AJ		 1247{
1248 int i, modes = 0;
1249 struct drm_display_mode *newmode;
1250 struct drm_device *dev = connector->dev;
1251
1252 for (i = 0; i < drm_num_dmt_modes; i++) {
b17e52ef 1253 if (mode_in_range(drm_dmt_modes + i, edid, timing)) {
07a5e632
AJ		 1254 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
1255 if (newmode) {
1256 drm_mode_probed_add(connector, newmode);
1257 modes++;
1258 }
1259 }
1260 }
1261
1262 return modes;
1263}
1264
9340d8cf
AJ		 1265static int drm_cvt_modes(struct drm_connector *connector,
1266 struct detailed_timing *timing)
1267{
1268 int i, j, modes = 0;
1269 struct drm_display_mode *newmode;
1270 struct drm_device *dev = connector->dev;
1271 struct cvt_timing *cvt;
1272 const int rates[] = { 60, 85, 75, 60, 50 };
69da3015 1273 const u8 empty[3] = { 0, 0, 0 };
9340d8cf
AJ		 1274
1275 for (i = 0; i < 4; i++) {
29ebdf92 1276 int uninitialized_var(width), height;
9340d8cf
AJ		 1277 cvt = &(timing->data.other_data.data.cvt[i]);
1278
69da3015
AJ		 1279 if (!memcmp(cvt->code, empty, 3))
1280 continue;
1281
8e10ee9a
AJ		 1282 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
1283 switch (cvt->code[1] & 0x0c) {
9340d8cf
AJ		 1284 case 0x00:
1285 width = height * 4 / 3;
1286 break;
8e10ee9a 1287 case 0x04:
9340d8cf
AJ		 1288 width = height * 16 / 9;
1289 break;
8e10ee9a 1290 case 0x08:
9340d8cf
AJ		 1291 width = height * 16 / 10;
1292 break;
8e10ee9a 1293 case 0x0c:
9340d8cf
AJ		 1294 width = height * 15 / 9;
1295 break;
1296 }
1297
1298 for (j = 1; j < 5; j++) {
1299 if (cvt->code[2] & (1 << j)) {
1300 newmode = drm_cvt_mode(dev, width, height,
1301 rates[j], j == 0,
1302 false, false);
1303 if (newmode) {
1304 drm_mode_probed_add(connector, newmode);
1305 modes++;
1306 }
1307 }
1308 }
1309 }
1310
1311 return modes;
1312}
1313
2255be14
AJ		 1314static const struct {
1315 short w;
1316 short h;
1317 short r;
1318 short rb;
1319} est3_modes[] = {
1320 /* byte 6 */
1321 { 640, 350, 85, 0 },
1322 { 640, 400, 85, 0 },
1323 { 720, 400, 85, 0 },
1324 { 640, 480, 85, 0 },
1325 { 848, 480, 60, 0 },
1326 { 800, 600, 85, 0 },
1327 { 1024, 768, 85, 0 },
1328 { 1152, 864, 75, 0 },
1329 /* byte 7 */
1330 { 1280, 768, 60, 1 },
1331 { 1280, 768, 60, 0 },
1332 { 1280, 768, 75, 0 },
1333 { 1280, 768, 85, 0 },
1334 { 1280, 960, 60, 0 },
1335 { 1280, 960, 85, 0 },
1336 { 1280, 1024, 60, 0 },
1337 { 1280, 1024, 85, 0 },
1338 /* byte 8 */
1339 { 1360, 768, 60, 0 },
1340 { 1440, 900, 60, 1 },
1341 { 1440, 900, 60, 0 },
1342 { 1440, 900, 75, 0 },
1343 { 1440, 900, 85, 0 },
1344 { 1400, 1050, 60, 1 },
1345 { 1400, 1050, 60, 0 },
1346 { 1400, 1050, 75, 0 },
1347 /* byte 9 */
1348 { 1400, 1050, 85, 0 },
1349 { 1680, 1050, 60, 1 },
1350 { 1680, 1050, 60, 0 },
1351 { 1680, 1050, 75, 0 },
1352 { 1680, 1050, 85, 0 },
1353 { 1600, 1200, 60, 0 },
1354 { 1600, 1200, 65, 0 },
1355 { 1600, 1200, 70, 0 },
1356 /* byte 10 */
1357 { 1600, 1200, 75, 0 },
1358 { 1600, 1200, 85, 0 },
1359 { 1792, 1344, 60, 0 },
1360 { 1792, 1344, 85, 0 },
1361 { 1856, 1392, 60, 0 },
1362 { 1856, 1392, 75, 0 },
1363 { 1920, 1200, 60, 1 },
1364 { 1920, 1200, 60, 0 },
1365 /* byte 11 */
1366 { 1920, 1200, 75, 0 },
1367 { 1920, 1200, 85, 0 },
1368 { 1920, 1440, 60, 0 },
1369 { 1920, 1440, 75, 0 },
1370};
1371static const int num_est3_modes = sizeof(est3_modes) / sizeof(est3_modes[0]);
1372
1373static int
1374drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
1375{
1376 int i, j, m, modes = 0;
1377 struct drm_display_mode *mode;
1378 u8 *est = ((u8 *)timing) + 5;
1379
1380 for (i = 0; i < 6; i++) {
1381 for (j = 7; j > 0; j--) {
1382 m = (i * 8) + (7 - j);
1383 if (m > num_est3_modes)
1384 break;
1385 if (est[i] & (1 << j)) {
1386 mode = drm_find_dmt(connector->dev,
1387 est3_modes[m].w,
1388 est3_modes[m].h,
1389 est3_modes[m].r
1390 /*, est3_modes[m].rb */);
1391 if (mode) {
1392 drm_mode_probed_add(connector, mode);
1393 modes++;
1394 }
1395 }
1396 }
1397 }
1398
1399 return modes;
1400}
1401
9cf00977
AJ		 1402static int add_detailed_modes(struct drm_connector *connector,
1403 struct detailed_timing *timing,
1404 struct edid *edid, u32 quirks, int preferred)
1405{
1406 int i, modes = 0;
1407 struct detailed_non_pixel *data = &timing->data.other_data;
07a5e632 1408 int gtf = (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF);
9cf00977
AJ		 1409 struct drm_display_mode *newmode;
1410 struct drm_device *dev = connector->dev;
1411
1412 if (timing->pixel_clock) {
1413 newmode = drm_mode_detailed(dev, edid, timing, quirks);
1414 if (!newmode)
1415 return 0;
1416
1417 if (preferred)
1418 newmode->type |= DRM_MODE_TYPE_PREFERRED;
1419
1420 drm_mode_probed_add(connector, newmode);
1421 return 1;
1422 }
1423
1424 /* other timing types */
1425 switch (data->type) {
1426 case EDID_DETAIL_MONITOR_RANGE:
07a5e632 1427 if (gtf)
b17e52ef
AJ		 1428 modes += drm_gtf_modes_for_range(connector, edid,
1429 timing);
9cf00977
AJ		 1430 break;
1431 case EDID_DETAIL_STD_MODES:
1432 /* Six modes per detailed section */
1433 for (i = 0; i < 6; i++) {
1434 struct std_timing *std;
1435 struct drm_display_mode *newmode;
1436
1437 std = &data->data.timings[i];
7a374350
AJ		 1438 newmode = drm_mode_std(connector, edid, std,
1439 edid->revision);
9cf00977
AJ		 1440 if (newmode) {
1441 drm_mode_probed_add(connector, newmode);
1442 modes++;
1443 }
1444 }
1445 break;
9340d8cf
AJ		 1446 case EDID_DETAIL_CVT_3BYTE:
1447 modes += drm_cvt_modes(connector, timing);
1448 break;
2255be14
AJ		 1449 case EDID_DETAIL_EST_TIMINGS:
1450 modes += drm_est3_modes(connector, timing);
1451 break;
9cf00977
AJ		 1452 default:
1453 break;
1454 }
1455
1456 return modes;
1457}
1458
f453ba04 1459/**
9cf00977 1460 * add_detailed_info - get detailed mode info from EDID data
f453ba04
DA		 1461 * @connector: attached connector
1462 * @edid: EDID block to scan
1463 * @quirks: quirks to apply
1464 *
1465 * Some of the detailed timing sections may contain mode information. Grab
1466 * it and add it to the list.
1467 */
1468static int add_detailed_info(struct drm_connector *connector,
1469 struct edid *edid, u32 quirks)
1470{
9cf00977 1471 int i, modes = 0;
f453ba04
DA		 1472
1473 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) {
1474 struct detailed_timing *timing = &edid->detailed_timings[i];
a327f6b8
AJ		 1475 int preferred = (i == 0);
1476
1477 if (preferred && edid->version == 1 && edid->revision < 4)
1478 preferred = (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
f453ba04 1479
9cf00977
AJ		 1480 /* In 1.0, only timings are allowed */
1481 if (!timing->pixel_clock && edid->version == 1 &&
1482 edid->revision == 0)
1483 continue;
f453ba04 1484
9cf00977
AJ		 1485 modes += add_detailed_modes(connector, timing, edid, quirks,
1486 preferred);
f453ba04
DA		 1487 }
1488
1489 return modes;
1490}
9cf00977 1491
882f0219
ZY		 1492/**
1493 * add_detailed_mode_eedid - get detailed mode info from addtional timing
1494 * EDID block
1495 * @connector: attached connector
1496 * @edid: EDID block to scan(It is only to get addtional timing EDID block)
1497 * @quirks: quirks to apply
1498 *
1499 * Some of the detailed timing sections may contain mode information. Grab
1500 * it and add it to the list.
1501 */
1502static int add_detailed_info_eedid(struct drm_connector *connector,
1503 struct edid *edid, u32 quirks)
1504{
9cf00977 1505 int i, modes = 0;
882f0219
ZY		 1506 char *edid_ext = NULL;
1507 struct detailed_timing *timing;
882f0219
ZY		 1508 int start_offset, end_offset;
1509 int timing_level;
1510
59d8aff6 1511 if (edid->version == 1 && edid->revision < 3)
882f0219 1512 return 0;
59d8aff6 1513 if (!edid->extensions)
882f0219 1514 return 0;
882f0219 1515
882f0219 1516 /* Find CEA extension */
7466f4cc 1517 for (i = 0; i < edid->extensions; i++) {
882f0219 1518 edid_ext = (char *)edid + EDID_LENGTH * (i + 1);
882f0219
ZY		 1519 if (edid_ext[0] == 0x02)
1520 break;
1521 }
1522
59d8aff6 1523 if (i == edid->extensions)
882f0219 1524 return 0;
882f0219
ZY		 1525
1526 /* Get the start offset of detailed timing block */
1527 start_offset = edid_ext[2];
1528 if (start_offset == 0) {
1529 /* If the start_offset is zero, it means that neither detailed
1530 * info nor data block exist. In such case it is also
1531 * unnecessary to parse the detailed timing info.
1532 */
1533 return 0;
1534 }
1535
1536 timing_level = standard_timing_level(edid);
1537 end_offset = EDID_LENGTH;
1538 end_offset -= sizeof(struct detailed_timing);
1539 for (i = start_offset; i < end_offset;
1540 i += sizeof(struct detailed_timing)) {
1541 timing = (struct detailed_timing *)(edid_ext + i);
9cf00977 1542 modes += add_detailed_modes(connector, timing, edid, quirks, 0);
882f0219
ZY		 1543 }
1544
1545 return modes;
1546}
f453ba04 1547
f23c20c8
ML		 1548#define HDMI_IDENTIFIER 0x000C03
1549#define VENDOR_BLOCK 0x03
1550/**
1551 * drm_detect_hdmi_monitor - detect whether monitor is hdmi.
1552 * @edid: monitor EDID information
1553 *
1554 * Parse the CEA extension according to CEA-861-B.
1555 * Return true if HDMI, false if not or unknown.
1556 */
1557bool drm_detect_hdmi_monitor(struct edid *edid)
1558{
1559 char *edid_ext = NULL;
7466f4cc 1560 int i, hdmi_id;
f23c20c8
ML		 1561 int start_offset, end_offset;
1562 bool is_hdmi = false;
1563
1564 /* No EDID or EDID extensions */
1565 if (edid == NULL || edid->extensions == 0)
1566 goto end;
1567
f23c20c8 1568 /* Find CEA extension */
7466f4cc 1569 for (i = 0; i < edid->extensions; i++) {
f23c20c8
ML		 1570 edid_ext = (char *)edid + EDID_LENGTH * (i + 1);
1571 /* This block is CEA extension */
1572 if (edid_ext[0] == 0x02)
1573 break;
1574 }
1575
7466f4cc 1576 if (i == edid->extensions)
f23c20c8
ML		 1577 goto end;
1578
1579 /* Data block offset in CEA extension block */
1580 start_offset = 4;
1581 end_offset = edid_ext[2];
1582
1583 /*
1584 * Because HDMI identifier is in Vendor Specific Block,
1585 * search it from all data blocks of CEA extension.
1586 */
1587 for (i = start_offset; i < end_offset;
1588 /* Increased by data block len */
1589 i += ((edid_ext[i] & 0x1f) + 1)) {
1590 /* Find vendor specific block */
1591 if ((edid_ext[i] >> 5) == VENDOR_BLOCK) {
1592 hdmi_id = edid_ext[i + 1] | (edid_ext[i + 2] << 8) |
1593 edid_ext[i + 3] << 16;
1594 /* Find HDMI identifier */
1595 if (hdmi_id == HDMI_IDENTIFIER)
1596 is_hdmi = true;
1597 break;
1598 }
1599 }
1600
1601end:
1602 return is_hdmi;
1603}
1604EXPORT_SYMBOL(drm_detect_hdmi_monitor);
1605
f453ba04
DA		 1606/**
1607 * drm_add_edid_modes - add modes from EDID data, if available
1608 * @connector: connector we're probing
1609 * @edid: edid data
1610 *
1611 * Add the specified modes to the connector's mode list.
1612 *
1613 * Return number of modes added or 0 if we couldn't find any.
1614 */
1615int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
1616{
1617 int num_modes = 0;
1618 u32 quirks;
1619
1620 if (edid == NULL) {
1621 return 0;
1622 }
3c537889 1623 if (!drm_edid_is_valid(edid)) {
f453ba04
DA		 1624 dev_warn(&connector->dev->pdev->dev, "%s: EDID invalid.\n",
1625 drm_get_connector_name(connector));
1626 return 0;
1627 }
1628
1629 quirks = edid_get_quirks(edid);
1630
c867df70
AJ		 1631 /*
1632 * EDID spec says modes should be preferred in this order:
1633 * - preferred detailed mode
1634 * - other detailed modes from base block
1635 * - detailed modes from extension blocks
1636 * - CVT 3-byte code modes
1637 * - standard timing codes
1638 * - established timing codes
1639 * - modes inferred from GTF or CVT range information
1640 *
1641 * We don't quite implement this yet, but we're close.
1642 *
1643 * XXX order for additional mode types in extension blocks?
1644 */
f453ba04 1645 num_modes += add_detailed_info(connector, edid, quirks);
882f0219 1646 num_modes += add_detailed_info_eedid(connector, edid, quirks);
c867df70
AJ		 1647 num_modes += add_standard_modes(connector, edid);
1648 num_modes += add_established_modes(connector, edid);
f453ba04
DA		 1649
1650 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
1651 edid_fixup_preferred(connector, quirks);
1652
0454beab
MD		 1653 connector->display_info.serration_vsync = (edid->input & DRM_EDID_INPUT_SERRATION_VSYNC) ? 1 : 0;
1654 connector->display_info.sync_on_green = (edid->input & DRM_EDID_INPUT_SYNC_ON_GREEN) ? 1 : 0;
1655 connector->display_info.composite_sync = (edid->input & DRM_EDID_INPUT_COMPOSITE_SYNC) ? 1 : 0;
1656 connector->display_info.separate_syncs = (edid->input & DRM_EDID_INPUT_SEPARATE_SYNCS) ? 1 : 0;
1657 connector->display_info.blank_to_black = (edid->input & DRM_EDID_INPUT_BLANK_TO_BLACK) ? 1 : 0;
1658 connector->display_info.video_level = (edid->input & DRM_EDID_INPUT_VIDEO_LEVEL) >> 5;
1659 connector->display_info.digital = (edid->input & DRM_EDID_INPUT_DIGITAL) ? 1 : 0;
f453ba04
DA		 1660 connector->display_info.width_mm = edid->width_cm * 10;
1661 connector->display_info.height_mm = edid->height_cm * 10;
1662 connector->display_info.gamma = edid->gamma;
0454beab
MD		 1663 connector->display_info.gtf_supported = (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) ? 1 : 0;
1664 connector->display_info.standard_color = (edid->features & DRM_EDID_FEATURE_STANDARD_COLOR) ? 1 : 0;
1665 connector->display_info.display_type = (edid->features & DRM_EDID_FEATURE_DISPLAY_TYPE) >> 3;
1666 connector->display_info.active_off_supported = (edid->features & DRM_EDID_FEATURE_PM_ACTIVE_OFF) ? 1 : 0;
1667 connector->display_info.suspend_supported = (edid->features & DRM_EDID_FEATURE_PM_SUSPEND) ? 1 : 0;
1668 connector->display_info.standby_supported = (edid->features & DRM_EDID_FEATURE_PM_STANDBY) ? 1 : 0;
f453ba04
DA		 1669 connector->display_info.gamma = edid->gamma;
1670
1671 return num_modes;
1672}
1673EXPORT_SYMBOL(drm_add_edid_modes);
f0fda0a4
ZY		 1674
1675/**
1676 * drm_add_modes_noedid - add modes for the connectors without EDID
1677 * @connector: connector we're probing
1678 * @hdisplay: the horizontal display limit
1679 * @vdisplay: the vertical display limit
1680 *
1681 * Add the specified modes to the connector's mode list. Only when the
1682 * hdisplay/vdisplay is not beyond the given limit, it will be added.
1683 *
1684 * Return number of modes added or 0 if we couldn't find any.
1685 */
1686int drm_add_modes_noedid(struct drm_connector *connector,
1687 int hdisplay, int vdisplay)
1688{
1689 int i, count, num_modes = 0;
1690 struct drm_display_mode *mode, *ptr;
1691 struct drm_device *dev = connector->dev;
1692
1693 count = sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode);
1694 if (hdisplay < 0)
1695 hdisplay = 0;
1696 if (vdisplay < 0)
1697 vdisplay = 0;
1698
1699 for (i = 0; i < count; i++) {
1700 ptr = &drm_dmt_modes[i];
1701 if (hdisplay && vdisplay) {
1702 /*
1703 * Only when two are valid, they will be used to check
1704 * whether the mode should be added to the mode list of
1705 * the connector.
1706 */
1707 if (ptr->hdisplay > hdisplay ||
1708 ptr->vdisplay > vdisplay)
1709 continue;
1710 }
f985dedb
AJ		 1711 if (drm_mode_vrefresh(ptr) > 61)
1712 continue;
f0fda0a4
ZY		 1713 mode = drm_mode_duplicate(dev, ptr);
1714 if (mode) {
1715 drm_mode_probed_add(connector, mode);
1716 num_modes++;
1717 }
1718 }
1719 return num_modes;
1720}
1721EXPORT_SYMBOL(drm_add_modes_noedid);
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