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drm/edid: shorten log output in case of all zeroes edid block
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / drm_edid.c
CommitLineData
f453ba04
DA		 1/*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
61e57a8d 5 * Copyright 2010 Red Hat, Inc.
f453ba04
DA		 6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30#include <linux/kernel.h>
5a0e3ad6 31#include <linux/slab.h>
10a85120 32#include <linux/hdmi.h>
f453ba04 33#include <linux/i2c.h>
47819ba2 34#include <linux/module.h>
760285e7
DH		 35#include <drm/drmP.h>
36#include <drm/drm_edid.h>
f453ba04 37
13931579
AJ		 38#define version_greater(edid, maj, min) \
39 (((edid)->version > (maj)) || \
40 ((edid)->version == (maj) && (edid)->revision > (min)))
f453ba04 41
d1ff6409
AJ		 42#define EDID_EST_TIMINGS 16
43#define EDID_STD_TIMINGS 8
44#define EDID_DETAILED_TIMINGS 4
f453ba04
DA		 45
46/*
47 * EDID blocks out in the wild have a variety of bugs, try to collect
48 * them here (note that userspace may work around broken monitors first,
49 * but fixes should make their way here so that the kernel "just works"
50 * on as many displays as possible).
51 */
52
53/* First detailed mode wrong, use largest 60Hz mode */
54#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
55/* Reported 135MHz pixel clock is too high, needs adjustment */
56#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
57/* Prefer the largest mode at 75 Hz */
58#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
59/* Detail timing is in cm not mm */
60#define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
61/* Detailed timing descriptors have bogus size values, so just take the
62 * maximum size and use that.
63 */
64#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
65/* Monitor forgot to set the first detailed is preferred bit. */
66#define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
67/* use +hsync +vsync for detailed mode */
68#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
bc42aabc
AJ		 69/* Force reduced-blanking timings for detailed modes */
70#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
49d45a31
RM		 71/* Force 8bpc */
72#define EDID_QUIRK_FORCE_8BPC (1 << 8)
bc5b9641
MK		 73/* Force 12bpc */
74#define EDID_QUIRK_FORCE_12BPC (1 << 9)
3c537889 75
13931579
AJ		 76struct detailed_mode_closure {
77 struct drm_connector *connector;
78 struct edid *edid;
79 bool preferred;
80 u32 quirks;
81 int modes;
82};
f453ba04 83
5c61259e
ZY		 84#define LEVEL_DMT 0
85#define LEVEL_GTF 1
7a374350
AJ		 86#define LEVEL_GTF2 2
87#define LEVEL_CVT 3
5c61259e 88
f453ba04 89static struct edid_quirk {
c51a3fd6 90 char vendor[4];
f453ba04
DA		 91 int product_id;
92 u32 quirks;
93} edid_quirk_list[] = {
94 /* Acer AL1706 */
95 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
96 /* Acer F51 */
97 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
98 /* Unknown Acer */
99 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
100
101 /* Belinea 10 15 55 */
102 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
103 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
104
105 /* Envision Peripherals, Inc. EN-7100e */
106 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
ba1163de
AJ		 107 /* Envision EN2028 */
108 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
f453ba04
DA		 109
110 /* Funai Electronics PM36B */
111 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
112 EDID_QUIRK_DETAILED_IN_CM },
113
114 /* LG Philips LCD LP154W01-A5 */
115 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
116 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
117
118 /* Philips 107p5 CRT */
119 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
120
121 /* Proview AY765C */
122 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
123
124 /* Samsung SyncMaster 205BW. Note: irony */
125 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
126 /* Samsung SyncMaster 22[5-6]BW */
127 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
128 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
bc42aabc 129
bc5b9641
MK		 130 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
131 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
132
bc42aabc
AJ		 133 /* ViewSonic VA2026w */
134 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
118bdbd8
AD		 135
136 /* Medion MD 30217 PG */
137 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
49d45a31
RM		 138
139 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
140 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
f453ba04
DA		 141};
142
a6b21831
TR		 143/*
144 * Autogenerated from the DMT spec.
145 * This table is copied from xfree86/modes/xf86EdidModes.c.
146 */
147static const struct drm_display_mode drm_dmt_modes[] = {
148 /* 640x350@85Hz */
149 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
150 736, 832, 0, 350, 382, 385, 445, 0,
151 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
152 /* 640x400@85Hz */
153 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
154 736, 832, 0, 400, 401, 404, 445, 0,
155 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
156 /* 720x400@85Hz */
157 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
158 828, 936, 0, 400, 401, 404, 446, 0,
159 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
160 /* 640x480@60Hz */
161 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
162 752, 800, 0, 480, 489, 492, 525, 0,
163 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
164 /* 640x480@72Hz */
165 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
166 704, 832, 0, 480, 489, 492, 520, 0,
167 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
168 /* 640x480@75Hz */
169 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
170 720, 840, 0, 480, 481, 484, 500, 0,
171 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
172 /* 640x480@85Hz */
173 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
174 752, 832, 0, 480, 481, 484, 509, 0,
175 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
176 /* 800x600@56Hz */
177 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
178 896, 1024, 0, 600, 601, 603, 625, 0,
179 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
180 /* 800x600@60Hz */
181 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
182 968, 1056, 0, 600, 601, 605, 628, 0,
183 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
184 /* 800x600@72Hz */
185 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
186 976, 1040, 0, 600, 637, 643, 666, 0,
187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
188 /* 800x600@75Hz */
189 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
190 896, 1056, 0, 600, 601, 604, 625, 0,
191 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
192 /* 800x600@85Hz */
193 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
194 896, 1048, 0, 600, 601, 604, 631, 0,
195 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
196 /* 800x600@120Hz RB */
197 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
198 880, 960, 0, 600, 603, 607, 636, 0,
199 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
200 /* 848x480@60Hz */
201 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
202 976, 1088, 0, 480, 486, 494, 517, 0,
203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
204 /* 1024x768@43Hz, interlace */
205 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
206 1208, 1264, 0, 768, 768, 772, 817, 0,
207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
208 DRM_MODE_FLAG_INTERLACE) },
209 /* 1024x768@60Hz */
210 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
211 1184, 1344, 0, 768, 771, 777, 806, 0,
212 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
213 /* 1024x768@70Hz */
214 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
215 1184, 1328, 0, 768, 771, 777, 806, 0,
216 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
217 /* 1024x768@75Hz */
218 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
219 1136, 1312, 0, 768, 769, 772, 800, 0,
220 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
221 /* 1024x768@85Hz */
222 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
223 1168, 1376, 0, 768, 769, 772, 808, 0,
224 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
225 /* 1024x768@120Hz RB */
226 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
227 1104, 1184, 0, 768, 771, 775, 813, 0,
228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
229 /* 1152x864@75Hz */
230 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
231 1344, 1600, 0, 864, 865, 868, 900, 0,
232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
233 /* 1280x768@60Hz RB */
234 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
235 1360, 1440, 0, 768, 771, 778, 790, 0,
236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
237 /* 1280x768@60Hz */
238 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
239 1472, 1664, 0, 768, 771, 778, 798, 0,
240 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
241 /* 1280x768@75Hz */
242 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
243 1488, 1696, 0, 768, 771, 778, 805, 0,
244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
245 /* 1280x768@85Hz */
246 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
247 1496, 1712, 0, 768, 771, 778, 809, 0,
248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
249 /* 1280x768@120Hz RB */
250 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
251 1360, 1440, 0, 768, 771, 778, 813, 0,
252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
253 /* 1280x800@60Hz RB */
254 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
255 1360, 1440, 0, 800, 803, 809, 823, 0,
256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
257 /* 1280x800@60Hz */
258 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
259 1480, 1680, 0, 800, 803, 809, 831, 0,
260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
261 /* 1280x800@75Hz */
262 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
263 1488, 1696, 0, 800, 803, 809, 838, 0,
264 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
265 /* 1280x800@85Hz */
266 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
267 1496, 1712, 0, 800, 803, 809, 843, 0,
268 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
269 /* 1280x800@120Hz RB */
270 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
271 1360, 1440, 0, 800, 803, 809, 847, 0,
272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
273 /* 1280x960@60Hz */
274 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
275 1488, 1800, 0, 960, 961, 964, 1000, 0,
276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
277 /* 1280x960@85Hz */
278 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
279 1504, 1728, 0, 960, 961, 964, 1011, 0,
280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
281 /* 1280x960@120Hz RB */
282 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
283 1360, 1440, 0, 960, 963, 967, 1017, 0,
284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
285 /* 1280x1024@60Hz */
286 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
287 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
289 /* 1280x1024@75Hz */
290 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
291 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
293 /* 1280x1024@85Hz */
294 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
295 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
297 /* 1280x1024@120Hz RB */
298 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
299 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
301 /* 1360x768@60Hz */
302 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
303 1536, 1792, 0, 768, 771, 777, 795, 0,
304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
305 /* 1360x768@120Hz RB */
306 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
307 1440, 1520, 0, 768, 771, 776, 813, 0,
308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
309 /* 1400x1050@60Hz RB */
310 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
311 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
313 /* 1400x1050@60Hz */
314 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
315 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
316 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
317 /* 1400x1050@75Hz */
318 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
319 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
320 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
321 /* 1400x1050@85Hz */
322 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
323 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
324 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
325 /* 1400x1050@120Hz RB */
326 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
327 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
329 /* 1440x900@60Hz RB */
330 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
331 1520, 1600, 0, 900, 903, 909, 926, 0,
332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
333 /* 1440x900@60Hz */
334 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
335 1672, 1904, 0, 900, 903, 909, 934, 0,
336 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
337 /* 1440x900@75Hz */
338 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
339 1688, 1936, 0, 900, 903, 909, 942, 0,
340 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
341 /* 1440x900@85Hz */
342 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
343 1696, 1952, 0, 900, 903, 909, 948, 0,
344 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
345 /* 1440x900@120Hz RB */
346 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
347 1520, 1600, 0, 900, 903, 909, 953, 0,
348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
349 /* 1600x1200@60Hz */
350 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
351 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
353 /* 1600x1200@65Hz */
354 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
355 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
356 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
357 /* 1600x1200@70Hz */
358 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
359 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
360 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
361 /* 1600x1200@75Hz */
362 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
363 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
365 /* 1600x1200@85Hz */
366 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
367 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
369 /* 1600x1200@120Hz RB */
370 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
371 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
373 /* 1680x1050@60Hz RB */
374 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
375 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
377 /* 1680x1050@60Hz */
378 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
379 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
380 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
381 /* 1680x1050@75Hz */
382 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
383 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
384 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
385 /* 1680x1050@85Hz */
386 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
387 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
388 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
389 /* 1680x1050@120Hz RB */
390 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
391 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
393 /* 1792x1344@60Hz */
394 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
395 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
396 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
397 /* 1792x1344@75Hz */
398 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
399 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
400 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
401 /* 1792x1344@120Hz RB */
402 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
403 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
404 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
405 /* 1856x1392@60Hz */
406 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
407 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
408 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
409 /* 1856x1392@75Hz */
410 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
411 2208, 2560, 0, 1392, 1395, 1399, 1500, 0,
412 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
413 /* 1856x1392@120Hz RB */
414 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
415 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
417 /* 1920x1200@60Hz RB */
418 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
419 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
421 /* 1920x1200@60Hz */
422 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
423 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
424 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
425 /* 1920x1200@75Hz */
426 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
427 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
428 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
429 /* 1920x1200@85Hz */
430 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
431 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
432 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
433 /* 1920x1200@120Hz RB */
434 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
435 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
437 /* 1920x1440@60Hz */
438 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
439 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
440 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
441 /* 1920x1440@75Hz */
442 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
443 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
444 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
445 /* 1920x1440@120Hz RB */
446 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
447 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
449 /* 2560x1600@60Hz RB */
450 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
451 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
453 /* 2560x1600@60Hz */
454 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
455 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
456 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
457 /* 2560x1600@75HZ */
458 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
459 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
460 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
461 /* 2560x1600@85HZ */
462 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
463 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
464 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
465 /* 2560x1600@120Hz RB */
466 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
467 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
469};
470
e7bfa5c4
VS		 471/*
472 * These more or less come from the DMT spec. The 720x400 modes are
473 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
474 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
475 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
476 * mode.
477 *
478 * The DMT modes have been fact-checked; the rest are mild guesses.
479 */
a6b21831
TR		 480static const struct drm_display_mode edid_est_modes[] = {
481 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
482 968, 1056, 0, 600, 601, 605, 628, 0,
483 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
484 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
485 896, 1024, 0, 600, 601, 603, 625, 0,
486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
487 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
488 720, 840, 0, 480, 481, 484, 500, 0,
489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
490 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
491 704, 832, 0, 480, 489, 491, 520, 0,
492 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
493 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
494 768, 864, 0, 480, 483, 486, 525, 0,
495 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
496 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656,
497 752, 800, 0, 480, 490, 492, 525, 0,
498 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
499 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
500 846, 900, 0, 400, 421, 423, 449, 0,
501 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
502 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
503 846, 900, 0, 400, 412, 414, 449, 0,
504 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
505 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
506 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
507 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
508 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040,
509 1136, 1312, 0, 768, 769, 772, 800, 0,
510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
511 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
512 1184, 1328, 0, 768, 771, 777, 806, 0,
513 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
514 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
515 1184, 1344, 0, 768, 771, 777, 806, 0,
516 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
517 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
518 1208, 1264, 0, 768, 768, 776, 817, 0,
519 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
520 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
521 928, 1152, 0, 624, 625, 628, 667, 0,
522 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
523 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
524 896, 1056, 0, 600, 601, 604, 625, 0,
525 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
526 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
527 976, 1040, 0, 600, 637, 643, 666, 0,
528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
529 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
530 1344, 1600, 0, 864, 865, 868, 900, 0,
531 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
532};
533
534struct minimode {
535 short w;
536 short h;
537 short r;
538 short rb;
539};
540
541static const struct minimode est3_modes[] = {
542 /* byte 6 */
543 { 640, 350, 85, 0 },
544 { 640, 400, 85, 0 },
545 { 720, 400, 85, 0 },
546 { 640, 480, 85, 0 },
547 { 848, 480, 60, 0 },
548 { 800, 600, 85, 0 },
549 { 1024, 768, 85, 0 },
550 { 1152, 864, 75, 0 },
551 /* byte 7 */
552 { 1280, 768, 60, 1 },
553 { 1280, 768, 60, 0 },
554 { 1280, 768, 75, 0 },
555 { 1280, 768, 85, 0 },
556 { 1280, 960, 60, 0 },
557 { 1280, 960, 85, 0 },
558 { 1280, 1024, 60, 0 },
559 { 1280, 1024, 85, 0 },
560 /* byte 8 */
561 { 1360, 768, 60, 0 },
562 { 1440, 900, 60, 1 },
563 { 1440, 900, 60, 0 },
564 { 1440, 900, 75, 0 },
565 { 1440, 900, 85, 0 },
566 { 1400, 1050, 60, 1 },
567 { 1400, 1050, 60, 0 },
568 { 1400, 1050, 75, 0 },
569 /* byte 9 */
570 { 1400, 1050, 85, 0 },
571 { 1680, 1050, 60, 1 },
572 { 1680, 1050, 60, 0 },
573 { 1680, 1050, 75, 0 },
574 { 1680, 1050, 85, 0 },
575 { 1600, 1200, 60, 0 },
576 { 1600, 1200, 65, 0 },
577 { 1600, 1200, 70, 0 },
578 /* byte 10 */
579 { 1600, 1200, 75, 0 },
580 { 1600, 1200, 85, 0 },
581 { 1792, 1344, 60, 0 },
c068b32a 582 { 1792, 1344, 75, 0 },
a6b21831
TR		 583 { 1856, 1392, 60, 0 },
584 { 1856, 1392, 75, 0 },
585 { 1920, 1200, 60, 1 },
586 { 1920, 1200, 60, 0 },
587 /* byte 11 */
588 { 1920, 1200, 75, 0 },
589 { 1920, 1200, 85, 0 },
590 { 1920, 1440, 60, 0 },
591 { 1920, 1440, 75, 0 },
592};
593
594static const struct minimode extra_modes[] = {
595 { 1024, 576, 60, 0 },
596 { 1366, 768, 60, 0 },
597 { 1600, 900, 60, 0 },
598 { 1680, 945, 60, 0 },
599 { 1920, 1080, 60, 0 },
600 { 2048, 1152, 60, 0 },
601 { 2048, 1536, 60, 0 },
602};
603
604/*
605 * Probably taken from CEA-861 spec.
606 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
607 */
608static const struct drm_display_mode edid_cea_modes[] = {
609 /* 1 - 640x480@60Hz */
610 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
611 752, 800, 0, 480, 490, 492, 525, 0,
ee7925bb 612 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 613 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 614 /* 2 - 720x480@60Hz */
615 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
616 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 617 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 618 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 619 /* 3 - 720x480@60Hz */
620 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
621 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 622 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 623 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 624 /* 4 - 1280x720@60Hz */
625 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
626 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 627 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 628 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 629 /* 5 - 1920x1080i@60Hz */
630 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
631 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
632 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
ee7925bb 633 DRM_MODE_FLAG_INTERLACE),
985e5dc2 634 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 635 /* 6 - 720(1440)x480i@60Hz */
636 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
637 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 638 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 639 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 640 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 641 /* 7 - 720(1440)x480i@60Hz */
642 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
643 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 644 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 645 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 646 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 647 /* 8 - 720(1440)x240@60Hz */
648 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
649 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 650 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 651 DRM_MODE_FLAG_DBLCLK),
985e5dc2 652 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 653 /* 9 - 720(1440)x240@60Hz */
654 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
655 801, 858, 0, 240, 244, 247, 262, 0,
a6b21831 656 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 657 DRM_MODE_FLAG_DBLCLK),
985e5dc2 658 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 659 /* 10 - 2880x480i@60Hz */
660 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
661 3204, 3432, 0, 480, 488, 494, 525, 0,
662 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 663 DRM_MODE_FLAG_INTERLACE),
985e5dc2 664 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 665 /* 11 - 2880x480i@60Hz */
666 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
667 3204, 3432, 0, 480, 488, 494, 525, 0,
668 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 669 DRM_MODE_FLAG_INTERLACE),
985e5dc2 670 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 671 /* 12 - 2880x240@60Hz */
672 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
673 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 674 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 675 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 676 /* 13 - 2880x240@60Hz */
677 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
678 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 679 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 680 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 681 /* 14 - 1440x480@60Hz */
682 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
683 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 684 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 685 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 686 /* 15 - 1440x480@60Hz */
687 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
688 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 689 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 690 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 691 /* 16 - 1920x1080@60Hz */
692 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
693 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 694 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 695 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 696 /* 17 - 720x576@50Hz */
697 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
698 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 699 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 700 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 701 /* 18 - 720x576@50Hz */
702 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
703 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 704 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 705 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 706 /* 19 - 1280x720@50Hz */
707 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
708 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 709 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 710 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 711 /* 20 - 1920x1080i@50Hz */
712 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
713 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
714 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
ee7925bb 715 DRM_MODE_FLAG_INTERLACE),
985e5dc2 716 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 717 /* 21 - 720(1440)x576i@50Hz */
718 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
719 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 720 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 721 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 722 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 723 /* 22 - 720(1440)x576i@50Hz */
724 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
725 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 726 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 727 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 728 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 729 /* 23 - 720(1440)x288@50Hz */
730 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
731 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 732 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 733 DRM_MODE_FLAG_DBLCLK),
985e5dc2 734 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 735 /* 24 - 720(1440)x288@50Hz */
736 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
737 795, 864, 0, 288, 290, 293, 312, 0,
a6b21831 738 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 739 DRM_MODE_FLAG_DBLCLK),
985e5dc2 740 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 741 /* 25 - 2880x576i@50Hz */
742 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
743 3180, 3456, 0, 576, 580, 586, 625, 0,
744 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 745 DRM_MODE_FLAG_INTERLACE),
985e5dc2 746 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 747 /* 26 - 2880x576i@50Hz */
748 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
749 3180, 3456, 0, 576, 580, 586, 625, 0,
750 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 751 DRM_MODE_FLAG_INTERLACE),
985e5dc2 752 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 753 /* 27 - 2880x288@50Hz */
754 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
755 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 756 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 757 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 758 /* 28 - 2880x288@50Hz */
759 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
760 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 761 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 762 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 763 /* 29 - 1440x576@50Hz */
764 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
765 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 766 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 767 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 768 /* 30 - 1440x576@50Hz */
769 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
770 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 771 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 772 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 773 /* 31 - 1920x1080@50Hz */
774 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
775 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 776 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 777 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 778 /* 32 - 1920x1080@24Hz */
779 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
780 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 781 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 782 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 783 /* 33 - 1920x1080@25Hz */
784 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
785 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 786 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 787 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 788 /* 34 - 1920x1080@30Hz */
789 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
790 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 791 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 792 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 793 /* 35 - 2880x480@60Hz */
794 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
795 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 796 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 797 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 798 /* 36 - 2880x480@60Hz */
799 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
800 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 801 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 802 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 803 /* 37 - 2880x576@50Hz */
804 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
805 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 806 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 807 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 808 /* 38 - 2880x576@50Hz */
809 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
810 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 811 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 812 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 813 /* 39 - 1920x1080i@50Hz */
814 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
815 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
816 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 817 DRM_MODE_FLAG_INTERLACE),
985e5dc2 818 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 819 /* 40 - 1920x1080i@100Hz */
820 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
821 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
822 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
ee7925bb 823 DRM_MODE_FLAG_INTERLACE),
985e5dc2 824 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 825 /* 41 - 1280x720@100Hz */
826 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
827 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 828 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 829 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 830 /* 42 - 720x576@100Hz */
831 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
832 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 833 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 834 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 835 /* 43 - 720x576@100Hz */
836 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
837 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 838 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 839 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 840 /* 44 - 720(1440)x576i@100Hz */
841 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
842 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 843 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
5a11f7f8 844 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 845 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 846 /* 45 - 720(1440)x576i@100Hz */
847 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
848 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 849 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
5a11f7f8 850 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 851 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 852 /* 46 - 1920x1080i@120Hz */
853 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
854 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
855 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
ee7925bb 856 DRM_MODE_FLAG_INTERLACE),
985e5dc2 857 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 858 /* 47 - 1280x720@120Hz */
859 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
860 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 861 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 862 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 863 /* 48 - 720x480@120Hz */
864 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
865 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 866 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 867 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 868 /* 49 - 720x480@120Hz */
869 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
870 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 871 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 872 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 873 /* 50 - 720(1440)x480i@120Hz */
874 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
875 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 876 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 877 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 878 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 879 /* 51 - 720(1440)x480i@120Hz */
880 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
881 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 882 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 883 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 884 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 885 /* 52 - 720x576@200Hz */
886 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
887 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 888 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 889 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 890 /* 53 - 720x576@200Hz */
891 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
892 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 893 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 894 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 895 /* 54 - 720(1440)x576i@200Hz */
896 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
897 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 898 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 899 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 900 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 901 /* 55 - 720(1440)x576i@200Hz */
902 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
903 795, 864, 0, 576, 580, 586, 625, 0,
a6b21831 904 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 905 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 906 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 907 /* 56 - 720x480@240Hz */
908 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
909 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 910 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 911 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 912 /* 57 - 720x480@240Hz */
913 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
914 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 915 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 916 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
fb01d280
CT		 917 /* 58 - 720(1440)x480i@240 */
918 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
919 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 920 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 921 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 922 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
fb01d280
CT		 923 /* 59 - 720(1440)x480i@240 */
924 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
925 801, 858, 0, 480, 488, 494, 525, 0,
a6b21831 926 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 927 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 928 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 929 /* 60 - 1280x720@24Hz */
930 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
931 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 932 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 933 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 934 /* 61 - 1280x720@25Hz */
935 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
936 3740, 3960, 0, 720, 725, 730, 750, 0,
ee7925bb 937 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 938 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 939 /* 62 - 1280x720@30Hz */
940 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
941 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 942 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 943 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 944 /* 63 - 1920x1080@120Hz */
945 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
946 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 947 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 948 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 949 /* 64 - 1920x1080@100Hz */
950 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
951 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
ee7925bb 952 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 953 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 954};
955
7ebe1963
LD		 956/*
957 * HDMI 1.4 4k modes.
958 */
959static const struct drm_display_mode edid_4k_modes[] = {
960 /* 1 - 3840x2160@30Hz */
961 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
962 3840, 4016, 4104, 4400, 0,
963 2160, 2168, 2178, 2250, 0,
964 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
965 .vrefresh = 30, },
966 /* 2 - 3840x2160@25Hz */
967 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
968 3840, 4896, 4984, 5280, 0,
969 2160, 2168, 2178, 2250, 0,
970 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
971 .vrefresh = 25, },
972 /* 3 - 3840x2160@24Hz */
973 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
974 3840, 5116, 5204, 5500, 0,
975 2160, 2168, 2178, 2250, 0,
976 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
977 .vrefresh = 24, },
978 /* 4 - 4096x2160@24Hz (SMPTE) */
979 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
980 4096, 5116, 5204, 5500, 0,
981 2160, 2168, 2178, 2250, 0,
982 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
983 .vrefresh = 24, },
984};
985
61e57a8d 986/*** DDC fetch and block validation ***/
f453ba04 987
083ae056
AJ		 988static const u8 edid_header[] = {
989 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
990};
f453ba04 991
db6cf833
TR		 992/**
993 * drm_edid_header_is_valid - sanity check the header of the base EDID block
994 * @raw_edid: pointer to raw base EDID block
995 *
996 * Sanity check the header of the base EDID block.
997 *
998 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
051963d4
TR		 999 */
1000int drm_edid_header_is_valid(const u8 *raw_edid)
1001{
1002 int i, score = 0;
1003
1004 for (i = 0; i < sizeof(edid_header); i++)
1005 if (raw_edid[i] == edid_header[i])
1006 score++;
1007
1008 return score;
1009}
1010EXPORT_SYMBOL(drm_edid_header_is_valid);
1011
47819ba2
AJ		 1012static int edid_fixup __read_mostly = 6;
1013module_param_named(edid_fixup, edid_fixup, int, 0400);
1014MODULE_PARM_DESC(edid_fixup,
1015 "Minimum number of valid EDID header bytes (0-8, default 6)");
051963d4 1016
d6885d65
SB		 1017static bool drm_edid_is_zero(const u8 *in_edid, int length)
1018{
1019 if (memchr_inv(in_edid, 0, length))
1020 return false;
1021
1022 return true;
1023}
1024
db6cf833
TR		 1025/**
1026 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1027 * @raw_edid: pointer to raw EDID block
1028 * @block: type of block to validate (0 for base, extension otherwise)
1029 * @print_bad_edid: if true, dump bad EDID blocks to the console
1030 *
1031 * Validate a base or extension EDID block and optionally dump bad blocks to
1032 * the console.
1033 *
1034 * Return: True if the block is valid, false otherwise.
f453ba04 1035 */
0b2443ed 1036bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid)
f453ba04 1037{
61e57a8d 1038 int i;
f453ba04 1039 u8 csum = 0;
61e57a8d 1040 struct edid *edid = (struct edid *)raw_edid;
f453ba04 1041
fe2ef780
SWK		 1042 if (WARN_ON(!raw_edid))
1043 return false;
1044
47819ba2
AJ		 1045 if (edid_fixup > 8 || edid_fixup < 0)
1046 edid_fixup = 6;
1047
f89ec8a4 1048 if (block == 0) {
051963d4 1049 int score = drm_edid_header_is_valid(raw_edid);
61e57a8d 1050 if (score == 8) ;
47819ba2 1051 else if (score >= edid_fixup) {
61e57a8d
AJ		 1052 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1053 memcpy(raw_edid, edid_header, sizeof(edid_header));
1054 } else {
1055 goto bad;
1056 }
1057 }
f453ba04
DA		 1058
1059 for (i = 0; i < EDID_LENGTH; i++)
1060 csum += raw_edid[i];
1061 if (csum) {
0b2443ed
JG		 1062 if (print_bad_edid) {
1063 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum);
1064 }
4a638b4e
AJ		 1065
1066 /* allow CEA to slide through, switches mangle this */
1067 if (raw_edid[0] != 0x02)
1068 goto bad;
f453ba04
DA		 1069 }
1070
61e57a8d
AJ		 1071 /* per-block-type checks */
1072 switch (raw_edid[0]) {
1073 case 0: /* base */
1074 if (edid->version != 1) {
1075 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version);
1076 goto bad;
1077 }
862b89c0 1078
61e57a8d
AJ		 1079 if (edid->revision > 4)
1080 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1081 break;
862b89c0 1082
61e57a8d
AJ		 1083 default:
1084 break;
1085 }
47ee4ccf 1086
fe2ef780 1087 return true;
f453ba04
DA		 1088
1089bad:
fe2ef780 1090 if (print_bad_edid) {
da4c07b7
SB		 1091 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1092 printk(KERN_ERR "EDID block is all zeroes\n");
1093 } else {
1094 printk(KERN_ERR "Raw EDID:\n");
1095 print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1,
0aff47f2 1096 raw_edid, EDID_LENGTH, false);
da4c07b7 1097 }
f453ba04 1098 }
fe2ef780 1099 return false;
f453ba04 1100}
da0df92b 1101EXPORT_SYMBOL(drm_edid_block_valid);
61e57a8d
AJ		 1102
1103/**
1104 * drm_edid_is_valid - sanity check EDID data
1105 * @edid: EDID data
1106 *
1107 * Sanity-check an entire EDID record (including extensions)
db6cf833
TR		 1108 *
1109 * Return: True if the EDID data is valid, false otherwise.
61e57a8d
AJ		 1110 */
1111bool drm_edid_is_valid(struct edid *edid)
1112{
1113 int i;
1114 u8 *raw = (u8 *)edid;
1115
1116 if (!edid)
1117 return false;
1118
1119 for (i = 0; i <= edid->extensions; i++)
0b2443ed 1120 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true))
61e57a8d
AJ		 1121 return false;
1122
1123 return true;
1124}
3c537889 1125EXPORT_SYMBOL(drm_edid_is_valid);
f453ba04 1126
61e57a8d
AJ		 1127#define DDC_SEGMENT_ADDR 0x30
1128/**
db6cf833
TR		 1129 * drm_do_probe_ddc_edid() - get EDID information via I2C
1130 * @adapter: I2C device adaptor
fc66811c
DV		 1131 * @buf: EDID data buffer to be filled
1132 * @block: 128 byte EDID block to start fetching from
1133 * @len: EDID data buffer length to fetch
1134 *
db6cf833 1135 * Try to fetch EDID information by calling I2C driver functions.
61e57a8d 1136 *
db6cf833 1137 * Return: 0 on success or -1 on failure.
61e57a8d
AJ		 1138 */
1139static int
1140drm_do_probe_ddc_edid(struct i2c_adapter *adapter, unsigned char *buf,
1141 int block, int len)
1142{
1143 unsigned char start = block * EDID_LENGTH;
cd004b3f
S		 1144 unsigned char segment = block >> 1;
1145 unsigned char xfers = segment ? 3 : 2;
4819d2e4
CW		 1146 int ret, retries = 5;
1147
db6cf833
TR		 1148 /*
1149 * The core I2C driver will automatically retry the transfer if the
4819d2e4
CW		 1150 * adapter reports EAGAIN. However, we find that bit-banging transfers
1151 * are susceptible to errors under a heavily loaded machine and
1152 * generate spurious NAKs and timeouts. Retrying the transfer
1153 * of the individual block a few times seems to overcome this.
1154 */
1155 do {
1156 struct i2c_msg msgs[] = {
1157 {
cd004b3f
S		 1158 .addr = DDC_SEGMENT_ADDR,
1159 .flags = 0,
1160 .len = 1,
1161 .buf = &segment,
1162 }, {
4819d2e4
CW		 1163 .addr = DDC_ADDR,
1164 .flags = 0,
1165 .len = 1,
1166 .buf = &start,
1167 }, {
1168 .addr = DDC_ADDR,
1169 .flags = I2C_M_RD,
1170 .len = len,
1171 .buf = buf,
1172 }
1173 };
cd004b3f 1174
db6cf833
TR		 1175 /*
1176 * Avoid sending the segment addr to not upset non-compliant
1177 * DDC monitors.
1178 */
cd004b3f
S		 1179 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1180
9292f37e
ED		 1181 if (ret == -ENXIO) {
1182 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1183 adapter->name);
1184 break;
1185 }
cd004b3f 1186 } while (ret != xfers && --retries);
4819d2e4 1187
cd004b3f 1188 return ret == xfers ? 0 : -1;
61e57a8d
AJ		 1189}
1190
1191static u8 *
1192drm_do_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
1193{
0ea75e23 1194 int i, j = 0, valid_extensions = 0;
61e57a8d 1195 u8 *block, *new;
0b2443ed 1196 bool print_bad_edid = !connector->bad_edid_counter || (drm_debug & DRM_UT_KMS);
61e57a8d
AJ		 1197
1198 if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1199 return NULL;
1200
1201 /* base block fetch */
1202 for (i = 0; i < 4; i++) {
1203 if (drm_do_probe_ddc_edid(adapter, block, 0, EDID_LENGTH))
1204 goto out;
0b2443ed 1205 if (drm_edid_block_valid(block, 0, print_bad_edid))
61e57a8d 1206 break;
4a9a8b71
DA		 1207 if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) {
1208 connector->null_edid_counter++;
1209 goto carp;
1210 }
61e57a8d
AJ		 1211 }
1212 if (i == 4)
1213 goto carp;
1214
1215 /* if there's no extensions, we're done */
1216 if (block[0x7e] == 0)
1217 return block;
1218
1219 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL);
1220 if (!new)
1221 goto out;
1222 block = new;
1223
1224 for (j = 1; j <= block[0x7e]; j++) {
1225 for (i = 0; i < 4; i++) {
0ea75e23
ST		 1226 if (drm_do_probe_ddc_edid(adapter,
1227 block + (valid_extensions + 1) * EDID_LENGTH,
1228 j, EDID_LENGTH))
61e57a8d 1229 goto out;
0b2443ed 1230 if (drm_edid_block_valid(block + (valid_extensions + 1) * EDID_LENGTH, j, print_bad_edid)) {
0ea75e23 1231 valid_extensions++;
61e57a8d 1232 break;
0ea75e23 1233 }
61e57a8d 1234 }
f934ec8c
ML		 1235
1236 if (i == 4 && print_bad_edid) {
0ea75e23
ST		 1237 dev_warn(connector->dev->dev,
1238 "%s: Ignoring invalid EDID block %d.\n",
25933820 1239 connector->name, j);
f934ec8c
ML		 1240
1241 connector->bad_edid_counter++;
1242 }
0ea75e23
ST		 1243 }
1244
1245 if (valid_extensions != block[0x7e]) {
1246 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions;
1247 block[0x7e] = valid_extensions;
1248 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1249 if (!new)
1250 goto out;
1251 block = new;
61e57a8d
AJ		 1252 }
1253
1254 return block;
1255
1256carp:
0b2443ed
JG		 1257 if (print_bad_edid) {
1258 dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n",
25933820 1259 connector->name, j);
0b2443ed
JG		 1260 }
1261 connector->bad_edid_counter++;
61e57a8d
AJ		 1262
1263out:
1264 kfree(block);
1265 return NULL;
1266}
1267
1268/**
db6cf833
TR		 1269 * drm_probe_ddc() - probe DDC presence
1270 * @adapter: I2C adapter to probe
fc66811c 1271 *
db6cf833 1272 * Return: True on success, false on failure.
61e57a8d 1273 */
fbff4690 1274bool
61e57a8d
AJ		 1275drm_probe_ddc(struct i2c_adapter *adapter)
1276{
1277 unsigned char out;
1278
1279 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1280}
fbff4690 1281EXPORT_SYMBOL(drm_probe_ddc);
61e57a8d
AJ		 1282
1283/**
1284 * drm_get_edid - get EDID data, if available
1285 * @connector: connector we're probing
db6cf833 1286 * @adapter: I2C adapter to use for DDC
61e57a8d 1287 *
db6cf833 1288 * Poke the given I2C channel to grab EDID data if possible. If found,
61e57a8d
AJ		 1289 * attach it to the connector.
1290 *
db6cf833 1291 * Return: Pointer to valid EDID or NULL if we couldn't find any.
61e57a8d
AJ		 1292 */
1293struct edid *drm_get_edid(struct drm_connector *connector,
1294 struct i2c_adapter *adapter)
1295{
1296 struct edid *edid = NULL;
1297
1298 if (drm_probe_ddc(adapter))
1299 edid = (struct edid *)drm_do_get_edid(connector, adapter);
1300
61e57a8d 1301 return edid;
61e57a8d
AJ		 1302}
1303EXPORT_SYMBOL(drm_get_edid);
1304
51f8da59
JN		 1305/**
1306 * drm_edid_duplicate - duplicate an EDID and the extensions
1307 * @edid: EDID to duplicate
1308 *
db6cf833 1309 * Return: Pointer to duplicated EDID or NULL on allocation failure.
51f8da59
JN		 1310 */
1311struct edid *drm_edid_duplicate(const struct edid *edid)
1312{
1313 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1314}
1315EXPORT_SYMBOL(drm_edid_duplicate);
1316
61e57a8d
AJ		 1317/*** EDID parsing ***/
1318
f453ba04
DA		 1319/**
1320 * edid_vendor - match a string against EDID's obfuscated vendor field
1321 * @edid: EDID to match
1322 * @vendor: vendor string
1323 *
1324 * Returns true if @vendor is in @edid, false otherwise
1325 */
1326static bool edid_vendor(struct edid *edid, char *vendor)
1327{
1328 char edid_vendor[3];
1329
1330 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1331 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1332 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
16456c87 1333 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
f453ba04
DA		 1334
1335 return !strncmp(edid_vendor, vendor, 3);
1336}
1337
1338/**
1339 * edid_get_quirks - return quirk flags for a given EDID
1340 * @edid: EDID to process
1341 *
1342 * This tells subsequent routines what fixes they need to apply.
1343 */
1344static u32 edid_get_quirks(struct edid *edid)
1345{
1346 struct edid_quirk *quirk;
1347 int i;
1348
1349 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1350 quirk = &edid_quirk_list[i];
1351
1352 if (edid_vendor(edid, quirk->vendor) &&
1353 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1354 return quirk->quirks;
1355 }
1356
1357 return 0;
1358}
1359
1360#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
339d202c 1361#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
f453ba04 1362
f453ba04
DA		 1363/**
1364 * edid_fixup_preferred - set preferred modes based on quirk list
1365 * @connector: has mode list to fix up
1366 * @quirks: quirks list
1367 *
1368 * Walk the mode list for @connector, clearing the preferred status
1369 * on existing modes and setting it anew for the right mode ala @quirks.
1370 */
1371static void edid_fixup_preferred(struct drm_connector *connector,
1372 u32 quirks)
1373{
1374 struct drm_display_mode *t, *cur_mode, *preferred_mode;
f890607b 1375 int target_refresh = 0;
339d202c 1376 int cur_vrefresh, preferred_vrefresh;
f453ba04
DA		 1377
1378 if (list_empty(&connector->probed_modes))
1379 return;
1380
1381 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1382 target_refresh = 60;
1383 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1384 target_refresh = 75;
1385
1386 preferred_mode = list_first_entry(&connector->probed_modes,
1387 struct drm_display_mode, head);
1388
1389 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1390 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1391
1392 if (cur_mode == preferred_mode)
1393 continue;
1394
1395 /* Largest mode is preferred */
1396 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1397 preferred_mode = cur_mode;
1398
339d202c
AD		 1399 cur_vrefresh = cur_mode->vrefresh ?
1400 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1401 preferred_vrefresh = preferred_mode->vrefresh ?
1402 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
f453ba04
DA		 1403 /* At a given size, try to get closest to target refresh */
1404 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
339d202c
AD		 1405 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1406 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
f453ba04
DA		 1407 preferred_mode = cur_mode;
1408 }
1409 }
1410
1411 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1412}
1413
f6e252ba
AJ		 1414static bool
1415mode_is_rb(const struct drm_display_mode *mode)
1416{
1417 return (mode->htotal - mode->hdisplay == 160) &&
1418 (mode->hsync_end - mode->hdisplay == 80) &&
1419 (mode->hsync_end - mode->hsync_start == 32) &&
1420 (mode->vsync_start - mode->vdisplay == 3);
1421}
1422
33c7531d
AJ		 1423/*
1424 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1425 * @dev: Device to duplicate against
1426 * @hsize: Mode width
1427 * @vsize: Mode height
1428 * @fresh: Mode refresh rate
f6e252ba 1429 * @rb: Mode reduced-blanking-ness
33c7531d
AJ		 1430 *
1431 * Walk the DMT mode list looking for a match for the given parameters.
db6cf833
TR		 1432 *
1433 * Return: A newly allocated copy of the mode, or NULL if not found.
33c7531d 1434 */
1d42bbc8 1435struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
f6e252ba
AJ		 1436 int hsize, int vsize, int fresh,
1437 bool rb)
559ee21d 1438{
07a5e632 1439 int i;
559ee21d 1440
a6b21831 1441 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
b1f559ec 1442 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
f8b46a05
AJ		 1443 if (hsize != ptr->hdisplay)
1444 continue;
1445 if (vsize != ptr->vdisplay)
1446 continue;
1447 if (fresh != drm_mode_vrefresh(ptr))
1448 continue;
f6e252ba
AJ		 1449 if (rb != mode_is_rb(ptr))
1450 continue;
f8b46a05
AJ		 1451
1452 return drm_mode_duplicate(dev, ptr);
559ee21d 1453 }
f8b46a05
AJ		 1454
1455 return NULL;
559ee21d 1456}
1d42bbc8 1457EXPORT_SYMBOL(drm_mode_find_dmt);
23425cae 1458
d1ff6409
AJ		 1459typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1460
4d76a221
AJ		 1461static void
1462cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1463{
1464 int i, n = 0;
4966b2a9 1465 u8 d = ext[0x02];
4d76a221
AJ		 1466 u8 *det_base = ext + d;
1467
4966b2a9 1468 n = (127 - d) / 18;
4d76a221
AJ		 1469 for (i = 0; i < n; i++)
1470 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1471}
1472
cbba98f8
AJ		 1473static void
1474vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1475{
1476 unsigned int i, n = min((int)ext[0x02], 6);
1477 u8 *det_base = ext + 5;
1478
1479 if (ext[0x01] != 1)
1480 return; /* unknown version */
1481
1482 for (i = 0; i < n; i++)
1483 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1484}
1485
d1ff6409
AJ		 1486static void
1487drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1488{
1489 int i;
1490 struct edid *edid = (struct edid *)raw_edid;
1491
1492 if (edid == NULL)
1493 return;
1494
1495 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1496 cb(&(edid->detailed_timings[i]), closure);
1497
4d76a221
AJ		 1498 for (i = 1; i <= raw_edid[0x7e]; i++) {
1499 u8 *ext = raw_edid + (i * EDID_LENGTH);
1500 switch (*ext) {
1501 case CEA_EXT:
1502 cea_for_each_detailed_block(ext, cb, closure);
1503 break;
cbba98f8
AJ		 1504 case VTB_EXT:
1505 vtb_for_each_detailed_block(ext, cb, closure);
1506 break;
4d76a221
AJ		 1507 default:
1508 break;
1509 }
1510 }
d1ff6409
AJ		 1511}
1512
1513static void
1514is_rb(struct detailed_timing *t, void *data)
1515{
1516 u8 *r = (u8 *)t;
1517 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
1518 if (r[15] & 0x10)
1519 *(bool *)data = true;
1520}
1521
1522/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
1523static bool
1524drm_monitor_supports_rb(struct edid *edid)
1525{
1526 if (edid->revision >= 4) {
b196a498 1527 bool ret = false;
d1ff6409
AJ		 1528 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
1529 return ret;
1530 }
1531
1532 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
1533}
1534
7a374350
AJ		 1535static void
1536find_gtf2(struct detailed_timing *t, void *data)
1537{
1538 u8 *r = (u8 *)t;
1539 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
1540 *(u8 **)data = r;
1541}
1542
1543/* Secondary GTF curve kicks in above some break frequency */
1544static int
1545drm_gtf2_hbreak(struct edid *edid)
1546{
1547 u8 *r = NULL;
1548 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1549 return r ? (r[12] * 2) : 0;
1550}
1551
1552static int
1553drm_gtf2_2c(struct edid *edid)
1554{
1555 u8 *r = NULL;
1556 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1557 return r ? r[13] : 0;
1558}
1559
1560static int
1561drm_gtf2_m(struct edid *edid)
1562{
1563 u8 *r = NULL;
1564 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1565 return r ? (r[15] << 8) + r[14] : 0;
1566}
1567
1568static int
1569drm_gtf2_k(struct edid *edid)
1570{
1571 u8 *r = NULL;
1572 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1573 return r ? r[16] : 0;
1574}
1575
1576static int
1577drm_gtf2_2j(struct edid *edid)
1578{
1579 u8 *r = NULL;
1580 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1581 return r ? r[17] : 0;
1582}
1583
1584/**
1585 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
1586 * @edid: EDID block to scan
1587 */
1588static int standard_timing_level(struct edid *edid)
1589{
1590 if (edid->revision >= 2) {
1591 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
1592 return LEVEL_CVT;
1593 if (drm_gtf2_hbreak(edid))
1594 return LEVEL_GTF2;
1595 return LEVEL_GTF;
1596 }
1597 return LEVEL_DMT;
1598}
1599
23425cae
AJ		 1600/*
1601 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
1602 * monitors fill with ascii space (0x20) instead.
1603 */
1604static int
1605bad_std_timing(u8 a, u8 b)
1606{
1607 return (a == 0x00 && b == 0x00) ||
1608 (a == 0x01 && b == 0x01) ||
1609 (a == 0x20 && b == 0x20);
1610}
1611
f453ba04
DA		 1612/**
1613 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
fc66811c
DV		 1614 * @connector: connector of for the EDID block
1615 * @edid: EDID block to scan
f453ba04
DA		 1616 * @t: standard timing params
1617 *
1618 * Take the standard timing params (in this case width, aspect, and refresh)
5c61259e 1619 * and convert them into a real mode using CVT/GTF/DMT.
f453ba04 1620 */
7ca6adb3 1621static struct drm_display_mode *
7a374350 1622drm_mode_std(struct drm_connector *connector, struct edid *edid,
464fdeca 1623 struct std_timing *t)
f453ba04 1624{
7ca6adb3
AJ		 1625 struct drm_device *dev = connector->dev;
1626 struct drm_display_mode *m, *mode = NULL;
5c61259e
ZY		 1627 int hsize, vsize;
1628 int vrefresh_rate;
0454beab
MD		 1629 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
1630 >> EDID_TIMING_ASPECT_SHIFT;
5c61259e
ZY		 1631 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
1632 >> EDID_TIMING_VFREQ_SHIFT;
7a374350 1633 int timing_level = standard_timing_level(edid);
5c61259e 1634
23425cae
AJ		 1635 if (bad_std_timing(t->hsize, t->vfreq_aspect))
1636 return NULL;
1637
5c61259e
ZY		 1638 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
1639 hsize = t->hsize * 8 + 248;
1640 /* vrefresh_rate = vfreq + 60 */
1641 vrefresh_rate = vfreq + 60;
1642 /* the vdisplay is calculated based on the aspect ratio */
f066a17d 1643 if (aspect_ratio == 0) {
464fdeca 1644 if (edid->revision < 3)
f066a17d
AJ		 1645 vsize = hsize;
1646 else
1647 vsize = (hsize * 10) / 16;
1648 } else if (aspect_ratio == 1)
f453ba04 1649 vsize = (hsize * 3) / 4;
0454beab 1650 else if (aspect_ratio == 2)
f453ba04
DA		 1651 vsize = (hsize * 4) / 5;
1652 else
1653 vsize = (hsize * 9) / 16;
a0910c8e
AJ		 1654
1655 /* HDTV hack, part 1 */
1656 if (vrefresh_rate == 60 &&
1657 ((hsize == 1360 && vsize == 765) ||
1658 (hsize == 1368 && vsize == 769))) {
1659 hsize = 1366;
1660 vsize = 768;
1661 }
1662
7ca6adb3
AJ		 1663 /*
1664 * If this connector already has a mode for this size and refresh
1665 * rate (because it came from detailed or CVT info), use that
1666 * instead. This way we don't have to guess at interlace or
1667 * reduced blanking.
1668 */
522032da 1669 list_for_each_entry(m, &connector->probed_modes, head)
7ca6adb3
AJ		 1670 if (m->hdisplay == hsize && m->vdisplay == vsize &&
1671 drm_mode_vrefresh(m) == vrefresh_rate)
1672 return NULL;
1673
a0910c8e
AJ		 1674 /* HDTV hack, part 2 */
1675 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
1676 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
d50ba256 1677 false);
559ee21d 1678 mode->hdisplay = 1366;
a4967de6
AJ		 1679 mode->hsync_start = mode->hsync_start - 1;
1680 mode->hsync_end = mode->hsync_end - 1;
559ee21d
ZY		 1681 return mode;
1682 }
a0910c8e 1683
559ee21d 1684 /* check whether it can be found in default mode table */
f6e252ba
AJ		 1685 if (drm_monitor_supports_rb(edid)) {
1686 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
1687 true);
1688 if (mode)
1689 return mode;
1690 }
1691 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
559ee21d
ZY		 1692 if (mode)
1693 return mode;
1694
f6e252ba 1695 /* okay, generate it */
5c61259e
ZY		 1696 switch (timing_level) {
1697 case LEVEL_DMT:
5c61259e
ZY		 1698 break;
1699 case LEVEL_GTF:
1700 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
1701 break;
7a374350
AJ		 1702 case LEVEL_GTF2:
1703 /*
1704 * This is potentially wrong if there's ever a monitor with
1705 * more than one ranges section, each claiming a different
1706 * secondary GTF curve. Please don't do that.
1707 */
1708 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
fc48f169
TI		 1709 if (!mode)
1710 return NULL;
7a374350 1711 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
aefd330e 1712 drm_mode_destroy(dev, mode);
7a374350
AJ		 1713 mode = drm_gtf_mode_complex(dev, hsize, vsize,
1714 vrefresh_rate, 0, 0,
1715 drm_gtf2_m(edid),
1716 drm_gtf2_2c(edid),
1717 drm_gtf2_k(edid),
1718 drm_gtf2_2j(edid));
1719 }
1720 break;
5c61259e 1721 case LEVEL_CVT:
d50ba256
DA		 1722 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
1723 false);
5c61259e
ZY		 1724 break;
1725 }
f453ba04
DA		 1726 return mode;
1727}
1728
b58db2c6
AJ		 1729/*
1730 * EDID is delightfully ambiguous about how interlaced modes are to be
1731 * encoded. Our internal representation is of frame height, but some
1732 * HDTV detailed timings are encoded as field height.
1733 *
1734 * The format list here is from CEA, in frame size. Technically we
1735 * should be checking refresh rate too. Whatever.
1736 */
1737static void
1738drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
1739 struct detailed_pixel_timing *pt)
1740{
1741 int i;
1742 static const struct {
1743 int w, h;
1744 } cea_interlaced[] = {
1745 { 1920, 1080 },
1746 { 720, 480 },
1747 { 1440, 480 },
1748 { 2880, 480 },
1749 { 720, 576 },
1750 { 1440, 576 },
1751 { 2880, 576 },
1752 };
b58db2c6
AJ		 1753
1754 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
1755 return;
1756
3c581411 1757 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
b58db2c6
AJ		 1758 if ((mode->hdisplay == cea_interlaced[i].w) &&
1759 (mode->vdisplay == cea_interlaced[i].h / 2)) {
1760 mode->vdisplay *= 2;
1761 mode->vsync_start *= 2;
1762 mode->vsync_end *= 2;
1763 mode->vtotal *= 2;
1764 mode->vtotal |= 1;
1765 }
1766 }
1767
1768 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1769}
1770
f453ba04
DA		 1771/**
1772 * drm_mode_detailed - create a new mode from an EDID detailed timing section
1773 * @dev: DRM device (needed to create new mode)
1774 * @edid: EDID block
1775 * @timing: EDID detailed timing info
1776 * @quirks: quirks to apply
1777 *
1778 * An EDID detailed timing block contains enough info for us to create and
1779 * return a new struct drm_display_mode.
1780 */
1781static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
1782 struct edid *edid,
1783 struct detailed_timing *timing,
1784 u32 quirks)
1785{
1786 struct drm_display_mode *mode;
1787 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
0454beab
MD		 1788 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
1789 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
1790 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
1791 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
e14cbee4
MD		 1792 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
1793 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
16dad1d7 1794 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
e14cbee4 1795 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
f453ba04 1796
fc438966 1797 /* ignore tiny modes */
0454beab 1798 if (hactive < 64 || vactive < 64)
fc438966
AJ		 1799 return NULL;
1800
0454beab 1801 if (pt->misc & DRM_EDID_PT_STEREO) {
c7d015f3 1802 DRM_DEBUG_KMS("stereo mode not supported\n");
f453ba04
DA		 1803 return NULL;
1804 }
0454beab 1805 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
c7d015f3 1806 DRM_DEBUG_KMS("composite sync not supported\n");
f453ba04
DA		 1807 }
1808
fcb45611
ZY		 1809 /* it is incorrect if hsync/vsync width is zero */
1810 if (!hsync_pulse_width || !vsync_pulse_width) {
1811 DRM_DEBUG_KMS("Incorrect Detailed timing. "
1812 "Wrong Hsync/Vsync pulse width\n");
1813 return NULL;
1814 }
bc42aabc
AJ		 1815
1816 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
1817 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
1818 if (!mode)
1819 return NULL;
1820
1821 goto set_size;
1822 }
1823
f453ba04
DA		 1824 mode = drm_mode_create(dev);
1825 if (!mode)
1826 return NULL;
1827
f453ba04 1828 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
0454beab
MD		 1829 timing->pixel_clock = cpu_to_le16(1088);
1830
1831 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
1832
1833 mode->hdisplay = hactive;
1834 mode->hsync_start = mode->hdisplay + hsync_offset;
1835 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
1836 mode->htotal = mode->hdisplay + hblank;
1837
1838 mode->vdisplay = vactive;
1839 mode->vsync_start = mode->vdisplay + vsync_offset;
1840 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
1841 mode->vtotal = mode->vdisplay + vblank;
f453ba04 1842
7064fef5
JB		 1843 /* Some EDIDs have bogus h/vtotal values */
1844 if (mode->hsync_end > mode->htotal)
1845 mode->htotal = mode->hsync_end + 1;
1846 if (mode->vsync_end > mode->vtotal)
1847 mode->vtotal = mode->vsync_end + 1;
1848
b58db2c6 1849 drm_mode_do_interlace_quirk(mode, pt);
f453ba04
DA		 1850
1851 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
0454beab 1852 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
f453ba04
DA		 1853 }
1854
0454beab
MD		 1855 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
1856 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
1857 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
1858 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
f453ba04 1859
bc42aabc 1860set_size:
e14cbee4
MD		 1861 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
1862 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
f453ba04
DA		 1863
1864 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
1865 mode->width_mm *= 10;
1866 mode->height_mm *= 10;
1867 }
1868
1869 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
1870 mode->width_mm = edid->width_cm * 10;
1871 mode->height_mm = edid->height_cm * 10;
1872 }
1873
bc42aabc 1874 mode->type = DRM_MODE_TYPE_DRIVER;
c19b3b0f 1875 mode->vrefresh = drm_mode_vrefresh(mode);
bc42aabc
AJ		 1876 drm_mode_set_name(mode);
1877
f453ba04
DA		 1878 return mode;
1879}
1880
b17e52ef 1881static bool
b1f559ec
CW		 1882mode_in_hsync_range(const struct drm_display_mode *mode,
1883 struct edid *edid, u8 *t)
b17e52ef
AJ		 1884{
1885 int hsync, hmin, hmax;
1886
1887 hmin = t[7];
1888 if (edid->revision >= 4)
1889 hmin += ((t[4] & 0x04) ? 255 : 0);
1890 hmax = t[8];
1891 if (edid->revision >= 4)
1892 hmax += ((t[4] & 0x08) ? 255 : 0);
07a5e632 1893 hsync = drm_mode_hsync(mode);
07a5e632 1894
b17e52ef
AJ		 1895 return (hsync <= hmax && hsync >= hmin);
1896}
1897
1898static bool
b1f559ec
CW		 1899mode_in_vsync_range(const struct drm_display_mode *mode,
1900 struct edid *edid, u8 *t)
b17e52ef
AJ		 1901{
1902 int vsync, vmin, vmax;
1903
1904 vmin = t[5];
1905 if (edid->revision >= 4)
1906 vmin += ((t[4] & 0x01) ? 255 : 0);
1907 vmax = t[6];
1908 if (edid->revision >= 4)
1909 vmax += ((t[4] & 0x02) ? 255 : 0);
1910 vsync = drm_mode_vrefresh(mode);
1911
1912 return (vsync <= vmax && vsync >= vmin);
1913}
1914
1915static u32
1916range_pixel_clock(struct edid *edid, u8 *t)
1917{
1918 /* unspecified */
1919 if (t[9] == 0 || t[9] == 255)
1920 return 0;
1921
1922 /* 1.4 with CVT support gives us real precision, yay */
1923 if (edid->revision >= 4 && t[10] == 0x04)
1924 return (t[9] * 10000) - ((t[12] >> 2) * 250);
1925
1926 /* 1.3 is pathetic, so fuzz up a bit */
1927 return t[9] * 10000 + 5001;
1928}
1929
b17e52ef 1930static bool
b1f559ec 1931mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
b17e52ef
AJ		 1932 struct detailed_timing *timing)
1933{
1934 u32 max_clock;
1935 u8 *t = (u8 *)timing;
1936
1937 if (!mode_in_hsync_range(mode, edid, t))
07a5e632
AJ		 1938 return false;
1939
b17e52ef 1940 if (!mode_in_vsync_range(mode, edid, t))
07a5e632
AJ		 1941 return false;
1942
b17e52ef 1943 if ((max_clock = range_pixel_clock(edid, t)))
07a5e632
AJ		 1944 if (mode->clock > max_clock)
1945 return false;
b17e52ef
AJ		 1946
1947 /* 1.4 max horizontal check */
1948 if (edid->revision >= 4 && t[10] == 0x04)
1949 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
1950 return false;
1951
1952 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
1953 return false;
07a5e632
AJ		 1954
1955 return true;
1956}
1957
7b668ebe
TI		 1958static bool valid_inferred_mode(const struct drm_connector *connector,
1959 const struct drm_display_mode *mode)
1960{
1961 struct drm_display_mode *m;
1962 bool ok = false;
1963
1964 list_for_each_entry(m, &connector->probed_modes, head) {
1965 if (mode->hdisplay == m->hdisplay &&
1966 mode->vdisplay == m->vdisplay &&
1967 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
1968 return false; /* duplicated */
1969 if (mode->hdisplay <= m->hdisplay &&
1970 mode->vdisplay <= m->vdisplay)
1971 ok = true;
1972 }
1973 return ok;
1974}
1975
b17e52ef 1976static int
cd4cd3de 1977drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
b17e52ef 1978 struct detailed_timing *timing)
07a5e632
AJ		 1979{
1980 int i, modes = 0;
1981 struct drm_display_mode *newmode;
1982 struct drm_device *dev = connector->dev;
1983
a6b21831 1984 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
7b668ebe
TI		 1985 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
1986 valid_inferred_mode(connector, drm_dmt_modes + i)) {
07a5e632
AJ		 1987 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
1988 if (newmode) {
1989 drm_mode_probed_add(connector, newmode);
1990 modes++;
1991 }
1992 }
1993 }
1994
1995 return modes;
1996}
1997
c09dedb7
TI		 1998/* fix up 1366x768 mode from 1368x768;
1999 * GFT/CVT can't express 1366 width which isn't dividable by 8
2000 */
2001static void fixup_mode_1366x768(struct drm_display_mode *mode)
2002{
2003 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2004 mode->hdisplay = 1366;
2005 mode->hsync_start--;
2006 mode->hsync_end--;
2007 drm_mode_set_name(mode);
2008 }
2009}
2010
b309bd37
AJ		 2011static int
2012drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2013 struct detailed_timing *timing)
2014{
2015 int i, modes = 0;
2016 struct drm_display_mode *newmode;
2017 struct drm_device *dev = connector->dev;
2018
a6b21831 2019 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37
AJ		 2020 const struct minimode *m = &extra_modes[i];
2021 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
fc48f169
TI		 2022 if (!newmode)
2023 return modes;
b309bd37 2024
c09dedb7 2025 fixup_mode_1366x768(newmode);
7b668ebe
TI		 2026 if (!mode_in_range(newmode, edid, timing) ||
2027 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 2028 drm_mode_destroy(dev, newmode);
2029 continue;
2030 }
2031
2032 drm_mode_probed_add(connector, newmode);
2033 modes++;
2034 }
2035
2036 return modes;
2037}
2038
2039static int
2040drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2041 struct detailed_timing *timing)
2042{
2043 int i, modes = 0;
2044 struct drm_display_mode *newmode;
2045 struct drm_device *dev = connector->dev;
2046 bool rb = drm_monitor_supports_rb(edid);
2047
a6b21831 2048 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37
AJ		 2049 const struct minimode *m = &extra_modes[i];
2050 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
fc48f169
TI		 2051 if (!newmode)
2052 return modes;
b309bd37 2053
c09dedb7 2054 fixup_mode_1366x768(newmode);
7b668ebe
TI		 2055 if (!mode_in_range(newmode, edid, timing) ||
2056 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 2057 drm_mode_destroy(dev, newmode);
2058 continue;
2059 }
2060
2061 drm_mode_probed_add(connector, newmode);
2062 modes++;
2063 }
2064
2065 return modes;
2066}
2067
13931579
AJ		 2068static void
2069do_inferred_modes(struct detailed_timing *timing, void *c)
9340d8cf 2070{
13931579
AJ		 2071 struct detailed_mode_closure *closure = c;
2072 struct detailed_non_pixel *data = &timing->data.other_data;
b309bd37 2073 struct detailed_data_monitor_range *range = &data->data.range;
9340d8cf 2074
cb21aafe
AJ		 2075 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2076 return;
2077
2078 closure->modes += drm_dmt_modes_for_range(closure->connector,
2079 closure->edid,
2080 timing);
b309bd37
AJ		 2081
2082 if (!version_greater(closure->edid, 1, 1))
2083 return; /* GTF not defined yet */
2084
2085 switch (range->flags) {
2086 case 0x02: /* secondary gtf, XXX could do more */
2087 case 0x00: /* default gtf */
2088 closure->modes += drm_gtf_modes_for_range(closure->connector,
2089 closure->edid,
2090 timing);
2091 break;
2092 case 0x04: /* cvt, only in 1.4+ */
2093 if (!version_greater(closure->edid, 1, 3))
2094 break;
2095
2096 closure->modes += drm_cvt_modes_for_range(closure->connector,
2097 closure->edid,
2098 timing);
2099 break;
2100 case 0x01: /* just the ranges, no formula */
2101 default:
2102 break;
2103 }
13931579 2104}
69da3015 2105
13931579
AJ		 2106static int
2107add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2108{
2109 struct detailed_mode_closure closure = {
d456ea2e
JL		 2110 .connector = connector,
2111 .edid = edid,
13931579 2112 };
9340d8cf 2113
13931579
AJ		 2114 if (version_greater(edid, 1, 0))
2115 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2116 &closure);
9340d8cf 2117
13931579 2118 return closure.modes;
9340d8cf
AJ		 2119}
2120
2255be14
AJ		 2121static int
2122drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2123{
2124 int i, j, m, modes = 0;
2125 struct drm_display_mode *mode;
2126 u8 *est = ((u8 *)timing) + 5;
2127
2128 for (i = 0; i < 6; i++) {
891a7469 2129 for (j = 7; j >= 0; j--) {
2255be14 2130 m = (i * 8) + (7 - j);
3c581411 2131 if (m >= ARRAY_SIZE(est3_modes))
2255be14
AJ		 2132 break;
2133 if (est[i] & (1 << j)) {
1d42bbc8
DA		 2134 mode = drm_mode_find_dmt(connector->dev,
2135 est3_modes[m].w,
2136 est3_modes[m].h,
f6e252ba
AJ		 2137 est3_modes[m].r,
2138 est3_modes[m].rb);
2255be14
AJ		 2139 if (mode) {
2140 drm_mode_probed_add(connector, mode);
2141 modes++;
2142 }
2143 }
2144 }
2145 }
2146
2147 return modes;
2148}
2149
13931579
AJ		 2150static void
2151do_established_modes(struct detailed_timing *timing, void *c)
9cf00977 2152{
13931579 2153 struct detailed_mode_closure *closure = c;
9cf00977 2154 struct detailed_non_pixel *data = &timing->data.other_data;
9cf00977 2155
13931579
AJ		 2156 if (data->type == EDID_DETAIL_EST_TIMINGS)
2157 closure->modes += drm_est3_modes(closure->connector, timing);
2158}
9cf00977 2159
13931579
AJ		 2160/**
2161 * add_established_modes - get est. modes from EDID and add them
db6cf833 2162 * @connector: connector to add mode(s) to
13931579
AJ		 2163 * @edid: EDID block to scan
2164 *
2165 * Each EDID block contains a bitmap of the supported "established modes" list
2166 * (defined above). Tease them out and add them to the global modes list.
2167 */
2168static int
2169add_established_modes(struct drm_connector *connector, struct edid *edid)
2170{
2171 struct drm_device *dev = connector->dev;
2172 unsigned long est_bits = edid->established_timings.t1 |
2173 (edid->established_timings.t2 << 8) |
2174 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2175 int i, modes = 0;
2176 struct detailed_mode_closure closure = {
d456ea2e
JL		 2177 .connector = connector,
2178 .edid = edid,
13931579 2179 };
9cf00977 2180
13931579
AJ		 2181 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2182 if (est_bits & (1<<i)) {
2183 struct drm_display_mode *newmode;
2184 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2185 if (newmode) {
2186 drm_mode_probed_add(connector, newmode);
2187 modes++;
2188 }
2189 }
9cf00977
AJ		 2190 }
2191
13931579
AJ		 2192 if (version_greater(edid, 1, 0))
2193 drm_for_each_detailed_block((u8 *)edid,
2194 do_established_modes, &closure);
2195
2196 return modes + closure.modes;
2197}
2198
2199static void
2200do_standard_modes(struct detailed_timing *timing, void *c)
2201{
2202 struct detailed_mode_closure *closure = c;
2203 struct detailed_non_pixel *data = &timing->data.other_data;
2204 struct drm_connector *connector = closure->connector;
2205 struct edid *edid = closure->edid;
2206
2207 if (data->type == EDID_DETAIL_STD_MODES) {
2208 int i;
9cf00977
AJ		 2209 for (i = 0; i < 6; i++) {
2210 struct std_timing *std;
2211 struct drm_display_mode *newmode;
2212
2213 std = &data->data.timings[i];
464fdeca 2214 newmode = drm_mode_std(connector, edid, std);
9cf00977
AJ		 2215 if (newmode) {
2216 drm_mode_probed_add(connector, newmode);
13931579 2217 closure->modes++;
9cf00977
AJ		 2218 }
2219 }
9cf00977 2220 }
9cf00977
AJ		 2221}
2222
f453ba04 2223/**
13931579 2224 * add_standard_modes - get std. modes from EDID and add them
db6cf833 2225 * @connector: connector to add mode(s) to
f453ba04 2226 * @edid: EDID block to scan
f453ba04 2227 *
13931579
AJ		 2228 * Standard modes can be calculated using the appropriate standard (DMT,
2229 * GTF or CVT. Grab them from @edid and add them to the list.
f453ba04 2230 */
13931579
AJ		 2231static int
2232add_standard_modes(struct drm_connector *connector, struct edid *edid)
f453ba04 2233{
9cf00977 2234 int i, modes = 0;
13931579 2235 struct detailed_mode_closure closure = {
d456ea2e
JL		 2236 .connector = connector,
2237 .edid = edid,
13931579
AJ		 2238 };
2239
2240 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2241 struct drm_display_mode *newmode;
2242
2243 newmode = drm_mode_std(connector, edid,
464fdeca 2244 &edid->standard_timings[i]);
13931579
AJ		 2245 if (newmode) {
2246 drm_mode_probed_add(connector, newmode);
2247 modes++;
2248 }
2249 }
2250
2251 if (version_greater(edid, 1, 0))
2252 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2253 &closure);
2254
2255 /* XXX should also look for standard codes in VTB blocks */
2256
2257 return modes + closure.modes;
2258}
f453ba04 2259
13931579
AJ		 2260static int drm_cvt_modes(struct drm_connector *connector,
2261 struct detailed_timing *timing)
2262{
2263 int i, j, modes = 0;
2264 struct drm_display_mode *newmode;
2265 struct drm_device *dev = connector->dev;
2266 struct cvt_timing *cvt;
2267 const int rates[] = { 60, 85, 75, 60, 50 };
2268 const u8 empty[3] = { 0, 0, 0 };
a327f6b8 2269
13931579
AJ		 2270 for (i = 0; i < 4; i++) {
2271 int uninitialized_var(width), height;
2272 cvt = &(timing->data.other_data.data.cvt[i]);
f453ba04 2273
13931579 2274 if (!memcmp(cvt->code, empty, 3))
9cf00977 2275 continue;
f453ba04 2276
13931579
AJ		 2277 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2278 switch (cvt->code[1] & 0x0c) {
2279 case 0x00:
2280 width = height * 4 / 3;
2281 break;
2282 case 0x04:
2283 width = height * 16 / 9;
2284 break;
2285 case 0x08:
2286 width = height * 16 / 10;
2287 break;
2288 case 0x0c:
2289 width = height * 15 / 9;
2290 break;
2291 }
2292
2293 for (j = 1; j < 5; j++) {
2294 if (cvt->code[2] & (1 << j)) {
2295 newmode = drm_cvt_mode(dev, width, height,
2296 rates[j], j == 0,
2297 false, false);
2298 if (newmode) {
2299 drm_mode_probed_add(connector, newmode);
2300 modes++;
2301 }
2302 }
2303 }
f453ba04
DA		 2304 }
2305
2306 return modes;
2307}
9cf00977 2308
13931579
AJ		 2309static void
2310do_cvt_mode(struct detailed_timing *timing, void *c)
882f0219 2311{
13931579
AJ		 2312 struct detailed_mode_closure *closure = c;
2313 struct detailed_non_pixel *data = &timing->data.other_data;
882f0219 2314
13931579
AJ		 2315 if (data->type == EDID_DETAIL_CVT_3BYTE)
2316 closure->modes += drm_cvt_modes(closure->connector, timing);
2317}
882f0219 2318
13931579
AJ		 2319static int
2320add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2321{
2322 struct detailed_mode_closure closure = {
d456ea2e
JL		 2323 .connector = connector,
2324 .edid = edid,
13931579 2325 };
882f0219 2326
13931579
AJ		 2327 if (version_greater(edid, 1, 2))
2328 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
882f0219 2329
13931579 2330 /* XXX should also look for CVT codes in VTB blocks */
882f0219 2331
13931579
AJ		 2332 return closure.modes;
2333}
2334
2335static void
2336do_detailed_mode(struct detailed_timing *timing, void *c)
2337{
2338 struct detailed_mode_closure *closure = c;
2339 struct drm_display_mode *newmode;
2340
2341 if (timing->pixel_clock) {
2342 newmode = drm_mode_detailed(closure->connector->dev,
2343 closure->edid, timing,
2344 closure->quirks);
2345 if (!newmode)
2346 return;
2347
2348 if (closure->preferred)
2349 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2350
2351 drm_mode_probed_add(closure->connector, newmode);
2352 closure->modes++;
2353 closure->preferred = 0;
882f0219 2354 }
13931579 2355}
882f0219 2356
13931579
AJ		 2357/*
2358 * add_detailed_modes - Add modes from detailed timings
2359 * @connector: attached connector
2360 * @edid: EDID block to scan
2361 * @quirks: quirks to apply
2362 */
2363static int
2364add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2365 u32 quirks)
2366{
2367 struct detailed_mode_closure closure = {
d456ea2e
JL		 2368 .connector = connector,
2369 .edid = edid,
2370 .preferred = 1,
2371 .quirks = quirks,
13931579
AJ		 2372 };
2373
2374 if (closure.preferred && !version_greater(edid, 1, 3))
2375 closure.preferred =
2376 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2377
2378 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2379
2380 return closure.modes;
882f0219 2381}
f453ba04 2382
8fe9790d 2383#define AUDIO_BLOCK 0x01
54ac76f8 2384#define VIDEO_BLOCK 0x02
f23c20c8 2385#define VENDOR_BLOCK 0x03
76adaa34 2386#define SPEAKER_BLOCK 0x04
b1edd6a6 2387#define VIDEO_CAPABILITY_BLOCK 0x07
8fe9790d 2388#define EDID_BASIC_AUDIO (1 << 6)
a988bc72
LPC		 2389#define EDID_CEA_YCRCB444 (1 << 5)
2390#define EDID_CEA_YCRCB422 (1 << 4)
b1edd6a6 2391#define EDID_CEA_VCDB_QS (1 << 6)
8fe9790d 2392
d4e4a31d 2393/*
8fe9790d 2394 * Search EDID for CEA extension block.
f23c20c8 2395 */
d4e4a31d 2396static u8 *drm_find_cea_extension(struct edid *edid)
f23c20c8 2397{
8fe9790d
ZW		 2398 u8 *edid_ext = NULL;
2399 int i;
f23c20c8
ML		 2400
2401 /* No EDID or EDID extensions */
2402 if (edid == NULL || edid->extensions == 0)
8fe9790d 2403 return NULL;
f23c20c8 2404
f23c20c8 2405 /* Find CEA extension */
7466f4cc 2406 for (i = 0; i < edid->extensions; i++) {
8fe9790d
ZW		 2407 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
2408 if (edid_ext[0] == CEA_EXT)
f23c20c8
ML		 2409 break;
2410 }
2411
7466f4cc 2412 if (i == edid->extensions)
8fe9790d
ZW		 2413 return NULL;
2414
2415 return edid_ext;
2416}
2417
e6e79209
VS		 2418/*
2419 * Calculate the alternate clock for the CEA mode
2420 * (60Hz vs. 59.94Hz etc.)
2421 */
2422static unsigned int
2423cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2424{
2425 unsigned int clock = cea_mode->clock;
2426
2427 if (cea_mode->vrefresh % 6 != 0)
2428 return clock;
2429
2430 /*
2431 * edid_cea_modes contains the 59.94Hz
2432 * variant for 240 and 480 line modes,
2433 * and the 60Hz variant otherwise.
2434 */
2435 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
2436 clock = clock * 1001 / 1000;
2437 else
2438 clock = DIV_ROUND_UP(clock * 1000, 1001);
2439
2440 return clock;
2441}
2442
18316c8c
TR		 2443/**
2444 * drm_match_cea_mode - look for a CEA mode matching given mode
2445 * @to_match: display mode
2446 *
db6cf833 2447 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
18316c8c 2448 * mode.
a4799037 2449 */
18316c8c 2450u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
a4799037 2451{
a4799037
SM		 2452 u8 mode;
2453
a90b590e
VS		 2454 if (!to_match->clock)
2455 return 0;
2456
a6b21831 2457 for (mode = 0; mode < ARRAY_SIZE(edid_cea_modes); mode++) {
a90b590e
VS		 2458 const struct drm_display_mode *cea_mode = &edid_cea_modes[mode];
2459 unsigned int clock1, clock2;
2460
a90b590e 2461 /* Check both 60Hz and 59.94Hz */
e6e79209
VS		 2462 clock1 = cea_mode->clock;
2463 clock2 = cea_mode_alternate_clock(cea_mode);
a4799037 2464
a90b590e
VS		 2465 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
2466 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
f2ecf2e3 2467 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode))
a4799037
SM		 2468 return mode + 1;
2469 }
2470 return 0;
2471}
2472EXPORT_SYMBOL(drm_match_cea_mode);
2473
0967e6a5
VK		 2474/**
2475 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
2476 * the input VIC from the CEA mode list
2477 * @video_code: ID given to each of the CEA modes
2478 *
2479 * Returns picture aspect ratio
2480 */
2481enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
2482{
2483 /* return picture aspect ratio for video_code - 1 to access the
2484 * right array element
2485 */
2486 return edid_cea_modes[video_code-1].picture_aspect_ratio;
2487}
2488EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
2489
3f2f6533
LD		 2490/*
2491 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
2492 * specific block).
2493 *
2494 * It's almost like cea_mode_alternate_clock(), we just need to add an
2495 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
2496 * one.
2497 */
2498static unsigned int
2499hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
2500{
2501 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
2502 return hdmi_mode->clock;
2503
2504 return cea_mode_alternate_clock(hdmi_mode);
2505}
2506
2507/*
2508 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
2509 * @to_match: display mode
2510 *
2511 * An HDMI mode is one defined in the HDMI vendor specific block.
2512 *
2513 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
2514 */
2515static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
2516{
2517 u8 mode;
2518
2519 if (!to_match->clock)
2520 return 0;
2521
2522 for (mode = 0; mode < ARRAY_SIZE(edid_4k_modes); mode++) {
2523 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[mode];
2524 unsigned int clock1, clock2;
2525
2526 /* Make sure to also match alternate clocks */
2527 clock1 = hdmi_mode->clock;
2528 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
2529
2530 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
2531 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
f2ecf2e3 2532 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode))
3f2f6533
LD		 2533 return mode + 1;
2534 }
2535 return 0;
2536}
2537
e6e79209
VS		 2538static int
2539add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
2540{
2541 struct drm_device *dev = connector->dev;
2542 struct drm_display_mode *mode, *tmp;
2543 LIST_HEAD(list);
2544 int modes = 0;
2545
2546 /* Don't add CEA modes if the CEA extension block is missing */
2547 if (!drm_find_cea_extension(edid))
2548 return 0;
2549
2550 /*
2551 * Go through all probed modes and create a new mode
2552 * with the alternate clock for certain CEA modes.
2553 */
2554 list_for_each_entry(mode, &connector->probed_modes, head) {
3f2f6533 2555 const struct drm_display_mode *cea_mode = NULL;
e6e79209 2556 struct drm_display_mode *newmode;
3f2f6533 2557 u8 mode_idx = drm_match_cea_mode(mode) - 1;
e6e79209
VS		 2558 unsigned int clock1, clock2;
2559
3f2f6533
LD		 2560 if (mode_idx < ARRAY_SIZE(edid_cea_modes)) {
2561 cea_mode = &edid_cea_modes[mode_idx];
2562 clock2 = cea_mode_alternate_clock(cea_mode);
2563 } else {
2564 mode_idx = drm_match_hdmi_mode(mode) - 1;
2565 if (mode_idx < ARRAY_SIZE(edid_4k_modes)) {
2566 cea_mode = &edid_4k_modes[mode_idx];
2567 clock2 = hdmi_mode_alternate_clock(cea_mode);
2568 }
2569 }
e6e79209 2570
3f2f6533
LD		 2571 if (!cea_mode)
2572 continue;
e6e79209
VS		 2573
2574 clock1 = cea_mode->clock;
e6e79209
VS		 2575
2576 if (clock1 == clock2)
2577 continue;
2578
2579 if (mode->clock != clock1 && mode->clock != clock2)
2580 continue;
2581
2582 newmode = drm_mode_duplicate(dev, cea_mode);
2583 if (!newmode)
2584 continue;
2585
27130212
DL		 2586 /* Carry over the stereo flags */
2587 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
2588
e6e79209
VS		 2589 /*
2590 * The current mode could be either variant. Make
2591 * sure to pick the "other" clock for the new mode.
2592 */
2593 if (mode->clock != clock1)
2594 newmode->clock = clock1;
2595 else
2596 newmode->clock = clock2;
2597
2598 list_add_tail(&newmode->head, &list);
2599 }
2600
2601 list_for_each_entry_safe(mode, tmp, &list, head) {
2602 list_del(&mode->head);
2603 drm_mode_probed_add(connector, mode);
2604 modes++;
2605 }
2606
2607 return modes;
2608}
a4799037 2609
aff04ace
TW		 2610static struct drm_display_mode *
2611drm_display_mode_from_vic_index(struct drm_connector *connector,
2612 const u8 *video_db, u8 video_len,
2613 u8 video_index)
54ac76f8
CS		 2614{
2615 struct drm_device *dev = connector->dev;
aff04ace 2616 struct drm_display_mode *newmode;
13ac3f55 2617 u8 cea_mode;
54ac76f8 2618
aff04ace
TW		 2619 if (video_db == NULL || video_index >= video_len)
2620 return NULL;
2621
2622 /* CEA modes are numbered 1..127 */
2623 cea_mode = (video_db[video_index] & 127) - 1;
2624 if (cea_mode >= ARRAY_SIZE(edid_cea_modes))
2625 return NULL;
2626
2627 newmode = drm_mode_duplicate(dev, &edid_cea_modes[cea_mode]);
409bbf1e
DL		 2628 if (!newmode)
2629 return NULL;
2630
aff04ace
TW		 2631 newmode->vrefresh = 0;
2632
2633 return newmode;
2634}
2635
2636static int
2637do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
2638{
2639 int i, modes = 0;
2640
2641 for (i = 0; i < len; i++) {
2642 struct drm_display_mode *mode;
2643 mode = drm_display_mode_from_vic_index(connector, db, len, i);
2644 if (mode) {
2645 drm_mode_probed_add(connector, mode);
2646 modes++;
54ac76f8
CS		 2647 }
2648 }
2649
2650 return modes;
2651}
2652
c858cfca
DL		 2653struct stereo_mandatory_mode {
2654 int width, height, vrefresh;
2655 unsigned int flags;
2656};
2657
2658static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
f7e121b7
DL		 2659 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2660 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
c858cfca
DL		 2661 { 1920, 1080, 50,
2662 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
2663 { 1920, 1080, 60,
2664 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
f7e121b7
DL		 2665 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2666 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
2667 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2668 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
c858cfca
DL		 2669};
2670
2671static bool
2672stereo_match_mandatory(const struct drm_display_mode *mode,
2673 const struct stereo_mandatory_mode *stereo_mode)
2674{
2675 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
2676
2677 return mode->hdisplay == stereo_mode->width &&
2678 mode->vdisplay == stereo_mode->height &&
2679 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
2680 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
2681}
2682
c858cfca
DL		 2683static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
2684{
2685 struct drm_device *dev = connector->dev;
2686 const struct drm_display_mode *mode;
2687 struct list_head stereo_modes;
f7e121b7 2688 int modes = 0, i;
c858cfca
DL		 2689
2690 INIT_LIST_HEAD(&stereo_modes);
2691
2692 list_for_each_entry(mode, &connector->probed_modes, head) {
f7e121b7
DL		 2693 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
2694 const struct stereo_mandatory_mode *mandatory;
c858cfca
DL		 2695 struct drm_display_mode *new_mode;
2696
f7e121b7
DL		 2697 if (!stereo_match_mandatory(mode,
2698 &stereo_mandatory_modes[i]))
2699 continue;
c858cfca 2700
f7e121b7 2701 mandatory = &stereo_mandatory_modes[i];
c858cfca
DL		 2702 new_mode = drm_mode_duplicate(dev, mode);
2703 if (!new_mode)
2704 continue;
2705
f7e121b7 2706 new_mode->flags |= mandatory->flags;
c858cfca
DL		 2707 list_add_tail(&new_mode->head, &stereo_modes);
2708 modes++;
f7e121b7 2709 }
c858cfca
DL		 2710 }
2711
2712 list_splice_tail(&stereo_modes, &connector->probed_modes);
2713
2714 return modes;
2715}
2716
1deee8d7
DL		 2717static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
2718{
2719 struct drm_device *dev = connector->dev;
2720 struct drm_display_mode *newmode;
2721
2722 vic--; /* VICs start at 1 */
2723 if (vic >= ARRAY_SIZE(edid_4k_modes)) {
2724 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
2725 return 0;
2726 }
2727
2728 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
2729 if (!newmode)
2730 return 0;
2731
2732 drm_mode_probed_add(connector, newmode);
2733
2734 return 1;
2735}
2736
fbf46025
TW		 2737static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
2738 const u8 *video_db, u8 video_len, u8 video_index)
2739{
fbf46025
TW		 2740 struct drm_display_mode *newmode;
2741 int modes = 0;
fbf46025
TW		 2742
2743 if (structure & (1 << 0)) {
aff04ace
TW		 2744 newmode = drm_display_mode_from_vic_index(connector, video_db,
2745 video_len,
2746 video_index);
fbf46025
TW		 2747 if (newmode) {
2748 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
2749 drm_mode_probed_add(connector, newmode);
2750 modes++;
2751 }
2752 }
2753 if (structure & (1 << 6)) {
aff04ace
TW		 2754 newmode = drm_display_mode_from_vic_index(connector, video_db,
2755 video_len,
2756 video_index);
fbf46025
TW		 2757 if (newmode) {
2758 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
2759 drm_mode_probed_add(connector, newmode);
2760 modes++;
2761 }
2762 }
2763 if (structure & (1 << 8)) {
aff04ace
TW		 2764 newmode = drm_display_mode_from_vic_index(connector, video_db,
2765 video_len,
2766 video_index);
fbf46025 2767 if (newmode) {
89570eeb 2768 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
fbf46025
TW		 2769 drm_mode_probed_add(connector, newmode);
2770 modes++;
2771 }
2772 }
2773
2774 return modes;
2775}
2776
7ebe1963
LD		 2777/*
2778 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
2779 * @connector: connector corresponding to the HDMI sink
2780 * @db: start of the CEA vendor specific block
2781 * @len: length of the CEA block payload, ie. one can access up to db[len]
2782 *
c858cfca
DL		 2783 * Parses the HDMI VSDB looking for modes to add to @connector. This function
2784 * also adds the stereo 3d modes when applicable.
7ebe1963
LD		 2785 */
2786static int
fbf46025
TW		 2787do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
2788 const u8 *video_db, u8 video_len)
7ebe1963 2789{
0e5083aa 2790 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
fbf46025
TW		 2791 u8 vic_len, hdmi_3d_len = 0;
2792 u16 mask;
2793 u16 structure_all;
7ebe1963
LD		 2794
2795 if (len < 8)
2796 goto out;
2797
2798 /* no HDMI_Video_Present */
2799 if (!(db[8] & (1 << 5)))
2800 goto out;
2801
2802 /* Latency_Fields_Present */
2803 if (db[8] & (1 << 7))
2804 offset += 2;
2805
2806 /* I_Latency_Fields_Present */
2807 if (db[8] & (1 << 6))
2808 offset += 2;
2809
2810 /* the declared length is not long enough for the 2 first bytes
2811 * of additional video format capabilities */
c858cfca 2812 if (len < (8 + offset + 2))
7ebe1963
LD		 2813 goto out;
2814
c858cfca
DL		 2815 /* 3D_Present */
2816 offset++;
fbf46025 2817 if (db[8 + offset] & (1 << 7)) {
c858cfca
DL		 2818 modes += add_hdmi_mandatory_stereo_modes(connector);
2819
fbf46025
TW		 2820 /* 3D_Multi_present */
2821 multi_present = (db[8 + offset] & 0x60) >> 5;
2822 }
2823
c858cfca 2824 offset++;
7ebe1963 2825 vic_len = db[8 + offset] >> 5;
fbf46025 2826 hdmi_3d_len = db[8 + offset] & 0x1f;
7ebe1963
LD		 2827
2828 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
7ebe1963
LD		 2829 u8 vic;
2830
2831 vic = db[9 + offset + i];
1deee8d7 2832 modes += add_hdmi_mode(connector, vic);
7ebe1963 2833 }
fbf46025
TW		 2834 offset += 1 + vic_len;
2835
0e5083aa
TW		 2836 if (multi_present == 1)
2837 multi_len = 2;
2838 else if (multi_present == 2)
2839 multi_len = 4;
2840 else
2841 multi_len = 0;
fbf46025 2842
0e5083aa 2843 if (len < (8 + offset + hdmi_3d_len - 1))
fbf46025
TW		 2844 goto out;
2845
0e5083aa 2846 if (hdmi_3d_len < multi_len)
fbf46025
TW		 2847 goto out;
2848
0e5083aa
TW		 2849 if (multi_present == 1 || multi_present == 2) {
2850 /* 3D_Structure_ALL */
2851 structure_all = (db[8 + offset] << 8) | db[9 + offset];
fbf46025 2852
0e5083aa
TW		 2853 /* check if 3D_MASK is present */
2854 if (multi_present == 2)
2855 mask = (db[10 + offset] << 8) | db[11 + offset];
2856 else
2857 mask = 0xffff;
2858
2859 for (i = 0; i < 16; i++) {
2860 if (mask & (1 << i))
2861 modes += add_3d_struct_modes(connector,
2862 structure_all,
2863 video_db,
2864 video_len, i);
2865 }
2866 }
2867
2868 offset += multi_len;
2869
2870 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
2871 int vic_index;
2872 struct drm_display_mode *newmode = NULL;
2873 unsigned int newflag = 0;
2874 bool detail_present;
2875
2876 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
2877
2878 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
2879 break;
2880
2881 /* 2D_VIC_order_X */
2882 vic_index = db[8 + offset + i] >> 4;
2883
2884 /* 3D_Structure_X */
2885 switch (db[8 + offset + i] & 0x0f) {
2886 case 0:
2887 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
2888 break;
2889 case 6:
2890 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
2891 break;
2892 case 8:
2893 /* 3D_Detail_X */
2894 if ((db[9 + offset + i] >> 4) == 1)
2895 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
2896 break;
2897 }
2898
2899 if (newflag != 0) {
2900 newmode = drm_display_mode_from_vic_index(connector,
2901 video_db,
2902 video_len,
2903 vic_index);
2904
2905 if (newmode) {
2906 newmode->flags |= newflag;
2907 drm_mode_probed_add(connector, newmode);
2908 modes++;
2909 }
2910 }
2911
2912 if (detail_present)
2913 i++;
fbf46025 2914 }
7ebe1963
LD		 2915
2916out:
2917 return modes;
2918}
2919
9e50b9d5
VS		 2920static int
2921cea_db_payload_len(const u8 *db)
2922{
2923 return db[0] & 0x1f;
2924}
2925
2926static int
2927cea_db_tag(const u8 *db)
2928{
2929 return db[0] >> 5;
2930}
2931
2932static int
2933cea_revision(const u8 *cea)
2934{
2935 return cea[1];
2936}
2937
2938static int
2939cea_db_offsets(const u8 *cea, int *start, int *end)
2940{
2941 /* Data block offset in CEA extension block */
2942 *start = 4;
2943 *end = cea[2];
2944 if (*end == 0)
2945 *end = 127;
2946 if (*end < 4 || *end > 127)
2947 return -ERANGE;
2948 return 0;
2949}
2950
7ebe1963
LD		 2951static bool cea_db_is_hdmi_vsdb(const u8 *db)
2952{
2953 int hdmi_id;
2954
2955 if (cea_db_tag(db) != VENDOR_BLOCK)
2956 return false;
2957
2958 if (cea_db_payload_len(db) < 5)
2959 return false;
2960
2961 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
2962
6cb3b7f1 2963 return hdmi_id == HDMI_IEEE_OUI;
7ebe1963
LD		 2964}
2965
9e50b9d5
VS		 2966#define for_each_cea_db(cea, i, start, end) \
2967 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
2968
54ac76f8
CS		 2969static int
2970add_cea_modes(struct drm_connector *connector, struct edid *edid)
2971{
13ac3f55 2972 const u8 *cea = drm_find_cea_extension(edid);
fbf46025
TW		 2973 const u8 *db, *hdmi = NULL, *video = NULL;
2974 u8 dbl, hdmi_len, video_len = 0;
54ac76f8
CS		 2975 int modes = 0;
2976
9e50b9d5
VS		 2977 if (cea && cea_revision(cea) >= 3) {
2978 int i, start, end;
2979
2980 if (cea_db_offsets(cea, &start, &end))
2981 return 0;
2982
2983 for_each_cea_db(cea, i, start, end) {
2984 db = &cea[i];
2985 dbl = cea_db_payload_len(db);
2986
fbf46025
TW		 2987 if (cea_db_tag(db) == VIDEO_BLOCK) {
2988 video = db + 1;
2989 video_len = dbl;
2990 modes += do_cea_modes(connector, video, dbl);
2991 }
c858cfca
DL		 2992 else if (cea_db_is_hdmi_vsdb(db)) {
2993 hdmi = db;
2994 hdmi_len = dbl;
2995 }
54ac76f8
CS		 2996 }
2997 }
2998
c858cfca
DL		 2999 /*
3000 * We parse the HDMI VSDB after having added the cea modes as we will
3001 * be patching their flags when the sink supports stereo 3D.
3002 */
3003 if (hdmi)
fbf46025
TW		 3004 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
3005 video_len);
c858cfca 3006
54ac76f8
CS		 3007 return modes;
3008}
3009
76adaa34 3010static void
8504072a 3011parse_hdmi_vsdb(struct drm_connector *connector, const u8 *db)
76adaa34 3012{
8504072a 3013 u8 len = cea_db_payload_len(db);
76adaa34 3014
8504072a
VS		 3015 if (len >= 6) {
3016 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */
3017 connector->dvi_dual = db[6] & 1;
3018 }
3019 if (len >= 7)
3020 connector->max_tmds_clock = db[7] * 5;
3021 if (len >= 8) {
3022 connector->latency_present[0] = db[8] >> 7;
3023 connector->latency_present[1] = (db[8] >> 6) & 1;
3024 }
3025 if (len >= 9)
3026 connector->video_latency[0] = db[9];
3027 if (len >= 10)
3028 connector->audio_latency[0] = db[10];
3029 if (len >= 11)
3030 connector->video_latency[1] = db[11];
3031 if (len >= 12)
3032 connector->audio_latency[1] = db[12];
76adaa34 3033
670c1ef6 3034 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
76adaa34
WF		 3035 "max TMDS clock %d, "
3036 "latency present %d %d, "
3037 "video latency %d %d, "
3038 "audio latency %d %d\n",
3039 connector->dvi_dual,
3040 connector->max_tmds_clock,
3041 (int) connector->latency_present[0],
3042 (int) connector->latency_present[1],
3043 connector->video_latency[0],
3044 connector->video_latency[1],
3045 connector->audio_latency[0],
3046 connector->audio_latency[1]);
3047}
3048
3049static void
3050monitor_name(struct detailed_timing *t, void *data)
3051{
3052 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
3053 *(u8 **)data = t->data.other_data.data.str.str;
14f77fdd
VS		 3054}
3055
76adaa34
WF		 3056/**
3057 * drm_edid_to_eld - build ELD from EDID
3058 * @connector: connector corresponding to the HDMI/DP sink
3059 * @edid: EDID to parse
3060 *
db6cf833
TR		 3061 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
3062 * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to
3063 * fill in.
76adaa34
WF		 3064 */
3065void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
3066{
3067 uint8_t *eld = connector->eld;
3068 u8 *cea;
3069 u8 *name;
3070 u8 *db;
3071 int sad_count = 0;
3072 int mnl;
3073 int dbl;
3074
3075 memset(eld, 0, sizeof(connector->eld));
3076
3077 cea = drm_find_cea_extension(edid);
3078 if (!cea) {
3079 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
3080 return;
3081 }
3082
3083 name = NULL;
3084 drm_for_each_detailed_block((u8 *)edid, monitor_name, &name);
3085 for (mnl = 0; name && mnl < 13; mnl++) {
3086 if (name[mnl] == 0x0a)
3087 break;
3088 eld[20 + mnl] = name[mnl];
3089 }
3090 eld[4] = (cea[1] << 5) | mnl;
3091 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20);
3092
3093 eld[0] = 2 << 3; /* ELD version: 2 */
3094
3095 eld[16] = edid->mfg_id[0];
3096 eld[17] = edid->mfg_id[1];
3097 eld[18] = edid->prod_code[0];
3098 eld[19] = edid->prod_code[1];
3099
9e50b9d5
VS		 3100 if (cea_revision(cea) >= 3) {
3101 int i, start, end;
3102
3103 if (cea_db_offsets(cea, &start, &end)) {
3104 start = 0;
3105 end = 0;
3106 }
3107
3108 for_each_cea_db(cea, i, start, end) {
3109 db = &cea[i];
3110 dbl = cea_db_payload_len(db);
3111
3112 switch (cea_db_tag(db)) {
a0ab734d
CS		 3113 case AUDIO_BLOCK:
3114 /* Audio Data Block, contains SADs */
3115 sad_count = dbl / 3;
9e50b9d5
VS		 3116 if (dbl >= 1)
3117 memcpy(eld + 20 + mnl, &db[1], dbl);
a0ab734d
CS		 3118 break;
3119 case SPEAKER_BLOCK:
9e50b9d5
VS		 3120 /* Speaker Allocation Data Block */
3121 if (dbl >= 1)
3122 eld[7] = db[1];
a0ab734d
CS		 3123 break;
3124 case VENDOR_BLOCK:
3125 /* HDMI Vendor-Specific Data Block */
14f77fdd 3126 if (cea_db_is_hdmi_vsdb(db))
a0ab734d
CS		 3127 parse_hdmi_vsdb(connector, db);
3128 break;
3129 default:
3130 break;
3131 }
76adaa34 3132 }
9e50b9d5 3133 }
76adaa34
WF		 3134 eld[5] |= sad_count << 4;
3135 eld[2] = (20 + mnl + sad_count * 3 + 3) / 4;
3136
3137 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", (int)eld[2], sad_count);
3138}
3139EXPORT_SYMBOL(drm_edid_to_eld);
3140
fe214163
RM		 3141/**
3142 * drm_edid_to_sad - extracts SADs from EDID
3143 * @edid: EDID to parse
3144 * @sads: pointer that will be set to the extracted SADs
3145 *
3146 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
fe214163 3147 *
db6cf833
TR		 3148 * Note: The returned pointer needs to be freed using kfree().
3149 *
3150 * Return: The number of found SADs or negative number on error.
fe214163
RM		 3151 */
3152int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
3153{
3154 int count = 0;
3155 int i, start, end, dbl;
3156 u8 *cea;
3157
3158 cea = drm_find_cea_extension(edid);
3159 if (!cea) {
3160 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3161 return -ENOENT;
3162 }
3163
3164 if (cea_revision(cea) < 3) {
3165 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3166 return -ENOTSUPP;
3167 }
3168
3169 if (cea_db_offsets(cea, &start, &end)) {
3170 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3171 return -EPROTO;
3172 }
3173
3174 for_each_cea_db(cea, i, start, end) {
3175 u8 *db = &cea[i];
3176
3177 if (cea_db_tag(db) == AUDIO_BLOCK) {
3178 int j;
3179 dbl = cea_db_payload_len(db);
3180
3181 count = dbl / 3; /* SAD is 3B */
3182 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
3183 if (!*sads)
3184 return -ENOMEM;
3185 for (j = 0; j < count; j++) {
3186 u8 *sad = &db[1 + j * 3];
3187
3188 (*sads)[j].format = (sad[0] & 0x78) >> 3;
3189 (*sads)[j].channels = sad[0] & 0x7;
3190 (*sads)[j].freq = sad[1] & 0x7F;
3191 (*sads)[j].byte2 = sad[2];
3192 }
3193 break;
3194 }
3195 }
3196
3197 return count;
3198}
3199EXPORT_SYMBOL(drm_edid_to_sad);
3200
d105f476
AD		 3201/**
3202 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
3203 * @edid: EDID to parse
3204 * @sadb: pointer to the speaker block
3205 *
3206 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
d105f476 3207 *
db6cf833
TR		 3208 * Note: The returned pointer needs to be freed using kfree().
3209 *
3210 * Return: The number of found Speaker Allocation Blocks or negative number on
3211 * error.
d105f476
AD		 3212 */
3213int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
3214{
3215 int count = 0;
3216 int i, start, end, dbl;
3217 const u8 *cea;
3218
3219 cea = drm_find_cea_extension(edid);
3220 if (!cea) {
3221 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3222 return -ENOENT;
3223 }
3224
3225 if (cea_revision(cea) < 3) {
3226 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3227 return -ENOTSUPP;
3228 }
3229
3230 if (cea_db_offsets(cea, &start, &end)) {
3231 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3232 return -EPROTO;
3233 }
3234
3235 for_each_cea_db(cea, i, start, end) {
3236 const u8 *db = &cea[i];
3237
3238 if (cea_db_tag(db) == SPEAKER_BLOCK) {
3239 dbl = cea_db_payload_len(db);
3240
3241 /* Speaker Allocation Data Block */
3242 if (dbl == 3) {
89086bca 3243 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
618e3776
AD		 3244 if (!*sadb)
3245 return -ENOMEM;
d105f476
AD		 3246 count = dbl;
3247 break;
3248 }
3249 }
3250 }
3251
3252 return count;
3253}
3254EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
3255
76adaa34 3256/**
db6cf833 3257 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
76adaa34
WF		 3258 * @connector: connector associated with the HDMI/DP sink
3259 * @mode: the display mode
db6cf833
TR		 3260 *
3261 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
3262 * the sink doesn't support audio or video.
76adaa34
WF		 3263 */
3264int drm_av_sync_delay(struct drm_connector *connector,
3265 struct drm_display_mode *mode)
3266{
3267 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
3268 int a, v;
3269
3270 if (!connector->latency_present[0])
3271 return 0;
3272 if (!connector->latency_present[1])
3273 i = 0;
3274
3275 a = connector->audio_latency[i];
3276 v = connector->video_latency[i];
3277
3278 /*
3279 * HDMI/DP sink doesn't support audio or video?
3280 */
3281 if (a == 255 || v == 255)
3282 return 0;
3283
3284 /*
3285 * Convert raw EDID values to millisecond.
3286 * Treat unknown latency as 0ms.
3287 */
3288 if (a)
3289 a = min(2 * (a - 1), 500);
3290 if (v)
3291 v = min(2 * (v - 1), 500);
3292
3293 return max(v - a, 0);
3294}
3295EXPORT_SYMBOL(drm_av_sync_delay);
3296
3297/**
3298 * drm_select_eld - select one ELD from multiple HDMI/DP sinks
3299 * @encoder: the encoder just changed display mode
3300 * @mode: the adjusted display mode
3301 *
3302 * It's possible for one encoder to be associated with multiple HDMI/DP sinks.
3303 * The policy is now hard coded to simply use the first HDMI/DP sink's ELD.
db6cf833
TR		 3304 *
3305 * Return: The connector associated with the first HDMI/DP sink that has ELD
3306 * attached to it.
76adaa34
WF		 3307 */
3308struct drm_connector *drm_select_eld(struct drm_encoder *encoder,
3309 struct drm_display_mode *mode)
3310{
3311 struct drm_connector *connector;
3312 struct drm_device *dev = encoder->dev;
3313
6e9f798d 3314 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
008f4045 3315 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
6e9f798d 3316
76adaa34
WF		 3317 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
3318 if (connector->encoder == encoder && connector->eld[0])
3319 return connector;
3320
3321 return NULL;
3322}
3323EXPORT_SYMBOL(drm_select_eld);
3324
8fe9790d 3325/**
db6cf833 3326 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
8fe9790d
ZW		 3327 * @edid: monitor EDID information
3328 *
3329 * Parse the CEA extension according to CEA-861-B.
db6cf833
TR		 3330 *
3331 * Return: True if the monitor is HDMI, false if not or unknown.
8fe9790d
ZW		 3332 */
3333bool drm_detect_hdmi_monitor(struct edid *edid)
3334{
3335 u8 *edid_ext;
14f77fdd 3336 int i;
8fe9790d 3337 int start_offset, end_offset;
8fe9790d
ZW		 3338
3339 edid_ext = drm_find_cea_extension(edid);
3340 if (!edid_ext)
14f77fdd 3341 return false;
f23c20c8 3342
9e50b9d5 3343 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
14f77fdd 3344 return false;
f23c20c8
ML		 3345
3346 /*
3347 * Because HDMI identifier is in Vendor Specific Block,
3348 * search it from all data blocks of CEA extension.
3349 */
9e50b9d5 3350 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
14f77fdd
VS		 3351 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
3352 return true;
f23c20c8
ML		 3353 }
3354
14f77fdd 3355 return false;
f23c20c8
ML		 3356}
3357EXPORT_SYMBOL(drm_detect_hdmi_monitor);
3358
8fe9790d
ZW		 3359/**
3360 * drm_detect_monitor_audio - check monitor audio capability
fc66811c 3361 * @edid: EDID block to scan
8fe9790d
ZW		 3362 *
3363 * Monitor should have CEA extension block.
3364 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
3365 * audio' only. If there is any audio extension block and supported
3366 * audio format, assume at least 'basic audio' support, even if 'basic
3367 * audio' is not defined in EDID.
3368 *
db6cf833 3369 * Return: True if the monitor supports audio, false otherwise.
8fe9790d
ZW		 3370 */
3371bool drm_detect_monitor_audio(struct edid *edid)
3372{
3373 u8 *edid_ext;
3374 int i, j;
3375 bool has_audio = false;
3376 int start_offset, end_offset;
3377
3378 edid_ext = drm_find_cea_extension(edid);
3379 if (!edid_ext)
3380 goto end;
3381
3382 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
3383
3384 if (has_audio) {
3385 DRM_DEBUG_KMS("Monitor has basic audio support\n");
3386 goto end;
3387 }
3388
9e50b9d5
VS		 3389 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3390 goto end;
8fe9790d 3391
9e50b9d5
VS		 3392 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3393 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
8fe9790d 3394 has_audio = true;
9e50b9d5 3395 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
8fe9790d
ZW		 3396 DRM_DEBUG_KMS("CEA audio format %d\n",
3397 (edid_ext[i + j] >> 3) & 0xf);
3398 goto end;
3399 }
3400 }
3401end:
3402 return has_audio;
3403}
3404EXPORT_SYMBOL(drm_detect_monitor_audio);
3405
b1edd6a6
VS		 3406/**
3407 * drm_rgb_quant_range_selectable - is RGB quantization range selectable?
fc66811c 3408 * @edid: EDID block to scan
b1edd6a6
VS		 3409 *
3410 * Check whether the monitor reports the RGB quantization range selection
3411 * as supported. The AVI infoframe can then be used to inform the monitor
3412 * which quantization range (full or limited) is used.
db6cf833
TR		 3413 *
3414 * Return: True if the RGB quantization range is selectable, false otherwise.
b1edd6a6
VS		 3415 */
3416bool drm_rgb_quant_range_selectable(struct edid *edid)
3417{
3418 u8 *edid_ext;
3419 int i, start, end;
3420
3421 edid_ext = drm_find_cea_extension(edid);
3422 if (!edid_ext)
3423 return false;
3424
3425 if (cea_db_offsets(edid_ext, &start, &end))
3426 return false;
3427
3428 for_each_cea_db(edid_ext, i, start, end) {
3429 if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK &&
3430 cea_db_payload_len(&edid_ext[i]) == 2) {
3431 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]);
3432 return edid_ext[i + 2] & EDID_CEA_VCDB_QS;
3433 }
3434 }
3435
3436 return false;
3437}
3438EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
3439
d0c94692
MK		 3440/**
3441 * drm_assign_hdmi_deep_color_info - detect whether monitor supports
3442 * hdmi deep color modes and update drm_display_info if so.
d0c94692
MK		 3443 * @edid: monitor EDID information
3444 * @info: Updated with maximum supported deep color bpc and color format
3445 * if deep color supported.
295ee853 3446 * @connector: DRM connector, used only for debug output
d0c94692
MK		 3447 *
3448 * Parse the CEA extension according to CEA-861-B.
3449 * Return true if HDMI deep color supported, false if not or unknown.
3450 */
3451static bool drm_assign_hdmi_deep_color_info(struct edid *edid,
3452 struct drm_display_info *info,
3453 struct drm_connector *connector)
3454{
3455 u8 *edid_ext, *hdmi;
3456 int i;
3457 int start_offset, end_offset;
3458 unsigned int dc_bpc = 0;
3459
3460 edid_ext = drm_find_cea_extension(edid);
3461 if (!edid_ext)
3462 return false;
3463
3464 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3465 return false;
3466
3467 /*
3468 * Because HDMI identifier is in Vendor Specific Block,
3469 * search it from all data blocks of CEA extension.
3470 */
3471 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3472 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) {
3473 /* HDMI supports at least 8 bpc */
3474 info->bpc = 8;
3475
3476 hdmi = &edid_ext[i];
3477 if (cea_db_payload_len(hdmi) < 6)
3478 return false;
3479
3480 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
3481 dc_bpc = 10;
5d02626d 3482 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
d0c94692 3483 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
25933820 3484 connector->name);
d0c94692
MK		 3485 }
3486
3487 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
3488 dc_bpc = 12;
5d02626d 3489 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
d0c94692 3490 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
25933820 3491 connector->name);
d0c94692
MK		 3492 }
3493
3494 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
3495 dc_bpc = 16;
5d02626d 3496 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
d0c94692 3497 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
25933820 3498 connector->name);
d0c94692
MK		 3499 }
3500
3501 if (dc_bpc > 0) {
3502 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
25933820 3503 connector->name, dc_bpc);
d0c94692
MK		 3504 info->bpc = dc_bpc;
3505
3506 /*
3507 * Deep color support mandates RGB444 support for all video
3508 * modes and forbids YCRCB422 support for all video modes per
3509 * HDMI 1.3 spec.
3510 */
3511 info->color_formats = DRM_COLOR_FORMAT_RGB444;
3512
3513 /* YCRCB444 is optional according to spec. */
3514 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
3515 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3516 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
25933820 3517 connector->name);
d0c94692
MK		 3518 }
3519
3520 /*
3521 * Spec says that if any deep color mode is supported at all,
3522 * then deep color 36 bit must be supported.
3523 */
3524 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
3525 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
25933820 3526 connector->name);
d0c94692
MK		 3527 }
3528
3529 return true;
3530 }
3531 else {
3532 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
25933820 3533 connector->name);
d0c94692
MK		 3534 }
3535 }
3536 }
3537
3538 return false;
3539}
3540
3b11228b
JB		 3541/**
3542 * drm_add_display_info - pull display info out if present
3543 * @edid: EDID data
3544 * @info: display info (attached to connector)
d0c94692 3545 * @connector: connector whose edid is used to build display info
3b11228b
JB		 3546 *
3547 * Grab any available display info and stuff it into the drm_display_info
3548 * structure that's part of the connector. Useful for tracking bpp and
3549 * color spaces.
3550 */
3551static void drm_add_display_info(struct edid *edid,
d0c94692
MK		 3552 struct drm_display_info *info,
3553 struct drm_connector *connector)
3b11228b 3554{
ebec9a7b
JB		 3555 u8 *edid_ext;
3556
3b11228b
JB		 3557 info->width_mm = edid->width_cm * 10;
3558 info->height_mm = edid->height_cm * 10;
3559
3560 /* driver figures it out in this case */
3561 info->bpc = 0;
da05a5a7 3562 info->color_formats = 0;
3b11228b 3563
a988bc72 3564 if (edid->revision < 3)
3b11228b
JB		 3565 return;
3566
3567 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
3568 return;
3569
a988bc72
LPC		 3570 /* Get data from CEA blocks if present */
3571 edid_ext = drm_find_cea_extension(edid);
3572 if (edid_ext) {
3573 info->cea_rev = edid_ext[1];
3574
3575 /* The existence of a CEA block should imply RGB support */
3576 info->color_formats = DRM_COLOR_FORMAT_RGB444;
3577 if (edid_ext[3] & EDID_CEA_YCRCB444)
3578 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3579 if (edid_ext[3] & EDID_CEA_YCRCB422)
3580 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
3581 }
3582
d0c94692
MK		 3583 /* HDMI deep color modes supported? Assign to info, if so */
3584 drm_assign_hdmi_deep_color_info(edid, info, connector);
3585
a988bc72
LPC		 3586 /* Only defined for 1.4 with digital displays */
3587 if (edid->revision < 4)
3588 return;
3589
3b11228b
JB		 3590 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
3591 case DRM_EDID_DIGITAL_DEPTH_6:
3592 info->bpc = 6;
3593 break;
3594 case DRM_EDID_DIGITAL_DEPTH_8:
3595 info->bpc = 8;
3596 break;
3597 case DRM_EDID_DIGITAL_DEPTH_10:
3598 info->bpc = 10;
3599 break;
3600 case DRM_EDID_DIGITAL_DEPTH_12:
3601 info->bpc = 12;
3602 break;
3603 case DRM_EDID_DIGITAL_DEPTH_14:
3604 info->bpc = 14;
3605 break;
3606 case DRM_EDID_DIGITAL_DEPTH_16:
3607 info->bpc = 16;
3608 break;
3609 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
3610 default:
3611 info->bpc = 0;
3612 break;
3613 }
da05a5a7 3614
d0c94692 3615 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
25933820 3616 connector->name, info->bpc);
d0c94692 3617
a988bc72 3618 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
ee58808d
LPC		 3619 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
3620 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3621 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
3622 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
3b11228b
JB		 3623}
3624
f453ba04
DA		 3625/**
3626 * drm_add_edid_modes - add modes from EDID data, if available
3627 * @connector: connector we're probing
db6cf833 3628 * @edid: EDID data
f453ba04
DA		 3629 *
3630 * Add the specified modes to the connector's mode list.
3631 *
db6cf833 3632 * Return: The number of modes added or 0 if we couldn't find any.
f453ba04
DA		 3633 */
3634int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
3635{
3636 int num_modes = 0;
3637 u32 quirks;
3638
3639 if (edid == NULL) {
3640 return 0;
3641 }
3c537889 3642 if (!drm_edid_is_valid(edid)) {
dcdb1674 3643 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
25933820 3644 connector->name);
f453ba04
DA		 3645 return 0;
3646 }
3647
3648 quirks = edid_get_quirks(edid);
3649
c867df70
AJ		 3650 /*
3651 * EDID spec says modes should be preferred in this order:
3652 * - preferred detailed mode
3653 * - other detailed modes from base block
3654 * - detailed modes from extension blocks
3655 * - CVT 3-byte code modes
3656 * - standard timing codes
3657 * - established timing codes
3658 * - modes inferred from GTF or CVT range information
3659 *
13931579 3660 * We get this pretty much right.
c867df70
AJ		 3661 *
3662 * XXX order for additional mode types in extension blocks?
3663 */
13931579
AJ		 3664 num_modes += add_detailed_modes(connector, edid, quirks);
3665 num_modes += add_cvt_modes(connector, edid);
c867df70
AJ		 3666 num_modes += add_standard_modes(connector, edid);
3667 num_modes += add_established_modes(connector, edid);
196e077d
PZ		 3668 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
3669 num_modes += add_inferred_modes(connector, edid);
54ac76f8 3670 num_modes += add_cea_modes(connector, edid);
e6e79209 3671 num_modes += add_alternate_cea_modes(connector, edid);
f453ba04
DA		 3672
3673 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
3674 edid_fixup_preferred(connector, quirks);
3675
d0c94692 3676 drm_add_display_info(edid, &connector->display_info, connector);
f453ba04 3677
49d45a31
RM		 3678 if (quirks & EDID_QUIRK_FORCE_8BPC)
3679 connector->display_info.bpc = 8;
3680
bc5b9641
MK		 3681 if (quirks & EDID_QUIRK_FORCE_12BPC)
3682 connector->display_info.bpc = 12;
3683
f453ba04
DA		 3684 return num_modes;
3685}
3686EXPORT_SYMBOL(drm_add_edid_modes);
f0fda0a4
ZY		 3687
3688/**
3689 * drm_add_modes_noedid - add modes for the connectors without EDID
3690 * @connector: connector we're probing
3691 * @hdisplay: the horizontal display limit
3692 * @vdisplay: the vertical display limit
3693 *
3694 * Add the specified modes to the connector's mode list. Only when the
3695 * hdisplay/vdisplay is not beyond the given limit, it will be added.
3696 *
db6cf833 3697 * Return: The number of modes added or 0 if we couldn't find any.
f0fda0a4
ZY		 3698 */
3699int drm_add_modes_noedid(struct drm_connector *connector,
3700 int hdisplay, int vdisplay)
3701{
3702 int i, count, num_modes = 0;
b1f559ec 3703 struct drm_display_mode *mode;
f0fda0a4
ZY		 3704 struct drm_device *dev = connector->dev;
3705
3706 count = sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode);
3707 if (hdisplay < 0)
3708 hdisplay = 0;
3709 if (vdisplay < 0)
3710 vdisplay = 0;
3711
3712 for (i = 0; i < count; i++) {
b1f559ec 3713 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
f0fda0a4
ZY		 3714 if (hdisplay && vdisplay) {
3715 /*
3716 * Only when two are valid, they will be used to check
3717 * whether the mode should be added to the mode list of
3718 * the connector.
3719 */
3720 if (ptr->hdisplay > hdisplay ||
3721 ptr->vdisplay > vdisplay)
3722 continue;
3723 }
f985dedb
AJ		 3724 if (drm_mode_vrefresh(ptr) > 61)
3725 continue;
f0fda0a4
ZY		 3726 mode = drm_mode_duplicate(dev, ptr);
3727 if (mode) {
3728 drm_mode_probed_add(connector, mode);
3729 num_modes++;
3730 }
3731 }
3732 return num_modes;
3733}
3734EXPORT_SYMBOL(drm_add_modes_noedid);
10a85120 3735
db6cf833
TR		 3736/**
3737 * drm_set_preferred_mode - Sets the preferred mode of a connector
3738 * @connector: connector whose mode list should be processed
3739 * @hpref: horizontal resolution of preferred mode
3740 * @vpref: vertical resolution of preferred mode
3741 *
3742 * Marks a mode as preferred if it matches the resolution specified by @hpref
3743 * and @vpref.
3744 */
3cf70daf
GH		 3745void drm_set_preferred_mode(struct drm_connector *connector,
3746 int hpref, int vpref)
3747{
3748 struct drm_display_mode *mode;
3749
3750 list_for_each_entry(mode, &connector->probed_modes, head) {
db6cf833 3751 if (mode->hdisplay == hpref &&
9d3de138 3752 mode->vdisplay == vpref)
3cf70daf
GH		 3753 mode->type |= DRM_MODE_TYPE_PREFERRED;
3754 }
3755}
3756EXPORT_SYMBOL(drm_set_preferred_mode);
3757
10a85120
TR		 3758/**
3759 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
3760 * data from a DRM display mode
3761 * @frame: HDMI AVI infoframe
3762 * @mode: DRM display mode
3763 *
db6cf833 3764 * Return: 0 on success or a negative error code on failure.
10a85120
TR		 3765 */
3766int
3767drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
3768 const struct drm_display_mode *mode)
3769{
3770 int err;
3771
3772 if (!frame || !mode)
3773 return -EINVAL;
3774
3775 err = hdmi_avi_infoframe_init(frame);
3776 if (err < 0)
3777 return err;
3778
bf02db99
DL		 3779 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
3780 frame->pixel_repeat = 1;
3781
10a85120 3782 frame->video_code = drm_match_cea_mode(mode);
10a85120
TR		 3783
3784 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
0967e6a5 3785
69ab6d35
VK		 3786 /*
3787 * Populate picture aspect ratio from either
3788 * user input (if specified) or from the CEA mode list.
3789 */
3790 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 ||
3791 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9)
3792 frame->picture_aspect = mode->picture_aspect_ratio;
3793 else if (frame->video_code > 0)
0967e6a5
VK		 3794 frame->picture_aspect = drm_get_cea_aspect_ratio(
3795 frame->video_code);
3796
10a85120 3797 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
24d01805 3798 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
10a85120
TR		 3799
3800 return 0;
3801}
3802EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
83dd0008 3803
4eed4a0a
DL		 3804static enum hdmi_3d_structure
3805s3d_structure_from_display_mode(const struct drm_display_mode *mode)
3806{
3807 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
3808
3809 switch (layout) {
3810 case DRM_MODE_FLAG_3D_FRAME_PACKING:
3811 return HDMI_3D_STRUCTURE_FRAME_PACKING;
3812 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
3813 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
3814 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
3815 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
3816 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
3817 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
3818 case DRM_MODE_FLAG_3D_L_DEPTH:
3819 return HDMI_3D_STRUCTURE_L_DEPTH;
3820 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
3821 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
3822 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
3823 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
3824 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
3825 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
3826 default:
3827 return HDMI_3D_STRUCTURE_INVALID;
3828 }
3829}
3830
83dd0008
LD		 3831/**
3832 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
3833 * data from a DRM display mode
3834 * @frame: HDMI vendor infoframe
3835 * @mode: DRM display mode
3836 *
3837 * Note that there's is a need to send HDMI vendor infoframes only when using a
3838 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
3839 * function will return -EINVAL, error that can be safely ignored.
3840 *
db6cf833 3841 * Return: 0 on success or a negative error code on failure.
83dd0008
LD		 3842 */
3843int
3844drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
3845 const struct drm_display_mode *mode)
3846{
3847 int err;
4eed4a0a 3848 u32 s3d_flags;
83dd0008
LD		 3849 u8 vic;
3850
3851 if (!frame || !mode)
3852 return -EINVAL;
3853
3854 vic = drm_match_hdmi_mode(mode);
4eed4a0a
DL		 3855 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
3856
3857 if (!vic && !s3d_flags)
3858 return -EINVAL;
3859
3860 if (vic && s3d_flags)
83dd0008
LD		 3861 return -EINVAL;
3862
3863 err = hdmi_vendor_infoframe_init(frame);
3864 if (err < 0)
3865 return err;
3866
4eed4a0a
DL		 3867 if (vic)
3868 frame->vic = vic;
3869 else
3870 frame->s3d_struct = s3d_structure_from_display_mode(mode);
83dd0008
LD		 3871
3872 return 0;
3873}
3874EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
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