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f453ba04 1/*
f453ba04
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2 * Copyright © 1997-2003 by The XFree86 Project, Inc.
3 * Copyright © 2007 Dave Airlie
4 * Copyright © 2007-2008 Intel Corporation
5 * Jesse Barnes <jesse.barnes@intel.com>
d782c3f9 6 * Copyright 2005-2006 Luc Verhaegen
26bbdada 7 * Copyright (c) 2001, Andy Ritger aritger@nvidia.com
f453ba04
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8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25 * OTHER DEALINGS IN THE SOFTWARE.
26 *
27 * Except as contained in this notice, the name of the copyright holder(s)
28 * and author(s) shall not be used in advertising or otherwise to promote
29 * the sale, use or other dealings in this Software without prior written
30 * authorization from the copyright holder(s) and author(s).
31 */
32
33#include <linux/list.h>
2c761270 34#include <linux/list_sort.h>
2d1a8a48 35#include <linux/export.h>
760285e7
DH
36#include <drm/drmP.h>
37#include <drm/drm_crtc.h>
edb37a95 38#include <video/of_videomode.h>
ebc64e45 39#include <video/videomode.h>
55310008 40#include <drm/drm_modes.h>
f453ba04 41
8bd441b2
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42#include "drm_crtc_internal.h"
43
f453ba04 44/**
3ec0db81 45 * drm_mode_debug_printmodeline - print a mode to dmesg
f453ba04
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46 * @mode: mode to print
47 *
f453ba04
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48 * Describe @mode using DRM_DEBUG.
49 */
0b3904ab 50void drm_mode_debug_printmodeline(const struct drm_display_mode *mode)
f453ba04 51{
65c7dc18 52 DRM_DEBUG_KMS("Modeline " DRM_MODE_FMT "\n", DRM_MODE_ARG(mode));
f453ba04
DA
53}
54EXPORT_SYMBOL(drm_mode_debug_printmodeline);
55
8bd441b2
DV
56/**
57 * drm_mode_create - create a new display mode
58 * @dev: DRM device
59 *
f5aabb97
DV
60 * Create a new, cleared drm_display_mode with kzalloc, allocate an ID for it
61 * and return it.
8bd441b2 62 *
f5aabb97 63 * Returns:
8bd441b2
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64 * Pointer to new mode on success, NULL on error.
65 */
66struct drm_display_mode *drm_mode_create(struct drm_device *dev)
67{
68 struct drm_display_mode *nmode;
69
70 nmode = kzalloc(sizeof(struct drm_display_mode), GFP_KERNEL);
71 if (!nmode)
72 return NULL;
73
74 if (drm_mode_object_get(dev, &nmode->base, DRM_MODE_OBJECT_MODE)) {
75 kfree(nmode);
76 return NULL;
77 }
78
79 return nmode;
80}
81EXPORT_SYMBOL(drm_mode_create);
82
83/**
84 * drm_mode_destroy - remove a mode
85 * @dev: DRM device
86 * @mode: mode to remove
87 *
f5aabb97 88 * Release @mode's unique ID, then free it @mode structure itself using kfree.
8bd441b2
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89 */
90void drm_mode_destroy(struct drm_device *dev, struct drm_display_mode *mode)
91{
92 if (!mode)
93 return;
94
7c8f6d25 95 drm_mode_object_unregister(dev, &mode->base);
8bd441b2
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96
97 kfree(mode);
98}
99EXPORT_SYMBOL(drm_mode_destroy);
100
101/**
f5aabb97 102 * drm_mode_probed_add - add a mode to a connector's probed_mode list
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103 * @connector: connector the new mode
104 * @mode: mode data
105 *
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106 * Add @mode to @connector's probed_mode list for later use. This list should
107 * then in a second step get filtered and all the modes actually supported by
108 * the hardware moved to the @connector's modes list.
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109 */
110void drm_mode_probed_add(struct drm_connector *connector,
111 struct drm_display_mode *mode)
112{
113 WARN_ON(!mutex_is_locked(&connector->dev->mode_config.mutex));
114
115 list_add_tail(&mode->head, &connector->probed_modes);
116}
117EXPORT_SYMBOL(drm_mode_probed_add);
118
d782c3f9 119/**
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120 * drm_cvt_mode -create a modeline based on the CVT algorithm
121 * @dev: drm device
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122 * @hdisplay: hdisplay size
123 * @vdisplay: vdisplay size
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124 * @vrefresh: vrefresh rate
125 * @reduced: whether to use reduced blanking
126 * @interlaced: whether to compute an interlaced mode
127 * @margins: whether to add margins (borders)
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128 *
129 * This function is called to generate the modeline based on CVT algorithm
130 * according to the hdisplay, vdisplay, vrefresh.
131 * It is based from the VESA(TM) Coordinated Video Timing Generator by
132 * Graham Loveridge April 9, 2003 available at
631dd1a8 133 * http://www.elo.utfsm.cl/~elo212/docs/CVTd6r1.xls
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134 *
135 * And it is copied from xf86CVTmode in xserver/hw/xfree86/modes/xf86cvt.c.
136 * What I have done is to translate it by using integer calculation.
f5aabb97
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137 *
138 * Returns:
139 * The modeline based on the CVT algorithm stored in a drm_display_mode object.
140 * The display mode object is allocated with drm_mode_create(). Returns NULL
141 * when no mode could be allocated.
d782c3f9 142 */
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143struct drm_display_mode *drm_cvt_mode(struct drm_device *dev, int hdisplay,
144 int vdisplay, int vrefresh,
d50ba256 145 bool reduced, bool interlaced, bool margins)
d782c3f9 146{
3ec0db81 147#define HV_FACTOR 1000
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148 /* 1) top/bottom margin size (% of height) - default: 1.8, */
149#define CVT_MARGIN_PERCENTAGE 18
150 /* 2) character cell horizontal granularity (pixels) - default 8 */
151#define CVT_H_GRANULARITY 8
152 /* 3) Minimum vertical porch (lines) - default 3 */
153#define CVT_MIN_V_PORCH 3
154 /* 4) Minimum number of vertical back porch lines - default 6 */
155#define CVT_MIN_V_BPORCH 6
156 /* Pixel Clock step (kHz) */
157#define CVT_CLOCK_STEP 250
158 struct drm_display_mode *drm_mode;
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159 unsigned int vfieldrate, hperiod;
160 int hdisplay_rnd, hmargin, vdisplay_rnd, vmargin, vsync;
161 int interlace;
8a5bbf32 162 u64 tmp;
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163
164 /* allocate the drm_display_mode structure. If failure, we will
165 * return directly
166 */
167 drm_mode = drm_mode_create(dev);
168 if (!drm_mode)
169 return NULL;
170
171 /* the CVT default refresh rate is 60Hz */
172 if (!vrefresh)
173 vrefresh = 60;
174
175 /* the required field fresh rate */
176 if (interlaced)
177 vfieldrate = vrefresh * 2;
178 else
179 vfieldrate = vrefresh;
180
181 /* horizontal pixels */
182 hdisplay_rnd = hdisplay - (hdisplay % CVT_H_GRANULARITY);
183
184 /* determine the left&right borders */
185 hmargin = 0;
186 if (margins) {
187 hmargin = hdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000;
188 hmargin -= hmargin % CVT_H_GRANULARITY;
189 }
190 /* find the total active pixels */
191 drm_mode->hdisplay = hdisplay_rnd + 2 * hmargin;
192
193 /* find the number of lines per field */
194 if (interlaced)
195 vdisplay_rnd = vdisplay / 2;
196 else
197 vdisplay_rnd = vdisplay;
198
199 /* find the top & bottom borders */
200 vmargin = 0;
201 if (margins)
202 vmargin = vdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000;
203
841b4117 204 drm_mode->vdisplay = vdisplay + 2 * vmargin;
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205
206 /* Interlaced */
207 if (interlaced)
208 interlace = 1;
209 else
210 interlace = 0;
211
212 /* Determine VSync Width from aspect ratio */
213 if (!(vdisplay % 3) && ((vdisplay * 4 / 3) == hdisplay))
214 vsync = 4;
215 else if (!(vdisplay % 9) && ((vdisplay * 16 / 9) == hdisplay))
216 vsync = 5;
217 else if (!(vdisplay % 10) && ((vdisplay * 16 / 10) == hdisplay))
218 vsync = 6;
219 else if (!(vdisplay % 4) && ((vdisplay * 5 / 4) == hdisplay))
220 vsync = 7;
221 else if (!(vdisplay % 9) && ((vdisplay * 15 / 9) == hdisplay))
222 vsync = 7;
223 else /* custom */
224 vsync = 10;
225
226 if (!reduced) {
227 /* simplify the GTF calculation */
228 /* 4) Minimum time of vertical sync + back porch interval (µs)
229 * default 550.0
230 */
231 int tmp1, tmp2;
232#define CVT_MIN_VSYNC_BP 550
233 /* 3) Nominal HSync width (% of line period) - default 8 */
234#define CVT_HSYNC_PERCENTAGE 8
235 unsigned int hblank_percentage;
236 int vsyncandback_porch, vback_porch, hblank;
237
238 /* estimated the horizontal period */
239 tmp1 = HV_FACTOR * 1000000 -
240 CVT_MIN_VSYNC_BP * HV_FACTOR * vfieldrate;
241 tmp2 = (vdisplay_rnd + 2 * vmargin + CVT_MIN_V_PORCH) * 2 +
242 interlace;
243 hperiod = tmp1 * 2 / (tmp2 * vfieldrate);
244
245 tmp1 = CVT_MIN_VSYNC_BP * HV_FACTOR / hperiod + 1;
246 /* 9. Find number of lines in sync + backporch */
247 if (tmp1 < (vsync + CVT_MIN_V_PORCH))
248 vsyncandback_porch = vsync + CVT_MIN_V_PORCH;
249 else
250 vsyncandback_porch = tmp1;
251 /* 10. Find number of lines in back porch */
252 vback_porch = vsyncandback_porch - vsync;
253 drm_mode->vtotal = vdisplay_rnd + 2 * vmargin +
254 vsyncandback_porch + CVT_MIN_V_PORCH;
255 /* 5) Definition of Horizontal blanking time limitation */
256 /* Gradient (%/kHz) - default 600 */
257#define CVT_M_FACTOR 600
258 /* Offset (%) - default 40 */
259#define CVT_C_FACTOR 40
260 /* Blanking time scaling factor - default 128 */
261#define CVT_K_FACTOR 128
262 /* Scaling factor weighting - default 20 */
263#define CVT_J_FACTOR 20
264#define CVT_M_PRIME (CVT_M_FACTOR * CVT_K_FACTOR / 256)
265#define CVT_C_PRIME ((CVT_C_FACTOR - CVT_J_FACTOR) * CVT_K_FACTOR / 256 + \
266 CVT_J_FACTOR)
267 /* 12. Find ideal blanking duty cycle from formula */
268 hblank_percentage = CVT_C_PRIME * HV_FACTOR - CVT_M_PRIME *
269 hperiod / 1000;
270 /* 13. Blanking time */
271 if (hblank_percentage < 20 * HV_FACTOR)
272 hblank_percentage = 20 * HV_FACTOR;
273 hblank = drm_mode->hdisplay * hblank_percentage /
274 (100 * HV_FACTOR - hblank_percentage);
275 hblank -= hblank % (2 * CVT_H_GRANULARITY);
2a97acd6 276 /* 14. find the total pixels per line */
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277 drm_mode->htotal = drm_mode->hdisplay + hblank;
278 drm_mode->hsync_end = drm_mode->hdisplay + hblank / 2;
279 drm_mode->hsync_start = drm_mode->hsync_end -
280 (drm_mode->htotal * CVT_HSYNC_PERCENTAGE) / 100;
281 drm_mode->hsync_start += CVT_H_GRANULARITY -
282 drm_mode->hsync_start % CVT_H_GRANULARITY;
283 /* fill the Vsync values */
284 drm_mode->vsync_start = drm_mode->vdisplay + CVT_MIN_V_PORCH;
285 drm_mode->vsync_end = drm_mode->vsync_start + vsync;
286 } else {
287 /* Reduced blanking */
288 /* Minimum vertical blanking interval time (µs)- default 460 */
289#define CVT_RB_MIN_VBLANK 460
290 /* Fixed number of clocks for horizontal sync */
291#define CVT_RB_H_SYNC 32
292 /* Fixed number of clocks for horizontal blanking */
293#define CVT_RB_H_BLANK 160
294 /* Fixed number of lines for vertical front porch - default 3*/
295#define CVT_RB_VFPORCH 3
296 int vbilines;
297 int tmp1, tmp2;
298 /* 8. Estimate Horizontal period. */
299 tmp1 = HV_FACTOR * 1000000 -
300 CVT_RB_MIN_VBLANK * HV_FACTOR * vfieldrate;
301 tmp2 = vdisplay_rnd + 2 * vmargin;
302 hperiod = tmp1 / (tmp2 * vfieldrate);
303 /* 9. Find number of lines in vertical blanking */
304 vbilines = CVT_RB_MIN_VBLANK * HV_FACTOR / hperiod + 1;
305 /* 10. Check if vertical blanking is sufficient */
306 if (vbilines < (CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH))
307 vbilines = CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH;
308 /* 11. Find total number of lines in vertical field */
309 drm_mode->vtotal = vdisplay_rnd + 2 * vmargin + vbilines;
310 /* 12. Find total number of pixels in a line */
311 drm_mode->htotal = drm_mode->hdisplay + CVT_RB_H_BLANK;
312 /* Fill in HSync values */
313 drm_mode->hsync_end = drm_mode->hdisplay + CVT_RB_H_BLANK / 2;
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314 drm_mode->hsync_start = drm_mode->hsync_end - CVT_RB_H_SYNC;
315 /* Fill in VSync values */
316 drm_mode->vsync_start = drm_mode->vdisplay + CVT_RB_VFPORCH;
317 drm_mode->vsync_end = drm_mode->vsync_start + vsync;
d782c3f9
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318 }
319 /* 15/13. Find pixel clock frequency (kHz for xf86) */
8a5bbf32
CW
320 tmp = drm_mode->htotal; /* perform intermediate calcs in u64 */
321 tmp *= HV_FACTOR * 1000;
322 do_div(tmp, hperiod);
323 tmp -= drm_mode->clock % CVT_CLOCK_STEP;
324 drm_mode->clock = tmp;
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325 /* 18/16. Find actual vertical frame frequency */
326 /* ignore - just set the mode flag for interlaced */
171fdd89 327 if (interlaced) {
d782c3f9 328 drm_mode->vtotal *= 2;
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AJ
329 drm_mode->flags |= DRM_MODE_FLAG_INTERLACE;
330 }
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331 /* Fill the mode line name */
332 drm_mode_set_name(drm_mode);
333 if (reduced)
334 drm_mode->flags |= (DRM_MODE_FLAG_PHSYNC |
335 DRM_MODE_FLAG_NVSYNC);
336 else
337 drm_mode->flags |= (DRM_MODE_FLAG_PVSYNC |
338 DRM_MODE_FLAG_NHSYNC);
d782c3f9 339
171fdd89 340 return drm_mode;
d782c3f9
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341}
342EXPORT_SYMBOL(drm_cvt_mode);
343
26bbdada 344/**
f5aabb97
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345 * drm_gtf_mode_complex - create the modeline based on the full GTF algorithm
346 * @dev: drm device
347 * @hdisplay: hdisplay size
348 * @vdisplay: vdisplay size
349 * @vrefresh: vrefresh rate.
350 * @interlaced: whether to compute an interlaced mode
351 * @margins: desired margin (borders) size
3ec0db81
DV
352 * @GTF_M: extended GTF formula parameters
353 * @GTF_2C: extended GTF formula parameters
354 * @GTF_K: extended GTF formula parameters
355 * @GTF_2J: extended GTF formula parameters
26bbdada 356 *
7a374350
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357 * GTF feature blocks specify C and J in multiples of 0.5, so we pass them
358 * in here multiplied by two. For a C of 40, pass in 80.
f5aabb97
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359 *
360 * Returns:
361 * The modeline based on the full GTF algorithm stored in a drm_display_mode object.
362 * The display mode object is allocated with drm_mode_create(). Returns NULL
363 * when no mode could be allocated.
26bbdada 364 */
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365struct drm_display_mode *
366drm_gtf_mode_complex(struct drm_device *dev, int hdisplay, int vdisplay,
367 int vrefresh, bool interlaced, int margins,
368 int GTF_M, int GTF_2C, int GTF_K, int GTF_2J)
369{ /* 1) top/bottom margin size (% of height) - default: 1.8, */
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370#define GTF_MARGIN_PERCENTAGE 18
371 /* 2) character cell horizontal granularity (pixels) - default 8 */
372#define GTF_CELL_GRAN 8
373 /* 3) Minimum vertical porch (lines) - default 3 */
374#define GTF_MIN_V_PORCH 1
375 /* width of vsync in lines */
376#define V_SYNC_RQD 3
377 /* width of hsync as % of total line */
378#define H_SYNC_PERCENT 8
379 /* min time of vsync + back porch (microsec) */
380#define MIN_VSYNC_PLUS_BP 550
26bbdada 381 /* C' and M' are part of the Blanking Duty Cycle computation */
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382#define GTF_C_PRIME ((((GTF_2C - GTF_2J) * GTF_K / 256) + GTF_2J) / 2)
383#define GTF_M_PRIME (GTF_K * GTF_M / 256)
26bbdada
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384 struct drm_display_mode *drm_mode;
385 unsigned int hdisplay_rnd, vdisplay_rnd, vfieldrate_rqd;
386 int top_margin, bottom_margin;
387 int interlace;
388 unsigned int hfreq_est;
389 int vsync_plus_bp, vback_porch;
390 unsigned int vtotal_lines, vfieldrate_est, hperiod;
391 unsigned int vfield_rate, vframe_rate;
392 int left_margin, right_margin;
393 unsigned int total_active_pixels, ideal_duty_cycle;
394 unsigned int hblank, total_pixels, pixel_freq;
395 int hsync, hfront_porch, vodd_front_porch_lines;
396 unsigned int tmp1, tmp2;
397
398 drm_mode = drm_mode_create(dev);
399 if (!drm_mode)
400 return NULL;
401
402 /* 1. In order to give correct results, the number of horizontal
403 * pixels requested is first processed to ensure that it is divisible
404 * by the character size, by rounding it to the nearest character
405 * cell boundary:
406 */
407 hdisplay_rnd = (hdisplay + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN;
408 hdisplay_rnd = hdisplay_rnd * GTF_CELL_GRAN;
409
410 /* 2. If interlace is requested, the number of vertical lines assumed
411 * by the calculation must be halved, as the computation calculates
412 * the number of vertical lines per field.
413 */
414 if (interlaced)
415 vdisplay_rnd = vdisplay / 2;
416 else
417 vdisplay_rnd = vdisplay;
418
419 /* 3. Find the frame rate required: */
420 if (interlaced)
421 vfieldrate_rqd = vrefresh * 2;
422 else
423 vfieldrate_rqd = vrefresh;
424
425 /* 4. Find number of lines in Top margin: */
426 top_margin = 0;
427 if (margins)
428 top_margin = (vdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) /
429 1000;
430 /* 5. Find number of lines in bottom margin: */
431 bottom_margin = top_margin;
432
433 /* 6. If interlace is required, then set variable interlace: */
434 if (interlaced)
435 interlace = 1;
436 else
437 interlace = 0;
438
439 /* 7. Estimate the Horizontal frequency */
440 {
441 tmp1 = (1000000 - MIN_VSYNC_PLUS_BP * vfieldrate_rqd) / 500;
442 tmp2 = (vdisplay_rnd + 2 * top_margin + GTF_MIN_V_PORCH) *
443 2 + interlace;
444 hfreq_est = (tmp2 * 1000 * vfieldrate_rqd) / tmp1;
445 }
446
447 /* 8. Find the number of lines in V sync + back porch */
448 /* [V SYNC+BP] = RINT(([MIN VSYNC+BP] * hfreq_est / 1000000)) */
449 vsync_plus_bp = MIN_VSYNC_PLUS_BP * hfreq_est / 1000;
450 vsync_plus_bp = (vsync_plus_bp + 500) / 1000;
451 /* 9. Find the number of lines in V back porch alone: */
452 vback_porch = vsync_plus_bp - V_SYNC_RQD;
453 /* 10. Find the total number of lines in Vertical field period: */
454 vtotal_lines = vdisplay_rnd + top_margin + bottom_margin +
455 vsync_plus_bp + GTF_MIN_V_PORCH;
456 /* 11. Estimate the Vertical field frequency: */
457 vfieldrate_est = hfreq_est / vtotal_lines;
458 /* 12. Find the actual horizontal period: */
459 hperiod = 1000000 / (vfieldrate_rqd * vtotal_lines);
460
461 /* 13. Find the actual Vertical field frequency: */
462 vfield_rate = hfreq_est / vtotal_lines;
463 /* 14. Find the Vertical frame frequency: */
464 if (interlaced)
465 vframe_rate = vfield_rate / 2;
466 else
467 vframe_rate = vfield_rate;
468 /* 15. Find number of pixels in left margin: */
469 if (margins)
470 left_margin = (hdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) /
471 1000;
472 else
473 left_margin = 0;
474
475 /* 16.Find number of pixels in right margin: */
476 right_margin = left_margin;
477 /* 17.Find total number of active pixels in image and left and right */
478 total_active_pixels = hdisplay_rnd + left_margin + right_margin;
479 /* 18.Find the ideal blanking duty cycle from blanking duty cycle */
480 ideal_duty_cycle = GTF_C_PRIME * 1000 -
481 (GTF_M_PRIME * 1000000 / hfreq_est);
482 /* 19.Find the number of pixels in the blanking time to the nearest
483 * double character cell: */
484 hblank = total_active_pixels * ideal_duty_cycle /
485 (100000 - ideal_duty_cycle);
486 hblank = (hblank + GTF_CELL_GRAN) / (2 * GTF_CELL_GRAN);
487 hblank = hblank * 2 * GTF_CELL_GRAN;
488 /* 20.Find total number of pixels: */
489 total_pixels = total_active_pixels + hblank;
490 /* 21.Find pixel clock frequency: */
491 pixel_freq = total_pixels * hfreq_est / 1000;
492 /* Stage 1 computations are now complete; I should really pass
493 * the results to another function and do the Stage 2 computations,
494 * but I only need a few more values so I'll just append the
495 * computations here for now */
496 /* 17. Find the number of pixels in the horizontal sync period: */
497 hsync = H_SYNC_PERCENT * total_pixels / 100;
498 hsync = (hsync + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN;
499 hsync = hsync * GTF_CELL_GRAN;
500 /* 18. Find the number of pixels in horizontal front porch period */
501 hfront_porch = hblank / 2 - hsync;
502 /* 36. Find the number of lines in the odd front porch period: */
503 vodd_front_porch_lines = GTF_MIN_V_PORCH ;
504
505 /* finally, pack the results in the mode struct */
506 drm_mode->hdisplay = hdisplay_rnd;
507 drm_mode->hsync_start = hdisplay_rnd + hfront_porch;
508 drm_mode->hsync_end = drm_mode->hsync_start + hsync;
509 drm_mode->htotal = total_pixels;
510 drm_mode->vdisplay = vdisplay_rnd;
511 drm_mode->vsync_start = vdisplay_rnd + vodd_front_porch_lines;
512 drm_mode->vsync_end = drm_mode->vsync_start + V_SYNC_RQD;
513 drm_mode->vtotal = vtotal_lines;
514
515 drm_mode->clock = pixel_freq;
516
26bbdada
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517 if (interlaced) {
518 drm_mode->vtotal *= 2;
519 drm_mode->flags |= DRM_MODE_FLAG_INTERLACE;
520 }
521
171fdd89 522 drm_mode_set_name(drm_mode);
c385e50c
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523 if (GTF_M == 600 && GTF_2C == 80 && GTF_K == 128 && GTF_2J == 40)
524 drm_mode->flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC;
525 else
526 drm_mode->flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC;
171fdd89 527
26bbdada
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528 return drm_mode;
529}
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AJ
530EXPORT_SYMBOL(drm_gtf_mode_complex);
531
532/**
f5aabb97
DV
533 * drm_gtf_mode - create the modeline based on the GTF algorithm
534 * @dev: drm device
535 * @hdisplay: hdisplay size
536 * @vdisplay: vdisplay size
537 * @vrefresh: vrefresh rate.
538 * @interlaced: whether to compute an interlaced mode
539 * @margins: desired margin (borders) size
7a374350 540 *
7a374350
AJ
541 * return the modeline based on GTF algorithm
542 *
543 * This function is to create the modeline based on the GTF algorithm.
544 * Generalized Timing Formula is derived from:
2e7a5701 545 *
7a374350
AJ
546 * GTF Spreadsheet by Andy Morrish (1/5/97)
547 * available at http://www.vesa.org
548 *
549 * And it is copied from the file of xserver/hw/xfree86/modes/xf86gtf.c.
550 * What I have done is to translate it by using integer calculation.
551 * I also refer to the function of fb_get_mode in the file of
552 * drivers/video/fbmon.c
553 *
da5335b8
DV
554 * Standard GTF parameters::
555 *
f03d8ede
DCLP
556 * M = 600
557 * C = 40
558 * K = 128
559 * J = 20
f5aabb97
DV
560 *
561 * Returns:
562 * The modeline based on the GTF algorithm stored in a drm_display_mode object.
563 * The display mode object is allocated with drm_mode_create(). Returns NULL
564 * when no mode could be allocated.
7a374350
AJ
565 */
566struct drm_display_mode *
567drm_gtf_mode(struct drm_device *dev, int hdisplay, int vdisplay, int vrefresh,
3ec0db81 568 bool interlaced, int margins)
7a374350 569{
3ec0db81
DV
570 return drm_gtf_mode_complex(dev, hdisplay, vdisplay, vrefresh,
571 interlaced, margins,
572 600, 40 * 2, 128, 20 * 2);
7a374350 573}
26bbdada 574EXPORT_SYMBOL(drm_gtf_mode);
7a374350 575
a38884f6 576#ifdef CONFIG_VIDEOMODE_HELPERS
f5aabb97
DV
577/**
578 * drm_display_mode_from_videomode - fill in @dmode using @vm,
579 * @vm: videomode structure to use as source
580 * @dmode: drm_display_mode structure to use as destination
581 *
582 * Fills out @dmode using the display mode specified in @vm.
583 */
ba0c2422
DV
584void drm_display_mode_from_videomode(const struct videomode *vm,
585 struct drm_display_mode *dmode)
ebc64e45
ST
586{
587 dmode->hdisplay = vm->hactive;
588 dmode->hsync_start = dmode->hdisplay + vm->hfront_porch;
589 dmode->hsync_end = dmode->hsync_start + vm->hsync_len;
590 dmode->htotal = dmode->hsync_end + vm->hback_porch;
591
592 dmode->vdisplay = vm->vactive;
593 dmode->vsync_start = dmode->vdisplay + vm->vfront_porch;
594 dmode->vsync_end = dmode->vsync_start + vm->vsync_len;
595 dmode->vtotal = dmode->vsync_end + vm->vback_porch;
596
597 dmode->clock = vm->pixelclock / 1000;
598
599 dmode->flags = 0;
06a33079 600 if (vm->flags & DISPLAY_FLAGS_HSYNC_HIGH)
ebc64e45 601 dmode->flags |= DRM_MODE_FLAG_PHSYNC;
06a33079 602 else if (vm->flags & DISPLAY_FLAGS_HSYNC_LOW)
ebc64e45 603 dmode->flags |= DRM_MODE_FLAG_NHSYNC;
06a33079 604 if (vm->flags & DISPLAY_FLAGS_VSYNC_HIGH)
ebc64e45 605 dmode->flags |= DRM_MODE_FLAG_PVSYNC;
06a33079 606 else if (vm->flags & DISPLAY_FLAGS_VSYNC_LOW)
ebc64e45 607 dmode->flags |= DRM_MODE_FLAG_NVSYNC;
06a33079 608 if (vm->flags & DISPLAY_FLAGS_INTERLACED)
ebc64e45 609 dmode->flags |= DRM_MODE_FLAG_INTERLACE;
06a33079 610 if (vm->flags & DISPLAY_FLAGS_DOUBLESCAN)
ebc64e45 611 dmode->flags |= DRM_MODE_FLAG_DBLSCAN;
328a4719
ST
612 if (vm->flags & DISPLAY_FLAGS_DOUBLECLK)
613 dmode->flags |= DRM_MODE_FLAG_DBLCLK;
ebc64e45 614 drm_mode_set_name(dmode);
ebc64e45
ST
615}
616EXPORT_SYMBOL_GPL(drm_display_mode_from_videomode);
ebc64e45 617
d490f455
SL
618/**
619 * drm_display_mode_to_videomode - fill in @vm using @dmode,
620 * @dmode: drm_display_mode structure to use as source
621 * @vm: videomode structure to use as destination
622 *
623 * Fills out @vm using the display mode specified in @dmode.
624 */
625void drm_display_mode_to_videomode(const struct drm_display_mode *dmode,
626 struct videomode *vm)
627{
628 vm->hactive = dmode->hdisplay;
629 vm->hfront_porch = dmode->hsync_start - dmode->hdisplay;
630 vm->hsync_len = dmode->hsync_end - dmode->hsync_start;
631 vm->hback_porch = dmode->htotal - dmode->hsync_end;
632
633 vm->vactive = dmode->vdisplay;
634 vm->vfront_porch = dmode->vsync_start - dmode->vdisplay;
635 vm->vsync_len = dmode->vsync_end - dmode->vsync_start;
636 vm->vback_porch = dmode->vtotal - dmode->vsync_end;
637
638 vm->pixelclock = dmode->clock * 1000;
639
640 vm->flags = 0;
641 if (dmode->flags & DRM_MODE_FLAG_PHSYNC)
642 vm->flags |= DISPLAY_FLAGS_HSYNC_HIGH;
643 else if (dmode->flags & DRM_MODE_FLAG_NHSYNC)
644 vm->flags |= DISPLAY_FLAGS_HSYNC_LOW;
645 if (dmode->flags & DRM_MODE_FLAG_PVSYNC)
646 vm->flags |= DISPLAY_FLAGS_VSYNC_HIGH;
647 else if (dmode->flags & DRM_MODE_FLAG_NVSYNC)
648 vm->flags |= DISPLAY_FLAGS_VSYNC_LOW;
649 if (dmode->flags & DRM_MODE_FLAG_INTERLACE)
650 vm->flags |= DISPLAY_FLAGS_INTERLACED;
651 if (dmode->flags & DRM_MODE_FLAG_DBLSCAN)
652 vm->flags |= DISPLAY_FLAGS_DOUBLESCAN;
653 if (dmode->flags & DRM_MODE_FLAG_DBLCLK)
654 vm->flags |= DISPLAY_FLAGS_DOUBLECLK;
655}
656EXPORT_SYMBOL_GPL(drm_display_mode_to_videomode);
657
cb34d7f2
LW
658/**
659 * drm_bus_flags_from_videomode - extract information about pixelclk and
660 * DE polarity from videomode and store it in a separate variable
661 * @vm: videomode structure to use
662 * @bus_flags: information about pixelclk and DE polarity will be stored here
663 *
664 * Sets DRM_BUS_FLAG_DE_(LOW|HIGH) and DRM_BUS_FLAG_PIXDATA_(POS|NEG)EDGE
665 * in @bus_flags according to DISPLAY_FLAGS found in @vm
666 */
d72daa0d
LW
667void drm_bus_flags_from_videomode(const struct videomode *vm, u32 *bus_flags)
668{
669 *bus_flags = 0;
670 if (vm->flags & DISPLAY_FLAGS_PIXDATA_POSEDGE)
671 *bus_flags |= DRM_BUS_FLAG_PIXDATA_POSEDGE;
672 if (vm->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
673 *bus_flags |= DRM_BUS_FLAG_PIXDATA_NEGEDGE;
674
675 if (vm->flags & DISPLAY_FLAGS_DE_LOW)
676 *bus_flags |= DRM_BUS_FLAG_DE_LOW;
677 if (vm->flags & DISPLAY_FLAGS_DE_HIGH)
678 *bus_flags |= DRM_BUS_FLAG_DE_HIGH;
679}
680EXPORT_SYMBOL_GPL(drm_bus_flags_from_videomode);
681
a38884f6 682#ifdef CONFIG_OF
edb37a95
ST
683/**
684 * of_get_drm_display_mode - get a drm_display_mode from devicetree
685 * @np: device_node with the timing specification
686 * @dmode: will be set to the return value
cb34d7f2 687 * @bus_flags: information about pixelclk and DE polarity
edb37a95
ST
688 * @index: index into the list of display timings in devicetree
689 *
690 * This function is expensive and should only be used, if only one mode is to be
691 * read from DT. To get multiple modes start with of_get_display_timings and
692 * work with that instead.
f5aabb97
DV
693 *
694 * Returns:
695 * 0 on success, a negative errno code when no of videomode node was found.
edb37a95
ST
696 */
697int of_get_drm_display_mode(struct device_node *np,
fafc79ef
LW
698 struct drm_display_mode *dmode, u32 *bus_flags,
699 int index)
edb37a95
ST
700{
701 struct videomode vm;
702 int ret;
703
704 ret = of_get_videomode(np, &vm, index);
705 if (ret)
706 return ret;
707
708 drm_display_mode_from_videomode(&vm, dmode);
fafc79ef
LW
709 if (bus_flags)
710 drm_bus_flags_from_videomode(&vm, bus_flags);
edb37a95
ST
711
712 pr_debug("%s: got %dx%d display mode from %s\n",
713 of_node_full_name(np), vm.hactive, vm.vactive, np->name);
714 drm_mode_debug_printmodeline(dmode);
715
716 return 0;
717}
718EXPORT_SYMBOL_GPL(of_get_drm_display_mode);
a38884f6
TV
719#endif /* CONFIG_OF */
720#endif /* CONFIG_VIDEOMODE_HELPERS */
edb37a95 721
f453ba04
DA
722/**
723 * drm_mode_set_name - set the name on a mode
724 * @mode: name will be set in this mode
725 *
f5aabb97
DV
726 * Set the name of @mode to a standard format which is <hdisplay>x<vdisplay>
727 * with an optional 'i' suffix for interlaced modes.
f453ba04
DA
728 */
729void drm_mode_set_name(struct drm_display_mode *mode)
730{
171fdd89
AJ
731 bool interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
732
733 snprintf(mode->name, DRM_DISPLAY_MODE_LEN, "%dx%d%s",
734 mode->hdisplay, mode->vdisplay,
735 interlaced ? "i" : "");
f453ba04
DA
736}
737EXPORT_SYMBOL(drm_mode_set_name);
738
30ecad77
DV
739/**
740 * drm_mode_hsync - get the hsync of a mode
7ac96a9c
AJ
741 * @mode: mode
742 *
f5aabb97
DV
743 * Returns:
744 * @modes's hsync rate in kHz, rounded to the nearest integer. Calculates the
745 * value first if it is not yet set.
7ac96a9c 746 */
b1f559ec 747int drm_mode_hsync(const struct drm_display_mode *mode)
7ac96a9c
AJ
748{
749 unsigned int calc_val;
750
751 if (mode->hsync)
752 return mode->hsync;
753
754 if (mode->htotal < 0)
755 return 0;
756
757 calc_val = (mode->clock * 1000) / mode->htotal; /* hsync in Hz */
758 calc_val += 500; /* round to 1000Hz */
759 calc_val /= 1000; /* truncate to kHz */
760
761 return calc_val;
762}
763EXPORT_SYMBOL(drm_mode_hsync);
764
f453ba04
DA
765/**
766 * drm_mode_vrefresh - get the vrefresh of a mode
767 * @mode: mode
768 *
f5aabb97
DV
769 * Returns:
770 * @modes's vrefresh rate in Hz, rounded to the nearest integer. Calculates the
771 * value first if it is not yet set.
f453ba04 772 */
b1f559ec 773int drm_mode_vrefresh(const struct drm_display_mode *mode)
f453ba04
DA
774{
775 int refresh = 0;
776 unsigned int calc_val;
777
778 if (mode->vrefresh > 0)
779 refresh = mode->vrefresh;
780 else if (mode->htotal > 0 && mode->vtotal > 0) {
559ee21d
ZY
781 int vtotal;
782 vtotal = mode->vtotal;
f453ba04
DA
783 /* work out vrefresh the value will be x1000 */
784 calc_val = (mode->clock * 1000);
f453ba04 785 calc_val /= mode->htotal;
559ee21d 786 refresh = (calc_val + vtotal / 2) / vtotal;
f453ba04 787
f453ba04
DA
788 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
789 refresh *= 2;
790 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
791 refresh /= 2;
792 if (mode->vscan > 1)
793 refresh /= mode->vscan;
794 }
795 return refresh;
796}
797EXPORT_SYMBOL(drm_mode_vrefresh);
798
799/**
f5aabb97 800 * drm_mode_set_crtcinfo - set CRTC modesetting timing parameters
f453ba04 801 * @p: mode
448cce25 802 * @adjust_flags: a combination of adjustment flags
f453ba04 803 *
f5aabb97 804 * Setup the CRTC modesetting timing parameters for @p, adjusting if necessary.
448cce25
DL
805 *
806 * - The CRTC_INTERLACE_HALVE_V flag can be used to halve vertical timings of
807 * interlaced modes.
808 * - The CRTC_STEREO_DOUBLE flag can be used to compute the timings for
809 * buffers containing two eyes (only adjust the timings when needed, eg. for
810 * "frame packing" or "side by side full").
ecb7e16b
GP
811 * - The CRTC_NO_DBLSCAN and CRTC_NO_VSCAN flags request that adjustment *not*
812 * be performed for doublescan and vscan > 1 modes respectively.
f453ba04
DA
813 */
814void drm_mode_set_crtcinfo(struct drm_display_mode *p, int adjust_flags)
815{
816 if ((p == NULL) || ((p->type & DRM_MODE_TYPE_CRTC_C) == DRM_MODE_TYPE_BUILTIN))
817 return;
818
bde2dcf7 819 p->crtc_clock = p->clock;
f453ba04
DA
820 p->crtc_hdisplay = p->hdisplay;
821 p->crtc_hsync_start = p->hsync_start;
822 p->crtc_hsync_end = p->hsync_end;
823 p->crtc_htotal = p->htotal;
824 p->crtc_hskew = p->hskew;
825 p->crtc_vdisplay = p->vdisplay;
826 p->crtc_vsync_start = p->vsync_start;
827 p->crtc_vsync_end = p->vsync_end;
828 p->crtc_vtotal = p->vtotal;
829
830 if (p->flags & DRM_MODE_FLAG_INTERLACE) {
831 if (adjust_flags & CRTC_INTERLACE_HALVE_V) {
832 p->crtc_vdisplay /= 2;
833 p->crtc_vsync_start /= 2;
834 p->crtc_vsync_end /= 2;
835 p->crtc_vtotal /= 2;
836 }
f453ba04
DA
837 }
838
ecb7e16b
GP
839 if (!(adjust_flags & CRTC_NO_DBLSCAN)) {
840 if (p->flags & DRM_MODE_FLAG_DBLSCAN) {
841 p->crtc_vdisplay *= 2;
842 p->crtc_vsync_start *= 2;
843 p->crtc_vsync_end *= 2;
844 p->crtc_vtotal *= 2;
845 }
f453ba04
DA
846 }
847
ecb7e16b
GP
848 if (!(adjust_flags & CRTC_NO_VSCAN)) {
849 if (p->vscan > 1) {
850 p->crtc_vdisplay *= p->vscan;
851 p->crtc_vsync_start *= p->vscan;
852 p->crtc_vsync_end *= p->vscan;
853 p->crtc_vtotal *= p->vscan;
854 }
f453ba04
DA
855 }
856
448cce25
DL
857 if (adjust_flags & CRTC_STEREO_DOUBLE) {
858 unsigned int layout = p->flags & DRM_MODE_FLAG_3D_MASK;
859
860 switch (layout) {
861 case DRM_MODE_FLAG_3D_FRAME_PACKING:
862 p->crtc_clock *= 2;
863 p->crtc_vdisplay += p->crtc_vtotal;
864 p->crtc_vsync_start += p->crtc_vtotal;
865 p->crtc_vsync_end += p->crtc_vtotal;
866 p->crtc_vtotal += p->crtc_vtotal;
867 break;
868 }
869 }
870
f453ba04
DA
871 p->crtc_vblank_start = min(p->crtc_vsync_start, p->crtc_vdisplay);
872 p->crtc_vblank_end = max(p->crtc_vsync_end, p->crtc_vtotal);
873 p->crtc_hblank_start = min(p->crtc_hsync_start, p->crtc_hdisplay);
874 p->crtc_hblank_end = max(p->crtc_hsync_end, p->crtc_htotal);
f453ba04
DA
875}
876EXPORT_SYMBOL(drm_mode_set_crtcinfo);
877
c3c50e8b
VS
878/**
879 * drm_mode_copy - copy the mode
880 * @dst: mode to overwrite
881 * @src: mode to copy
882 *
72e45e92
VS
883 * Copy an existing mode into another mode, preserving the object id and
884 * list head of the destination mode.
c3c50e8b
VS
885 */
886void drm_mode_copy(struct drm_display_mode *dst, const struct drm_display_mode *src)
887{
888 int id = dst->base.id;
72e45e92 889 struct list_head head = dst->head;
c3c50e8b
VS
890
891 *dst = *src;
892 dst->base.id = id;
72e45e92 893 dst->head = head;
c3c50e8b
VS
894}
895EXPORT_SYMBOL(drm_mode_copy);
896
f453ba04
DA
897/**
898 * drm_mode_duplicate - allocate and duplicate an existing mode
3ec0db81
DV
899 * @dev: drm_device to allocate the duplicated mode for
900 * @mode: mode to duplicate
f453ba04 901 *
f453ba04
DA
902 * Just allocate a new mode, copy the existing mode into it, and return
903 * a pointer to it. Used to create new instances of established modes.
f5aabb97
DV
904 *
905 * Returns:
906 * Pointer to duplicated mode on success, NULL on error.
f453ba04
DA
907 */
908struct drm_display_mode *drm_mode_duplicate(struct drm_device *dev,
b1f559ec 909 const struct drm_display_mode *mode)
f453ba04
DA
910{
911 struct drm_display_mode *nmode;
f453ba04
DA
912
913 nmode = drm_mode_create(dev);
914 if (!nmode)
915 return NULL;
916
c3c50e8b
VS
917 drm_mode_copy(nmode, mode);
918
f453ba04
DA
919 return nmode;
920}
921EXPORT_SYMBOL(drm_mode_duplicate);
922
923/**
924 * drm_mode_equal - test modes for equality
925 * @mode1: first mode
926 * @mode2: second mode
927 *
f453ba04
DA
928 * Check to see if @mode1 and @mode2 are equivalent.
929 *
f5aabb97 930 * Returns:
f453ba04
DA
931 * True if the modes are equal, false otherwise.
932 */
0b3904ab 933bool drm_mode_equal(const struct drm_display_mode *mode1, const struct drm_display_mode *mode2)
f453ba04 934{
54270952
DS
935 if (!mode1 && !mode2)
936 return true;
937
938 if (!mode1 || !mode2)
939 return false;
940
f453ba04
DA
941 /* do clock check convert to PICOS so fb modes get matched
942 * the same */
943 if (mode1->clock && mode2->clock) {
944 if (KHZ2PICOS(mode1->clock) != KHZ2PICOS(mode2->clock))
945 return false;
946 } else if (mode1->clock != mode2->clock)
947 return false;
948
4c6bcf44
VS
949 return drm_mode_equal_no_clocks(mode1, mode2);
950}
951EXPORT_SYMBOL(drm_mode_equal);
952
953/**
954 * drm_mode_equal_no_clocks - test modes for equality
955 * @mode1: first mode
956 * @mode2: second mode
957 *
958 * Check to see if @mode1 and @mode2 are equivalent, but
959 * don't check the pixel clocks.
960 *
961 * Returns:
962 * True if the modes are equal, false otherwise.
963 */
964bool drm_mode_equal_no_clocks(const struct drm_display_mode *mode1, const struct drm_display_mode *mode2)
965{
f2ecf2e3
DL
966 if ((mode1->flags & DRM_MODE_FLAG_3D_MASK) !=
967 (mode2->flags & DRM_MODE_FLAG_3D_MASK))
968 return false;
969
970 return drm_mode_equal_no_clocks_no_stereo(mode1, mode2);
8cc3f23c 971}
4c6bcf44 972EXPORT_SYMBOL(drm_mode_equal_no_clocks);
8cc3f23c
VS
973
974/**
f2ecf2e3 975 * drm_mode_equal_no_clocks_no_stereo - test modes for equality
8cc3f23c
VS
976 * @mode1: first mode
977 * @mode2: second mode
978 *
8cc3f23c 979 * Check to see if @mode1 and @mode2 are equivalent, but
f2ecf2e3 980 * don't check the pixel clocks nor the stereo layout.
8cc3f23c 981 *
f5aabb97 982 * Returns:
8cc3f23c
VS
983 * True if the modes are equal, false otherwise.
984 */
f2ecf2e3
DL
985bool drm_mode_equal_no_clocks_no_stereo(const struct drm_display_mode *mode1,
986 const struct drm_display_mode *mode2)
8cc3f23c 987{
f453ba04
DA
988 if (mode1->hdisplay == mode2->hdisplay &&
989 mode1->hsync_start == mode2->hsync_start &&
990 mode1->hsync_end == mode2->hsync_end &&
991 mode1->htotal == mode2->htotal &&
992 mode1->hskew == mode2->hskew &&
993 mode1->vdisplay == mode2->vdisplay &&
994 mode1->vsync_start == mode2->vsync_start &&
995 mode1->vsync_end == mode2->vsync_end &&
996 mode1->vtotal == mode2->vtotal &&
997 mode1->vscan == mode2->vscan &&
f2ecf2e3
DL
998 (mode1->flags & ~DRM_MODE_FLAG_3D_MASK) ==
999 (mode2->flags & ~DRM_MODE_FLAG_3D_MASK))
f453ba04
DA
1000 return true;
1001
1002 return false;
1003}
f2ecf2e3 1004EXPORT_SYMBOL(drm_mode_equal_no_clocks_no_stereo);
f453ba04 1005
abc0b144
VS
1006/**
1007 * drm_mode_validate_basic - make sure the mode is somewhat sane
1008 * @mode: mode to check
1009 *
1010 * Check that the mode timings are at least somewhat reasonable.
1011 * Any hardware specific limits are left up for each driver to check.
1012 *
1013 * Returns:
1014 * The mode status
1015 */
1016enum drm_mode_status
1017drm_mode_validate_basic(const struct drm_display_mode *mode)
1018{
1019 if (mode->clock == 0)
1020 return MODE_CLOCK_LOW;
1021
1022 if (mode->hdisplay == 0 ||
1023 mode->hsync_start < mode->hdisplay ||
1024 mode->hsync_end < mode->hsync_start ||
1025 mode->htotal < mode->hsync_end)
1026 return MODE_H_ILLEGAL;
1027
1028 if (mode->vdisplay == 0 ||
1029 mode->vsync_start < mode->vdisplay ||
1030 mode->vsync_end < mode->vsync_start ||
1031 mode->vtotal < mode->vsync_end)
1032 return MODE_V_ILLEGAL;
1033
1034 return MODE_OK;
1035}
1036EXPORT_SYMBOL(drm_mode_validate_basic);
1037
f453ba04
DA
1038/**
1039 * drm_mode_validate_size - make sure modes adhere to size constraints
05acaec3 1040 * @mode: mode to check
f453ba04
DA
1041 * @maxX: maximum width
1042 * @maxY: maximum height
f453ba04 1043 *
f5aabb97
DV
1044 * This function is a helper which can be used to validate modes against size
1045 * limitations of the DRM device/connector. If a mode is too big its status
32197aab 1046 * member is updated with the appropriate validation failure code. The list
f5aabb97 1047 * itself is not changed.
05acaec3
VS
1048 *
1049 * Returns:
1050 * The mode status
f453ba04 1051 */
05acaec3
VS
1052enum drm_mode_status
1053drm_mode_validate_size(const struct drm_display_mode *mode,
1054 int maxX, int maxY)
f453ba04 1055{
05acaec3
VS
1056 if (maxX > 0 && mode->hdisplay > maxX)
1057 return MODE_VIRTUAL_X;
f453ba04 1058
05acaec3
VS
1059 if (maxY > 0 && mode->vdisplay > maxY)
1060 return MODE_VIRTUAL_Y;
f453ba04 1061
05acaec3 1062 return MODE_OK;
f453ba04
DA
1063}
1064EXPORT_SYMBOL(drm_mode_validate_size);
1065
e4bf44b3
VS
1066#define MODE_STATUS(status) [MODE_ ## status + 3] = #status
1067
1068static const char * const drm_mode_status_names[] = {
1069 MODE_STATUS(OK),
1070 MODE_STATUS(HSYNC),
1071 MODE_STATUS(VSYNC),
1072 MODE_STATUS(H_ILLEGAL),
1073 MODE_STATUS(V_ILLEGAL),
1074 MODE_STATUS(BAD_WIDTH),
1075 MODE_STATUS(NOMODE),
1076 MODE_STATUS(NO_INTERLACE),
1077 MODE_STATUS(NO_DBLESCAN),
1078 MODE_STATUS(NO_VSCAN),
1079 MODE_STATUS(MEM),
1080 MODE_STATUS(VIRTUAL_X),
1081 MODE_STATUS(VIRTUAL_Y),
1082 MODE_STATUS(MEM_VIRT),
1083 MODE_STATUS(NOCLOCK),
1084 MODE_STATUS(CLOCK_HIGH),
1085 MODE_STATUS(CLOCK_LOW),
1086 MODE_STATUS(CLOCK_RANGE),
1087 MODE_STATUS(BAD_HVALUE),
1088 MODE_STATUS(BAD_VVALUE),
1089 MODE_STATUS(BAD_VSCAN),
1090 MODE_STATUS(HSYNC_NARROW),
1091 MODE_STATUS(HSYNC_WIDE),
1092 MODE_STATUS(HBLANK_NARROW),
1093 MODE_STATUS(HBLANK_WIDE),
1094 MODE_STATUS(VSYNC_NARROW),
1095 MODE_STATUS(VSYNC_WIDE),
1096 MODE_STATUS(VBLANK_NARROW),
1097 MODE_STATUS(VBLANK_WIDE),
1098 MODE_STATUS(PANEL),
1099 MODE_STATUS(INTERLACE_WIDTH),
1100 MODE_STATUS(ONE_WIDTH),
1101 MODE_STATUS(ONE_HEIGHT),
1102 MODE_STATUS(ONE_SIZE),
1103 MODE_STATUS(NO_REDUCED),
1104 MODE_STATUS(NO_STEREO),
5ba89406 1105 MODE_STATUS(STALE),
e4bf44b3
VS
1106 MODE_STATUS(BAD),
1107 MODE_STATUS(ERROR),
1108};
1109
1110#undef MODE_STATUS
1111
1112static const char *drm_get_mode_status_name(enum drm_mode_status status)
1113{
1114 int index = status + 3;
1115
1116 if (WARN_ON(index < 0 || index >= ARRAY_SIZE(drm_mode_status_names)))
1117 return "";
1118
1119 return drm_mode_status_names[index];
1120}
1121
f453ba04
DA
1122/**
1123 * drm_mode_prune_invalid - remove invalid modes from mode list
1124 * @dev: DRM device
1125 * @mode_list: list of modes to check
1126 * @verbose: be verbose about it
1127 *
f5aabb97
DV
1128 * This helper function can be used to prune a display mode list after
1129 * validation has been completed. All modes who's status is not MODE_OK will be
1130 * removed from the list, and if @verbose the status code and mode name is also
1131 * printed to dmesg.
f453ba04
DA
1132 */
1133void drm_mode_prune_invalid(struct drm_device *dev,
1134 struct list_head *mode_list, bool verbose)
1135{
1136 struct drm_display_mode *mode, *t;
1137
1138 list_for_each_entry_safe(mode, t, mode_list, head) {
1139 if (mode->status != MODE_OK) {
1140 list_del(&mode->head);
1141 if (verbose) {
1142 drm_mode_debug_printmodeline(mode);
e4bf44b3
VS
1143 DRM_DEBUG_KMS("Not using %s mode: %s\n",
1144 mode->name,
1145 drm_get_mode_status_name(mode->status));
f453ba04
DA
1146 }
1147 drm_mode_destroy(dev, mode);
1148 }
1149 }
1150}
1151EXPORT_SYMBOL(drm_mode_prune_invalid);
1152
1153/**
1154 * drm_mode_compare - compare modes for favorability
2c761270 1155 * @priv: unused
f453ba04
DA
1156 * @lh_a: list_head for first mode
1157 * @lh_b: list_head for second mode
1158 *
f453ba04
DA
1159 * Compare two modes, given by @lh_a and @lh_b, returning a value indicating
1160 * which is better.
1161 *
f5aabb97 1162 * Returns:
f453ba04
DA
1163 * Negative if @lh_a is better than @lh_b, zero if they're equivalent, or
1164 * positive if @lh_b is better than @lh_a.
1165 */
2c761270 1166static int drm_mode_compare(void *priv, struct list_head *lh_a, struct list_head *lh_b)
f453ba04
DA
1167{
1168 struct drm_display_mode *a = list_entry(lh_a, struct drm_display_mode, head);
1169 struct drm_display_mode *b = list_entry(lh_b, struct drm_display_mode, head);
1170 int diff;
1171
1172 diff = ((b->type & DRM_MODE_TYPE_PREFERRED) != 0) -
1173 ((a->type & DRM_MODE_TYPE_PREFERRED) != 0);
1174 if (diff)
1175 return diff;
1176 diff = b->hdisplay * b->vdisplay - a->hdisplay * a->vdisplay;
1177 if (diff)
1178 return diff;
9bc3cd56
VS
1179
1180 diff = b->vrefresh - a->vrefresh;
1181 if (diff)
1182 return diff;
1183
f453ba04
DA
1184 diff = b->clock - a->clock;
1185 return diff;
1186}
1187
f453ba04
DA
1188/**
1189 * drm_mode_sort - sort mode list
f5aabb97 1190 * @mode_list: list of drm_display_mode structures to sort
f453ba04 1191 *
f5aabb97 1192 * Sort @mode_list by favorability, moving good modes to the head of the list.
f453ba04
DA
1193 */
1194void drm_mode_sort(struct list_head *mode_list)
1195{
2c761270 1196 list_sort(NULL, mode_list, drm_mode_compare);
f453ba04
DA
1197}
1198EXPORT_SYMBOL(drm_mode_sort);
1199
1200/**
1201 * drm_mode_connector_list_update - update the mode list for the connector
1202 * @connector: the connector to update
1203 *
f453ba04
DA
1204 * This moves the modes from the @connector probed_modes list
1205 * to the actual mode list. It compares the probed mode against the current
f5aabb97
DV
1206 * list and only adds different/new modes.
1207 *
1208 * This is just a helper functions doesn't validate any modes itself and also
1209 * doesn't prune any invalid modes. Callers need to do that themselves.
f453ba04 1210 */
6af3e656 1211void drm_mode_connector_list_update(struct drm_connector *connector)
f453ba04 1212{
f453ba04 1213 struct drm_display_mode *pmode, *pt;
f453ba04 1214
63951385
DV
1215 WARN_ON(!mutex_is_locked(&connector->dev->mode_config.mutex));
1216
2f8c19e7
VS
1217 list_for_each_entry_safe(pmode, pt, &connector->probed_modes, head) {
1218 struct drm_display_mode *mode;
1219 bool found_it = false;
1220
f453ba04
DA
1221 /* go through current modes checking for the new probed mode */
1222 list_for_each_entry(mode, &connector->modes, head) {
2f8c19e7
VS
1223 if (!drm_mode_equal(pmode, mode))
1224 continue;
1225
1226 found_it = true;
fc245f88
VS
1227
1228 /*
1229 * If the old matching mode is stale (ie. left over
1230 * from a previous probe) just replace it outright.
1231 * Otherwise just merge the type bits between all
1232 * equal probed modes.
1233 *
1234 * If two probed modes are considered equal, pick the
1235 * actual timings from the one that's marked as
1236 * preferred (in case the match isn't 100%). If
1237 * multiple or zero preferred modes are present, favor
1238 * the mode added to the probed_modes list first.
1239 */
1240 if (mode->status == MODE_STALE) {
1241 drm_mode_copy(mode, pmode);
1242 } else if ((mode->type & DRM_MODE_TYPE_PREFERRED) == 0 &&
1243 (pmode->type & DRM_MODE_TYPE_PREFERRED) != 0) {
6af3e656 1244 pmode->type |= mode->type;
fc245f88
VS
1245 drm_mode_copy(mode, pmode);
1246 } else {
6af3e656 1247 mode->type |= pmode->type;
fc245f88
VS
1248 }
1249
2f8c19e7
VS
1250 list_del(&pmode->head);
1251 drm_mode_destroy(connector->dev, pmode);
1252 break;
f453ba04
DA
1253 }
1254
1255 if (!found_it) {
1256 list_move_tail(&pmode->head, &connector->modes);
1257 }
1258 }
1259}
1260EXPORT_SYMBOL(drm_mode_connector_list_update);
1794d257
CW
1261
1262/**
f5aabb97
DV
1263 * drm_mode_parse_command_line_for_connector - parse command line modeline for connector
1264 * @mode_option: optional per connector mode option
1265 * @connector: connector to parse modeline for
1266 * @mode: preallocated drm_cmdline_mode structure to fill out
1267 *
1268 * This parses @mode_option command line modeline for modes and options to
1269 * configure the connector. If @mode_option is NULL the default command line
1270 * modeline in fb_mode_option will be parsed instead.
1794d257 1271 *
f5aabb97
DV
1272 * This uses the same parameters as the fb modedb.c, except for an extra
1273 * force-enable, force-enable-digital and force-disable bit at the end:
1794d257 1274 *
f03d8ede 1275 * <xres>x<yres>[M][R][-<bpp>][@<refresh>][i][m][eDd]
1794d257 1276 *
f5aabb97 1277 * The intermediate drm_cmdline_mode structure is required to store additional
2a97acd6 1278 * options from the command line modline like the force-enable/disable flag.
f5aabb97
DV
1279 *
1280 * Returns:
1281 * True if a valid modeline has been parsed, false otherwise.
1794d257
CW
1282 */
1283bool drm_mode_parse_command_line_for_connector(const char *mode_option,
1284 struct drm_connector *connector,
1285 struct drm_cmdline_mode *mode)
1286{
1287 const char *name;
1288 unsigned int namelen;
04fee895 1289 bool res_specified = false, bpp_specified = false, refresh_specified = false;
1794d257 1290 unsigned int xres = 0, yres = 0, bpp = 32, refresh = 0;
04fee895
REB
1291 bool yres_specified = false, cvt = false, rb = false;
1292 bool interlace = false, margins = false, was_digit = false;
d6e6e14f 1293 int i;
1794d257
CW
1294 enum drm_connector_force force = DRM_FORCE_UNSPECIFIED;
1295
cb3c438e 1296#ifdef CONFIG_FB
1794d257
CW
1297 if (!mode_option)
1298 mode_option = fb_mode_option;
cb3c438e 1299#endif
1794d257
CW
1300
1301 if (!mode_option) {
1302 mode->specified = false;
1303 return false;
1304 }
1305
1306 name = mode_option;
1307 namelen = strlen(name);
1308 for (i = namelen-1; i >= 0; i--) {
1309 switch (name[i]) {
1310 case '@':
1794d257 1311 if (!refresh_specified && !bpp_specified &&
04fee895 1312 !yres_specified && !cvt && !rb && was_digit) {
d6e6e14f 1313 refresh = simple_strtol(&name[i+1], NULL, 10);
04fee895
REB
1314 refresh_specified = true;
1315 was_digit = false;
1794d257
CW
1316 } else
1317 goto done;
1318 break;
1319 case '-':
04fee895
REB
1320 if (!bpp_specified && !yres_specified && !cvt &&
1321 !rb && was_digit) {
d6e6e14f 1322 bpp = simple_strtol(&name[i+1], NULL, 10);
04fee895
REB
1323 bpp_specified = true;
1324 was_digit = false;
1794d257
CW
1325 } else
1326 goto done;
1327 break;
1328 case 'x':
04fee895 1329 if (!yres_specified && was_digit) {
d6e6e14f 1330 yres = simple_strtol(&name[i+1], NULL, 10);
04fee895
REB
1331 yres_specified = true;
1332 was_digit = false;
1794d257
CW
1333 } else
1334 goto done;
97fbfbf4 1335 break;
1794d257 1336 case '0' ... '9':
04fee895 1337 was_digit = true;
1794d257
CW
1338 break;
1339 case 'M':
04fee895
REB
1340 if (yres_specified || cvt || was_digit)
1341 goto done;
1342 cvt = true;
1794d257
CW
1343 break;
1344 case 'R':
04fee895
REB
1345 if (yres_specified || cvt || rb || was_digit)
1346 goto done;
1347 rb = true;
1794d257
CW
1348 break;
1349 case 'm':
04fee895
REB
1350 if (cvt || yres_specified || was_digit)
1351 goto done;
1352 margins = true;
1794d257
CW
1353 break;
1354 case 'i':
04fee895
REB
1355 if (cvt || yres_specified || was_digit)
1356 goto done;
1357 interlace = true;
1794d257
CW
1358 break;
1359 case 'e':
04fee895
REB
1360 if (yres_specified || bpp_specified || refresh_specified ||
1361 was_digit || (force != DRM_FORCE_UNSPECIFIED))
1362 goto done;
1363
1794d257
CW
1364 force = DRM_FORCE_ON;
1365 break;
1366 case 'D':
04fee895
REB
1367 if (yres_specified || bpp_specified || refresh_specified ||
1368 was_digit || (force != DRM_FORCE_UNSPECIFIED))
1369 goto done;
1370
1794d257
CW
1371 if ((connector->connector_type != DRM_MODE_CONNECTOR_DVII) &&
1372 (connector->connector_type != DRM_MODE_CONNECTOR_HDMIB))
1373 force = DRM_FORCE_ON;
1374 else
1375 force = DRM_FORCE_ON_DIGITAL;
1376 break;
1377 case 'd':
04fee895
REB
1378 if (yres_specified || bpp_specified || refresh_specified ||
1379 was_digit || (force != DRM_FORCE_UNSPECIFIED))
1380 goto done;
1381
1794d257
CW
1382 force = DRM_FORCE_OFF;
1383 break;
1384 default:
1385 goto done;
1386 }
1387 }
04fee895 1388
1794d257 1389 if (i < 0 && yres_specified) {
04fee895
REB
1390 char *ch;
1391 xres = simple_strtol(name, &ch, 10);
1392 if ((ch != NULL) && (*ch == 'x'))
1393 res_specified = true;
1394 else
1395 i = ch - name;
1396 } else if (!yres_specified && was_digit) {
1397 /* catch mode that begins with digits but has no 'x' */
1398 i = 0;
1794d257
CW
1399 }
1400done:
04fee895 1401 if (i >= 0) {
67fe85dd 1402 pr_warn("[drm] parse error at position %i in video mode '%s'\n",
04fee895
REB
1403 i, name);
1404 mode->specified = false;
1405 return false;
1406 }
1407
1794d257
CW
1408 if (res_specified) {
1409 mode->specified = true;
1410 mode->xres = xres;
1411 mode->yres = yres;
1412 }
1413
1414 if (refresh_specified) {
1415 mode->refresh_specified = true;
1416 mode->refresh = refresh;
1417 }
1418
1419 if (bpp_specified) {
1420 mode->bpp_specified = true;
1421 mode->bpp = bpp;
1422 }
04fee895
REB
1423 mode->rb = rb;
1424 mode->cvt = cvt;
1425 mode->interlace = interlace;
1426 mode->margins = margins;
1794d257
CW
1427 mode->force = force;
1428
1429 return true;
1430}
1431EXPORT_SYMBOL(drm_mode_parse_command_line_for_connector);
1432
f5aabb97
DV
1433/**
1434 * drm_mode_create_from_cmdline_mode - convert a command line modeline into a DRM display mode
1435 * @dev: DRM device to create the new mode for
1436 * @cmd: input command line modeline
1437 *
1438 * Returns:
1439 * Pointer to converted mode on success, NULL on error.
1440 */
1794d257
CW
1441struct drm_display_mode *
1442drm_mode_create_from_cmdline_mode(struct drm_device *dev,
1443 struct drm_cmdline_mode *cmd)
1444{
1445 struct drm_display_mode *mode;
1446
1447 if (cmd->cvt)
1448 mode = drm_cvt_mode(dev,
1449 cmd->xres, cmd->yres,
1450 cmd->refresh_specified ? cmd->refresh : 60,
1451 cmd->rb, cmd->interlace,
1452 cmd->margins);
1453 else
1454 mode = drm_gtf_mode(dev,
1455 cmd->xres, cmd->yres,
1456 cmd->refresh_specified ? cmd->refresh : 60,
1457 cmd->interlace,
1458 cmd->margins);
1459 if (!mode)
1460 return NULL;
1461
eaf99c74 1462 mode->type |= DRM_MODE_TYPE_USERDEF;
fdf35a6b
TI
1463 /* fix up 1368x768: GFT/CVT can't express 1366 width due to alignment */
1464 if (cmd->xres == 1366 && mode->hdisplay == 1368) {
1465 mode->hdisplay = 1366;
1466 mode->hsync_start--;
1467 mode->hsync_end--;
1468 drm_mode_set_name(mode);
1469 }
1794d257
CW
1470 drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V);
1471 return mode;
1472}
1473EXPORT_SYMBOL(drm_mode_create_from_cmdline_mode);
934a8a89
DS
1474
1475/**
1476 * drm_crtc_convert_to_umode - convert a drm_display_mode into a modeinfo
1477 * @out: drm_mode_modeinfo struct to return to the user
1478 * @in: drm_display_mode to use
1479 *
1480 * Convert a drm_display_mode into a drm_mode_modeinfo structure to return to
1481 * the user.
1482 */
1483void drm_mode_convert_to_umode(struct drm_mode_modeinfo *out,
1484 const struct drm_display_mode *in)
1485{
1486 WARN(in->hdisplay > USHRT_MAX || in->hsync_start > USHRT_MAX ||
1487 in->hsync_end > USHRT_MAX || in->htotal > USHRT_MAX ||
1488 in->hskew > USHRT_MAX || in->vdisplay > USHRT_MAX ||
1489 in->vsync_start > USHRT_MAX || in->vsync_end > USHRT_MAX ||
1490 in->vtotal > USHRT_MAX || in->vscan > USHRT_MAX,
1491 "timing values too large for mode info\n");
1492
1493 out->clock = in->clock;
1494 out->hdisplay = in->hdisplay;
1495 out->hsync_start = in->hsync_start;
1496 out->hsync_end = in->hsync_end;
1497 out->htotal = in->htotal;
1498 out->hskew = in->hskew;
1499 out->vdisplay = in->vdisplay;
1500 out->vsync_start = in->vsync_start;
1501 out->vsync_end = in->vsync_end;
1502 out->vtotal = in->vtotal;
1503 out->vscan = in->vscan;
1504 out->vrefresh = in->vrefresh;
1505 out->flags = in->flags;
1506 out->type = in->type;
1507 strncpy(out->name, in->name, DRM_DISPLAY_MODE_LEN);
1508 out->name[DRM_DISPLAY_MODE_LEN-1] = 0;
1509}
1510
1511/**
1512 * drm_crtc_convert_umode - convert a modeinfo into a drm_display_mode
1513 * @out: drm_display_mode to return to the user
1514 * @in: drm_mode_modeinfo to use
1515 *
1516 * Convert a drm_mode_modeinfo into a drm_display_mode structure to return to
1517 * the caller.
1518 *
1519 * Returns:
1520 * Zero on success, negative errno on failure.
1521 */
1522int drm_mode_convert_umode(struct drm_display_mode *out,
1523 const struct drm_mode_modeinfo *in)
1524{
1525 int ret = -EINVAL;
1526
1527 if (in->clock > INT_MAX || in->vrefresh > INT_MAX) {
1528 ret = -ERANGE;
1529 goto out;
1530 }
1531
1532 if ((in->flags & DRM_MODE_FLAG_3D_MASK) > DRM_MODE_FLAG_3D_MAX)
1533 goto out;
1534
1535 out->clock = in->clock;
1536 out->hdisplay = in->hdisplay;
1537 out->hsync_start = in->hsync_start;
1538 out->hsync_end = in->hsync_end;
1539 out->htotal = in->htotal;
1540 out->hskew = in->hskew;
1541 out->vdisplay = in->vdisplay;
1542 out->vsync_start = in->vsync_start;
1543 out->vsync_end = in->vsync_end;
1544 out->vtotal = in->vtotal;
1545 out->vscan = in->vscan;
1546 out->vrefresh = in->vrefresh;
1547 out->flags = in->flags;
1548 out->type = in->type;
1549 strncpy(out->name, in->name, DRM_DISPLAY_MODE_LEN);
1550 out->name[DRM_DISPLAY_MODE_LEN-1] = 0;
1551
1552 out->status = drm_mode_validate_basic(out);
1553 if (out->status != MODE_OK)
1554 goto out;
1555
b201e743
TV
1556 drm_mode_set_crtcinfo(out, CRTC_INTERLACE_HALVE_V);
1557
934a8a89
DS
1558 ret = 0;
1559
1560out:
1561 return ret;
f03d8ede 1562}