[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / drm_scdc_helper.c

/*
 * Copyright (c) 2015 NVIDIA Corporation. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sub license,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#include <linux/slab.h>
#include <linux/delay.h>

#include <drm/drm_scdc_helper.h>
#include <drm/drmP.h>

/**
 * DOC: scdc helpers
 *
 * Status and Control Data Channel (SCDC) is a mechanism introduced by the
 * HDMI 2.0 specification. It is a point-to-point protocol that allows the
 * HDMI source and HDMI sink to exchange data. The same I2C interface that
 * is used to access EDID serves as the transport mechanism for SCDC.
 */

#define SCDC_I2C_SLAVE_ADDRESS 0x54

/**
 * drm_scdc_read - read a block of data from SCDC
 * @adapter: I2C controller
 * @offset: start offset of block to read
 * @buffer: return location for the block to read
 * @size: size of the block to read
 *
 * Reads a block of data from SCDC, starting at a given offset.
 *
 * Returns:
 * 0 on success, negative error code on failure.
 */
ssize_t drm_scdc_read(struct i2c_adapter *adapter, u8 offset, void *buffer,
		      size_t size)
{
	int ret;
	struct i2c_msg msgs[2] = {
		{
			.addr = SCDC_I2C_SLAVE_ADDRESS,
			.flags = 0,
			.len = 1,
			.buf = &offset,
		}, {
			.addr = SCDC_I2C_SLAVE_ADDRESS,
			.flags = I2C_M_RD,
			.len = size,
			.buf = buffer,
		}
	};

	ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
	if (ret < 0)
		return ret;
	if (ret != ARRAY_SIZE(msgs))
		return -EPROTO;

	return 0;
}
EXPORT_SYMBOL(drm_scdc_read);

/**
 * drm_scdc_write - write a block of data to SCDC
 * @adapter: I2C controller
 * @offset: start offset of block to write
 * @buffer: block of data to write
 * @size: size of the block to write
 *
 * Writes a block of data to SCDC, starting at a given offset.
 *
 * Returns:
 * 0 on success, negative error code on failure.
 */
ssize_t drm_scdc_write(struct i2c_adapter *adapter, u8 offset,
		       const void *buffer, size_t size)
{
	struct i2c_msg msg = {
		.addr = SCDC_I2C_SLAVE_ADDRESS,
		.flags = 0,
		.len = 1 + size,
		.buf = NULL,
	};
	void *data;
	int err;

	data = kmalloc(1 + size, GFP_TEMPORARY);
	if (!data)
		return -ENOMEM;

	msg.buf = data;

	memcpy(data, &offset, sizeof(offset));
	memcpy(data + 1, buffer, size);

	err = i2c_transfer(adapter, &msg, 1);

	kfree(data);

	if (err < 0)
		return err;
	if (err != 1)
		return -EPROTO;

	return 0;
}
EXPORT_SYMBOL(drm_scdc_write);

/**
 * drm_scdc_check_scrambling_status - what is status of scrambling?
 * @adapter: I2C adapter for DDC channel
 *
 * Reads the scrambler status over SCDC, and checks the
 * scrambling status.
 *
 * Returns:
 * True if the scrambling is enabled, false otherwise.
 */

bool drm_scdc_get_scrambling_status(struct i2c_adapter *adapter)
{
	u8 status;
	int ret;

	ret = drm_scdc_readb(adapter, SCDC_SCRAMBLER_STATUS, &status);
	if (ret < 0) {
		DRM_ERROR("Failed to read scrambling status, error %d\n", ret);
		return false;
	}

	return status & SCDC_SCRAMBLING_STATUS;
}
EXPORT_SYMBOL(drm_scdc_get_scrambling_status);

/**
 * drm_scdc_set_scrambling - enable scrambling
 * @adapter: I2C adapter for DDC channel
 * @enable: bool to indicate if scrambling is to be enabled/disabled
 *
 * Writes the TMDS config register over SCDC channel, and:
 * enables scrambling when enable = 1
 * disables scrambling when enable = 0
 *
 * Returns:
 * True if scrambling is set/reset successfully, false otherwise.
 */

bool drm_scdc_set_scrambling(struct i2c_adapter *adapter, bool enable)
{
	u8 config;
	int ret;

	ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
	if (ret < 0) {
		DRM_ERROR("Failed to read tmds config, err=%d\n", ret);
		return false;
	}

	if (enable)
		config |= SCDC_SCRAMBLING_ENABLE;
	else
		config &= ~SCDC_SCRAMBLING_ENABLE;

	ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config);
	if (ret < 0) {
		DRM_ERROR("Failed to enable scrambling, error %d\n", ret);
		return false;
	}

	return true;
}
EXPORT_SYMBOL(drm_scdc_set_scrambling);

/**
 * drm_scdc_set_high_tmds_clock_ratio - set TMDS clock ratio
 * @adapter: I2C adapter for DDC channel
 * @set: ret or reset the high clock ratio
 *
 *
 *	TMDS clock ratio calculations go like this:
 *		TMDS character = 10 bit TMDS encoded value
 *
 *		TMDS character rate = The rate at which TMDS characters are
 *		transmitted (Mcsc)
 *
 *		TMDS bit rate = 10x TMDS character rate
 *
 *	As per the spec:
 *		TMDS clock rate for pixel clock < 340 MHz = 1x the character
 *		rate = 1/10 pixel clock rate
 *
 *		TMDS clock rate for pixel clock > 340 MHz = 0.25x the character
 *		rate = 1/40 pixel clock rate
 *
 *	Writes to the TMDS config register over SCDC channel, and:
 *		sets TMDS clock ratio to 1/40 when set = 1
 *
 *		sets TMDS clock ratio to 1/10 when set = 0
 *
 * Returns:
 * True if write is successful, false otherwise.
 */
bool drm_scdc_set_high_tmds_clock_ratio(struct i2c_adapter *adapter, bool set)
{
	u8 config;
	int ret;

	ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
	if (ret < 0) {
		DRM_ERROR("Failed to read tmds config, err=%d\n", ret);
		return false;
	}

	if (set)
		config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40;
	else
		config &= ~SCDC_TMDS_BIT_CLOCK_RATIO_BY_40;

	ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config);
	if (ret < 0) {
		DRM_ERROR("Failed to set TMDS clock ratio, error %d\n", ret);
		return false;
	}

	/*
	 * The spec says that a source should wait minimum 1ms and maximum
	 * 100ms after writing the TMDS config for clock ratio. Lets allow a
	 * wait of upto 2ms here.
	 */
	usleep_range(1000, 2000);
	return true;
}
EXPORT_SYMBOL(drm_scdc_set_high_tmds_clock_ratio);
Commit	Line	Data
3ad33ae2 TR	1	/*
	2	* Copyright (c) 2015 NVIDIA Corporation. All rights reserved.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sub license,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the
	12	* next paragraph) shall be included in all copies or substantial portions
	13	* of the Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	21	* DEALINGS IN THE SOFTWARE.
	22	*/
	23
	24	#include <linux/slab.h>
62c58af3	25	#include <linux/delay.h>
3ad33ae2 TR	26
3ad33ae2 TR	27	#include <drm/drm_scdc_helper.h>
62c58af3	28	#include <drm/drmP.h>
3ad33ae2 TR	29
	30	/**
	31	* DOC: scdc helpers
	32	*
	33	* Status and Control Data Channel (SCDC) is a mechanism introduced by the
	34	* HDMI 2.0 specification. It is a point-to-point protocol that allows the
	35	* HDMI source and HDMI sink to exchange data. The same I2C interface that
	36	* is used to access EDID serves as the transport mechanism for SCDC.
	37	*/
	38
	39	#define SCDC_I2C_SLAVE_ADDRESS 0x54
	40
	41	/**
	42	* drm_scdc_read - read a block of data from SCDC
	43	* @adapter: I2C controller
	44	* @offset: start offset of block to read
	45	* @buffer: return location for the block to read
	46	* @size: size of the block to read
	47	*
	48	* Reads a block of data from SCDC, starting at a given offset.
	49	*
	50	* Returns:
	51	* 0 on success, negative error code on failure.
	52	*/
	53	ssize_t drm_scdc_read(struct i2c_adapter adapter, u8 offset, void buffer,
	54	size_t size)
	55	{
	56	int ret;
	57	struct i2c_msg msgs[2] = {
	58	{
	59	.addr = SCDC_I2C_SLAVE_ADDRESS,
	60	.flags = 0,
	61	.len = 1,
	62	.buf = &offset,
	63	}, {
	64	.addr = SCDC_I2C_SLAVE_ADDRESS,
	65	.flags = I2C_M_RD,
	66	.len = size,
	67	.buf = buffer,
	68	}
	69	};
	70
	71	ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
	72	if (ret < 0)
	73	return ret;
	74	if (ret != ARRAY_SIZE(msgs))
	75	return -EPROTO;
	76
	77	return 0;
	78	}
	79	EXPORT_SYMBOL(drm_scdc_read);
	80
	81	/**
	82	* drm_scdc_write - write a block of data to SCDC
	83	* @adapter: I2C controller
	84	* @offset: start offset of block to write
	85	* @buffer: block of data to write
	86	* @size: size of the block to write
	87	*
	88	* Writes a block of data to SCDC, starting at a given offset.
	89	*
	90	* Returns:
	91	* 0 on success, negative error code on failure.
	92	*/
93	ssize_t drm_scdc_write(struct i2c_adapter *adapter, u8 offset,
94	const void *buffer, size_t size)
95	{
96	struct i2c_msg msg = {
97	.addr = SCDC_I2C_SLAVE_ADDRESS,
98	.flags = 0,
99	.len = 1 + size,
100	.buf = NULL,
101	};
102	void *data;
103	int err;
104
105	data = kmalloc(1 + size, GFP_TEMPORARY);
106	if (!data)
107	return -ENOMEM;
108
109	msg.buf = data;
110
111	memcpy(data, &offset, sizeof(offset));
112	memcpy(data + 1, buffer, size);
113
114	err = i2c_transfer(adapter, &msg, 1);
115
116	kfree(data);
117
118	if (err < 0)
119	return err;
120	if (err != 1)
121	return -EPROTO;
122
123	return 0;
124	}
125	EXPORT_SYMBOL(drm_scdc_write);
62c58af3 SS	126
	127	/**
	128	* drm_scdc_check_scrambling_status - what is status of scrambling?
	129	* @adapter: I2C adapter for DDC channel
	130	*
	131	* Reads the scrambler status over SCDC, and checks the
	132	* scrambling status.
	133	*
	134	* Returns:
	135	* True if the scrambling is enabled, false otherwise.
	136	*/
	137
	138	bool drm_scdc_get_scrambling_status(struct i2c_adapter *adapter)
	139	{
	140	u8 status;
	141	int ret;
	142
	143	ret = drm_scdc_readb(adapter, SCDC_SCRAMBLER_STATUS, &status);
	144	if (ret < 0) {
	145	DRM_ERROR("Failed to read scrambling status, error %d\n", ret);
	146	return false;
	147	}
	148
	149	return status & SCDC_SCRAMBLING_STATUS;
	150	}
	151	EXPORT_SYMBOL(drm_scdc_get_scrambling_status);
	152
	153	/**
	154	* drm_scdc_set_scrambling - enable scrambling
	155	* @adapter: I2C adapter for DDC channel
	156	* @enable: bool to indicate if scrambling is to be enabled/disabled
	157	*
	158	* Writes the TMDS config register over SCDC channel, and:
	159	* enables scrambling when enable = 1
	160	* disables scrambling when enable = 0
	161	*
	162	* Returns:
	163	* True if scrambling is set/reset successfully, false otherwise.
	164	*/
	165
	166	bool drm_scdc_set_scrambling(struct i2c_adapter *adapter, bool enable)
	167	{
	168	u8 config;
	169	int ret;
	170
	171	ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
	172	if (ret < 0) {
	173	DRM_ERROR("Failed to read tmds config, err=%d\n", ret);
	174	return false;
	175	}
	176
	177	if (enable)
	178	config \|= SCDC_SCRAMBLING_ENABLE;
	179	else
	180	config &= ~SCDC_SCRAMBLING_ENABLE;
	181
	182	ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config);
	183	if (ret < 0) {
	184	DRM_ERROR("Failed to enable scrambling, error %d\n", ret);
	185	return false;
	186	}
	187
	188	return true;
	189	}
190	EXPORT_SYMBOL(drm_scdc_set_scrambling);
191
192	/**
193	* drm_scdc_set_high_tmds_clock_ratio - set TMDS clock ratio
194	* @adapter: I2C adapter for DDC channel
195	* @set: ret or reset the high clock ratio
196	*
6c70faf1 SP	197	*
	198	* TMDS clock ratio calculations go like this:
	199	* TMDS character = 10 bit TMDS encoded value
	200	*
	201	* TMDS character rate = The rate at which TMDS characters are
	202	* transmitted (Mcsc)
	203	*
	204	* TMDS bit rate = 10x TMDS character rate
	205	*
	206	* As per the spec:
	207	* TMDS clock rate for pixel clock < 340 MHz = 1x the character
	208	* rate = 1/10 pixel clock rate
	209	*
	210	* TMDS clock rate for pixel clock > 340 MHz = 0.25x the character
	211	* rate = 1/40 pixel clock rate
	212	*
	213	* Writes to the TMDS config register over SCDC channel, and:
	214	* sets TMDS clock ratio to 1/40 when set = 1
	215	*
	216	* sets TMDS clock ratio to 1/10 when set = 0
62c58af3 SS	217	*
	218	* Returns:
	219	* True if write is successful, false otherwise.
	220	*/
	221	bool drm_scdc_set_high_tmds_clock_ratio(struct i2c_adapter *adapter, bool set)
	222	{
	223	u8 config;
	224	int ret;
	225
	226	ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
	227	if (ret < 0) {
	228	DRM_ERROR("Failed to read tmds config, err=%d\n", ret);
	229	return false;
	230	}
	231
	232	if (set)
	233	config \|= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40;
	234	else
	235	config &= ~SCDC_TMDS_BIT_CLOCK_RATIO_BY_40;
	236
	237	ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config);
	238	if (ret < 0) {
	239	DRM_ERROR("Failed to set TMDS clock ratio, error %d\n", ret);
	240	return false;
	241	}
	242
	243	/*
	244	* The spec says that a source should wait minimum 1ms and maximum
	245	* 100ms after writing the TMDS config for clock ratio. Lets allow a
	246	* wait of upto 2ms here.
	247	*/
	248	usleep_range(1000, 2000);
	249	return true;
	250	}
	251	EXPORT_SYMBOL(drm_scdc_set_high_tmds_clock_ratio);