[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / etnaviv / etnaviv_buffer.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2014-2018 Etnaviv Project
 */

#include <drm/drm_drv.h>

#include "etnaviv_cmdbuf.h"
#include "etnaviv_gpu.h"
#include "etnaviv_gem.h"
#include "etnaviv_mmu.h"

#include "common.xml.h"
#include "state.xml.h"
#include "state_blt.xml.h"
#include "state_hi.xml.h"
#include "state_3d.xml.h"
#include "cmdstream.xml.h"

/*
 * Command Buffer helper:
 */


static inline void OUT(struct etnaviv_cmdbuf *buffer, u32 data)
{
	u32 *vaddr = (u32 *)buffer->vaddr;

	BUG_ON(buffer->user_size >= buffer->size);

	vaddr[buffer->user_size / 4] = data;
	buffer->user_size += 4;
}

static inline void CMD_LOAD_STATE(struct etnaviv_cmdbuf *buffer,
	u32 reg, u32 value)
{
	u32 index = reg >> VIV_FE_LOAD_STATE_HEADER_OFFSET__SHR;

	buffer->user_size = ALIGN(buffer->user_size, 8);

	/* write a register via cmd stream */
	OUT(buffer, VIV_FE_LOAD_STATE_HEADER_OP_LOAD_STATE |
		    VIV_FE_LOAD_STATE_HEADER_COUNT(1) |
		    VIV_FE_LOAD_STATE_HEADER_OFFSET(index));
	OUT(buffer, value);
}

static inline void CMD_END(struct etnaviv_cmdbuf *buffer)
{
	buffer->user_size = ALIGN(buffer->user_size, 8);

	OUT(buffer, VIV_FE_END_HEADER_OP_END);
}

static inline void CMD_WAIT(struct etnaviv_cmdbuf *buffer)
{
	buffer->user_size = ALIGN(buffer->user_size, 8);

	OUT(buffer, VIV_FE_WAIT_HEADER_OP_WAIT | 200);
}

static inline void CMD_LINK(struct etnaviv_cmdbuf *buffer,
	u16 prefetch, u32 address)
{
	buffer->user_size = ALIGN(buffer->user_size, 8);

	OUT(buffer, VIV_FE_LINK_HEADER_OP_LINK |
		    VIV_FE_LINK_HEADER_PREFETCH(prefetch));
	OUT(buffer, address);
}

static inline void CMD_STALL(struct etnaviv_cmdbuf *buffer,
	u32 from, u32 to)
{
	buffer->user_size = ALIGN(buffer->user_size, 8);

	OUT(buffer, VIV_FE_STALL_HEADER_OP_STALL);
	OUT(buffer, VIV_FE_STALL_TOKEN_FROM(from) | VIV_FE_STALL_TOKEN_TO(to));
}

static inline void CMD_SEM(struct etnaviv_cmdbuf *buffer, u32 from, u32 to)
{
	CMD_LOAD_STATE(buffer, VIVS_GL_SEMAPHORE_TOKEN,
		       VIVS_GL_SEMAPHORE_TOKEN_FROM(from) |
		       VIVS_GL_SEMAPHORE_TOKEN_TO(to));
}

static void etnaviv_cmd_select_pipe(struct etnaviv_gpu *gpu,
	struct etnaviv_cmdbuf *buffer, u8 pipe)
{
	u32 flush = 0;

	lockdep_assert_held(&gpu->lock);

	/*
	 * This assumes that if we're switching to 2D, we're switching
	 * away from 3D, and vice versa.  Hence, if we're switching to
	 * the 2D core, we need to flush the 3D depth and color caches,
	 * otherwise we need to flush the 2D pixel engine cache.
	 */
	if (gpu->exec_state == ETNA_PIPE_2D)
		flush = VIVS_GL_FLUSH_CACHE_PE2D;
	else if (gpu->exec_state == ETNA_PIPE_3D)
		flush = VIVS_GL_FLUSH_CACHE_DEPTH | VIVS_GL_FLUSH_CACHE_COLOR;

	CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_CACHE, flush);
	CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
	CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);

	CMD_LOAD_STATE(buffer, VIVS_GL_PIPE_SELECT,
		       VIVS_GL_PIPE_SELECT_PIPE(pipe));
}

static void etnaviv_buffer_dump(struct etnaviv_gpu *gpu,
	struct etnaviv_cmdbuf *buf, u32 off, u32 len)
{
	u32 size = buf->size;
	u32 *ptr = buf->vaddr + off;

	dev_info(gpu->dev, "virt %p phys 0x%08x free 0x%08x\n",
			ptr, etnaviv_cmdbuf_get_va(buf,
			&gpu->mmu_context->cmdbuf_mapping) +
			off, size - len * 4 - off);

	print_hex_dump(KERN_INFO, "cmd ", DUMP_PREFIX_OFFSET, 16, 4,
			ptr, len * 4, 0);
}

/*
 * Safely replace the WAIT of a waitlink with a new command and argument.
 * The GPU may be executing this WAIT while we're modifying it, so we have
 * to write it in a specific order to avoid the GPU branching to somewhere
 * else.  'wl_offset' is the offset to the first byte of the WAIT command.
 */
static void etnaviv_buffer_replace_wait(struct etnaviv_cmdbuf *buffer,
	unsigned int wl_offset, u32 cmd, u32 arg)
{
	u32 *lw = buffer->vaddr + wl_offset;

	lw[1] = arg;
	mb();
	lw[0] = cmd;
	mb();
}

/*
 * Ensure that there is space in the command buffer to contiguously write
 * 'cmd_dwords' 64-bit words into the buffer, wrapping if necessary.
 */
static u32 etnaviv_buffer_reserve(struct etnaviv_gpu *gpu,
	struct etnaviv_cmdbuf *buffer, unsigned int cmd_dwords)
{
	if (buffer->user_size + cmd_dwords * sizeof(u64) > buffer->size)
		buffer->user_size = 0;

	return etnaviv_cmdbuf_get_va(buffer,
				     &gpu->mmu_context->cmdbuf_mapping) +
	       buffer->user_size;
}

u16 etnaviv_buffer_init(struct etnaviv_gpu *gpu)
{
	struct etnaviv_cmdbuf *buffer = &gpu->buffer;

	lockdep_assert_held(&gpu->lock);

	/* initialize buffer */
	buffer->user_size = 0;

	CMD_WAIT(buffer);
	CMD_LINK(buffer, 2,
		 etnaviv_cmdbuf_get_va(buffer, &gpu->mmu_context->cmdbuf_mapping)
		 + buffer->user_size - 4);

	return buffer->user_size / 8;
}

u16 etnaviv_buffer_config_mmuv2(struct etnaviv_gpu *gpu, u32 mtlb_addr, u32 safe_addr)
{
	struct etnaviv_cmdbuf *buffer = &gpu->buffer;

	lockdep_assert_held(&gpu->lock);

	buffer->user_size = 0;

	if (gpu->identity.features & chipFeatures_PIPE_3D) {
		CMD_LOAD_STATE(buffer, VIVS_GL_PIPE_SELECT,
			       VIVS_GL_PIPE_SELECT_PIPE(ETNA_PIPE_3D));
		CMD_LOAD_STATE(buffer, VIVS_MMUv2_CONFIGURATION,
			mtlb_addr | VIVS_MMUv2_CONFIGURATION_MODE_MODE4_K);
		CMD_LOAD_STATE(buffer, VIVS_MMUv2_SAFE_ADDRESS, safe_addr);
		CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
		CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
	}

	if (gpu->identity.features & chipFeatures_PIPE_2D) {
		CMD_LOAD_STATE(buffer, VIVS_GL_PIPE_SELECT,
			       VIVS_GL_PIPE_SELECT_PIPE(ETNA_PIPE_2D));
		CMD_LOAD_STATE(buffer, VIVS_MMUv2_CONFIGURATION,
			mtlb_addr | VIVS_MMUv2_CONFIGURATION_MODE_MODE4_K);
		CMD_LOAD_STATE(buffer, VIVS_MMUv2_SAFE_ADDRESS, safe_addr);
		CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
		CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
	}

	CMD_END(buffer);

	buffer->user_size = ALIGN(buffer->user_size, 8);

	return buffer->user_size / 8;
}

u16 etnaviv_buffer_config_pta(struct etnaviv_gpu *gpu, unsigned short id)
{
	struct etnaviv_cmdbuf *buffer = &gpu->buffer;

	lockdep_assert_held(&gpu->lock);

	buffer->user_size = 0;

	CMD_LOAD_STATE(buffer, VIVS_MMUv2_PTA_CONFIG,
		       VIVS_MMUv2_PTA_CONFIG_INDEX(id));

	CMD_END(buffer);

	buffer->user_size = ALIGN(buffer->user_size, 8);

	return buffer->user_size / 8;
}

void etnaviv_buffer_end(struct etnaviv_gpu *gpu)
{
	struct etnaviv_cmdbuf *buffer = &gpu->buffer;
	unsigned int waitlink_offset = buffer->user_size - 16;
	u32 link_target, flush = 0;
	bool has_blt = !!(gpu->identity.minor_features5 &
			  chipMinorFeatures5_BLT_ENGINE);

	lockdep_assert_held(&gpu->lock);

	if (gpu->exec_state == ETNA_PIPE_2D)
		flush = VIVS_GL_FLUSH_CACHE_PE2D;
	else if (gpu->exec_state == ETNA_PIPE_3D)
		flush = VIVS_GL_FLUSH_CACHE_DEPTH |
			VIVS_GL_FLUSH_CACHE_COLOR |
			VIVS_GL_FLUSH_CACHE_TEXTURE |
			VIVS_GL_FLUSH_CACHE_TEXTUREVS |
			VIVS_GL_FLUSH_CACHE_SHADER_L2;

	if (flush) {
		unsigned int dwords = 7;

		if (has_blt)
			dwords += 10;

		link_target = etnaviv_buffer_reserve(gpu, buffer, dwords);

		CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
		CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
		if (has_blt) {
			CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x1);
			CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_BLT);
			CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_BLT);
			CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x0);
		}
		CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_CACHE, flush);
		if (gpu->exec_state == ETNA_PIPE_3D) {
			if (has_blt) {
				CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x1);
				CMD_LOAD_STATE(buffer, VIVS_BLT_SET_COMMAND, 0x1);
				CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x0);
			} else {
				CMD_LOAD_STATE(buffer, VIVS_TS_FLUSH_CACHE,
					       VIVS_TS_FLUSH_CACHE_FLUSH);
			}
		}
		CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
		CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
		if (has_blt) {
			CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x1);
			CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_BLT);
			CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_BLT);
			CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x0);
		}
		CMD_END(buffer);

		etnaviv_buffer_replace_wait(buffer, waitlink_offset,
					    VIV_FE_LINK_HEADER_OP_LINK |
					    VIV_FE_LINK_HEADER_PREFETCH(dwords),
					    link_target);
	} else {
		/* Replace the last link-wait with an "END" command */
		etnaviv_buffer_replace_wait(buffer, waitlink_offset,
					    VIV_FE_END_HEADER_OP_END, 0);
	}
}

/* Append a 'sync point' to the ring buffer. */
void etnaviv_sync_point_queue(struct etnaviv_gpu *gpu, unsigned int event)
{
	struct etnaviv_cmdbuf *buffer = &gpu->buffer;
	unsigned int waitlink_offset = buffer->user_size - 16;
	u32 dwords, target;

	lockdep_assert_held(&gpu->lock);

	/*
	 * We need at most 3 dwords in the return target:
	 * 1 event + 1 end + 1 wait + 1 link.
	 */
	dwords = 4;
	target = etnaviv_buffer_reserve(gpu, buffer, dwords);

	/* Signal sync point event */
	CMD_LOAD_STATE(buffer, VIVS_GL_EVENT, VIVS_GL_EVENT_EVENT_ID(event) |
		       VIVS_GL_EVENT_FROM_PE);

	/* Stop the FE to 'pause' the GPU */
	CMD_END(buffer);

	/* Append waitlink */
	CMD_WAIT(buffer);
	CMD_LINK(buffer, 2,
		 etnaviv_cmdbuf_get_va(buffer, &gpu->mmu_context->cmdbuf_mapping)
		 + buffer->user_size - 4);

	/*
	 * Kick off the 'sync point' command by replacing the previous
	 * WAIT with a link to the address in the ring buffer.
	 */
	etnaviv_buffer_replace_wait(buffer, waitlink_offset,
				    VIV_FE_LINK_HEADER_OP_LINK |
				    VIV_FE_LINK_HEADER_PREFETCH(dwords),
				    target);
}

/* Append a command buffer to the ring buffer. */
void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32 exec_state,
	struct etnaviv_iommu_context *mmu_context, unsigned int event,
	struct etnaviv_cmdbuf *cmdbuf)
{
	struct etnaviv_cmdbuf *buffer = &gpu->buffer;
	unsigned int waitlink_offset = buffer->user_size - 16;
	u32 return_target, return_dwords;
	u32 link_target, link_dwords;
	bool switch_context = gpu->exec_state != exec_state;
	bool switch_mmu_context = gpu->mmu_context != mmu_context;
	unsigned int new_flush_seq = READ_ONCE(gpu->mmu_context->flush_seq);
	bool need_flush = switch_mmu_context || gpu->flush_seq != new_flush_seq;
	bool has_blt = !!(gpu->identity.minor_features5 &
			  chipMinorFeatures5_BLT_ENGINE);

	lockdep_assert_held(&gpu->lock);

	if (drm_debug_enabled(DRM_UT_DRIVER))
		etnaviv_buffer_dump(gpu, buffer, 0, 0x50);

	link_target = etnaviv_cmdbuf_get_va(cmdbuf,
					    &gpu->mmu_context->cmdbuf_mapping);
	link_dwords = cmdbuf->size / 8;

	/*
	 * If we need maintenance prior to submitting this buffer, we will
	 * need to append a mmu flush load state, followed by a new
	 * link to this buffer - a total of four additional words.
	 */
	if (need_flush || switch_context) {
		u32 target, extra_dwords;

		/* link command */
		extra_dwords = 1;

		/* flush command */
		if (need_flush) {
			if (gpu->mmu_context->global->version == ETNAVIV_IOMMU_V1)
				extra_dwords += 1;
			else
				extra_dwords += 3;
		}

		/* pipe switch commands */
		if (switch_context)
			extra_dwords += 4;

		/* PTA load command */
		if (switch_mmu_context && gpu->sec_mode == ETNA_SEC_KERNEL)
			extra_dwords += 1;

		target = etnaviv_buffer_reserve(gpu, buffer, extra_dwords);
		/*
		 * Switch MMU context if necessary. Must be done after the
		 * link target has been calculated, as the jump forward in the
		 * kernel ring still uses the last active MMU context before
		 * the switch.
		 */
		if (switch_mmu_context) {
			struct etnaviv_iommu_context *old_context = gpu->mmu_context;

			gpu->mmu_context = etnaviv_iommu_context_get(mmu_context);
			etnaviv_iommu_context_put(old_context);
		}

		if (need_flush) {
			/* Add the MMU flush */
			if (gpu->mmu_context->global->version == ETNAVIV_IOMMU_V1) {
				CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_MMU,
					       VIVS_GL_FLUSH_MMU_FLUSH_FEMMU |
					       VIVS_GL_FLUSH_MMU_FLUSH_UNK1 |
					       VIVS_GL_FLUSH_MMU_FLUSH_UNK2 |
					       VIVS_GL_FLUSH_MMU_FLUSH_PEMMU |
					       VIVS_GL_FLUSH_MMU_FLUSH_UNK4);
			} else {
				u32 flush = VIVS_MMUv2_CONFIGURATION_MODE_MASK |
					    VIVS_MMUv2_CONFIGURATION_FLUSH_FLUSH;

				if (switch_mmu_context &&
				    gpu->sec_mode == ETNA_SEC_KERNEL) {
					unsigned short id =
						etnaviv_iommuv2_get_pta_id(gpu->mmu_context);
					CMD_LOAD_STATE(buffer,
						VIVS_MMUv2_PTA_CONFIG,
						VIVS_MMUv2_PTA_CONFIG_INDEX(id));
				}

				if (gpu->sec_mode == ETNA_SEC_NONE)
					flush |= etnaviv_iommuv2_get_mtlb_addr(gpu->mmu_context);

				CMD_LOAD_STATE(buffer, VIVS_MMUv2_CONFIGURATION,
					       flush);
				CMD_SEM(buffer, SYNC_RECIPIENT_FE,
					SYNC_RECIPIENT_PE);
				CMD_STALL(buffer, SYNC_RECIPIENT_FE,
					SYNC_RECIPIENT_PE);
			}

			gpu->flush_seq = new_flush_seq;
		}

		if (switch_context) {
			etnaviv_cmd_select_pipe(gpu, buffer, exec_state);
			gpu->exec_state = exec_state;
		}

		/* And the link to the submitted buffer */
		link_target = etnaviv_cmdbuf_get_va(cmdbuf,
					&gpu->mmu_context->cmdbuf_mapping);
		CMD_LINK(buffer, link_dwords, link_target);

		/* Update the link target to point to above instructions */
		link_target = target;
		link_dwords = extra_dwords;
	}

	/*
	 * Append a LINK to the submitted command buffer to return to
	 * the ring buffer.  return_target is the ring target address.
	 * We need at most 7 dwords in the return target: 2 cache flush +
	 * 2 semaphore stall + 1 event + 1 wait + 1 link.
	 */
	return_dwords = 7;

	/*
	 * When the BLT engine is present we need 6 more dwords in the return
	 * target: 3 enable/flush/disable + 4 enable/semaphore stall/disable,
	 * but we don't need the normal TS flush state.
	 */
	if (has_blt)
		return_dwords += 6;

	return_target = etnaviv_buffer_reserve(gpu, buffer, return_dwords);
	CMD_LINK(cmdbuf, return_dwords, return_target);

	/*
	 * Append a cache flush, stall, event, wait and link pointing back to
	 * the wait command to the ring buffer.
	 */
	if (gpu->exec_state == ETNA_PIPE_2D) {
		CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_CACHE,
				       VIVS_GL_FLUSH_CACHE_PE2D);
	} else {
		CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_CACHE,
				       VIVS_GL_FLUSH_CACHE_DEPTH |
				       VIVS_GL_FLUSH_CACHE_COLOR);
		if (has_blt) {
			CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x1);
			CMD_LOAD_STATE(buffer, VIVS_BLT_SET_COMMAND, 0x1);
			CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x0);
		} else {
			CMD_LOAD_STATE(buffer, VIVS_TS_FLUSH_CACHE,
					       VIVS_TS_FLUSH_CACHE_FLUSH);
		}
	}
	CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
	CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);

	if (has_blt) {
		CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x1);
		CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_BLT);
		CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_BLT);
		CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x0);
	}

	CMD_LOAD_STATE(buffer, VIVS_GL_EVENT, VIVS_GL_EVENT_EVENT_ID(event) |
		       VIVS_GL_EVENT_FROM_PE);
	CMD_WAIT(buffer);
	CMD_LINK(buffer, 2,
		 etnaviv_cmdbuf_get_va(buffer, &gpu->mmu_context->cmdbuf_mapping)
		 + buffer->user_size - 4);

	if (drm_debug_enabled(DRM_UT_DRIVER))
		pr_info("stream link to 0x%08x @ 0x%08x %p\n",
			return_target,
			etnaviv_cmdbuf_get_va(cmdbuf, &gpu->mmu_context->cmdbuf_mapping),
			cmdbuf->vaddr);

	if (drm_debug_enabled(DRM_UT_DRIVER)) {
		print_hex_dump(KERN_INFO, "cmd ", DUMP_PREFIX_OFFSET, 16, 4,
			       cmdbuf->vaddr, cmdbuf->size, 0);

		pr_info("link op: %p\n", buffer->vaddr + waitlink_offset);
		pr_info("addr: 0x%08x\n", link_target);
		pr_info("back: 0x%08x\n", return_target);
		pr_info("event: %d\n", event);
	}

	/*
	 * Kick off the submitted command by replacing the previous
	 * WAIT with a link to the address in the ring buffer.
	 */
	etnaviv_buffer_replace_wait(buffer, waitlink_offset,
				    VIV_FE_LINK_HEADER_OP_LINK |
				    VIV_FE_LINK_HEADER_PREFETCH(link_dwords),
				    link_target);

	if (drm_debug_enabled(DRM_UT_DRIVER))
		etnaviv_buffer_dump(gpu, buffer, 0, 0x50);
}
Commit	Line	Data
f6ffbd4f	1	// SPDX-License-Identifier: GPL-2.0
a8c21a54	2	/*
f6ffbd4f	3	* Copyright (C) 2014-2018 Etnaviv Project
a8c21a54 T	4	*/
a8c21a54 T	5
6eae41fe SR	6	#include <drm/drm_drv.h>
6eae41fe SR	7
ea1f5729	8	#include "etnaviv_cmdbuf.h"
a8c21a54 T	9	#include "etnaviv_gpu.h"
	10	#include "etnaviv_gem.h"
	11	#include "etnaviv_mmu.h"
	12
	13	#include "common.xml.h"
	14	#include "state.xml.h"
f232d9ec	15	#include "state_blt.xml.h"
de08e8ef	16	#include "state_hi.xml.h"
8581d814	17	#include "state_3d.xml.h"
a8c21a54 T	18	#include "cmdstream.xml.h"
	19
	20	/*
	21	* Command Buffer helper:
	22	*/
	23
	24
	25	static inline void OUT(struct etnaviv_cmdbuf *buffer, u32 data)
	26	{
	27	u32 vaddr = (u32 )buffer->vaddr;
	28
	29	BUG_ON(buffer->user_size >= buffer->size);
	30
	31	vaddr[buffer->user_size / 4] = data;
	32	buffer->user_size += 4;
	33	}
	34
	35	static inline void CMD_LOAD_STATE(struct etnaviv_cmdbuf *buffer,
	36	u32 reg, u32 value)
	37	{
	38	u32 index = reg >> VIV_FE_LOAD_STATE_HEADER_OFFSET__SHR;
	39
	40	buffer->user_size = ALIGN(buffer->user_size, 8);
	41
	42	/* write a register via cmd stream */
	43	OUT(buffer, VIV_FE_LOAD_STATE_HEADER_OP_LOAD_STATE \|
	44	VIV_FE_LOAD_STATE_HEADER_COUNT(1) \|
	45	VIV_FE_LOAD_STATE_HEADER_OFFSET(index));
	46	OUT(buffer, value);
	47	}
	48
	49	static inline void CMD_END(struct etnaviv_cmdbuf *buffer)
	50	{
	51	buffer->user_size = ALIGN(buffer->user_size, 8);
	52
	53	OUT(buffer, VIV_FE_END_HEADER_OP_END);
	54	}
	55
	56	static inline void CMD_WAIT(struct etnaviv_cmdbuf *buffer)
	57	{
	58	buffer->user_size = ALIGN(buffer->user_size, 8);
	59
	60	OUT(buffer, VIV_FE_WAIT_HEADER_OP_WAIT \| 200);
	61	}
	62
	63	static inline void CMD_LINK(struct etnaviv_cmdbuf *buffer,
	64	u16 prefetch, u32 address)
	65	{
	66	buffer->user_size = ALIGN(buffer->user_size, 8);
	67
	68	OUT(buffer, VIV_FE_LINK_HEADER_OP_LINK \|
	69	VIV_FE_LINK_HEADER_PREFETCH(prefetch));
	70	OUT(buffer, address);
	71	}
	72
	73	static inline void CMD_STALL(struct etnaviv_cmdbuf *buffer,
	74	u32 from, u32 to)
	75	{
	76	buffer->user_size = ALIGN(buffer->user_size, 8);
	77
	78	OUT(buffer, VIV_FE_STALL_HEADER_OP_STALL);
	79	OUT(buffer, VIV_FE_STALL_TOKEN_FROM(from) \| VIV_FE_STALL_TOKEN_TO(to));
	80	}
	81
18060f4d RK	82	static inline void CMD_SEM(struct etnaviv_cmdbuf *buffer, u32 from, u32 to)
	83	{
	84	CMD_LOAD_STATE(buffer, VIVS_GL_SEMAPHORE_TOKEN,
	85	VIVS_GL_SEMAPHORE_TOKEN_FROM(from) \|
	86	VIVS_GL_SEMAPHORE_TOKEN_TO(to));
	87	}
	88
90747b95 RK	89	static void etnaviv_cmd_select_pipe(struct etnaviv_gpu *gpu,
90747b95 RK	90	struct etnaviv_cmdbuf *buffer, u8 pipe)
a8c21a54	91	{
90747b95	92	u32 flush = 0;
a8c21a54	93
b6d6223f LS	94	lockdep_assert_held(&gpu->lock);
b6d6223f LS	95
a8c21a54 T	96	/*
	97	* This assumes that if we're switching to 2D, we're switching
	98	* away from 3D, and vice versa. Hence, if we're switching to
	99	* the 2D core, we need to flush the 3D depth and color caches,
	100	* otherwise we need to flush the 2D pixel engine cache.
	101	*/
90747b95	102	if (gpu->exec_state == ETNA_PIPE_2D)
a8c21a54	103	flush = VIVS_GL_FLUSH_CACHE_PE2D;
90747b95 RK	104	else if (gpu->exec_state == ETNA_PIPE_3D)
90747b95 RK	105	flush = VIVS_GL_FLUSH_CACHE_DEPTH \| VIVS_GL_FLUSH_CACHE_COLOR;
a8c21a54	106
a8c21a54	107	CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_CACHE, flush);
18060f4d	108	CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
a8c21a54 T	109	CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
	110
	111	CMD_LOAD_STATE(buffer, VIVS_GL_PIPE_SELECT,
	112	VIVS_GL_PIPE_SELECT_PIPE(pipe));
	113	}
	114
a8c21a54 T	115	static void etnaviv_buffer_dump(struct etnaviv_gpu *gpu,
	116	struct etnaviv_cmdbuf *buf, u32 off, u32 len)
	117	{
	118	u32 size = buf->size;
	119	u32 *ptr = buf->vaddr + off;
	120
	121	dev_info(gpu->dev, "virt %p phys 0x%08x free 0x%08x\n",
17e4660a LS	122	ptr, etnaviv_cmdbuf_get_va(buf,
17e4660a LS	123	&gpu->mmu_context->cmdbuf_mapping) +
db82a043	124	off, size - len * 4 - off);
a8c21a54 T	125
	126	print_hex_dump(KERN_INFO, "cmd ", DUMP_PREFIX_OFFSET, 16, 4,
	127	ptr, len * 4, 0);
	128	}
	129
6e138f76 RK	130	/*
	131	* Safely replace the WAIT of a waitlink with a new command and argument.
	132	* The GPU may be executing this WAIT while we're modifying it, so we have
	133	* to write it in a specific order to avoid the GPU branching to somewhere
	134	* else. 'wl_offset' is the offset to the first byte of the WAIT command.
	135	*/
	136	static void etnaviv_buffer_replace_wait(struct etnaviv_cmdbuf *buffer,
	137	unsigned int wl_offset, u32 cmd, u32 arg)
	138	{
	139	u32 *lw = buffer->vaddr + wl_offset;
	140
	141	lw[1] = arg;
	142	mb();
	143	lw[0] = cmd;
	144	mb();
	145	}
	146
584a13c6 RK	147	/*
	148	* Ensure that there is space in the command buffer to contiguously write
	149	* 'cmd_dwords' 64-bit words into the buffer, wrapping if necessary.
	150	*/
	151	static u32 etnaviv_buffer_reserve(struct etnaviv_gpu *gpu,
	152	struct etnaviv_cmdbuf *buffer, unsigned int cmd_dwords)
	153	{
	154	if (buffer->user_size + cmd_dwords * sizeof(u64) > buffer->size)
	155	buffer->user_size = 0;
	156
17e4660a LS	157	return etnaviv_cmdbuf_get_va(buffer,
17e4660a LS	158	&gpu->mmu_context->cmdbuf_mapping) +
db82a043	159	buffer->user_size;
584a13c6 RK	160	}
584a13c6 RK	161
a8c21a54 T	162	u16 etnaviv_buffer_init(struct etnaviv_gpu *gpu)
a8c21a54 T	163	{
2f9225db	164	struct etnaviv_cmdbuf *buffer = &gpu->buffer;
a8c21a54	165
b6d6223f LS	166	lockdep_assert_held(&gpu->lock);
b6d6223f LS	167
a8c21a54 T	168	/* initialize buffer */
	169	buffer->user_size = 0;
	170
	171	CMD_WAIT(buffer);
17e4660a LS	172	CMD_LINK(buffer, 2,
17e4660a LS	173	etnaviv_cmdbuf_get_va(buffer, &gpu->mmu_context->cmdbuf_mapping)
db82a043	174	+ buffer->user_size - 4);
a8c21a54 T	175
	176	return buffer->user_size / 8;
	177	}
	178
de08e8ef LS	179	u16 etnaviv_buffer_config_mmuv2(struct etnaviv_gpu *gpu, u32 mtlb_addr, u32 safe_addr)
de08e8ef LS	180	{
2f9225db	181	struct etnaviv_cmdbuf *buffer = &gpu->buffer;
de08e8ef	182
b6d6223f LS	183	lockdep_assert_held(&gpu->lock);
b6d6223f LS	184
de08e8ef LS	185	buffer->user_size = 0;
	186
	187	if (gpu->identity.features & chipFeatures_PIPE_3D) {
	188	CMD_LOAD_STATE(buffer, VIVS_GL_PIPE_SELECT,
	189	VIVS_GL_PIPE_SELECT_PIPE(ETNA_PIPE_3D));
	190	CMD_LOAD_STATE(buffer, VIVS_MMUv2_CONFIGURATION,
	191	mtlb_addr \| VIVS_MMUv2_CONFIGURATION_MODE_MODE4_K);
	192	CMD_LOAD_STATE(buffer, VIVS_MMUv2_SAFE_ADDRESS, safe_addr);
	193	CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
	194	CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
	195	}
	196
	197	if (gpu->identity.features & chipFeatures_PIPE_2D) {
	198	CMD_LOAD_STATE(buffer, VIVS_GL_PIPE_SELECT,
	199	VIVS_GL_PIPE_SELECT_PIPE(ETNA_PIPE_2D));
	200	CMD_LOAD_STATE(buffer, VIVS_MMUv2_CONFIGURATION,
	201	mtlb_addr \| VIVS_MMUv2_CONFIGURATION_MODE_MODE4_K);
	202	CMD_LOAD_STATE(buffer, VIVS_MMUv2_SAFE_ADDRESS, safe_addr);
	203	CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
	204	CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
	205	}
	206
	207	CMD_END(buffer);
	208
	209	buffer->user_size = ALIGN(buffer->user_size, 8);
	210
	211	return buffer->user_size / 8;
	212	}
	213
27b67278	214	u16 etnaviv_buffer_config_pta(struct etnaviv_gpu *gpu, unsigned short id)
1137bef6 LS	215	{
	216	struct etnaviv_cmdbuf *buffer = &gpu->buffer;
	217
	218	lockdep_assert_held(&gpu->lock);
	219
	220	buffer->user_size = 0;
	221
	222	CMD_LOAD_STATE(buffer, VIVS_MMUv2_PTA_CONFIG,
27b67278	223	VIVS_MMUv2_PTA_CONFIG_INDEX(id));
1137bef6 LS	224
	225	CMD_END(buffer);
	226
	227	buffer->user_size = ALIGN(buffer->user_size, 8);
	228
	229	return buffer->user_size / 8;
	230	}
	231
a8c21a54 T	232	void etnaviv_buffer_end(struct etnaviv_gpu *gpu)
a8c21a54 T	233	{
2f9225db	234	struct etnaviv_cmdbuf *buffer = &gpu->buffer;
8581d814 RK	235	unsigned int waitlink_offset = buffer->user_size - 16;
8581d814 RK	236	u32 link_target, flush = 0;
f232d9ec LS	237	bool has_blt = !!(gpu->identity.minor_features5 &
f232d9ec LS	238	chipMinorFeatures5_BLT_ENGINE);
a8c21a54	239
b6d6223f LS	240	lockdep_assert_held(&gpu->lock);
b6d6223f LS	241
8581d814 RK	242	if (gpu->exec_state == ETNA_PIPE_2D)
	243	flush = VIVS_GL_FLUSH_CACHE_PE2D;
	244	else if (gpu->exec_state == ETNA_PIPE_3D)
	245	flush = VIVS_GL_FLUSH_CACHE_DEPTH \|
	246	VIVS_GL_FLUSH_CACHE_COLOR \|
	247	VIVS_GL_FLUSH_CACHE_TEXTURE \|
	248	VIVS_GL_FLUSH_CACHE_TEXTUREVS \|
	249	VIVS_GL_FLUSH_CACHE_SHADER_L2;
	250
	251	if (flush) {
	252	unsigned int dwords = 7;
	253
f232d9ec LS	254	if (has_blt)
	255	dwords += 10;
	256
8581d814 RK	257	link_target = etnaviv_buffer_reserve(gpu, buffer, dwords);
	258
	259	CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
	260	CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
f232d9ec LS	261	if (has_blt) {
	262	CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x1);
	263	CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_BLT);
	264	CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_BLT);
	265	CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x0);
	266	}
8581d814	267	CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_CACHE, flush);
f232d9ec LS	268	if (gpu->exec_state == ETNA_PIPE_3D) {
	269	if (has_blt) {
	270	CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x1);
	271	CMD_LOAD_STATE(buffer, VIVS_BLT_SET_COMMAND, 0x1);
	272	CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x0);
	273	} else {
	274	CMD_LOAD_STATE(buffer, VIVS_TS_FLUSH_CACHE,
	275	VIVS_TS_FLUSH_CACHE_FLUSH);
	276	}
	277	}
8581d814 RK	278	CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
8581d814 RK	279	CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
f232d9ec LS	280	if (has_blt) {
	281	CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x1);
	282	CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_BLT);
	283	CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_BLT);
	284	CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x0);
	285	}
8581d814 RK	286	CMD_END(buffer);
	287
	288	etnaviv_buffer_replace_wait(buffer, waitlink_offset,
	289	VIV_FE_LINK_HEADER_OP_LINK \|
	290	VIV_FE_LINK_HEADER_PREFETCH(dwords),
	291	link_target);
	292	} else {
	293	/* Replace the last link-wait with an "END" command */
	294	etnaviv_buffer_replace_wait(buffer, waitlink_offset,
	295	VIV_FE_END_HEADER_OP_END, 0);
	296	}
a8c21a54 T	297	}
a8c21a54 T	298
357713ce CG	299	/* Append a 'sync point' to the ring buffer. */
	300	void etnaviv_sync_point_queue(struct etnaviv_gpu *gpu, unsigned int event)
	301	{
2f9225db	302	struct etnaviv_cmdbuf *buffer = &gpu->buffer;
357713ce CG	303	unsigned int waitlink_offset = buffer->user_size - 16;
	304	u32 dwords, target;
	305
b6d6223f LS	306	lockdep_assert_held(&gpu->lock);
b6d6223f LS	307
357713ce CG	308	/*
	309	* We need at most 3 dwords in the return target:
	310	* 1 event + 1 end + 1 wait + 1 link.
	311	*/
	312	dwords = 4;
	313	target = etnaviv_buffer_reserve(gpu, buffer, dwords);
	314
	315	/* Signal sync point event */
	316	CMD_LOAD_STATE(buffer, VIVS_GL_EVENT, VIVS_GL_EVENT_EVENT_ID(event) \|
	317	VIVS_GL_EVENT_FROM_PE);
	318
	319	/* Stop the FE to 'pause' the GPU */
	320	CMD_END(buffer);
	321
	322	/* Append waitlink */
	323	CMD_WAIT(buffer);
17e4660a LS	324	CMD_LINK(buffer, 2,
17e4660a LS	325	etnaviv_cmdbuf_get_va(buffer, &gpu->mmu_context->cmdbuf_mapping)
db82a043	326	+ buffer->user_size - 4);
357713ce CG	327
	328	/*
	329	* Kick off the 'sync point' command by replacing the previous
	330	* WAIT with a link to the address in the ring buffer.
	331	*/
	332	etnaviv_buffer_replace_wait(buffer, waitlink_offset,
	333	VIV_FE_LINK_HEADER_OP_LINK \|
	334	VIV_FE_LINK_HEADER_PREFETCH(dwords),
	335	target);
	336	}
	337
41db12df	338	/* Append a command buffer to the ring buffer. */
797b0159	339	void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32 exec_state,
17e4660a LS	340	struct etnaviv_iommu_context *mmu_context, unsigned int event,
17e4660a LS	341	struct etnaviv_cmdbuf *cmdbuf)
a8c21a54	342	{
2f9225db	343	struct etnaviv_cmdbuf *buffer = &gpu->buffer;
6e138f76	344	unsigned int waitlink_offset = buffer->user_size - 16;
41db12df	345	u32 return_target, return_dwords;
33b1be99	346	u32 link_target, link_dwords;
797b0159	347	bool switch_context = gpu->exec_state != exec_state;
17e4660a	348	bool switch_mmu_context = gpu->mmu_context != mmu_context;
27b67278	349	unsigned int new_flush_seq = READ_ONCE(gpu->mmu_context->flush_seq);
17e4660a	350	bool need_flush = switch_mmu_context \|\| gpu->flush_seq != new_flush_seq;
f232d9ec LS	351	bool has_blt = !!(gpu->identity.minor_features5 &
f232d9ec LS	352	chipMinorFeatures5_BLT_ENGINE);
a8c21a54	353
b6d6223f LS	354	lockdep_assert_held(&gpu->lock);
b6d6223f LS	355
6511a945	356	if (drm_debug_enabled(DRM_UT_DRIVER))
a8c21a54 T	357	etnaviv_buffer_dump(gpu, buffer, 0, 0x50);
a8c21a54 T	358
17e4660a LS	359	link_target = etnaviv_cmdbuf_get_va(cmdbuf,
17e4660a LS	360	&gpu->mmu_context->cmdbuf_mapping);
41db12df RK	361	link_dwords = cmdbuf->size / 8;
41db12df RK	362
a8c21a54	363	/*
17e4660a	364	* If we need maintenance prior to submitting this buffer, we will
41db12df	365	* need to append a mmu flush load state, followed by a new
a8c21a54 T	366	* link to this buffer - a total of four additional words.
a8c21a54 T	367	*/
4900dda9	368	if (need_flush \|\| switch_context) {
41db12df RK	369	u32 target, extra_dwords;
41db12df RK	370
a8c21a54	371	/* link command */
41db12df RK	372	extra_dwords = 1;
41db12df RK	373
a8c21a54	374	/* flush command */
4900dda9	375	if (need_flush) {
27b67278	376	if (gpu->mmu_context->global->version == ETNAVIV_IOMMU_V1)
2e145a22 LS	377	extra_dwords += 1;
	378	else
	379	extra_dwords += 3;
	380	}
41db12df	381
a8c21a54	382	/* pipe switch commands */
4375ffff	383	if (switch_context)
41db12df	384	extra_dwords += 4;
a8c21a54	385
17e4660a LS	386	/* PTA load command */
	387	if (switch_mmu_context && gpu->sec_mode == ETNA_SEC_KERNEL)
	388	extra_dwords += 1;
	389
41db12df	390	target = etnaviv_buffer_reserve(gpu, buffer, extra_dwords);
17e4660a LS	391	/*
	392	* Switch MMU context if necessary. Must be done after the
	393	* link target has been calculated, as the jump forward in the
	394	* kernel ring still uses the last active MMU context before
	395	* the switch.
	396	*/
	397	if (switch_mmu_context) {
	398	struct etnaviv_iommu_context *old_context = gpu->mmu_context;
	399
78edefc0	400	gpu->mmu_context = etnaviv_iommu_context_get(mmu_context);
17e4660a LS	401	etnaviv_iommu_context_put(old_context);
17e4660a LS	402	}
a8c21a54	403
4900dda9	404	if (need_flush) {
a8c21a54	405	/* Add the MMU flush */
27b67278	406	if (gpu->mmu_context->global->version == ETNAVIV_IOMMU_V1) {
2e145a22 LS	407	CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_MMU,
	408	VIVS_GL_FLUSH_MMU_FLUSH_FEMMU \|
	409	VIVS_GL_FLUSH_MMU_FLUSH_UNK1 \|
	410	VIVS_GL_FLUSH_MMU_FLUSH_UNK2 \|
	411	VIVS_GL_FLUSH_MMU_FLUSH_PEMMU \|
	412	VIVS_GL_FLUSH_MMU_FLUSH_UNK4);
	413	} else {
17e4660a LS	414	u32 flush = VIVS_MMUv2_CONFIGURATION_MODE_MASK \|
	415	VIVS_MMUv2_CONFIGURATION_FLUSH_FLUSH;
	416
	417	if (switch_mmu_context &&
	418	gpu->sec_mode == ETNA_SEC_KERNEL) {
	419	unsigned short id =
	420	etnaviv_iommuv2_get_pta_id(gpu->mmu_context);
	421	CMD_LOAD_STATE(buffer,
	422	VIVS_MMUv2_PTA_CONFIG,
	423	VIVS_MMUv2_PTA_CONFIG_INDEX(id));
	424	}
	425
	426	if (gpu->sec_mode == ETNA_SEC_NONE)
	427	flush \|= etnaviv_iommuv2_get_mtlb_addr(gpu->mmu_context);
	428
2e145a22	429	CMD_LOAD_STATE(buffer, VIVS_MMUv2_CONFIGURATION,
17e4660a	430	flush);
2e145a22 LS	431	CMD_SEM(buffer, SYNC_RECIPIENT_FE,
	432	SYNC_RECIPIENT_PE);
	433	CMD_STALL(buffer, SYNC_RECIPIENT_FE,
	434	SYNC_RECIPIENT_PE);
	435	}
a8c21a54	436
4900dda9	437	gpu->flush_seq = new_flush_seq;
a8c21a54 T	438	}
a8c21a54 T	439
4375ffff	440	if (switch_context) {
797b0159 LS	441	etnaviv_cmd_select_pipe(gpu, buffer, exec_state);
797b0159 LS	442	gpu->exec_state = exec_state;
a8c21a54 T	443	}
a8c21a54 T	444
33b1be99	445	/* And the link to the submitted buffer */
17e4660a LS	446	link_target = etnaviv_cmdbuf_get_va(cmdbuf,
17e4660a LS	447	&gpu->mmu_context->cmdbuf_mapping);
33b1be99	448	CMD_LINK(buffer, link_dwords, link_target);
a8c21a54 T	449
a8c21a54 T	450	/* Update the link target to point to above instructions */
41db12df RK	451	link_target = target;
41db12df RK	452	link_dwords = extra_dwords;
a8c21a54 T	453	}
a8c21a54 T	454
41db12df RK	455	/*
	456	* Append a LINK to the submitted command buffer to return to
	457	* the ring buffer. return_target is the ring target address.
8c136b59 LS	458	* We need at most 7 dwords in the return target: 2 cache flush +
8c136b59 LS	459	* 2 semaphore stall + 1 event + 1 wait + 1 link.
41db12df	460	*/
8c136b59	461	return_dwords = 7;
f232d9ec LS	462
	463	/*
	464	* When the BLT engine is present we need 6 more dwords in the return
	465	* target: 3 enable/flush/disable + 4 enable/semaphore stall/disable,
	466	* but we don't need the normal TS flush state.
	467	*/
	468	if (has_blt)
	469	return_dwords += 6;
	470
41db12df RK	471	return_target = etnaviv_buffer_reserve(gpu, buffer, return_dwords);
	472	CMD_LINK(cmdbuf, return_dwords, return_target);
	473
	474	/*
8c136b59 LS	475	* Append a cache flush, stall, event, wait and link pointing back to
8c136b59 LS	476	* the wait command to the ring buffer.
41db12df	477	*/
8c136b59 LS	478	if (gpu->exec_state == ETNA_PIPE_2D) {
	479	CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_CACHE,
	480	VIVS_GL_FLUSH_CACHE_PE2D);
	481	} else {
	482	CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_CACHE,
	483	VIVS_GL_FLUSH_CACHE_DEPTH \|
	484	VIVS_GL_FLUSH_CACHE_COLOR);
f232d9ec LS	485	if (has_blt) {
	486	CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x1);
	487	CMD_LOAD_STATE(buffer, VIVS_BLT_SET_COMMAND, 0x1);
	488	CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x0);
	489	} else {
	490	CMD_LOAD_STATE(buffer, VIVS_TS_FLUSH_CACHE,
	491	VIVS_TS_FLUSH_CACHE_FLUSH);
	492	}
8c136b59 LS	493	}
	494	CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
	495	CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
f232d9ec LS	496
	497	if (has_blt) {
	498	CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x1);
	499	CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_BLT);
	500	CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_BLT);
	501	CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x0);
	502	}
	503
a8c21a54 T	504	CMD_LOAD_STATE(buffer, VIVS_GL_EVENT, VIVS_GL_EVENT_EVENT_ID(event) \|
a8c21a54 T	505	VIVS_GL_EVENT_FROM_PE);
a8c21a54	506	CMD_WAIT(buffer);
17e4660a LS	507	CMD_LINK(buffer, 2,
17e4660a LS	508	etnaviv_cmdbuf_get_va(buffer, &gpu->mmu_context->cmdbuf_mapping)
db82a043	509	+ buffer->user_size - 4);
41db12df	510
6511a945	511	if (drm_debug_enabled(DRM_UT_DRIVER))
41db12df	512	pr_info("stream link to 0x%08x @ 0x%08x %p\n",
db82a043	513	return_target,
17e4660a	514	etnaviv_cmdbuf_get_va(cmdbuf, &gpu->mmu_context->cmdbuf_mapping),
c3ef4b8c	515	cmdbuf->vaddr);
41db12df	516
6511a945	517	if (drm_debug_enabled(DRM_UT_DRIVER)) {
41db12df RK	518	print_hex_dump(KERN_INFO, "cmd ", DUMP_PREFIX_OFFSET, 16, 4,
	519	cmdbuf->vaddr, cmdbuf->size, 0);
	520
	521	pr_info("link op: %p\n", buffer->vaddr + waitlink_offset);
	522	pr_info("addr: 0x%08x\n", link_target);
	523	pr_info("back: 0x%08x\n", return_target);
	524	pr_info("event: %d\n", event);
	525	}
a8c21a54	526
41db12df RK	527	/*
	528	* Kick off the submitted command by replacing the previous
	529	* WAIT with a link to the address in the ring buffer.
	530	*/
6e138f76 RK	531	etnaviv_buffer_replace_wait(buffer, waitlink_offset,
6e138f76 RK	532	VIV_FE_LINK_HEADER_OP_LINK \|
33b1be99	533	VIV_FE_LINK_HEADER_PREFETCH(link_dwords),
6e138f76	534	link_target);
a8c21a54	535
6511a945	536	if (drm_debug_enabled(DRM_UT_DRIVER))
a8c21a54 T	537	etnaviv_buffer_dump(gpu, buffer, 0, 0x50);
a8c21a54 T	538	}