[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / etnaviv / etnaviv_buffer.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2014-2018 Etnaviv Project
 */

#include <drm/drm_drv.h>

#include "etnaviv_cmdbuf.h"
#include "etnaviv_gpu.h"
#include "etnaviv_gem.h"
#include "etnaviv_mmu.h"

#include "common.xml.h"
#include "state.xml.h"
#include "state_hi.xml.h"
#include "state_3d.xml.h"
#include "cmdstream.xml.h"

/*
 * Command Buffer helper:
 */


static inline void OUT(struct etnaviv_cmdbuf *buffer, u32 data)
{
	u32 *vaddr = (u32 *)buffer->vaddr;

	BUG_ON(buffer->user_size >= buffer->size);

	vaddr[buffer->user_size / 4] = data;
	buffer->user_size += 4;
}

static inline void CMD_LOAD_STATE(struct etnaviv_cmdbuf *buffer,
	u32 reg, u32 value)
{
	u32 index = reg >> VIV_FE_LOAD_STATE_HEADER_OFFSET__SHR;

	buffer->user_size = ALIGN(buffer->user_size, 8);

	/* write a register via cmd stream */
	OUT(buffer, VIV_FE_LOAD_STATE_HEADER_OP_LOAD_STATE |
		    VIV_FE_LOAD_STATE_HEADER_COUNT(1) |
		    VIV_FE_LOAD_STATE_HEADER_OFFSET(index));
	OUT(buffer, value);
}

static inline void CMD_END(struct etnaviv_cmdbuf *buffer)
{
	buffer->user_size = ALIGN(buffer->user_size, 8);

	OUT(buffer, VIV_FE_END_HEADER_OP_END);
}

static inline void CMD_WAIT(struct etnaviv_cmdbuf *buffer)
{
	buffer->user_size = ALIGN(buffer->user_size, 8);

	OUT(buffer, VIV_FE_WAIT_HEADER_OP_WAIT | 200);
}

static inline void CMD_LINK(struct etnaviv_cmdbuf *buffer,
	u16 prefetch, u32 address)
{
	buffer->user_size = ALIGN(buffer->user_size, 8);

	OUT(buffer, VIV_FE_LINK_HEADER_OP_LINK |
		    VIV_FE_LINK_HEADER_PREFETCH(prefetch));
	OUT(buffer, address);
}

static inline void CMD_STALL(struct etnaviv_cmdbuf *buffer,
	u32 from, u32 to)
{
	buffer->user_size = ALIGN(buffer->user_size, 8);

	OUT(buffer, VIV_FE_STALL_HEADER_OP_STALL);
	OUT(buffer, VIV_FE_STALL_TOKEN_FROM(from) | VIV_FE_STALL_TOKEN_TO(to));
}

static inline void CMD_SEM(struct etnaviv_cmdbuf *buffer, u32 from, u32 to)
{
	CMD_LOAD_STATE(buffer, VIVS_GL_SEMAPHORE_TOKEN,
		       VIVS_GL_SEMAPHORE_TOKEN_FROM(from) |
		       VIVS_GL_SEMAPHORE_TOKEN_TO(to));
}

static void etnaviv_cmd_select_pipe(struct etnaviv_gpu *gpu,
	struct etnaviv_cmdbuf *buffer, u8 pipe)
{
	u32 flush = 0;

	lockdep_assert_held(&gpu->lock);

	/*
	 * This assumes that if we're switching to 2D, we're switching
	 * away from 3D, and vice versa.  Hence, if we're switching to
	 * the 2D core, we need to flush the 3D depth and color caches,
	 * otherwise we need to flush the 2D pixel engine cache.
	 */
	if (gpu->exec_state == ETNA_PIPE_2D)
		flush = VIVS_GL_FLUSH_CACHE_PE2D;
	else if (gpu->exec_state == ETNA_PIPE_3D)
		flush = VIVS_GL_FLUSH_CACHE_DEPTH | VIVS_GL_FLUSH_CACHE_COLOR;

	CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_CACHE, flush);
	CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
	CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);

	CMD_LOAD_STATE(buffer, VIVS_GL_PIPE_SELECT,
		       VIVS_GL_PIPE_SELECT_PIPE(pipe));
}

static void etnaviv_buffer_dump(struct etnaviv_gpu *gpu,
	struct etnaviv_cmdbuf *buf, u32 off, u32 len)
{
	u32 size = buf->size;
	u32 *ptr = buf->vaddr + off;

	dev_info(gpu->dev, "virt %p phys 0x%08x free 0x%08x\n",
			ptr, etnaviv_cmdbuf_get_va(buf, &gpu->cmdbuf_mapping) +
			off, size - len * 4 - off);

	print_hex_dump(KERN_INFO, "cmd ", DUMP_PREFIX_OFFSET, 16, 4,
			ptr, len * 4, 0);
}

/*
 * Safely replace the WAIT of a waitlink with a new command and argument.
 * The GPU may be executing this WAIT while we're modifying it, so we have
 * to write it in a specific order to avoid the GPU branching to somewhere
 * else.  'wl_offset' is the offset to the first byte of the WAIT command.
 */
static void etnaviv_buffer_replace_wait(struct etnaviv_cmdbuf *buffer,
	unsigned int wl_offset, u32 cmd, u32 arg)
{
	u32 *lw = buffer->vaddr + wl_offset;

	lw[1] = arg;
	mb();
	lw[0] = cmd;
	mb();
}

/*
 * Ensure that there is space in the command buffer to contiguously write
 * 'cmd_dwords' 64-bit words into the buffer, wrapping if necessary.
 */
static u32 etnaviv_buffer_reserve(struct etnaviv_gpu *gpu,
	struct etnaviv_cmdbuf *buffer, unsigned int cmd_dwords)
{
	if (buffer->user_size + cmd_dwords * sizeof(u64) > buffer->size)
		buffer->user_size = 0;

	return etnaviv_cmdbuf_get_va(buffer, &gpu->cmdbuf_mapping) +
	       buffer->user_size;
}

u16 etnaviv_buffer_init(struct etnaviv_gpu *gpu)
{
	struct etnaviv_cmdbuf *buffer = &gpu->buffer;

	lockdep_assert_held(&gpu->lock);

	/* initialize buffer */
	buffer->user_size = 0;

	CMD_WAIT(buffer);
	CMD_LINK(buffer, 2, etnaviv_cmdbuf_get_va(buffer, &gpu->cmdbuf_mapping)
		 + buffer->user_size - 4);

	return buffer->user_size / 8;
}

u16 etnaviv_buffer_config_mmuv2(struct etnaviv_gpu *gpu, u32 mtlb_addr, u32 safe_addr)
{
	struct etnaviv_cmdbuf *buffer = &gpu->buffer;

	lockdep_assert_held(&gpu->lock);

	buffer->user_size = 0;

	if (gpu->identity.features & chipFeatures_PIPE_3D) {
		CMD_LOAD_STATE(buffer, VIVS_GL_PIPE_SELECT,
			       VIVS_GL_PIPE_SELECT_PIPE(ETNA_PIPE_3D));
		CMD_LOAD_STATE(buffer, VIVS_MMUv2_CONFIGURATION,
			mtlb_addr | VIVS_MMUv2_CONFIGURATION_MODE_MODE4_K);
		CMD_LOAD_STATE(buffer, VIVS_MMUv2_SAFE_ADDRESS, safe_addr);
		CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
		CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
	}

	if (gpu->identity.features & chipFeatures_PIPE_2D) {
		CMD_LOAD_STATE(buffer, VIVS_GL_PIPE_SELECT,
			       VIVS_GL_PIPE_SELECT_PIPE(ETNA_PIPE_2D));
		CMD_LOAD_STATE(buffer, VIVS_MMUv2_CONFIGURATION,
			mtlb_addr | VIVS_MMUv2_CONFIGURATION_MODE_MODE4_K);
		CMD_LOAD_STATE(buffer, VIVS_MMUv2_SAFE_ADDRESS, safe_addr);
		CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
		CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
	}

	CMD_END(buffer);

	buffer->user_size = ALIGN(buffer->user_size, 8);

	return buffer->user_size / 8;
}

u16 etnaviv_buffer_config_pta(struct etnaviv_gpu *gpu)
{
	struct etnaviv_cmdbuf *buffer = &gpu->buffer;

	lockdep_assert_held(&gpu->lock);

	buffer->user_size = 0;

	CMD_LOAD_STATE(buffer, VIVS_MMUv2_PTA_CONFIG,
		       VIVS_MMUv2_PTA_CONFIG_INDEX(0));

	CMD_END(buffer);

	buffer->user_size = ALIGN(buffer->user_size, 8);

	return buffer->user_size / 8;
}

void etnaviv_buffer_end(struct etnaviv_gpu *gpu)
{
	struct etnaviv_cmdbuf *buffer = &gpu->buffer;
	unsigned int waitlink_offset = buffer->user_size - 16;
	u32 link_target, flush = 0;

	lockdep_assert_held(&gpu->lock);

	if (gpu->exec_state == ETNA_PIPE_2D)
		flush = VIVS_GL_FLUSH_CACHE_PE2D;
	else if (gpu->exec_state == ETNA_PIPE_3D)
		flush = VIVS_GL_FLUSH_CACHE_DEPTH |
			VIVS_GL_FLUSH_CACHE_COLOR |
			VIVS_GL_FLUSH_CACHE_TEXTURE |
			VIVS_GL_FLUSH_CACHE_TEXTUREVS |
			VIVS_GL_FLUSH_CACHE_SHADER_L2;

	if (flush) {
		unsigned int dwords = 7;

		link_target = etnaviv_buffer_reserve(gpu, buffer, dwords);

		CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
		CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
		CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_CACHE, flush);
		if (gpu->exec_state == ETNA_PIPE_3D)
			CMD_LOAD_STATE(buffer, VIVS_TS_FLUSH_CACHE,
				       VIVS_TS_FLUSH_CACHE_FLUSH);
		CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
		CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
		CMD_END(buffer);

		etnaviv_buffer_replace_wait(buffer, waitlink_offset,
					    VIV_FE_LINK_HEADER_OP_LINK |
					    VIV_FE_LINK_HEADER_PREFETCH(dwords),
					    link_target);
	} else {
		/* Replace the last link-wait with an "END" command */
		etnaviv_buffer_replace_wait(buffer, waitlink_offset,
					    VIV_FE_END_HEADER_OP_END, 0);
	}
}

/* Append a 'sync point' to the ring buffer. */
void etnaviv_sync_point_queue(struct etnaviv_gpu *gpu, unsigned int event)
{
	struct etnaviv_cmdbuf *buffer = &gpu->buffer;
	unsigned int waitlink_offset = buffer->user_size - 16;
	u32 dwords, target;

	lockdep_assert_held(&gpu->lock);

	/*
	 * We need at most 3 dwords in the return target:
	 * 1 event + 1 end + 1 wait + 1 link.
	 */
	dwords = 4;
	target = etnaviv_buffer_reserve(gpu, buffer, dwords);

	/* Signal sync point event */
	CMD_LOAD_STATE(buffer, VIVS_GL_EVENT, VIVS_GL_EVENT_EVENT_ID(event) |
		       VIVS_GL_EVENT_FROM_PE);

	/* Stop the FE to 'pause' the GPU */
	CMD_END(buffer);

	/* Append waitlink */
	CMD_WAIT(buffer);
	CMD_LINK(buffer, 2, etnaviv_cmdbuf_get_va(buffer, &gpu->cmdbuf_mapping)
		 + buffer->user_size - 4);

	/*
	 * Kick off the 'sync point' command by replacing the previous
	 * WAIT with a link to the address in the ring buffer.
	 */
	etnaviv_buffer_replace_wait(buffer, waitlink_offset,
				    VIV_FE_LINK_HEADER_OP_LINK |
				    VIV_FE_LINK_HEADER_PREFETCH(dwords),
				    target);
}

/* Append a command buffer to the ring buffer. */
void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32 exec_state,
	unsigned int event, struct etnaviv_cmdbuf *cmdbuf)
{
	struct etnaviv_cmdbuf *buffer = &gpu->buffer;
	unsigned int waitlink_offset = buffer->user_size - 16;
	u32 return_target, return_dwords;
	u32 link_target, link_dwords;
	bool switch_context = gpu->exec_state != exec_state;

	lockdep_assert_held(&gpu->lock);

	if (drm_debug & DRM_UT_DRIVER)
		etnaviv_buffer_dump(gpu, buffer, 0, 0x50);

	link_target = etnaviv_cmdbuf_get_va(cmdbuf, &gpu->cmdbuf_mapping);
	link_dwords = cmdbuf->size / 8;

	/*
	 * If we need maintanence prior to submitting this buffer, we will
	 * need to append a mmu flush load state, followed by a new
	 * link to this buffer - a total of four additional words.
	 */
	if (gpu->mmu->need_flush || switch_context) {
		u32 target, extra_dwords;

		/* link command */
		extra_dwords = 1;

		/* flush command */
		if (gpu->mmu->need_flush) {
			if (gpu->mmu->version == ETNAVIV_IOMMU_V1)
				extra_dwords += 1;
			else
				extra_dwords += 3;
		}

		/* pipe switch commands */
		if (switch_context)
			extra_dwords += 4;

		target = etnaviv_buffer_reserve(gpu, buffer, extra_dwords);

		if (gpu->mmu->need_flush) {
			/* Add the MMU flush */
			if (gpu->mmu->version == ETNAVIV_IOMMU_V1) {
				CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_MMU,
					       VIVS_GL_FLUSH_MMU_FLUSH_FEMMU |
					       VIVS_GL_FLUSH_MMU_FLUSH_UNK1 |
					       VIVS_GL_FLUSH_MMU_FLUSH_UNK2 |
					       VIVS_GL_FLUSH_MMU_FLUSH_PEMMU |
					       VIVS_GL_FLUSH_MMU_FLUSH_UNK4);
			} else {
				CMD_LOAD_STATE(buffer, VIVS_MMUv2_CONFIGURATION,
					VIVS_MMUv2_CONFIGURATION_MODE_MASK |
					VIVS_MMUv2_CONFIGURATION_ADDRESS_MASK |
					VIVS_MMUv2_CONFIGURATION_FLUSH_FLUSH);
				CMD_SEM(buffer, SYNC_RECIPIENT_FE,
					SYNC_RECIPIENT_PE);
				CMD_STALL(buffer, SYNC_RECIPIENT_FE,
					SYNC_RECIPIENT_PE);
			}

			gpu->mmu->need_flush = false;
		}

		if (switch_context) {
			etnaviv_cmd_select_pipe(gpu, buffer, exec_state);
			gpu->exec_state = exec_state;
		}

		/* And the link to the submitted buffer */
		CMD_LINK(buffer, link_dwords, link_target);

		/* Update the link target to point to above instructions */
		link_target = target;
		link_dwords = extra_dwords;
	}

	/*
	 * Append a LINK to the submitted command buffer to return to
	 * the ring buffer.  return_target is the ring target address.
	 * We need at most 7 dwords in the return target: 2 cache flush +
	 * 2 semaphore stall + 1 event + 1 wait + 1 link.
	 */
	return_dwords = 7;
	return_target = etnaviv_buffer_reserve(gpu, buffer, return_dwords);
	CMD_LINK(cmdbuf, return_dwords, return_target);

	/*
	 * Append a cache flush, stall, event, wait and link pointing back to
	 * the wait command to the ring buffer.
	 */
	if (gpu->exec_state == ETNA_PIPE_2D) {
		CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_CACHE,
				       VIVS_GL_FLUSH_CACHE_PE2D);
	} else {
		CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_CACHE,
				       VIVS_GL_FLUSH_CACHE_DEPTH |
				       VIVS_GL_FLUSH_CACHE_COLOR);
		CMD_LOAD_STATE(buffer, VIVS_TS_FLUSH_CACHE,
				       VIVS_TS_FLUSH_CACHE_FLUSH);
	}
	CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
	CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
	CMD_LOAD_STATE(buffer, VIVS_GL_EVENT, VIVS_GL_EVENT_EVENT_ID(event) |
		       VIVS_GL_EVENT_FROM_PE);
	CMD_WAIT(buffer);
	CMD_LINK(buffer, 2, etnaviv_cmdbuf_get_va(buffer, &gpu->cmdbuf_mapping)
		 + buffer->user_size - 4);

	if (drm_debug & DRM_UT_DRIVER)
		pr_info("stream link to 0x%08x @ 0x%08x %p\n",
			return_target,
			etnaviv_cmdbuf_get_va(cmdbuf, &gpu->cmdbuf_mapping),
			cmdbuf->vaddr);

	if (drm_debug & DRM_UT_DRIVER) {
		print_hex_dump(KERN_INFO, "cmd ", DUMP_PREFIX_OFFSET, 16, 4,
			       cmdbuf->vaddr, cmdbuf->size, 0);

		pr_info("link op: %p\n", buffer->vaddr + waitlink_offset);
		pr_info("addr: 0x%08x\n", link_target);
		pr_info("back: 0x%08x\n", return_target);
		pr_info("event: %d\n", event);
	}

	/*
	 * Kick off the submitted command by replacing the previous
	 * WAIT with a link to the address in the ring buffer.
	 */
	etnaviv_buffer_replace_wait(buffer, waitlink_offset,
				    VIV_FE_LINK_HEADER_OP_LINK |
				    VIV_FE_LINK_HEADER_PREFETCH(link_dwords),
				    link_target);

	if (drm_debug & DRM_UT_DRIVER)
		etnaviv_buffer_dump(gpu, buffer, 0, 0x50);
}
Commit	Line	Data
f6ffbd4f	1	// SPDX-License-Identifier: GPL-2.0
a8c21a54	2	/*
f6ffbd4f	3	* Copyright (C) 2014-2018 Etnaviv Project
a8c21a54 T	4	*/
a8c21a54 T	5
6eae41fe SR	6	#include <drm/drm_drv.h>
6eae41fe SR	7
ea1f5729	8	#include "etnaviv_cmdbuf.h"
a8c21a54 T	9	#include "etnaviv_gpu.h"
	10	#include "etnaviv_gem.h"
	11	#include "etnaviv_mmu.h"
	12
	13	#include "common.xml.h"
	14	#include "state.xml.h"
de08e8ef	15	#include "state_hi.xml.h"
8581d814	16	#include "state_3d.xml.h"
a8c21a54 T	17	#include "cmdstream.xml.h"
	18
	19	/*
	20	* Command Buffer helper:
	21	*/
	22
	23
	24	static inline void OUT(struct etnaviv_cmdbuf *buffer, u32 data)
	25	{
	26	u32 vaddr = (u32 )buffer->vaddr;
	27
	28	BUG_ON(buffer->user_size >= buffer->size);
	29
	30	vaddr[buffer->user_size / 4] = data;
	31	buffer->user_size += 4;
	32	}
	33
	34	static inline void CMD_LOAD_STATE(struct etnaviv_cmdbuf *buffer,
	35	u32 reg, u32 value)
	36	{
	37	u32 index = reg >> VIV_FE_LOAD_STATE_HEADER_OFFSET__SHR;
	38
	39	buffer->user_size = ALIGN(buffer->user_size, 8);
	40
	41	/* write a register via cmd stream */
	42	OUT(buffer, VIV_FE_LOAD_STATE_HEADER_OP_LOAD_STATE \|
	43	VIV_FE_LOAD_STATE_HEADER_COUNT(1) \|
	44	VIV_FE_LOAD_STATE_HEADER_OFFSET(index));
	45	OUT(buffer, value);
	46	}
	47
	48	static inline void CMD_END(struct etnaviv_cmdbuf *buffer)
	49	{
	50	buffer->user_size = ALIGN(buffer->user_size, 8);
	51
	52	OUT(buffer, VIV_FE_END_HEADER_OP_END);
	53	}
	54
	55	static inline void CMD_WAIT(struct etnaviv_cmdbuf *buffer)
	56	{
	57	buffer->user_size = ALIGN(buffer->user_size, 8);
	58
	59	OUT(buffer, VIV_FE_WAIT_HEADER_OP_WAIT \| 200);
	60	}
	61
	62	static inline void CMD_LINK(struct etnaviv_cmdbuf *buffer,
	63	u16 prefetch, u32 address)
	64	{
	65	buffer->user_size = ALIGN(buffer->user_size, 8);
	66
	67	OUT(buffer, VIV_FE_LINK_HEADER_OP_LINK \|
	68	VIV_FE_LINK_HEADER_PREFETCH(prefetch));
	69	OUT(buffer, address);
	70	}
	71
	72	static inline void CMD_STALL(struct etnaviv_cmdbuf *buffer,
	73	u32 from, u32 to)
	74	{
	75	buffer->user_size = ALIGN(buffer->user_size, 8);
	76
	77	OUT(buffer, VIV_FE_STALL_HEADER_OP_STALL);
	78	OUT(buffer, VIV_FE_STALL_TOKEN_FROM(from) \| VIV_FE_STALL_TOKEN_TO(to));
	79	}
	80
18060f4d RK	81	static inline void CMD_SEM(struct etnaviv_cmdbuf *buffer, u32 from, u32 to)
	82	{
	83	CMD_LOAD_STATE(buffer, VIVS_GL_SEMAPHORE_TOKEN,
	84	VIVS_GL_SEMAPHORE_TOKEN_FROM(from) \|
	85	VIVS_GL_SEMAPHORE_TOKEN_TO(to));
	86	}
	87
90747b95 RK	88	static void etnaviv_cmd_select_pipe(struct etnaviv_gpu *gpu,
90747b95 RK	89	struct etnaviv_cmdbuf *buffer, u8 pipe)
a8c21a54	90	{
90747b95	91	u32 flush = 0;
a8c21a54	92
b6d6223f LS	93	lockdep_assert_held(&gpu->lock);
b6d6223f LS	94
a8c21a54 T	95	/*
	96	* This assumes that if we're switching to 2D, we're switching
	97	* away from 3D, and vice versa. Hence, if we're switching to
	98	* the 2D core, we need to flush the 3D depth and color caches,
	99	* otherwise we need to flush the 2D pixel engine cache.
	100	*/
90747b95	101	if (gpu->exec_state == ETNA_PIPE_2D)
a8c21a54	102	flush = VIVS_GL_FLUSH_CACHE_PE2D;
90747b95 RK	103	else if (gpu->exec_state == ETNA_PIPE_3D)
90747b95 RK	104	flush = VIVS_GL_FLUSH_CACHE_DEPTH \| VIVS_GL_FLUSH_CACHE_COLOR;
a8c21a54	105
a8c21a54	106	CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_CACHE, flush);
18060f4d	107	CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
a8c21a54 T	108	CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
	109
	110	CMD_LOAD_STATE(buffer, VIVS_GL_PIPE_SELECT,
	111	VIVS_GL_PIPE_SELECT_PIPE(pipe));
	112	}
	113
a8c21a54 T	114	static void etnaviv_buffer_dump(struct etnaviv_gpu *gpu,
	115	struct etnaviv_cmdbuf *buf, u32 off, u32 len)
	116	{
	117	u32 size = buf->size;
	118	u32 *ptr = buf->vaddr + off;
	119
	120	dev_info(gpu->dev, "virt %p phys 0x%08x free 0x%08x\n",
db82a043 LS	121	ptr, etnaviv_cmdbuf_get_va(buf, &gpu->cmdbuf_mapping) +
db82a043 LS	122	off, size - len * 4 - off);
a8c21a54 T	123
	124	print_hex_dump(KERN_INFO, "cmd ", DUMP_PREFIX_OFFSET, 16, 4,
	125	ptr, len * 4, 0);
	126	}
	127
6e138f76 RK	128	/*
	129	* Safely replace the WAIT of a waitlink with a new command and argument.
	130	* The GPU may be executing this WAIT while we're modifying it, so we have
	131	* to write it in a specific order to avoid the GPU branching to somewhere
	132	* else. 'wl_offset' is the offset to the first byte of the WAIT command.
	133	*/
	134	static void etnaviv_buffer_replace_wait(struct etnaviv_cmdbuf *buffer,
	135	unsigned int wl_offset, u32 cmd, u32 arg)
	136	{
	137	u32 *lw = buffer->vaddr + wl_offset;
	138
	139	lw[1] = arg;
	140	mb();
	141	lw[0] = cmd;
	142	mb();
	143	}
	144
584a13c6 RK	145	/*
	146	* Ensure that there is space in the command buffer to contiguously write
	147	* 'cmd_dwords' 64-bit words into the buffer, wrapping if necessary.
	148	*/
	149	static u32 etnaviv_buffer_reserve(struct etnaviv_gpu *gpu,
	150	struct etnaviv_cmdbuf *buffer, unsigned int cmd_dwords)
	151	{
	152	if (buffer->user_size + cmd_dwords * sizeof(u64) > buffer->size)
	153	buffer->user_size = 0;
	154
db82a043 LS	155	return etnaviv_cmdbuf_get_va(buffer, &gpu->cmdbuf_mapping) +
db82a043 LS	156	buffer->user_size;
584a13c6 RK	157	}
584a13c6 RK	158
a8c21a54 T	159	u16 etnaviv_buffer_init(struct etnaviv_gpu *gpu)
a8c21a54 T	160	{
2f9225db	161	struct etnaviv_cmdbuf *buffer = &gpu->buffer;
a8c21a54	162
b6d6223f LS	163	lockdep_assert_held(&gpu->lock);
b6d6223f LS	164
a8c21a54 T	165	/* initialize buffer */
	166	buffer->user_size = 0;
	167
	168	CMD_WAIT(buffer);
db82a043 LS	169	CMD_LINK(buffer, 2, etnaviv_cmdbuf_get_va(buffer, &gpu->cmdbuf_mapping)
db82a043 LS	170	+ buffer->user_size - 4);
a8c21a54 T	171
	172	return buffer->user_size / 8;
	173	}
	174
de08e8ef LS	175	u16 etnaviv_buffer_config_mmuv2(struct etnaviv_gpu *gpu, u32 mtlb_addr, u32 safe_addr)
de08e8ef LS	176	{
2f9225db	177	struct etnaviv_cmdbuf *buffer = &gpu->buffer;
de08e8ef	178
b6d6223f LS	179	lockdep_assert_held(&gpu->lock);
b6d6223f LS	180
de08e8ef LS	181	buffer->user_size = 0;
	182
	183	if (gpu->identity.features & chipFeatures_PIPE_3D) {
	184	CMD_LOAD_STATE(buffer, VIVS_GL_PIPE_SELECT,
	185	VIVS_GL_PIPE_SELECT_PIPE(ETNA_PIPE_3D));
	186	CMD_LOAD_STATE(buffer, VIVS_MMUv2_CONFIGURATION,
	187	mtlb_addr \| VIVS_MMUv2_CONFIGURATION_MODE_MODE4_K);
	188	CMD_LOAD_STATE(buffer, VIVS_MMUv2_SAFE_ADDRESS, safe_addr);
	189	CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
	190	CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
	191	}
	192
	193	if (gpu->identity.features & chipFeatures_PIPE_2D) {
	194	CMD_LOAD_STATE(buffer, VIVS_GL_PIPE_SELECT,
	195	VIVS_GL_PIPE_SELECT_PIPE(ETNA_PIPE_2D));
	196	CMD_LOAD_STATE(buffer, VIVS_MMUv2_CONFIGURATION,
	197	mtlb_addr \| VIVS_MMUv2_CONFIGURATION_MODE_MODE4_K);
	198	CMD_LOAD_STATE(buffer, VIVS_MMUv2_SAFE_ADDRESS, safe_addr);
	199	CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
	200	CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
	201	}
	202
	203	CMD_END(buffer);
	204
	205	buffer->user_size = ALIGN(buffer->user_size, 8);
	206
	207	return buffer->user_size / 8;
	208	}
	209
1137bef6 LS	210	u16 etnaviv_buffer_config_pta(struct etnaviv_gpu *gpu)
	211	{
	212	struct etnaviv_cmdbuf *buffer = &gpu->buffer;
	213
	214	lockdep_assert_held(&gpu->lock);
	215
	216	buffer->user_size = 0;
	217
	218	CMD_LOAD_STATE(buffer, VIVS_MMUv2_PTA_CONFIG,
	219	VIVS_MMUv2_PTA_CONFIG_INDEX(0));
	220
	221	CMD_END(buffer);
	222
	223	buffer->user_size = ALIGN(buffer->user_size, 8);
	224
	225	return buffer->user_size / 8;
	226	}
	227
a8c21a54 T	228	void etnaviv_buffer_end(struct etnaviv_gpu *gpu)
a8c21a54 T	229	{
2f9225db	230	struct etnaviv_cmdbuf *buffer = &gpu->buffer;
8581d814 RK	231	unsigned int waitlink_offset = buffer->user_size - 16;
8581d814 RK	232	u32 link_target, flush = 0;
a8c21a54	233
b6d6223f LS	234	lockdep_assert_held(&gpu->lock);
b6d6223f LS	235
8581d814 RK	236	if (gpu->exec_state == ETNA_PIPE_2D)
	237	flush = VIVS_GL_FLUSH_CACHE_PE2D;
	238	else if (gpu->exec_state == ETNA_PIPE_3D)
	239	flush = VIVS_GL_FLUSH_CACHE_DEPTH \|
	240	VIVS_GL_FLUSH_CACHE_COLOR \|
	241	VIVS_GL_FLUSH_CACHE_TEXTURE \|
	242	VIVS_GL_FLUSH_CACHE_TEXTUREVS \|
	243	VIVS_GL_FLUSH_CACHE_SHADER_L2;
	244
	245	if (flush) {
	246	unsigned int dwords = 7;
	247
	248	link_target = etnaviv_buffer_reserve(gpu, buffer, dwords);
	249
	250	CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
	251	CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
	252	CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_CACHE, flush);
	253	if (gpu->exec_state == ETNA_PIPE_3D)
	254	CMD_LOAD_STATE(buffer, VIVS_TS_FLUSH_CACHE,
	255	VIVS_TS_FLUSH_CACHE_FLUSH);
	256	CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
	257	CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
	258	CMD_END(buffer);
	259
	260	etnaviv_buffer_replace_wait(buffer, waitlink_offset,
	261	VIV_FE_LINK_HEADER_OP_LINK \|
	262	VIV_FE_LINK_HEADER_PREFETCH(dwords),
	263	link_target);
	264	} else {
	265	/* Replace the last link-wait with an "END" command */
	266	etnaviv_buffer_replace_wait(buffer, waitlink_offset,
	267	VIV_FE_END_HEADER_OP_END, 0);
	268	}
a8c21a54 T	269	}
a8c21a54 T	270
357713ce CG	271	/* Append a 'sync point' to the ring buffer. */
	272	void etnaviv_sync_point_queue(struct etnaviv_gpu *gpu, unsigned int event)
	273	{
2f9225db	274	struct etnaviv_cmdbuf *buffer = &gpu->buffer;
357713ce CG	275	unsigned int waitlink_offset = buffer->user_size - 16;
	276	u32 dwords, target;
	277
b6d6223f LS	278	lockdep_assert_held(&gpu->lock);
b6d6223f LS	279
357713ce CG	280	/*
	281	* We need at most 3 dwords in the return target:
	282	* 1 event + 1 end + 1 wait + 1 link.
	283	*/
	284	dwords = 4;
	285	target = etnaviv_buffer_reserve(gpu, buffer, dwords);
	286
	287	/* Signal sync point event */
	288	CMD_LOAD_STATE(buffer, VIVS_GL_EVENT, VIVS_GL_EVENT_EVENT_ID(event) \|
	289	VIVS_GL_EVENT_FROM_PE);
	290
	291	/* Stop the FE to 'pause' the GPU */
	292	CMD_END(buffer);
	293
	294	/* Append waitlink */
	295	CMD_WAIT(buffer);
db82a043 LS	296	CMD_LINK(buffer, 2, etnaviv_cmdbuf_get_va(buffer, &gpu->cmdbuf_mapping)
db82a043 LS	297	+ buffer->user_size - 4);
357713ce CG	298
	299	/*
	300	* Kick off the 'sync point' command by replacing the previous
	301	* WAIT with a link to the address in the ring buffer.
	302	*/
	303	etnaviv_buffer_replace_wait(buffer, waitlink_offset,
	304	VIV_FE_LINK_HEADER_OP_LINK \|
	305	VIV_FE_LINK_HEADER_PREFETCH(dwords),
	306	target);
	307	}
	308
41db12df	309	/* Append a command buffer to the ring buffer. */
797b0159 LS	310	void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32 exec_state,
797b0159 LS	311	unsigned int event, struct etnaviv_cmdbuf *cmdbuf)
a8c21a54	312	{
2f9225db	313	struct etnaviv_cmdbuf *buffer = &gpu->buffer;
6e138f76	314	unsigned int waitlink_offset = buffer->user_size - 16;
41db12df	315	u32 return_target, return_dwords;
33b1be99	316	u32 link_target, link_dwords;
797b0159	317	bool switch_context = gpu->exec_state != exec_state;
a8c21a54	318
b6d6223f LS	319	lockdep_assert_held(&gpu->lock);
b6d6223f LS	320
a8c21a54 T	321	if (drm_debug & DRM_UT_DRIVER)
	322	etnaviv_buffer_dump(gpu, buffer, 0, 0x50);
	323
db82a043	324	link_target = etnaviv_cmdbuf_get_va(cmdbuf, &gpu->cmdbuf_mapping);
41db12df RK	325	link_dwords = cmdbuf->size / 8;
41db12df RK	326
a8c21a54	327	/*
41db12df RK	328	* If we need maintanence prior to submitting this buffer, we will
41db12df RK	329	* need to append a mmu flush load state, followed by a new
a8c21a54 T	330	* link to this buffer - a total of four additional words.
a8c21a54 T	331	*/
4375ffff	332	if (gpu->mmu->need_flush \|\| switch_context) {
41db12df RK	333	u32 target, extra_dwords;
41db12df RK	334
a8c21a54	335	/* link command */
41db12df RK	336	extra_dwords = 1;
41db12df RK	337
a8c21a54	338	/* flush command */
2e145a22 LS	339	if (gpu->mmu->need_flush) {
	340	if (gpu->mmu->version == ETNAVIV_IOMMU_V1)
	341	extra_dwords += 1;
	342	else
	343	extra_dwords += 3;
	344	}
41db12df	345
a8c21a54	346	/* pipe switch commands */
4375ffff	347	if (switch_context)
41db12df	348	extra_dwords += 4;
a8c21a54	349
41db12df	350	target = etnaviv_buffer_reserve(gpu, buffer, extra_dwords);
a8c21a54 T	351
	352	if (gpu->mmu->need_flush) {
	353	/* Add the MMU flush */
2e145a22 LS	354	if (gpu->mmu->version == ETNAVIV_IOMMU_V1) {
	355	CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_MMU,
	356	VIVS_GL_FLUSH_MMU_FLUSH_FEMMU \|
	357	VIVS_GL_FLUSH_MMU_FLUSH_UNK1 \|
	358	VIVS_GL_FLUSH_MMU_FLUSH_UNK2 \|
	359	VIVS_GL_FLUSH_MMU_FLUSH_PEMMU \|
	360	VIVS_GL_FLUSH_MMU_FLUSH_UNK4);
	361	} else {
	362	CMD_LOAD_STATE(buffer, VIVS_MMUv2_CONFIGURATION,
	363	VIVS_MMUv2_CONFIGURATION_MODE_MASK \|
	364	VIVS_MMUv2_CONFIGURATION_ADDRESS_MASK \|
	365	VIVS_MMUv2_CONFIGURATION_FLUSH_FLUSH);
	366	CMD_SEM(buffer, SYNC_RECIPIENT_FE,
	367	SYNC_RECIPIENT_PE);
	368	CMD_STALL(buffer, SYNC_RECIPIENT_FE,
	369	SYNC_RECIPIENT_PE);
	370	}
a8c21a54 T	371
	372	gpu->mmu->need_flush = false;
	373	}
	374
4375ffff	375	if (switch_context) {
797b0159 LS	376	etnaviv_cmd_select_pipe(gpu, buffer, exec_state);
797b0159 LS	377	gpu->exec_state = exec_state;
a8c21a54 T	378	}
a8c21a54 T	379
33b1be99 RK	380	/* And the link to the submitted buffer */
33b1be99 RK	381	CMD_LINK(buffer, link_dwords, link_target);
a8c21a54 T	382
a8c21a54 T	383	/* Update the link target to point to above instructions */
41db12df RK	384	link_target = target;
41db12df RK	385	link_dwords = extra_dwords;
a8c21a54 T	386	}
a8c21a54 T	387
41db12df RK	388	/*
	389	* Append a LINK to the submitted command buffer to return to
	390	* the ring buffer. return_target is the ring target address.
8c136b59 LS	391	* We need at most 7 dwords in the return target: 2 cache flush +
8c136b59 LS	392	* 2 semaphore stall + 1 event + 1 wait + 1 link.
41db12df	393	*/
8c136b59	394	return_dwords = 7;
41db12df RK	395	return_target = etnaviv_buffer_reserve(gpu, buffer, return_dwords);
	396	CMD_LINK(cmdbuf, return_dwords, return_target);
	397
	398	/*
8c136b59 LS	399	* Append a cache flush, stall, event, wait and link pointing back to
8c136b59 LS	400	* the wait command to the ring buffer.
41db12df	401	*/
8c136b59 LS	402	if (gpu->exec_state == ETNA_PIPE_2D) {
	403	CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_CACHE,
	404	VIVS_GL_FLUSH_CACHE_PE2D);
	405	} else {
	406	CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_CACHE,
	407	VIVS_GL_FLUSH_CACHE_DEPTH \|
	408	VIVS_GL_FLUSH_CACHE_COLOR);
	409	CMD_LOAD_STATE(buffer, VIVS_TS_FLUSH_CACHE,
	410	VIVS_TS_FLUSH_CACHE_FLUSH);
	411	}
	412	CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
	413	CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
a8c21a54 T	414	CMD_LOAD_STATE(buffer, VIVS_GL_EVENT, VIVS_GL_EVENT_EVENT_ID(event) \|
a8c21a54 T	415	VIVS_GL_EVENT_FROM_PE);
a8c21a54	416	CMD_WAIT(buffer);
db82a043 LS	417	CMD_LINK(buffer, 2, etnaviv_cmdbuf_get_va(buffer, &gpu->cmdbuf_mapping)
db82a043 LS	418	+ buffer->user_size - 4);
41db12df RK	419
	420	if (drm_debug & DRM_UT_DRIVER)
	421	pr_info("stream link to 0x%08x @ 0x%08x %p\n",
db82a043 LS	422	return_target,
db82a043 LS	423	etnaviv_cmdbuf_get_va(cmdbuf, &gpu->cmdbuf_mapping),
c3ef4b8c	424	cmdbuf->vaddr);
41db12df RK	425
	426	if (drm_debug & DRM_UT_DRIVER) {
	427	print_hex_dump(KERN_INFO, "cmd ", DUMP_PREFIX_OFFSET, 16, 4,
	428	cmdbuf->vaddr, cmdbuf->size, 0);
	429
	430	pr_info("link op: %p\n", buffer->vaddr + waitlink_offset);
	431	pr_info("addr: 0x%08x\n", link_target);
	432	pr_info("back: 0x%08x\n", return_target);
	433	pr_info("event: %d\n", event);
	434	}
a8c21a54	435
41db12df RK	436	/*
	437	* Kick off the submitted command by replacing the previous
	438	* WAIT with a link to the address in the ring buffer.
	439	*/
6e138f76 RK	440	etnaviv_buffer_replace_wait(buffer, waitlink_offset,
6e138f76 RK	441	VIV_FE_LINK_HEADER_OP_LINK \|
33b1be99	442	VIV_FE_LINK_HEADER_PREFETCH(link_dwords),
6e138f76	443	link_target);
a8c21a54 T	444
	445	if (drm_debug & DRM_UT_DRIVER)
	446	etnaviv_buffer_dump(gpu, buffer, 0, 0x50);
	447	}