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96976c3d AK |
1 | /* drivers/gpu/drm/exynos/exynos7_drm_decon.c |
2 | * | |
3 | * Copyright (C) 2014 Samsung Electronics Co.Ltd | |
4 | * Authors: | |
5 | * Akshu Agarwal <akshua@gmail.com> | |
6 | * Ajay Kumar <ajaykumar.rs@samsung.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | */ | |
14 | #include <drm/drmP.h> | |
15 | #include <drm/exynos_drm.h> | |
16 | ||
17 | #include <linux/clk.h> | |
18 | #include <linux/component.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/of.h> | |
21 | #include <linux/of_address.h> | |
22 | #include <linux/of_device.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/pm_runtime.h> | |
25 | ||
26 | #include <video/of_display_timing.h> | |
27 | #include <video/of_videomode.h> | |
28 | #include <video/exynos7_decon.h> | |
29 | ||
30 | #include "exynos_drm_crtc.h" | |
7ee14cdc | 31 | #include "exynos_drm_plane.h" |
96976c3d | 32 | #include "exynos_drm_drv.h" |
0488f50e | 33 | #include "exynos_drm_fb.h" |
96976c3d AK |
34 | #include "exynos_drm_fbdev.h" |
35 | #include "exynos_drm_iommu.h" | |
36 | ||
37 | /* | |
38 | * DECON stands for Display and Enhancement controller. | |
39 | */ | |
40 | ||
96976c3d AK |
41 | #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 |
42 | ||
43 | #define WINDOWS_NR 2 | |
44 | ||
96976c3d AK |
45 | struct decon_context { |
46 | struct device *dev; | |
47 | struct drm_device *drm_dev; | |
48 | struct exynos_drm_crtc *crtc; | |
7ee14cdc | 49 | struct exynos_drm_plane planes[WINDOWS_NR]; |
fd2d2fc2 | 50 | struct exynos_drm_plane_config configs[WINDOWS_NR]; |
96976c3d AK |
51 | struct clk *pclk; |
52 | struct clk *aclk; | |
53 | struct clk *eclk; | |
54 | struct clk *vclk; | |
55 | void __iomem *regs; | |
96976c3d AK |
56 | unsigned long irq_flags; |
57 | bool i80_if; | |
58 | bool suspended; | |
59 | int pipe; | |
60 | wait_queue_head_t wait_vsync_queue; | |
61 | atomic_t wait_vsync_event; | |
62 | ||
2b8376c8 | 63 | struct drm_encoder *encoder; |
96976c3d AK |
64 | }; |
65 | ||
66 | static const struct of_device_id decon_driver_dt_match[] = { | |
67 | {.compatible = "samsung,exynos7-decon"}, | |
68 | {}, | |
69 | }; | |
70 | MODULE_DEVICE_TABLE(of, decon_driver_dt_match); | |
71 | ||
fbbb1e1a MS |
72 | static const uint32_t decon_formats[] = { |
73 | DRM_FORMAT_RGB565, | |
74 | DRM_FORMAT_XRGB8888, | |
75 | DRM_FORMAT_XBGR8888, | |
76 | DRM_FORMAT_RGBX8888, | |
77 | DRM_FORMAT_BGRX8888, | |
78 | DRM_FORMAT_ARGB8888, | |
79 | DRM_FORMAT_ABGR8888, | |
80 | DRM_FORMAT_RGBA8888, | |
81 | DRM_FORMAT_BGRA8888, | |
82 | }; | |
83 | ||
fd2d2fc2 MS |
84 | static const enum drm_plane_type decon_win_types[WINDOWS_NR] = { |
85 | DRM_PLANE_TYPE_PRIMARY, | |
86 | DRM_PLANE_TYPE_CURSOR, | |
87 | }; | |
88 | ||
96976c3d AK |
89 | static void decon_wait_for_vblank(struct exynos_drm_crtc *crtc) |
90 | { | |
91 | struct decon_context *ctx = crtc->ctx; | |
92 | ||
93 | if (ctx->suspended) | |
94 | return; | |
95 | ||
96 | atomic_set(&ctx->wait_vsync_event, 1); | |
97 | ||
98 | /* | |
99 | * wait for DECON to signal VSYNC interrupt or return after | |
100 | * timeout which is set to 50ms (refresh rate of 20). | |
101 | */ | |
102 | if (!wait_event_timeout(ctx->wait_vsync_queue, | |
103 | !atomic_read(&ctx->wait_vsync_event), | |
104 | HZ/20)) | |
105 | DRM_DEBUG_KMS("vblank wait timed out.\n"); | |
106 | } | |
107 | ||
fc2e013f | 108 | static void decon_clear_channels(struct exynos_drm_crtc *crtc) |
96976c3d | 109 | { |
fc2e013f | 110 | struct decon_context *ctx = crtc->ctx; |
5b1d5bc6 | 111 | unsigned int win, ch_enabled = 0; |
96976c3d AK |
112 | |
113 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
114 | ||
115 | /* Check if any channel is enabled. */ | |
116 | for (win = 0; win < WINDOWS_NR; win++) { | |
117 | u32 val = readl(ctx->regs + WINCON(win)); | |
118 | ||
119 | if (val & WINCONx_ENWIN) { | |
120 | val &= ~WINCONx_ENWIN; | |
121 | writel(val, ctx->regs + WINCON(win)); | |
122 | ch_enabled = 1; | |
123 | } | |
124 | } | |
125 | ||
126 | /* Wait for vsync, as disable channel takes effect at next vsync */ | |
681c801e | 127 | if (ch_enabled) |
96976c3d | 128 | decon_wait_for_vblank(ctx->crtc); |
96976c3d AK |
129 | } |
130 | ||
131 | static int decon_ctx_initialize(struct decon_context *ctx, | |
132 | struct drm_device *drm_dev) | |
133 | { | |
134 | struct exynos_drm_private *priv = drm_dev->dev_private; | |
fc2e013f | 135 | int ret; |
96976c3d AK |
136 | |
137 | ctx->drm_dev = drm_dev; | |
138 | ctx->pipe = priv->pipe++; | |
139 | ||
eb7a3fc7 JS |
140 | decon_clear_channels(ctx->crtc); |
141 | ||
142 | ret = drm_iommu_attach_device(drm_dev, ctx->dev); | |
fc2e013f HH |
143 | if (ret) |
144 | priv->pipe--; | |
96976c3d | 145 | |
fc2e013f | 146 | return ret; |
96976c3d AK |
147 | } |
148 | ||
149 | static void decon_ctx_remove(struct decon_context *ctx) | |
150 | { | |
151 | /* detach this sub driver from iommu mapping if supported. */ | |
bf56608a | 152 | drm_iommu_detach_device(ctx->drm_dev, ctx->dev); |
96976c3d AK |
153 | } |
154 | ||
155 | static u32 decon_calc_clkdiv(struct decon_context *ctx, | |
156 | const struct drm_display_mode *mode) | |
157 | { | |
158 | unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh; | |
159 | u32 clkdiv; | |
160 | ||
161 | /* Find the clock divider value that gets us closest to ideal_clk */ | |
162 | clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk); | |
163 | ||
164 | return (clkdiv < 0x100) ? clkdiv : 0xff; | |
165 | } | |
166 | ||
96976c3d AK |
167 | static void decon_commit(struct exynos_drm_crtc *crtc) |
168 | { | |
169 | struct decon_context *ctx = crtc->ctx; | |
020e79de | 170 | struct drm_display_mode *mode = &crtc->base.state->adjusted_mode; |
96976c3d AK |
171 | u32 val, clkdiv; |
172 | ||
173 | if (ctx->suspended) | |
174 | return; | |
175 | ||
176 | /* nothing to do if we haven't set the mode yet */ | |
177 | if (mode->htotal == 0 || mode->vtotal == 0) | |
178 | return; | |
179 | ||
180 | if (!ctx->i80_if) { | |
181 | int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd; | |
182 | /* setup vertical timing values. */ | |
183 | vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; | |
184 | vbpd = mode->crtc_vtotal - mode->crtc_vsync_end; | |
185 | vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay; | |
186 | ||
187 | val = VIDTCON0_VBPD(vbpd - 1) | VIDTCON0_VFPD(vfpd - 1); | |
188 | writel(val, ctx->regs + VIDTCON0); | |
189 | ||
190 | val = VIDTCON1_VSPW(vsync_len - 1); | |
191 | writel(val, ctx->regs + VIDTCON1); | |
192 | ||
193 | /* setup horizontal timing values. */ | |
194 | hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; | |
195 | hbpd = mode->crtc_htotal - mode->crtc_hsync_end; | |
196 | hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay; | |
197 | ||
198 | /* setup horizontal timing values. */ | |
199 | val = VIDTCON2_HBPD(hbpd - 1) | VIDTCON2_HFPD(hfpd - 1); | |
200 | writel(val, ctx->regs + VIDTCON2); | |
201 | ||
202 | val = VIDTCON3_HSPW(hsync_len - 1); | |
203 | writel(val, ctx->regs + VIDTCON3); | |
204 | } | |
205 | ||
206 | /* setup horizontal and vertical display size. */ | |
207 | val = VIDTCON4_LINEVAL(mode->vdisplay - 1) | | |
208 | VIDTCON4_HOZVAL(mode->hdisplay - 1); | |
209 | writel(val, ctx->regs + VIDTCON4); | |
210 | ||
211 | writel(mode->vdisplay - 1, ctx->regs + LINECNT_OP_THRESHOLD); | |
212 | ||
213 | /* | |
214 | * fields of register with prefix '_F' would be updated | |
215 | * at vsync(same as dma start) | |
216 | */ | |
217 | val = VIDCON0_ENVID | VIDCON0_ENVID_F; | |
218 | writel(val, ctx->regs + VIDCON0); | |
219 | ||
220 | clkdiv = decon_calc_clkdiv(ctx, mode); | |
221 | if (clkdiv > 1) { | |
222 | val = VCLKCON1_CLKVAL_NUM_VCLK(clkdiv - 1); | |
223 | writel(val, ctx->regs + VCLKCON1); | |
224 | writel(val, ctx->regs + VCLKCON2); | |
225 | } | |
226 | ||
227 | val = readl(ctx->regs + DECON_UPDATE); | |
228 | val |= DECON_UPDATE_STANDALONE_F; | |
229 | writel(val, ctx->regs + DECON_UPDATE); | |
230 | } | |
231 | ||
232 | static int decon_enable_vblank(struct exynos_drm_crtc *crtc) | |
233 | { | |
234 | struct decon_context *ctx = crtc->ctx; | |
235 | u32 val; | |
236 | ||
237 | if (ctx->suspended) | |
238 | return -EPERM; | |
239 | ||
240 | if (!test_and_set_bit(0, &ctx->irq_flags)) { | |
241 | val = readl(ctx->regs + VIDINTCON0); | |
242 | ||
243 | val |= VIDINTCON0_INT_ENABLE; | |
244 | ||
245 | if (!ctx->i80_if) { | |
246 | val |= VIDINTCON0_INT_FRAME; | |
247 | val &= ~VIDINTCON0_FRAMESEL0_MASK; | |
248 | val |= VIDINTCON0_FRAMESEL0_VSYNC; | |
249 | } | |
250 | ||
251 | writel(val, ctx->regs + VIDINTCON0); | |
252 | } | |
253 | ||
254 | return 0; | |
255 | } | |
256 | ||
257 | static void decon_disable_vblank(struct exynos_drm_crtc *crtc) | |
258 | { | |
259 | struct decon_context *ctx = crtc->ctx; | |
260 | u32 val; | |
261 | ||
262 | if (ctx->suspended) | |
263 | return; | |
264 | ||
265 | if (test_and_clear_bit(0, &ctx->irq_flags)) { | |
266 | val = readl(ctx->regs + VIDINTCON0); | |
267 | ||
268 | val &= ~VIDINTCON0_INT_ENABLE; | |
269 | if (!ctx->i80_if) | |
270 | val &= ~VIDINTCON0_INT_FRAME; | |
271 | ||
272 | writel(val, ctx->regs + VIDINTCON0); | |
273 | } | |
274 | } | |
275 | ||
2eeb2e5e GP |
276 | static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, |
277 | struct drm_framebuffer *fb) | |
96976c3d | 278 | { |
96976c3d | 279 | unsigned long val; |
7ee14cdc | 280 | int padding; |
96976c3d AK |
281 | |
282 | val = readl(ctx->regs + WINCON(win)); | |
283 | val &= ~WINCONx_BPPMODE_MASK; | |
284 | ||
2eeb2e5e | 285 | switch (fb->pixel_format) { |
96976c3d AK |
286 | case DRM_FORMAT_RGB565: |
287 | val |= WINCONx_BPPMODE_16BPP_565; | |
288 | val |= WINCONx_BURSTLEN_16WORD; | |
289 | break; | |
290 | case DRM_FORMAT_XRGB8888: | |
291 | val |= WINCONx_BPPMODE_24BPP_xRGB; | |
292 | val |= WINCONx_BURSTLEN_16WORD; | |
293 | break; | |
294 | case DRM_FORMAT_XBGR8888: | |
295 | val |= WINCONx_BPPMODE_24BPP_xBGR; | |
296 | val |= WINCONx_BURSTLEN_16WORD; | |
297 | break; | |
298 | case DRM_FORMAT_RGBX8888: | |
299 | val |= WINCONx_BPPMODE_24BPP_RGBx; | |
300 | val |= WINCONx_BURSTLEN_16WORD; | |
301 | break; | |
302 | case DRM_FORMAT_BGRX8888: | |
303 | val |= WINCONx_BPPMODE_24BPP_BGRx; | |
304 | val |= WINCONx_BURSTLEN_16WORD; | |
305 | break; | |
306 | case DRM_FORMAT_ARGB8888: | |
307 | val |= WINCONx_BPPMODE_32BPP_ARGB | WINCONx_BLD_PIX | | |
308 | WINCONx_ALPHA_SEL; | |
309 | val |= WINCONx_BURSTLEN_16WORD; | |
310 | break; | |
311 | case DRM_FORMAT_ABGR8888: | |
312 | val |= WINCONx_BPPMODE_32BPP_ABGR | WINCONx_BLD_PIX | | |
313 | WINCONx_ALPHA_SEL; | |
314 | val |= WINCONx_BURSTLEN_16WORD; | |
315 | break; | |
316 | case DRM_FORMAT_RGBA8888: | |
317 | val |= WINCONx_BPPMODE_32BPP_RGBA | WINCONx_BLD_PIX | | |
318 | WINCONx_ALPHA_SEL; | |
319 | val |= WINCONx_BURSTLEN_16WORD; | |
320 | break; | |
321 | case DRM_FORMAT_BGRA8888: | |
322 | val |= WINCONx_BPPMODE_32BPP_BGRA | WINCONx_BLD_PIX | | |
323 | WINCONx_ALPHA_SEL; | |
324 | val |= WINCONx_BURSTLEN_16WORD; | |
325 | break; | |
326 | default: | |
327 | DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n"); | |
328 | ||
329 | val |= WINCONx_BPPMODE_24BPP_xRGB; | |
330 | val |= WINCONx_BURSTLEN_16WORD; | |
331 | break; | |
332 | } | |
333 | ||
2eeb2e5e | 334 | DRM_DEBUG_KMS("bpp = %d\n", fb->bits_per_pixel); |
96976c3d AK |
335 | |
336 | /* | |
337 | * In case of exynos, setting dma-burst to 16Word causes permanent | |
338 | * tearing for very small buffers, e.g. cursor buffer. Burst Mode | |
339 | * switching which is based on plane size is not recommended as | |
340 | * plane size varies a lot towards the end of the screen and rapid | |
341 | * movement causes unstable DMA which results into iommu crash/tear. | |
342 | */ | |
343 | ||
2eeb2e5e GP |
344 | padding = (fb->pitches[0] / (fb->bits_per_pixel >> 3)) - fb->width; |
345 | if (fb->width + padding < MIN_FB_WIDTH_FOR_16WORD_BURST) { | |
96976c3d AK |
346 | val &= ~WINCONx_BURSTLEN_MASK; |
347 | val |= WINCONx_BURSTLEN_8WORD; | |
348 | } | |
349 | ||
350 | writel(val, ctx->regs + WINCON(win)); | |
351 | } | |
352 | ||
353 | static void decon_win_set_colkey(struct decon_context *ctx, unsigned int win) | |
354 | { | |
355 | unsigned int keycon0 = 0, keycon1 = 0; | |
356 | ||
357 | keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F | | |
358 | WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); | |
359 | ||
360 | keycon1 = WxKEYCON1_COLVAL(0xffffffff); | |
361 | ||
362 | writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); | |
363 | writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); | |
364 | } | |
365 | ||
366 | /** | |
367 | * shadow_protect_win() - disable updating values from shadow registers at vsync | |
368 | * | |
369 | * @win: window to protect registers for | |
370 | * @protect: 1 to protect (disable updates) | |
371 | */ | |
372 | static void decon_shadow_protect_win(struct decon_context *ctx, | |
6e2a3b66 | 373 | unsigned int win, bool protect) |
96976c3d AK |
374 | { |
375 | u32 bits, val; | |
376 | ||
377 | bits = SHADOWCON_WINx_PROTECT(win); | |
378 | ||
379 | val = readl(ctx->regs + SHADOWCON); | |
380 | if (protect) | |
381 | val |= bits; | |
382 | else | |
383 | val &= ~bits; | |
384 | writel(val, ctx->regs + SHADOWCON); | |
385 | } | |
386 | ||
d29c2c14 | 387 | static void decon_atomic_begin(struct exynos_drm_crtc *crtc) |
cc5a7b35 HH |
388 | { |
389 | struct decon_context *ctx = crtc->ctx; | |
d29c2c14 | 390 | int i; |
cc5a7b35 HH |
391 | |
392 | if (ctx->suspended) | |
393 | return; | |
394 | ||
d29c2c14 MS |
395 | for (i = 0; i < WINDOWS_NR; i++) |
396 | decon_shadow_protect_win(ctx, i, true); | |
cc5a7b35 HH |
397 | } |
398 | ||
1e1d1393 GP |
399 | static void decon_update_plane(struct exynos_drm_crtc *crtc, |
400 | struct exynos_drm_plane *plane) | |
96976c3d | 401 | { |
0114f404 MS |
402 | struct exynos_drm_plane_state *state = |
403 | to_exynos_plane_state(plane->base.state); | |
96976c3d | 404 | struct decon_context *ctx = crtc->ctx; |
0114f404 | 405 | struct drm_framebuffer *fb = state->base.fb; |
6e2a3b66 | 406 | int padding; |
96976c3d AK |
407 | unsigned long val, alpha; |
408 | unsigned int last_x; | |
409 | unsigned int last_y; | |
40bdfb0a | 410 | unsigned int win = plane->index; |
0488f50e MS |
411 | unsigned int bpp = fb->bits_per_pixel >> 3; |
412 | unsigned int pitch = fb->pitches[0]; | |
96976c3d AK |
413 | |
414 | if (ctx->suspended) | |
415 | return; | |
416 | ||
96976c3d AK |
417 | /* |
418 | * SHADOWCON/PRTCON register is used for enabling timing. | |
419 | * | |
420 | * for example, once only width value of a register is set, | |
421 | * if the dma is started then decon hardware could malfunction so | |
422 | * with protect window setting, the register fields with prefix '_F' | |
423 | * wouldn't be updated at vsync also but updated once unprotect window | |
424 | * is set. | |
425 | */ | |
426 | ||
96976c3d | 427 | /* buffer start address */ |
0488f50e | 428 | val = (unsigned long)exynos_drm_fb_dma_addr(fb, 0); |
96976c3d AK |
429 | writel(val, ctx->regs + VIDW_BUF_START(win)); |
430 | ||
0488f50e | 431 | padding = (pitch / bpp) - fb->width; |
7ee14cdc | 432 | |
96976c3d | 433 | /* buffer size */ |
0488f50e MS |
434 | writel(fb->width + padding, ctx->regs + VIDW_WHOLE_X(win)); |
435 | writel(fb->height, ctx->regs + VIDW_WHOLE_Y(win)); | |
96976c3d AK |
436 | |
437 | /* offset from the start of the buffer to read */ | |
0114f404 MS |
438 | writel(state->src.x, ctx->regs + VIDW_OFFSET_X(win)); |
439 | writel(state->src.y, ctx->regs + VIDW_OFFSET_Y(win)); | |
96976c3d AK |
440 | |
441 | DRM_DEBUG_KMS("start addr = 0x%lx\n", | |
7ee14cdc | 442 | (unsigned long)val); |
96976c3d | 443 | DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", |
0114f404 | 444 | state->crtc.w, state->crtc.h); |
96976c3d | 445 | |
0114f404 MS |
446 | val = VIDOSDxA_TOPLEFT_X(state->crtc.x) | |
447 | VIDOSDxA_TOPLEFT_Y(state->crtc.y); | |
96976c3d AK |
448 | writel(val, ctx->regs + VIDOSD_A(win)); |
449 | ||
0114f404 | 450 | last_x = state->crtc.x + state->crtc.w; |
96976c3d AK |
451 | if (last_x) |
452 | last_x--; | |
0114f404 | 453 | last_y = state->crtc.y + state->crtc.h; |
96976c3d AK |
454 | if (last_y) |
455 | last_y--; | |
456 | ||
457 | val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y); | |
458 | ||
459 | writel(val, ctx->regs + VIDOSD_B(win)); | |
460 | ||
461 | DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", | |
0114f404 | 462 | state->crtc.x, state->crtc.y, last_x, last_y); |
96976c3d AK |
463 | |
464 | /* OSD alpha */ | |
465 | alpha = VIDOSDxC_ALPHA0_R_F(0x0) | | |
466 | VIDOSDxC_ALPHA0_G_F(0x0) | | |
467 | VIDOSDxC_ALPHA0_B_F(0x0); | |
468 | ||
469 | writel(alpha, ctx->regs + VIDOSD_C(win)); | |
470 | ||
471 | alpha = VIDOSDxD_ALPHA1_R_F(0xff) | | |
472 | VIDOSDxD_ALPHA1_G_F(0xff) | | |
473 | VIDOSDxD_ALPHA1_B_F(0xff); | |
474 | ||
475 | writel(alpha, ctx->regs + VIDOSD_D(win)); | |
476 | ||
0488f50e | 477 | decon_win_set_pixfmt(ctx, win, fb); |
96976c3d AK |
478 | |
479 | /* hardware window 0 doesn't support color key. */ | |
480 | if (win != 0) | |
481 | decon_win_set_colkey(ctx, win); | |
482 | ||
483 | /* wincon */ | |
484 | val = readl(ctx->regs + WINCON(win)); | |
485 | val |= WINCONx_TRIPLE_BUF_MODE; | |
486 | val |= WINCONx_ENWIN; | |
487 | writel(val, ctx->regs + WINCON(win)); | |
488 | ||
489 | /* Enable DMA channel and unprotect windows */ | |
490 | decon_shadow_protect_win(ctx, win, false); | |
491 | ||
492 | val = readl(ctx->regs + DECON_UPDATE); | |
493 | val |= DECON_UPDATE_STANDALONE_F; | |
494 | writel(val, ctx->regs + DECON_UPDATE); | |
96976c3d AK |
495 | } |
496 | ||
1e1d1393 GP |
497 | static void decon_disable_plane(struct exynos_drm_crtc *crtc, |
498 | struct exynos_drm_plane *plane) | |
96976c3d AK |
499 | { |
500 | struct decon_context *ctx = crtc->ctx; | |
40bdfb0a | 501 | unsigned int win = plane->index; |
96976c3d AK |
502 | u32 val; |
503 | ||
c329f667 | 504 | if (ctx->suspended) |
96976c3d | 505 | return; |
96976c3d AK |
506 | |
507 | /* protect windows */ | |
508 | decon_shadow_protect_win(ctx, win, true); | |
509 | ||
510 | /* wincon */ | |
511 | val = readl(ctx->regs + WINCON(win)); | |
512 | val &= ~WINCONx_ENWIN; | |
513 | writel(val, ctx->regs + WINCON(win)); | |
514 | ||
96976c3d AK |
515 | val = readl(ctx->regs + DECON_UPDATE); |
516 | val |= DECON_UPDATE_STANDALONE_F; | |
517 | writel(val, ctx->regs + DECON_UPDATE); | |
96976c3d AK |
518 | } |
519 | ||
d29c2c14 | 520 | static void decon_atomic_flush(struct exynos_drm_crtc *crtc) |
cc5a7b35 HH |
521 | { |
522 | struct decon_context *ctx = crtc->ctx; | |
d29c2c14 | 523 | int i; |
cc5a7b35 HH |
524 | |
525 | if (ctx->suspended) | |
526 | return; | |
527 | ||
d29c2c14 MS |
528 | for (i = 0; i < WINDOWS_NR; i++) |
529 | decon_shadow_protect_win(ctx, i, false); | |
cc5a7b35 HH |
530 | } |
531 | ||
96976c3d AK |
532 | static void decon_init(struct decon_context *ctx) |
533 | { | |
534 | u32 val; | |
535 | ||
536 | writel(VIDCON0_SWRESET, ctx->regs + VIDCON0); | |
537 | ||
538 | val = VIDOUTCON0_DISP_IF_0_ON; | |
539 | if (!ctx->i80_if) | |
540 | val |= VIDOUTCON0_RGBIF; | |
541 | writel(val, ctx->regs + VIDOUTCON0); | |
542 | ||
543 | writel(VCLKCON0_CLKVALUP | VCLKCON0_VCLKFREE, ctx->regs + VCLKCON0); | |
544 | ||
545 | if (!ctx->i80_if) | |
546 | writel(VIDCON1_VCLK_HOLD, ctx->regs + VIDCON1(0)); | |
547 | } | |
548 | ||
3cecda03 | 549 | static void decon_enable(struct exynos_drm_crtc *crtc) |
96976c3d | 550 | { |
3cecda03 | 551 | struct decon_context *ctx = crtc->ctx; |
96976c3d AK |
552 | |
553 | if (!ctx->suspended) | |
3cecda03 | 554 | return; |
96976c3d | 555 | |
96976c3d AK |
556 | pm_runtime_get_sync(ctx->dev); |
557 | ||
96976c3d AK |
558 | decon_init(ctx); |
559 | ||
560 | /* if vblank was enabled status, enable it again. */ | |
3cecda03 GP |
561 | if (test_and_clear_bit(0, &ctx->irq_flags)) |
562 | decon_enable_vblank(ctx->crtc); | |
96976c3d | 563 | |
c329f667 | 564 | decon_commit(ctx->crtc); |
681c801e GP |
565 | |
566 | ctx->suspended = false; | |
96976c3d AK |
567 | } |
568 | ||
3cecda03 | 569 | static void decon_disable(struct exynos_drm_crtc *crtc) |
96976c3d | 570 | { |
3cecda03 | 571 | struct decon_context *ctx = crtc->ctx; |
c329f667 | 572 | int i; |
3cecda03 | 573 | |
96976c3d | 574 | if (ctx->suspended) |
3cecda03 | 575 | return; |
96976c3d AK |
576 | |
577 | /* | |
578 | * We need to make sure that all windows are disabled before we | |
579 | * suspend that connector. Otherwise we might try to scan from | |
580 | * a destroyed buffer later. | |
581 | */ | |
c329f667 | 582 | for (i = 0; i < WINDOWS_NR; i++) |
1e1d1393 | 583 | decon_disable_plane(crtc, &ctx->planes[i]); |
96976c3d | 584 | |
96976c3d AK |
585 | pm_runtime_put_sync(ctx->dev); |
586 | ||
587 | ctx->suspended = true; | |
96976c3d AK |
588 | } |
589 | ||
f3aaf762 | 590 | static const struct exynos_drm_crtc_ops decon_crtc_ops = { |
3cecda03 GP |
591 | .enable = decon_enable, |
592 | .disable = decon_disable, | |
96976c3d AK |
593 | .commit = decon_commit, |
594 | .enable_vblank = decon_enable_vblank, | |
595 | .disable_vblank = decon_disable_vblank, | |
596 | .wait_for_vblank = decon_wait_for_vblank, | |
cc5a7b35 | 597 | .atomic_begin = decon_atomic_begin, |
9cc7610a GP |
598 | .update_plane = decon_update_plane, |
599 | .disable_plane = decon_disable_plane, | |
cc5a7b35 | 600 | .atomic_flush = decon_atomic_flush, |
96976c3d AK |
601 | }; |
602 | ||
603 | ||
604 | static irqreturn_t decon_irq_handler(int irq, void *dev_id) | |
605 | { | |
606 | struct decon_context *ctx = (struct decon_context *)dev_id; | |
607 | u32 val, clear_bit; | |
822f6dfd | 608 | int win; |
96976c3d AK |
609 | |
610 | val = readl(ctx->regs + VIDINTCON1); | |
611 | ||
612 | clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME; | |
613 | if (val & clear_bit) | |
614 | writel(clear_bit, ctx->regs + VIDINTCON1); | |
615 | ||
616 | /* check the crtc is detached already from encoder */ | |
617 | if (ctx->pipe < 0 || !ctx->drm_dev) | |
618 | goto out; | |
619 | ||
620 | if (!ctx->i80_if) { | |
eafd540a | 621 | drm_crtc_handle_vblank(&ctx->crtc->base); |
822f6dfd GP |
622 | for (win = 0 ; win < WINDOWS_NR ; win++) { |
623 | struct exynos_drm_plane *plane = &ctx->planes[win]; | |
624 | ||
625 | if (!plane->pending_fb) | |
626 | continue; | |
627 | ||
628 | exynos_drm_crtc_finish_update(ctx->crtc, plane); | |
629 | } | |
96976c3d AK |
630 | |
631 | /* set wait vsync event to zero and wake up queue. */ | |
632 | if (atomic_read(&ctx->wait_vsync_event)) { | |
633 | atomic_set(&ctx->wait_vsync_event, 0); | |
634 | wake_up(&ctx->wait_vsync_queue); | |
635 | } | |
636 | } | |
637 | out: | |
638 | return IRQ_HANDLED; | |
639 | } | |
640 | ||
641 | static int decon_bind(struct device *dev, struct device *master, void *data) | |
642 | { | |
643 | struct decon_context *ctx = dev_get_drvdata(dev); | |
644 | struct drm_device *drm_dev = data; | |
7ee14cdc | 645 | struct exynos_drm_plane *exynos_plane; |
fd2d2fc2 | 646 | unsigned int i; |
6e2a3b66 | 647 | int ret; |
96976c3d AK |
648 | |
649 | ret = decon_ctx_initialize(ctx, drm_dev); | |
650 | if (ret) { | |
651 | DRM_ERROR("decon_ctx_initialize failed.\n"); | |
652 | return ret; | |
653 | } | |
654 | ||
fd2d2fc2 MS |
655 | for (i = 0; i < WINDOWS_NR; i++) { |
656 | ctx->configs[i].pixel_formats = decon_formats; | |
657 | ctx->configs[i].num_pixel_formats = ARRAY_SIZE(decon_formats); | |
658 | ctx->configs[i].zpos = i; | |
659 | ctx->configs[i].type = decon_win_types[i]; | |
660 | ||
40bdfb0a | 661 | ret = exynos_plane_init(drm_dev, &ctx->planes[i], i, |
fd2d2fc2 | 662 | 1 << ctx->pipe, &ctx->configs[i]); |
7ee14cdc GP |
663 | if (ret) |
664 | return ret; | |
665 | } | |
666 | ||
5d3d0995 | 667 | exynos_plane = &ctx->planes[DEFAULT_WIN]; |
7ee14cdc GP |
668 | ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, |
669 | ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD, | |
96976c3d AK |
670 | &decon_crtc_ops, ctx); |
671 | if (IS_ERR(ctx->crtc)) { | |
672 | decon_ctx_remove(ctx); | |
673 | return PTR_ERR(ctx->crtc); | |
674 | } | |
675 | ||
cf67cc9a | 676 | if (ctx->encoder) |
a2986e80 | 677 | exynos_dpi_bind(drm_dev, ctx->encoder); |
96976c3d AK |
678 | |
679 | return 0; | |
680 | ||
681 | } | |
682 | ||
683 | static void decon_unbind(struct device *dev, struct device *master, | |
684 | void *data) | |
685 | { | |
686 | struct decon_context *ctx = dev_get_drvdata(dev); | |
687 | ||
3cecda03 | 688 | decon_disable(ctx->crtc); |
96976c3d | 689 | |
cf67cc9a GP |
690 | if (ctx->encoder) |
691 | exynos_dpi_remove(ctx->encoder); | |
96976c3d AK |
692 | |
693 | decon_ctx_remove(ctx); | |
694 | } | |
695 | ||
696 | static const struct component_ops decon_component_ops = { | |
697 | .bind = decon_bind, | |
698 | .unbind = decon_unbind, | |
699 | }; | |
700 | ||
701 | static int decon_probe(struct platform_device *pdev) | |
702 | { | |
703 | struct device *dev = &pdev->dev; | |
704 | struct decon_context *ctx; | |
705 | struct device_node *i80_if_timings; | |
706 | struct resource *res; | |
707 | int ret; | |
708 | ||
709 | if (!dev->of_node) | |
710 | return -ENODEV; | |
711 | ||
712 | ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); | |
713 | if (!ctx) | |
714 | return -ENOMEM; | |
715 | ||
96976c3d AK |
716 | ctx->dev = dev; |
717 | ctx->suspended = true; | |
718 | ||
719 | i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings"); | |
720 | if (i80_if_timings) | |
721 | ctx->i80_if = true; | |
722 | of_node_put(i80_if_timings); | |
723 | ||
724 | ctx->regs = of_iomap(dev->of_node, 0); | |
86650408 AH |
725 | if (!ctx->regs) |
726 | return -ENOMEM; | |
96976c3d AK |
727 | |
728 | ctx->pclk = devm_clk_get(dev, "pclk_decon0"); | |
729 | if (IS_ERR(ctx->pclk)) { | |
730 | dev_err(dev, "failed to get bus clock pclk\n"); | |
731 | ret = PTR_ERR(ctx->pclk); | |
732 | goto err_iounmap; | |
733 | } | |
734 | ||
735 | ctx->aclk = devm_clk_get(dev, "aclk_decon0"); | |
736 | if (IS_ERR(ctx->aclk)) { | |
737 | dev_err(dev, "failed to get bus clock aclk\n"); | |
738 | ret = PTR_ERR(ctx->aclk); | |
739 | goto err_iounmap; | |
740 | } | |
741 | ||
742 | ctx->eclk = devm_clk_get(dev, "decon0_eclk"); | |
743 | if (IS_ERR(ctx->eclk)) { | |
744 | dev_err(dev, "failed to get eclock\n"); | |
745 | ret = PTR_ERR(ctx->eclk); | |
746 | goto err_iounmap; | |
747 | } | |
748 | ||
749 | ctx->vclk = devm_clk_get(dev, "decon0_vclk"); | |
750 | if (IS_ERR(ctx->vclk)) { | |
751 | dev_err(dev, "failed to get vclock\n"); | |
752 | ret = PTR_ERR(ctx->vclk); | |
753 | goto err_iounmap; | |
754 | } | |
755 | ||
756 | res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, | |
757 | ctx->i80_if ? "lcd_sys" : "vsync"); | |
758 | if (!res) { | |
759 | dev_err(dev, "irq request failed.\n"); | |
760 | ret = -ENXIO; | |
761 | goto err_iounmap; | |
762 | } | |
763 | ||
764 | ret = devm_request_irq(dev, res->start, decon_irq_handler, | |
765 | 0, "drm_decon", ctx); | |
766 | if (ret) { | |
767 | dev_err(dev, "irq request failed.\n"); | |
768 | goto err_iounmap; | |
769 | } | |
770 | ||
771 | init_waitqueue_head(&ctx->wait_vsync_queue); | |
772 | atomic_set(&ctx->wait_vsync_event, 0); | |
773 | ||
774 | platform_set_drvdata(pdev, ctx); | |
775 | ||
cf67cc9a GP |
776 | ctx->encoder = exynos_dpi_probe(dev); |
777 | if (IS_ERR(ctx->encoder)) { | |
778 | ret = PTR_ERR(ctx->encoder); | |
96976c3d AK |
779 | goto err_iounmap; |
780 | } | |
781 | ||
782 | pm_runtime_enable(dev); | |
783 | ||
784 | ret = component_add(dev, &decon_component_ops); | |
785 | if (ret) | |
786 | goto err_disable_pm_runtime; | |
787 | ||
788 | return ret; | |
789 | ||
790 | err_disable_pm_runtime: | |
791 | pm_runtime_disable(dev); | |
792 | ||
793 | err_iounmap: | |
794 | iounmap(ctx->regs); | |
795 | ||
96976c3d AK |
796 | return ret; |
797 | } | |
798 | ||
799 | static int decon_remove(struct platform_device *pdev) | |
800 | { | |
801 | struct decon_context *ctx = dev_get_drvdata(&pdev->dev); | |
802 | ||
803 | pm_runtime_disable(&pdev->dev); | |
804 | ||
805 | iounmap(ctx->regs); | |
806 | ||
807 | component_del(&pdev->dev, &decon_component_ops); | |
96976c3d AK |
808 | |
809 | return 0; | |
810 | } | |
811 | ||
681c801e GP |
812 | #ifdef CONFIG_PM |
813 | static int exynos7_decon_suspend(struct device *dev) | |
814 | { | |
815 | struct decon_context *ctx = dev_get_drvdata(dev); | |
816 | ||
817 | clk_disable_unprepare(ctx->vclk); | |
818 | clk_disable_unprepare(ctx->eclk); | |
819 | clk_disable_unprepare(ctx->aclk); | |
820 | clk_disable_unprepare(ctx->pclk); | |
821 | ||
822 | return 0; | |
823 | } | |
824 | ||
825 | static int exynos7_decon_resume(struct device *dev) | |
826 | { | |
827 | struct decon_context *ctx = dev_get_drvdata(dev); | |
828 | int ret; | |
829 | ||
830 | ret = clk_prepare_enable(ctx->pclk); | |
831 | if (ret < 0) { | |
832 | DRM_ERROR("Failed to prepare_enable the pclk [%d]\n", ret); | |
833 | return ret; | |
834 | } | |
835 | ||
836 | ret = clk_prepare_enable(ctx->aclk); | |
837 | if (ret < 0) { | |
838 | DRM_ERROR("Failed to prepare_enable the aclk [%d]\n", ret); | |
839 | return ret; | |
840 | } | |
841 | ||
842 | ret = clk_prepare_enable(ctx->eclk); | |
843 | if (ret < 0) { | |
844 | DRM_ERROR("Failed to prepare_enable the eclk [%d]\n", ret); | |
845 | return ret; | |
846 | } | |
847 | ||
848 | ret = clk_prepare_enable(ctx->vclk); | |
849 | if (ret < 0) { | |
850 | DRM_ERROR("Failed to prepare_enable the vclk [%d]\n", ret); | |
851 | return ret; | |
852 | } | |
853 | ||
854 | return 0; | |
855 | } | |
856 | #endif | |
857 | ||
858 | static const struct dev_pm_ops exynos7_decon_pm_ops = { | |
859 | SET_RUNTIME_PM_OPS(exynos7_decon_suspend, exynos7_decon_resume, | |
860 | NULL) | |
861 | }; | |
862 | ||
96976c3d AK |
863 | struct platform_driver decon_driver = { |
864 | .probe = decon_probe, | |
865 | .remove = decon_remove, | |
866 | .driver = { | |
867 | .name = "exynos-decon", | |
681c801e | 868 | .pm = &exynos7_decon_pm_ops, |
96976c3d AK |
869 | .of_match_table = decon_driver_dt_match, |
870 | }, | |
871 | }; |