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drm/exynos: Add the dependency for DRM_EXYNOS to DPI/DSI/DP
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / exynos / exynos7_drm_decon.c
CommitLineData
96976c3d
AK		 1/* drivers/gpu/drm/exynos/exynos7_drm_decon.c
2 *
3 * Copyright (C) 2014 Samsung Electronics Co.Ltd
4 * Authors:
5 * Akshu Agarwal <akshua@gmail.com>
6 * Ajay Kumar <ajaykumar.rs@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14#include <drm/drmP.h>
15#include <drm/exynos_drm.h>
16
17#include <linux/clk.h>
18#include <linux/component.h>
19#include <linux/kernel.h>
20#include <linux/of.h>
21#include <linux/of_address.h>
22#include <linux/of_device.h>
23#include <linux/platform_device.h>
24#include <linux/pm_runtime.h>
25
26#include <video/of_display_timing.h>
27#include <video/of_videomode.h>
28#include <video/exynos7_decon.h>
29
30#include "exynos_drm_crtc.h"
7ee14cdc 31#include "exynos_drm_plane.h"
96976c3d
AK		 32#include "exynos_drm_drv.h"
33#include "exynos_drm_fbdev.h"
34#include "exynos_drm_iommu.h"
35
36/*
37 * DECON stands for Display and Enhancement controller.
38 */
39
40#define DECON_DEFAULT_FRAMERATE 60
41#define MIN_FB_WIDTH_FOR_16WORD_BURST 128
42
43#define WINDOWS_NR 2
44
96976c3d
AK		 45struct decon_context {
46 struct device *dev;
47 struct drm_device *drm_dev;
48 struct exynos_drm_crtc *crtc;
7ee14cdc 49 struct exynos_drm_plane planes[WINDOWS_NR];
96976c3d
AK		 50 struct clk *pclk;
51 struct clk *aclk;
52 struct clk *eclk;
53 struct clk *vclk;
54 void __iomem *regs;
96976c3d
AK		 55 unsigned int default_win;
56 unsigned long irq_flags;
57 bool i80_if;
58 bool suspended;
59 int pipe;
60 wait_queue_head_t wait_vsync_queue;
61 atomic_t wait_vsync_event;
62
63 struct exynos_drm_panel_info panel;
64 struct exynos_drm_display *display;
65};
66
67static const struct of_device_id decon_driver_dt_match[] = {
68 {.compatible = "samsung,exynos7-decon"},
69 {},
70};
71MODULE_DEVICE_TABLE(of, decon_driver_dt_match);
72
73static void decon_wait_for_vblank(struct exynos_drm_crtc *crtc)
74{
75 struct decon_context *ctx = crtc->ctx;
76
77 if (ctx->suspended)
78 return;
79
80 atomic_set(&ctx->wait_vsync_event, 1);
81
82 /*
83 * wait for DECON to signal VSYNC interrupt or return after
84 * timeout which is set to 50ms (refresh rate of 20).
85 */
86 if (!wait_event_timeout(ctx->wait_vsync_queue,
87 !atomic_read(&ctx->wait_vsync_event),
88 HZ/20))
89 DRM_DEBUG_KMS("vblank wait timed out.\n");
90}
91
92static void decon_clear_channel(struct decon_context *ctx)
93{
5b1d5bc6 94 unsigned int win, ch_enabled = 0;
96976c3d
AK		 95
96 DRM_DEBUG_KMS("%s\n", __FILE__);
97
98 /* Check if any channel is enabled. */
99 for (win = 0; win < WINDOWS_NR; win++) {
100 u32 val = readl(ctx->regs + WINCON(win));
101
102 if (val & WINCONx_ENWIN) {
103 val &= ~WINCONx_ENWIN;
104 writel(val, ctx->regs + WINCON(win));
105 ch_enabled = 1;
106 }
107 }
108
109 /* Wait for vsync, as disable channel takes effect at next vsync */
110 if (ch_enabled) {
111 unsigned int state = ctx->suspended;
112
113 ctx->suspended = 0;
114 decon_wait_for_vblank(ctx->crtc);
115 ctx->suspended = state;
116 }
117}
118
119static int decon_ctx_initialize(struct decon_context *ctx,
120 struct drm_device *drm_dev)
121{
122 struct exynos_drm_private *priv = drm_dev->dev_private;
123
124 ctx->drm_dev = drm_dev;
125 ctx->pipe = priv->pipe++;
126
127 /* attach this sub driver to iommu mapping if supported. */
128 if (is_drm_iommu_supported(ctx->drm_dev)) {
129 int ret;
130
131 /*
132 * If any channel is already active, iommu will throw
133 * a PAGE FAULT when enabled. So clear any channel if enabled.
134 */
135 decon_clear_channel(ctx);
136 ret = drm_iommu_attach_device(ctx->drm_dev, ctx->dev);
137 if (ret) {
138 DRM_ERROR("drm_iommu_attach failed.\n");
139 return ret;
140 }
141 }
142
143 return 0;
144}
145
146static void decon_ctx_remove(struct decon_context *ctx)
147{
148 /* detach this sub driver from iommu mapping if supported. */
149 if (is_drm_iommu_supported(ctx->drm_dev))
150 drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
151}
152
153static u32 decon_calc_clkdiv(struct decon_context *ctx,
154 const struct drm_display_mode *mode)
155{
156 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
157 u32 clkdiv;
158
159 /* Find the clock divider value that gets us closest to ideal_clk */
160 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk);
161
162 return (clkdiv < 0x100) ? clkdiv : 0xff;
163}
164
165static bool decon_mode_fixup(struct exynos_drm_crtc *crtc,
166 const struct drm_display_mode *mode,
167 struct drm_display_mode *adjusted_mode)
168{
169 if (adjusted_mode->vrefresh == 0)
170 adjusted_mode->vrefresh = DECON_DEFAULT_FRAMERATE;
171
172 return true;
173}
174
175static void decon_commit(struct exynos_drm_crtc *crtc)
176{
177 struct decon_context *ctx = crtc->ctx;
020e79de 178 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
96976c3d
AK		 179 u32 val, clkdiv;
180
181 if (ctx->suspended)
182 return;
183
184 /* nothing to do if we haven't set the mode yet */
185 if (mode->htotal == 0 || mode->vtotal == 0)
186 return;
187
188 if (!ctx->i80_if) {
189 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
190 /* setup vertical timing values. */
191 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
192 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
193 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
194
195 val = VIDTCON0_VBPD(vbpd - 1) | VIDTCON0_VFPD(vfpd - 1);
196 writel(val, ctx->regs + VIDTCON0);
197
198 val = VIDTCON1_VSPW(vsync_len - 1);
199 writel(val, ctx->regs + VIDTCON1);
200
201 /* setup horizontal timing values. */
202 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
203 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
204 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
205
206 /* setup horizontal timing values. */
207 val = VIDTCON2_HBPD(hbpd - 1) | VIDTCON2_HFPD(hfpd - 1);
208 writel(val, ctx->regs + VIDTCON2);
209
210 val = VIDTCON3_HSPW(hsync_len - 1);
211 writel(val, ctx->regs + VIDTCON3);
212 }
213
214 /* setup horizontal and vertical display size. */
215 val = VIDTCON4_LINEVAL(mode->vdisplay - 1) |
216 VIDTCON4_HOZVAL(mode->hdisplay - 1);
217 writel(val, ctx->regs + VIDTCON4);
218
219 writel(mode->vdisplay - 1, ctx->regs + LINECNT_OP_THRESHOLD);
220
221 /*
222 * fields of register with prefix '_F' would be updated
223 * at vsync(same as dma start)
224 */
225 val = VIDCON0_ENVID | VIDCON0_ENVID_F;
226 writel(val, ctx->regs + VIDCON0);
227
228 clkdiv = decon_calc_clkdiv(ctx, mode);
229 if (clkdiv > 1) {
230 val = VCLKCON1_CLKVAL_NUM_VCLK(clkdiv - 1);
231 writel(val, ctx->regs + VCLKCON1);
232 writel(val, ctx->regs + VCLKCON2);
233 }
234
235 val = readl(ctx->regs + DECON_UPDATE);
236 val |= DECON_UPDATE_STANDALONE_F;
237 writel(val, ctx->regs + DECON_UPDATE);
238}
239
240static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
241{
242 struct decon_context *ctx = crtc->ctx;
243 u32 val;
244
245 if (ctx->suspended)
246 return -EPERM;
247
248 if (!test_and_set_bit(0, &ctx->irq_flags)) {
249 val = readl(ctx->regs + VIDINTCON0);
250
251 val |= VIDINTCON0_INT_ENABLE;
252
253 if (!ctx->i80_if) {
254 val |= VIDINTCON0_INT_FRAME;
255 val &= ~VIDINTCON0_FRAMESEL0_MASK;
256 val |= VIDINTCON0_FRAMESEL0_VSYNC;
257 }
258
259 writel(val, ctx->regs + VIDINTCON0);
260 }
261
262 return 0;
263}
264
265static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
266{
267 struct decon_context *ctx = crtc->ctx;
268 u32 val;
269
270 if (ctx->suspended)
271 return;
272
273 if (test_and_clear_bit(0, &ctx->irq_flags)) {
274 val = readl(ctx->regs + VIDINTCON0);
275
276 val &= ~VIDINTCON0_INT_ENABLE;
277 if (!ctx->i80_if)
278 val &= ~VIDINTCON0_INT_FRAME;
279
280 writel(val, ctx->regs + VIDINTCON0);
281 }
282}
283
96976c3d
AK		 284static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win)
285{
7ee14cdc 286 struct exynos_drm_plane *plane = &ctx->planes[win];
96976c3d 287 unsigned long val;
7ee14cdc 288 int padding;
96976c3d
AK		 289
290 val = readl(ctx->regs + WINCON(win));
291 val &= ~WINCONx_BPPMODE_MASK;
292
7ee14cdc 293 switch (plane->pixel_format) {
96976c3d
AK		 294 case DRM_FORMAT_RGB565:
295 val |= WINCONx_BPPMODE_16BPP_565;
296 val |= WINCONx_BURSTLEN_16WORD;
297 break;
298 case DRM_FORMAT_XRGB8888:
299 val |= WINCONx_BPPMODE_24BPP_xRGB;
300 val |= WINCONx_BURSTLEN_16WORD;
301 break;
302 case DRM_FORMAT_XBGR8888:
303 val |= WINCONx_BPPMODE_24BPP_xBGR;
304 val |= WINCONx_BURSTLEN_16WORD;
305 break;
306 case DRM_FORMAT_RGBX8888:
307 val |= WINCONx_BPPMODE_24BPP_RGBx;
308 val |= WINCONx_BURSTLEN_16WORD;
309 break;
310 case DRM_FORMAT_BGRX8888:
311 val |= WINCONx_BPPMODE_24BPP_BGRx;
312 val |= WINCONx_BURSTLEN_16WORD;
313 break;
314 case DRM_FORMAT_ARGB8888:
315 val |= WINCONx_BPPMODE_32BPP_ARGB | WINCONx_BLD_PIX |
316 WINCONx_ALPHA_SEL;
317 val |= WINCONx_BURSTLEN_16WORD;
318 break;
319 case DRM_FORMAT_ABGR8888:
320 val |= WINCONx_BPPMODE_32BPP_ABGR | WINCONx_BLD_PIX |
321 WINCONx_ALPHA_SEL;
322 val |= WINCONx_BURSTLEN_16WORD;
323 break;
324 case DRM_FORMAT_RGBA8888:
325 val |= WINCONx_BPPMODE_32BPP_RGBA | WINCONx_BLD_PIX |
326 WINCONx_ALPHA_SEL;
327 val |= WINCONx_BURSTLEN_16WORD;
328 break;
329 case DRM_FORMAT_BGRA8888:
330 val |= WINCONx_BPPMODE_32BPP_BGRA | WINCONx_BLD_PIX |
331 WINCONx_ALPHA_SEL;
332 val |= WINCONx_BURSTLEN_16WORD;
333 break;
334 default:
335 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
336
337 val |= WINCONx_BPPMODE_24BPP_xRGB;
338 val |= WINCONx_BURSTLEN_16WORD;
339 break;
340 }
341
7ee14cdc 342 DRM_DEBUG_KMS("bpp = %d\n", plane->bpp);
96976c3d
AK		 343
344 /*
345 * In case of exynos, setting dma-burst to 16Word causes permanent
346 * tearing for very small buffers, e.g. cursor buffer. Burst Mode
347 * switching which is based on plane size is not recommended as
348 * plane size varies a lot towards the end of the screen and rapid
349 * movement causes unstable DMA which results into iommu crash/tear.
350 */
351
7ee14cdc
GP		 352 padding = (plane->pitch / (plane->bpp >> 3)) - plane->fb_width;
353 if (plane->fb_width + padding < MIN_FB_WIDTH_FOR_16WORD_BURST) {
96976c3d
AK		 354 val &= ~WINCONx_BURSTLEN_MASK;
355 val |= WINCONx_BURSTLEN_8WORD;
356 }
357
358 writel(val, ctx->regs + WINCON(win));
359}
360
361static void decon_win_set_colkey(struct decon_context *ctx, unsigned int win)
362{
363 unsigned int keycon0 = 0, keycon1 = 0;
364
365 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
366 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
367
368 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
369
370 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
371 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
372}
373
374/**
375 * shadow_protect_win() - disable updating values from shadow registers at vsync
376 *
377 * @win: window to protect registers for
378 * @protect: 1 to protect (disable updates)
379 */
380static void decon_shadow_protect_win(struct decon_context *ctx,
6e2a3b66 381 unsigned int win, bool protect)
96976c3d
AK		 382{
383 u32 bits, val;
384
385 bits = SHADOWCON_WINx_PROTECT(win);
386
387 val = readl(ctx->regs + SHADOWCON);
388 if (protect)
389 val |= bits;
390 else
391 val &= ~bits;
392 writel(val, ctx->regs + SHADOWCON);
393}
394
6e2a3b66 395static void decon_win_commit(struct exynos_drm_crtc *crtc, unsigned int win)
96976c3d
AK		 396{
397 struct decon_context *ctx = crtc->ctx;
020e79de 398 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
7ee14cdc 399 struct exynos_drm_plane *plane;
6e2a3b66 400 int padding;
96976c3d
AK		 401 unsigned long val, alpha;
402 unsigned int last_x;
403 unsigned int last_y;
404
405 if (ctx->suspended)
406 return;
407
96976c3d
AK		 408 if (win < 0 || win >= WINDOWS_NR)
409 return;
410
7ee14cdc 411 plane = &ctx->planes[win];
96976c3d 412
c329f667 413 if (ctx->suspended)
96976c3d 414 return;
96976c3d
AK		 415
416 /*
417 * SHADOWCON/PRTCON register is used for enabling timing.
418 *
419 * for example, once only width value of a register is set,
420 * if the dma is started then decon hardware could malfunction so
421 * with protect window setting, the register fields with prefix '_F'
422 * wouldn't be updated at vsync also but updated once unprotect window
423 * is set.
424 */
425
426 /* protect windows */
427 decon_shadow_protect_win(ctx, win, true);
428
429 /* buffer start address */
7ee14cdc 430 val = (unsigned long)plane->dma_addr[0];
96976c3d
AK		 431 writel(val, ctx->regs + VIDW_BUF_START(win));
432
7ee14cdc
GP		 433 padding = (plane->pitch / (plane->bpp >> 3)) - plane->fb_width;
434
96976c3d 435 /* buffer size */
7ee14cdc
GP		 436 writel(plane->fb_width + padding, ctx->regs + VIDW_WHOLE_X(win));
437 writel(plane->fb_height, ctx->regs + VIDW_WHOLE_Y(win));
96976c3d
AK		 438
439 /* offset from the start of the buffer to read */
cb8a3db2
JS		 440 writel(plane->src_x, ctx->regs + VIDW_OFFSET_X(win));
441 writel(plane->src_y, ctx->regs + VIDW_OFFSET_Y(win));
96976c3d
AK		 442
443 DRM_DEBUG_KMS("start addr = 0x%lx\n",
7ee14cdc 444 (unsigned long)val);
96976c3d 445 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
7ee14cdc 446 plane->crtc_width, plane->crtc_height);
96976c3d
AK		 447
448 /*
449 * OSD position.
450 * In case the window layout goes of LCD layout, DECON fails.
451 */
7ee14cdc
GP		 452 if ((plane->crtc_x + plane->crtc_width) > mode->hdisplay)
453 plane->crtc_x = mode->hdisplay - plane->crtc_width;
454 if ((plane->crtc_y + plane->crtc_height) > mode->vdisplay)
455 plane->crtc_y = mode->vdisplay - plane->crtc_height;
96976c3d 456
7ee14cdc
GP		 457 val = VIDOSDxA_TOPLEFT_X(plane->crtc_x) |
458 VIDOSDxA_TOPLEFT_Y(plane->crtc_y);
96976c3d
AK		 459 writel(val, ctx->regs + VIDOSD_A(win));
460
7ee14cdc 461 last_x = plane->crtc_x + plane->crtc_width;
96976c3d
AK		 462 if (last_x)
463 last_x--;
7ee14cdc 464 last_y = plane->crtc_y + plane->crtc_height;
96976c3d
AK		 465 if (last_y)
466 last_y--;
467
468 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y);
469
470 writel(val, ctx->regs + VIDOSD_B(win));
471
472 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
7ee14cdc 473 plane->crtc_x, plane->crtc_y, last_x, last_y);
96976c3d
AK		 474
475 /* OSD alpha */
476 alpha = VIDOSDxC_ALPHA0_R_F(0x0) |
477 VIDOSDxC_ALPHA0_G_F(0x0) |
478 VIDOSDxC_ALPHA0_B_F(0x0);
479
480 writel(alpha, ctx->regs + VIDOSD_C(win));
481
482 alpha = VIDOSDxD_ALPHA1_R_F(0xff) |
483 VIDOSDxD_ALPHA1_G_F(0xff) |
484 VIDOSDxD_ALPHA1_B_F(0xff);
485
486 writel(alpha, ctx->regs + VIDOSD_D(win));
487
488 decon_win_set_pixfmt(ctx, win);
489
490 /* hardware window 0 doesn't support color key. */
491 if (win != 0)
492 decon_win_set_colkey(ctx, win);
493
494 /* wincon */
495 val = readl(ctx->regs + WINCON(win));
496 val |= WINCONx_TRIPLE_BUF_MODE;
497 val |= WINCONx_ENWIN;
498 writel(val, ctx->regs + WINCON(win));
499
500 /* Enable DMA channel and unprotect windows */
501 decon_shadow_protect_win(ctx, win, false);
502
503 val = readl(ctx->regs + DECON_UPDATE);
504 val |= DECON_UPDATE_STANDALONE_F;
505 writel(val, ctx->regs + DECON_UPDATE);
96976c3d
AK		 506}
507
6e2a3b66 508static void decon_win_disable(struct exynos_drm_crtc *crtc, unsigned int win)
96976c3d
AK		 509{
510 struct decon_context *ctx = crtc->ctx;
7ee14cdc 511 struct exynos_drm_plane *plane;
96976c3d
AK		 512 u32 val;
513
96976c3d
AK		 514 if (win < 0 || win >= WINDOWS_NR)
515 return;
516
7ee14cdc 517 plane = &ctx->planes[win];
96976c3d 518
c329f667 519 if (ctx->suspended)
96976c3d 520 return;
96976c3d
AK		 521
522 /* protect windows */
523 decon_shadow_protect_win(ctx, win, true);
524
525 /* wincon */
526 val = readl(ctx->regs + WINCON(win));
527 val &= ~WINCONx_ENWIN;
528 writel(val, ctx->regs + WINCON(win));
529
530 /* unprotect windows */
531 decon_shadow_protect_win(ctx, win, false);
532
533 val = readl(ctx->regs + DECON_UPDATE);
534 val |= DECON_UPDATE_STANDALONE_F;
535 writel(val, ctx->regs + DECON_UPDATE);
96976c3d
AK		 536}
537
538static void decon_init(struct decon_context *ctx)
539{
540 u32 val;
541
542 writel(VIDCON0_SWRESET, ctx->regs + VIDCON0);
543
544 val = VIDOUTCON0_DISP_IF_0_ON;
545 if (!ctx->i80_if)
546 val |= VIDOUTCON0_RGBIF;
547 writel(val, ctx->regs + VIDOUTCON0);
548
549 writel(VCLKCON0_CLKVALUP | VCLKCON0_VCLKFREE, ctx->regs + VCLKCON0);
550
551 if (!ctx->i80_if)
552 writel(VIDCON1_VCLK_HOLD, ctx->regs + VIDCON1(0));
553}
554
3cecda03 555static void decon_enable(struct exynos_drm_crtc *crtc)
96976c3d 556{
3cecda03 557 struct decon_context *ctx = crtc->ctx;
38000dbb 558 int ret;
96976c3d
AK		 559
560 if (!ctx->suspended)
3cecda03 561 return;
96976c3d
AK		 562
563 ctx->suspended = false;
564
565 pm_runtime_get_sync(ctx->dev);
566
38000dbb
GP		 567 ret = clk_prepare_enable(ctx->pclk);
568 if (ret < 0) {
569 DRM_ERROR("Failed to prepare_enable the pclk [%d]\n", ret);
570 return;
571 }
572
573 ret = clk_prepare_enable(ctx->aclk);
574 if (ret < 0) {
575 DRM_ERROR("Failed to prepare_enable the aclk [%d]\n", ret);
576 return;
577 }
578
579 ret = clk_prepare_enable(ctx->eclk);
580 if (ret < 0) {
581 DRM_ERROR("Failed to prepare_enable the eclk [%d]\n", ret);
582 return;
583 }
584
585 ret = clk_prepare_enable(ctx->vclk);
586 if (ret < 0) {
587 DRM_ERROR("Failed to prepare_enable the vclk [%d]\n", ret);
588 return;
589 }
96976c3d
AK		 590
591 decon_init(ctx);
592
593 /* if vblank was enabled status, enable it again. */
3cecda03
GP		 594 if (test_and_clear_bit(0, &ctx->irq_flags))
595 decon_enable_vblank(ctx->crtc);
96976c3d 596
c329f667 597 decon_commit(ctx->crtc);
96976c3d
AK		 598}
599
3cecda03 600static void decon_disable(struct exynos_drm_crtc *crtc)
96976c3d 601{
3cecda03 602 struct decon_context *ctx = crtc->ctx;
c329f667 603 int i;
3cecda03 604
96976c3d 605 if (ctx->suspended)
3cecda03 606 return;
96976c3d
AK		 607
608 /*
609 * We need to make sure that all windows are disabled before we
610 * suspend that connector. Otherwise we might try to scan from
611 * a destroyed buffer later.
612 */
c329f667
JS		 613 for (i = 0; i < WINDOWS_NR; i++)
614 decon_win_disable(crtc, i);
96976c3d
AK		 615
616 clk_disable_unprepare(ctx->vclk);
617 clk_disable_unprepare(ctx->eclk);
618 clk_disable_unprepare(ctx->aclk);
619 clk_disable_unprepare(ctx->pclk);
620
621 pm_runtime_put_sync(ctx->dev);
622
623 ctx->suspended = true;
96976c3d
AK		 624}
625
f3aaf762 626static const struct exynos_drm_crtc_ops decon_crtc_ops = {
3cecda03
GP		 627 .enable = decon_enable,
628 .disable = decon_disable,
96976c3d
AK		 629 .mode_fixup = decon_mode_fixup,
630 .commit = decon_commit,
631 .enable_vblank = decon_enable_vblank,
632 .disable_vblank = decon_disable_vblank,
633 .wait_for_vblank = decon_wait_for_vblank,
96976c3d
AK		 634 .win_commit = decon_win_commit,
635 .win_disable = decon_win_disable,
636};
637
638
639static irqreturn_t decon_irq_handler(int irq, void *dev_id)
640{
641 struct decon_context *ctx = (struct decon_context *)dev_id;
642 u32 val, clear_bit;
643
644 val = readl(ctx->regs + VIDINTCON1);
645
646 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
647 if (val & clear_bit)
648 writel(clear_bit, ctx->regs + VIDINTCON1);
649
650 /* check the crtc is detached already from encoder */
651 if (ctx->pipe < 0 || !ctx->drm_dev)
652 goto out;
653
654 if (!ctx->i80_if) {
655 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
656 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
657
658 /* set wait vsync event to zero and wake up queue. */
659 if (atomic_read(&ctx->wait_vsync_event)) {
660 atomic_set(&ctx->wait_vsync_event, 0);
661 wake_up(&ctx->wait_vsync_queue);
662 }
663 }
664out:
665 return IRQ_HANDLED;
666}
667
668static int decon_bind(struct device *dev, struct device *master, void *data)
669{
670 struct decon_context *ctx = dev_get_drvdata(dev);
671 struct drm_device *drm_dev = data;
7ee14cdc
GP		 672 struct exynos_drm_plane *exynos_plane;
673 enum drm_plane_type type;
6e2a3b66
GP		 674 unsigned int zpos;
675 int ret;
96976c3d
AK		 676
677 ret = decon_ctx_initialize(ctx, drm_dev);
678 if (ret) {
679 DRM_ERROR("decon_ctx_initialize failed.\n");
680 return ret;
681 }
682
7ee14cdc
GP		 683 for (zpos = 0; zpos < WINDOWS_NR; zpos++) {
684 type = (zpos == ctx->default_win) ? DRM_PLANE_TYPE_PRIMARY :
685 DRM_PLANE_TYPE_OVERLAY;
686 ret = exynos_plane_init(drm_dev, &ctx->planes[zpos],
6e2a3b66 687 1 << ctx->pipe, type, zpos);
7ee14cdc
GP		 688 if (ret)
689 return ret;
690 }
691
692 exynos_plane = &ctx->planes[ctx->default_win];
693 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
694 ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD,
96976c3d
AK		 695 &decon_crtc_ops, ctx);
696 if (IS_ERR(ctx->crtc)) {
697 decon_ctx_remove(ctx);
698 return PTR_ERR(ctx->crtc);
699 }
700
701 if (ctx->display)
702 exynos_drm_create_enc_conn(drm_dev, ctx->display);
703
704 return 0;
705
706}
707
708static void decon_unbind(struct device *dev, struct device *master,
709 void *data)
710{
711 struct decon_context *ctx = dev_get_drvdata(dev);
712
3cecda03 713 decon_disable(ctx->crtc);
96976c3d
AK		 714
715 if (ctx->display)
716 exynos_dpi_remove(ctx->display);
717
718 decon_ctx_remove(ctx);
719}
720
721static const struct component_ops decon_component_ops = {
722 .bind = decon_bind,
723 .unbind = decon_unbind,
724};
725
726static int decon_probe(struct platform_device *pdev)
727{
728 struct device *dev = &pdev->dev;
729 struct decon_context *ctx;
730 struct device_node *i80_if_timings;
731 struct resource *res;
732 int ret;
733
734 if (!dev->of_node)
735 return -ENODEV;
736
737 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
738 if (!ctx)
739 return -ENOMEM;
740
96976c3d
AK		 741 ctx->dev = dev;
742 ctx->suspended = true;
743
744 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
745 if (i80_if_timings)
746 ctx->i80_if = true;
747 of_node_put(i80_if_timings);
748
749 ctx->regs = of_iomap(dev->of_node, 0);
86650408
AH		 750 if (!ctx->regs)
751 return -ENOMEM;
96976c3d
AK		 752
753 ctx->pclk = devm_clk_get(dev, "pclk_decon0");
754 if (IS_ERR(ctx->pclk)) {
755 dev_err(dev, "failed to get bus clock pclk\n");
756 ret = PTR_ERR(ctx->pclk);
757 goto err_iounmap;
758 }
759
760 ctx->aclk = devm_clk_get(dev, "aclk_decon0");
761 if (IS_ERR(ctx->aclk)) {
762 dev_err(dev, "failed to get bus clock aclk\n");
763 ret = PTR_ERR(ctx->aclk);
764 goto err_iounmap;
765 }
766
767 ctx->eclk = devm_clk_get(dev, "decon0_eclk");
768 if (IS_ERR(ctx->eclk)) {
769 dev_err(dev, "failed to get eclock\n");
770 ret = PTR_ERR(ctx->eclk);
771 goto err_iounmap;
772 }
773
774 ctx->vclk = devm_clk_get(dev, "decon0_vclk");
775 if (IS_ERR(ctx->vclk)) {
776 dev_err(dev, "failed to get vclock\n");
777 ret = PTR_ERR(ctx->vclk);
778 goto err_iounmap;
779 }
780
781 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
782 ctx->i80_if ? "lcd_sys" : "vsync");
783 if (!res) {
784 dev_err(dev, "irq request failed.\n");
785 ret = -ENXIO;
786 goto err_iounmap;
787 }
788
789 ret = devm_request_irq(dev, res->start, decon_irq_handler,
790 0, "drm_decon", ctx);
791 if (ret) {
792 dev_err(dev, "irq request failed.\n");
793 goto err_iounmap;
794 }
795
796 init_waitqueue_head(&ctx->wait_vsync_queue);
797 atomic_set(&ctx->wait_vsync_event, 0);
798
799 platform_set_drvdata(pdev, ctx);
800
801 ctx->display = exynos_dpi_probe(dev);
802 if (IS_ERR(ctx->display)) {
803 ret = PTR_ERR(ctx->display);
804 goto err_iounmap;
805 }
806
807 pm_runtime_enable(dev);
808
809 ret = component_add(dev, &decon_component_ops);
810 if (ret)
811 goto err_disable_pm_runtime;
812
813 return ret;
814
815err_disable_pm_runtime:
816 pm_runtime_disable(dev);
817
818err_iounmap:
819 iounmap(ctx->regs);
820
96976c3d
AK		 821 return ret;
822}
823
824static int decon_remove(struct platform_device *pdev)
825{
826 struct decon_context *ctx = dev_get_drvdata(&pdev->dev);
827
828 pm_runtime_disable(&pdev->dev);
829
830 iounmap(ctx->regs);
831
832 component_del(&pdev->dev, &decon_component_ops);
96976c3d
AK		 833
834 return 0;
835}
836
837struct platform_driver decon_driver = {
838 .probe = decon_probe,
839 .remove = decon_remove,
840 .driver = {
841 .name = "exynos-decon",
842 .of_match_table = decon_driver_dt_match,
843 },
844};
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