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96976c3d AK |
1 | /* drivers/gpu/drm/exynos/exynos7_drm_decon.c |
2 | * | |
3 | * Copyright (C) 2014 Samsung Electronics Co.Ltd | |
4 | * Authors: | |
5 | * Akshu Agarwal <akshua@gmail.com> | |
6 | * Ajay Kumar <ajaykumar.rs@samsung.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | */ | |
14 | #include <drm/drmP.h> | |
15 | #include <drm/exynos_drm.h> | |
16 | ||
17 | #include <linux/clk.h> | |
18 | #include <linux/component.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/of.h> | |
21 | #include <linux/of_address.h> | |
22 | #include <linux/of_device.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/pm_runtime.h> | |
25 | ||
26 | #include <video/of_display_timing.h> | |
27 | #include <video/of_videomode.h> | |
28 | #include <video/exynos7_decon.h> | |
29 | ||
30 | #include "exynos_drm_crtc.h" | |
7ee14cdc | 31 | #include "exynos_drm_plane.h" |
96976c3d AK |
32 | #include "exynos_drm_drv.h" |
33 | #include "exynos_drm_fbdev.h" | |
34 | #include "exynos_drm_iommu.h" | |
35 | ||
36 | /* | |
37 | * DECON stands for Display and Enhancement controller. | |
38 | */ | |
39 | ||
40 | #define DECON_DEFAULT_FRAMERATE 60 | |
41 | #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 | |
42 | ||
43 | #define WINDOWS_NR 2 | |
44 | ||
96976c3d AK |
45 | struct decon_context { |
46 | struct device *dev; | |
47 | struct drm_device *drm_dev; | |
48 | struct exynos_drm_crtc *crtc; | |
7ee14cdc | 49 | struct exynos_drm_plane planes[WINDOWS_NR]; |
96976c3d AK |
50 | struct clk *pclk; |
51 | struct clk *aclk; | |
52 | struct clk *eclk; | |
53 | struct clk *vclk; | |
54 | void __iomem *regs; | |
96976c3d AK |
55 | unsigned int default_win; |
56 | unsigned long irq_flags; | |
57 | bool i80_if; | |
58 | bool suspended; | |
59 | int pipe; | |
60 | wait_queue_head_t wait_vsync_queue; | |
61 | atomic_t wait_vsync_event; | |
62 | ||
63 | struct exynos_drm_panel_info panel; | |
64 | struct exynos_drm_display *display; | |
65 | }; | |
66 | ||
67 | static const struct of_device_id decon_driver_dt_match[] = { | |
68 | {.compatible = "samsung,exynos7-decon"}, | |
69 | {}, | |
70 | }; | |
71 | MODULE_DEVICE_TABLE(of, decon_driver_dt_match); | |
72 | ||
73 | static void decon_wait_for_vblank(struct exynos_drm_crtc *crtc) | |
74 | { | |
75 | struct decon_context *ctx = crtc->ctx; | |
76 | ||
77 | if (ctx->suspended) | |
78 | return; | |
79 | ||
80 | atomic_set(&ctx->wait_vsync_event, 1); | |
81 | ||
82 | /* | |
83 | * wait for DECON to signal VSYNC interrupt or return after | |
84 | * timeout which is set to 50ms (refresh rate of 20). | |
85 | */ | |
86 | if (!wait_event_timeout(ctx->wait_vsync_queue, | |
87 | !atomic_read(&ctx->wait_vsync_event), | |
88 | HZ/20)) | |
89 | DRM_DEBUG_KMS("vblank wait timed out.\n"); | |
90 | } | |
91 | ||
fc2e013f | 92 | static void decon_clear_channels(struct exynos_drm_crtc *crtc) |
96976c3d | 93 | { |
fc2e013f | 94 | struct decon_context *ctx = crtc->ctx; |
5b1d5bc6 | 95 | unsigned int win, ch_enabled = 0; |
96976c3d AK |
96 | |
97 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
98 | ||
99 | /* Check if any channel is enabled. */ | |
100 | for (win = 0; win < WINDOWS_NR; win++) { | |
101 | u32 val = readl(ctx->regs + WINCON(win)); | |
102 | ||
103 | if (val & WINCONx_ENWIN) { | |
104 | val &= ~WINCONx_ENWIN; | |
105 | writel(val, ctx->regs + WINCON(win)); | |
106 | ch_enabled = 1; | |
107 | } | |
108 | } | |
109 | ||
110 | /* Wait for vsync, as disable channel takes effect at next vsync */ | |
111 | if (ch_enabled) { | |
112 | unsigned int state = ctx->suspended; | |
113 | ||
114 | ctx->suspended = 0; | |
115 | decon_wait_for_vblank(ctx->crtc); | |
116 | ctx->suspended = state; | |
117 | } | |
118 | } | |
119 | ||
120 | static int decon_ctx_initialize(struct decon_context *ctx, | |
121 | struct drm_device *drm_dev) | |
122 | { | |
123 | struct exynos_drm_private *priv = drm_dev->dev_private; | |
fc2e013f | 124 | int ret; |
96976c3d AK |
125 | |
126 | ctx->drm_dev = drm_dev; | |
127 | ctx->pipe = priv->pipe++; | |
128 | ||
fc2e013f HH |
129 | ret = drm_iommu_attach_device_if_possible(ctx->crtc, drm_dev, ctx->dev); |
130 | if (ret) | |
131 | priv->pipe--; | |
96976c3d | 132 | |
fc2e013f | 133 | return ret; |
96976c3d AK |
134 | } |
135 | ||
136 | static void decon_ctx_remove(struct decon_context *ctx) | |
137 | { | |
138 | /* detach this sub driver from iommu mapping if supported. */ | |
bf56608a | 139 | drm_iommu_detach_device(ctx->drm_dev, ctx->dev); |
96976c3d AK |
140 | } |
141 | ||
142 | static u32 decon_calc_clkdiv(struct decon_context *ctx, | |
143 | const struct drm_display_mode *mode) | |
144 | { | |
145 | unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh; | |
146 | u32 clkdiv; | |
147 | ||
148 | /* Find the clock divider value that gets us closest to ideal_clk */ | |
149 | clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk); | |
150 | ||
151 | return (clkdiv < 0x100) ? clkdiv : 0xff; | |
152 | } | |
153 | ||
154 | static bool decon_mode_fixup(struct exynos_drm_crtc *crtc, | |
155 | const struct drm_display_mode *mode, | |
156 | struct drm_display_mode *adjusted_mode) | |
157 | { | |
158 | if (adjusted_mode->vrefresh == 0) | |
159 | adjusted_mode->vrefresh = DECON_DEFAULT_FRAMERATE; | |
160 | ||
161 | return true; | |
162 | } | |
163 | ||
164 | static void decon_commit(struct exynos_drm_crtc *crtc) | |
165 | { | |
166 | struct decon_context *ctx = crtc->ctx; | |
020e79de | 167 | struct drm_display_mode *mode = &crtc->base.state->adjusted_mode; |
96976c3d AK |
168 | u32 val, clkdiv; |
169 | ||
170 | if (ctx->suspended) | |
171 | return; | |
172 | ||
173 | /* nothing to do if we haven't set the mode yet */ | |
174 | if (mode->htotal == 0 || mode->vtotal == 0) | |
175 | return; | |
176 | ||
177 | if (!ctx->i80_if) { | |
178 | int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd; | |
179 | /* setup vertical timing values. */ | |
180 | vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; | |
181 | vbpd = mode->crtc_vtotal - mode->crtc_vsync_end; | |
182 | vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay; | |
183 | ||
184 | val = VIDTCON0_VBPD(vbpd - 1) | VIDTCON0_VFPD(vfpd - 1); | |
185 | writel(val, ctx->regs + VIDTCON0); | |
186 | ||
187 | val = VIDTCON1_VSPW(vsync_len - 1); | |
188 | writel(val, ctx->regs + VIDTCON1); | |
189 | ||
190 | /* setup horizontal timing values. */ | |
191 | hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; | |
192 | hbpd = mode->crtc_htotal - mode->crtc_hsync_end; | |
193 | hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay; | |
194 | ||
195 | /* setup horizontal timing values. */ | |
196 | val = VIDTCON2_HBPD(hbpd - 1) | VIDTCON2_HFPD(hfpd - 1); | |
197 | writel(val, ctx->regs + VIDTCON2); | |
198 | ||
199 | val = VIDTCON3_HSPW(hsync_len - 1); | |
200 | writel(val, ctx->regs + VIDTCON3); | |
201 | } | |
202 | ||
203 | /* setup horizontal and vertical display size. */ | |
204 | val = VIDTCON4_LINEVAL(mode->vdisplay - 1) | | |
205 | VIDTCON4_HOZVAL(mode->hdisplay - 1); | |
206 | writel(val, ctx->regs + VIDTCON4); | |
207 | ||
208 | writel(mode->vdisplay - 1, ctx->regs + LINECNT_OP_THRESHOLD); | |
209 | ||
210 | /* | |
211 | * fields of register with prefix '_F' would be updated | |
212 | * at vsync(same as dma start) | |
213 | */ | |
214 | val = VIDCON0_ENVID | VIDCON0_ENVID_F; | |
215 | writel(val, ctx->regs + VIDCON0); | |
216 | ||
217 | clkdiv = decon_calc_clkdiv(ctx, mode); | |
218 | if (clkdiv > 1) { | |
219 | val = VCLKCON1_CLKVAL_NUM_VCLK(clkdiv - 1); | |
220 | writel(val, ctx->regs + VCLKCON1); | |
221 | writel(val, ctx->regs + VCLKCON2); | |
222 | } | |
223 | ||
224 | val = readl(ctx->regs + DECON_UPDATE); | |
225 | val |= DECON_UPDATE_STANDALONE_F; | |
226 | writel(val, ctx->regs + DECON_UPDATE); | |
227 | } | |
228 | ||
229 | static int decon_enable_vblank(struct exynos_drm_crtc *crtc) | |
230 | { | |
231 | struct decon_context *ctx = crtc->ctx; | |
232 | u32 val; | |
233 | ||
234 | if (ctx->suspended) | |
235 | return -EPERM; | |
236 | ||
237 | if (!test_and_set_bit(0, &ctx->irq_flags)) { | |
238 | val = readl(ctx->regs + VIDINTCON0); | |
239 | ||
240 | val |= VIDINTCON0_INT_ENABLE; | |
241 | ||
242 | if (!ctx->i80_if) { | |
243 | val |= VIDINTCON0_INT_FRAME; | |
244 | val &= ~VIDINTCON0_FRAMESEL0_MASK; | |
245 | val |= VIDINTCON0_FRAMESEL0_VSYNC; | |
246 | } | |
247 | ||
248 | writel(val, ctx->regs + VIDINTCON0); | |
249 | } | |
250 | ||
251 | return 0; | |
252 | } | |
253 | ||
254 | static void decon_disable_vblank(struct exynos_drm_crtc *crtc) | |
255 | { | |
256 | struct decon_context *ctx = crtc->ctx; | |
257 | u32 val; | |
258 | ||
259 | if (ctx->suspended) | |
260 | return; | |
261 | ||
262 | if (test_and_clear_bit(0, &ctx->irq_flags)) { | |
263 | val = readl(ctx->regs + VIDINTCON0); | |
264 | ||
265 | val &= ~VIDINTCON0_INT_ENABLE; | |
266 | if (!ctx->i80_if) | |
267 | val &= ~VIDINTCON0_INT_FRAME; | |
268 | ||
269 | writel(val, ctx->regs + VIDINTCON0); | |
270 | } | |
271 | } | |
272 | ||
96976c3d AK |
273 | static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win) |
274 | { | |
7ee14cdc | 275 | struct exynos_drm_plane *plane = &ctx->planes[win]; |
96976c3d | 276 | unsigned long val; |
7ee14cdc | 277 | int padding; |
96976c3d AK |
278 | |
279 | val = readl(ctx->regs + WINCON(win)); | |
280 | val &= ~WINCONx_BPPMODE_MASK; | |
281 | ||
7ee14cdc | 282 | switch (plane->pixel_format) { |
96976c3d AK |
283 | case DRM_FORMAT_RGB565: |
284 | val |= WINCONx_BPPMODE_16BPP_565; | |
285 | val |= WINCONx_BURSTLEN_16WORD; | |
286 | break; | |
287 | case DRM_FORMAT_XRGB8888: | |
288 | val |= WINCONx_BPPMODE_24BPP_xRGB; | |
289 | val |= WINCONx_BURSTLEN_16WORD; | |
290 | break; | |
291 | case DRM_FORMAT_XBGR8888: | |
292 | val |= WINCONx_BPPMODE_24BPP_xBGR; | |
293 | val |= WINCONx_BURSTLEN_16WORD; | |
294 | break; | |
295 | case DRM_FORMAT_RGBX8888: | |
296 | val |= WINCONx_BPPMODE_24BPP_RGBx; | |
297 | val |= WINCONx_BURSTLEN_16WORD; | |
298 | break; | |
299 | case DRM_FORMAT_BGRX8888: | |
300 | val |= WINCONx_BPPMODE_24BPP_BGRx; | |
301 | val |= WINCONx_BURSTLEN_16WORD; | |
302 | break; | |
303 | case DRM_FORMAT_ARGB8888: | |
304 | val |= WINCONx_BPPMODE_32BPP_ARGB | WINCONx_BLD_PIX | | |
305 | WINCONx_ALPHA_SEL; | |
306 | val |= WINCONx_BURSTLEN_16WORD; | |
307 | break; | |
308 | case DRM_FORMAT_ABGR8888: | |
309 | val |= WINCONx_BPPMODE_32BPP_ABGR | WINCONx_BLD_PIX | | |
310 | WINCONx_ALPHA_SEL; | |
311 | val |= WINCONx_BURSTLEN_16WORD; | |
312 | break; | |
313 | case DRM_FORMAT_RGBA8888: | |
314 | val |= WINCONx_BPPMODE_32BPP_RGBA | WINCONx_BLD_PIX | | |
315 | WINCONx_ALPHA_SEL; | |
316 | val |= WINCONx_BURSTLEN_16WORD; | |
317 | break; | |
318 | case DRM_FORMAT_BGRA8888: | |
319 | val |= WINCONx_BPPMODE_32BPP_BGRA | WINCONx_BLD_PIX | | |
320 | WINCONx_ALPHA_SEL; | |
321 | val |= WINCONx_BURSTLEN_16WORD; | |
322 | break; | |
323 | default: | |
324 | DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n"); | |
325 | ||
326 | val |= WINCONx_BPPMODE_24BPP_xRGB; | |
327 | val |= WINCONx_BURSTLEN_16WORD; | |
328 | break; | |
329 | } | |
330 | ||
7ee14cdc | 331 | DRM_DEBUG_KMS("bpp = %d\n", plane->bpp); |
96976c3d AK |
332 | |
333 | /* | |
334 | * In case of exynos, setting dma-burst to 16Word causes permanent | |
335 | * tearing for very small buffers, e.g. cursor buffer. Burst Mode | |
336 | * switching which is based on plane size is not recommended as | |
337 | * plane size varies a lot towards the end of the screen and rapid | |
338 | * movement causes unstable DMA which results into iommu crash/tear. | |
339 | */ | |
340 | ||
7ee14cdc GP |
341 | padding = (plane->pitch / (plane->bpp >> 3)) - plane->fb_width; |
342 | if (plane->fb_width + padding < MIN_FB_WIDTH_FOR_16WORD_BURST) { | |
96976c3d AK |
343 | val &= ~WINCONx_BURSTLEN_MASK; |
344 | val |= WINCONx_BURSTLEN_8WORD; | |
345 | } | |
346 | ||
347 | writel(val, ctx->regs + WINCON(win)); | |
348 | } | |
349 | ||
350 | static void decon_win_set_colkey(struct decon_context *ctx, unsigned int win) | |
351 | { | |
352 | unsigned int keycon0 = 0, keycon1 = 0; | |
353 | ||
354 | keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F | | |
355 | WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); | |
356 | ||
357 | keycon1 = WxKEYCON1_COLVAL(0xffffffff); | |
358 | ||
359 | writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); | |
360 | writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); | |
361 | } | |
362 | ||
363 | /** | |
364 | * shadow_protect_win() - disable updating values from shadow registers at vsync | |
365 | * | |
366 | * @win: window to protect registers for | |
367 | * @protect: 1 to protect (disable updates) | |
368 | */ | |
369 | static void decon_shadow_protect_win(struct decon_context *ctx, | |
6e2a3b66 | 370 | unsigned int win, bool protect) |
96976c3d AK |
371 | { |
372 | u32 bits, val; | |
373 | ||
374 | bits = SHADOWCON_WINx_PROTECT(win); | |
375 | ||
376 | val = readl(ctx->regs + SHADOWCON); | |
377 | if (protect) | |
378 | val |= bits; | |
379 | else | |
380 | val &= ~bits; | |
381 | writel(val, ctx->regs + SHADOWCON); | |
382 | } | |
383 | ||
6e2a3b66 | 384 | static void decon_win_commit(struct exynos_drm_crtc *crtc, unsigned int win) |
96976c3d AK |
385 | { |
386 | struct decon_context *ctx = crtc->ctx; | |
020e79de | 387 | struct drm_display_mode *mode = &crtc->base.state->adjusted_mode; |
7ee14cdc | 388 | struct exynos_drm_plane *plane; |
6e2a3b66 | 389 | int padding; |
96976c3d AK |
390 | unsigned long val, alpha; |
391 | unsigned int last_x; | |
392 | unsigned int last_y; | |
393 | ||
394 | if (ctx->suspended) | |
395 | return; | |
396 | ||
96976c3d AK |
397 | if (win < 0 || win >= WINDOWS_NR) |
398 | return; | |
399 | ||
7ee14cdc | 400 | plane = &ctx->planes[win]; |
96976c3d | 401 | |
c329f667 | 402 | if (ctx->suspended) |
96976c3d | 403 | return; |
96976c3d AK |
404 | |
405 | /* | |
406 | * SHADOWCON/PRTCON register is used for enabling timing. | |
407 | * | |
408 | * for example, once only width value of a register is set, | |
409 | * if the dma is started then decon hardware could malfunction so | |
410 | * with protect window setting, the register fields with prefix '_F' | |
411 | * wouldn't be updated at vsync also but updated once unprotect window | |
412 | * is set. | |
413 | */ | |
414 | ||
415 | /* protect windows */ | |
416 | decon_shadow_protect_win(ctx, win, true); | |
417 | ||
418 | /* buffer start address */ | |
7ee14cdc | 419 | val = (unsigned long)plane->dma_addr[0]; |
96976c3d AK |
420 | writel(val, ctx->regs + VIDW_BUF_START(win)); |
421 | ||
7ee14cdc GP |
422 | padding = (plane->pitch / (plane->bpp >> 3)) - plane->fb_width; |
423 | ||
96976c3d | 424 | /* buffer size */ |
7ee14cdc GP |
425 | writel(plane->fb_width + padding, ctx->regs + VIDW_WHOLE_X(win)); |
426 | writel(plane->fb_height, ctx->regs + VIDW_WHOLE_Y(win)); | |
96976c3d AK |
427 | |
428 | /* offset from the start of the buffer to read */ | |
cb8a3db2 JS |
429 | writel(plane->src_x, ctx->regs + VIDW_OFFSET_X(win)); |
430 | writel(plane->src_y, ctx->regs + VIDW_OFFSET_Y(win)); | |
96976c3d AK |
431 | |
432 | DRM_DEBUG_KMS("start addr = 0x%lx\n", | |
7ee14cdc | 433 | (unsigned long)val); |
96976c3d | 434 | DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", |
7ee14cdc | 435 | plane->crtc_width, plane->crtc_height); |
96976c3d AK |
436 | |
437 | /* | |
438 | * OSD position. | |
439 | * In case the window layout goes of LCD layout, DECON fails. | |
440 | */ | |
7ee14cdc GP |
441 | if ((plane->crtc_x + plane->crtc_width) > mode->hdisplay) |
442 | plane->crtc_x = mode->hdisplay - plane->crtc_width; | |
443 | if ((plane->crtc_y + plane->crtc_height) > mode->vdisplay) | |
444 | plane->crtc_y = mode->vdisplay - plane->crtc_height; | |
96976c3d | 445 | |
7ee14cdc GP |
446 | val = VIDOSDxA_TOPLEFT_X(plane->crtc_x) | |
447 | VIDOSDxA_TOPLEFT_Y(plane->crtc_y); | |
96976c3d AK |
448 | writel(val, ctx->regs + VIDOSD_A(win)); |
449 | ||
7ee14cdc | 450 | last_x = plane->crtc_x + plane->crtc_width; |
96976c3d AK |
451 | if (last_x) |
452 | last_x--; | |
7ee14cdc | 453 | last_y = plane->crtc_y + plane->crtc_height; |
96976c3d AK |
454 | if (last_y) |
455 | last_y--; | |
456 | ||
457 | val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y); | |
458 | ||
459 | writel(val, ctx->regs + VIDOSD_B(win)); | |
460 | ||
461 | DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", | |
7ee14cdc | 462 | plane->crtc_x, plane->crtc_y, last_x, last_y); |
96976c3d AK |
463 | |
464 | /* OSD alpha */ | |
465 | alpha = VIDOSDxC_ALPHA0_R_F(0x0) | | |
466 | VIDOSDxC_ALPHA0_G_F(0x0) | | |
467 | VIDOSDxC_ALPHA0_B_F(0x0); | |
468 | ||
469 | writel(alpha, ctx->regs + VIDOSD_C(win)); | |
470 | ||
471 | alpha = VIDOSDxD_ALPHA1_R_F(0xff) | | |
472 | VIDOSDxD_ALPHA1_G_F(0xff) | | |
473 | VIDOSDxD_ALPHA1_B_F(0xff); | |
474 | ||
475 | writel(alpha, ctx->regs + VIDOSD_D(win)); | |
476 | ||
477 | decon_win_set_pixfmt(ctx, win); | |
478 | ||
479 | /* hardware window 0 doesn't support color key. */ | |
480 | if (win != 0) | |
481 | decon_win_set_colkey(ctx, win); | |
482 | ||
483 | /* wincon */ | |
484 | val = readl(ctx->regs + WINCON(win)); | |
485 | val |= WINCONx_TRIPLE_BUF_MODE; | |
486 | val |= WINCONx_ENWIN; | |
487 | writel(val, ctx->regs + WINCON(win)); | |
488 | ||
489 | /* Enable DMA channel and unprotect windows */ | |
490 | decon_shadow_protect_win(ctx, win, false); | |
491 | ||
492 | val = readl(ctx->regs + DECON_UPDATE); | |
493 | val |= DECON_UPDATE_STANDALONE_F; | |
494 | writel(val, ctx->regs + DECON_UPDATE); | |
96976c3d AK |
495 | } |
496 | ||
6e2a3b66 | 497 | static void decon_win_disable(struct exynos_drm_crtc *crtc, unsigned int win) |
96976c3d AK |
498 | { |
499 | struct decon_context *ctx = crtc->ctx; | |
7ee14cdc | 500 | struct exynos_drm_plane *plane; |
96976c3d AK |
501 | u32 val; |
502 | ||
96976c3d AK |
503 | if (win < 0 || win >= WINDOWS_NR) |
504 | return; | |
505 | ||
7ee14cdc | 506 | plane = &ctx->planes[win]; |
96976c3d | 507 | |
c329f667 | 508 | if (ctx->suspended) |
96976c3d | 509 | return; |
96976c3d AK |
510 | |
511 | /* protect windows */ | |
512 | decon_shadow_protect_win(ctx, win, true); | |
513 | ||
514 | /* wincon */ | |
515 | val = readl(ctx->regs + WINCON(win)); | |
516 | val &= ~WINCONx_ENWIN; | |
517 | writel(val, ctx->regs + WINCON(win)); | |
518 | ||
519 | /* unprotect windows */ | |
520 | decon_shadow_protect_win(ctx, win, false); | |
521 | ||
522 | val = readl(ctx->regs + DECON_UPDATE); | |
523 | val |= DECON_UPDATE_STANDALONE_F; | |
524 | writel(val, ctx->regs + DECON_UPDATE); | |
96976c3d AK |
525 | } |
526 | ||
527 | static void decon_init(struct decon_context *ctx) | |
528 | { | |
529 | u32 val; | |
530 | ||
531 | writel(VIDCON0_SWRESET, ctx->regs + VIDCON0); | |
532 | ||
533 | val = VIDOUTCON0_DISP_IF_0_ON; | |
534 | if (!ctx->i80_if) | |
535 | val |= VIDOUTCON0_RGBIF; | |
536 | writel(val, ctx->regs + VIDOUTCON0); | |
537 | ||
538 | writel(VCLKCON0_CLKVALUP | VCLKCON0_VCLKFREE, ctx->regs + VCLKCON0); | |
539 | ||
540 | if (!ctx->i80_if) | |
541 | writel(VIDCON1_VCLK_HOLD, ctx->regs + VIDCON1(0)); | |
542 | } | |
543 | ||
3cecda03 | 544 | static void decon_enable(struct exynos_drm_crtc *crtc) |
96976c3d | 545 | { |
3cecda03 | 546 | struct decon_context *ctx = crtc->ctx; |
38000dbb | 547 | int ret; |
96976c3d AK |
548 | |
549 | if (!ctx->suspended) | |
3cecda03 | 550 | return; |
96976c3d AK |
551 | |
552 | ctx->suspended = false; | |
553 | ||
554 | pm_runtime_get_sync(ctx->dev); | |
555 | ||
38000dbb GP |
556 | ret = clk_prepare_enable(ctx->pclk); |
557 | if (ret < 0) { | |
558 | DRM_ERROR("Failed to prepare_enable the pclk [%d]\n", ret); | |
559 | return; | |
560 | } | |
561 | ||
562 | ret = clk_prepare_enable(ctx->aclk); | |
563 | if (ret < 0) { | |
564 | DRM_ERROR("Failed to prepare_enable the aclk [%d]\n", ret); | |
565 | return; | |
566 | } | |
567 | ||
568 | ret = clk_prepare_enable(ctx->eclk); | |
569 | if (ret < 0) { | |
570 | DRM_ERROR("Failed to prepare_enable the eclk [%d]\n", ret); | |
571 | return; | |
572 | } | |
573 | ||
574 | ret = clk_prepare_enable(ctx->vclk); | |
575 | if (ret < 0) { | |
576 | DRM_ERROR("Failed to prepare_enable the vclk [%d]\n", ret); | |
577 | return; | |
578 | } | |
96976c3d AK |
579 | |
580 | decon_init(ctx); | |
581 | ||
582 | /* if vblank was enabled status, enable it again. */ | |
3cecda03 GP |
583 | if (test_and_clear_bit(0, &ctx->irq_flags)) |
584 | decon_enable_vblank(ctx->crtc); | |
96976c3d | 585 | |
c329f667 | 586 | decon_commit(ctx->crtc); |
96976c3d AK |
587 | } |
588 | ||
3cecda03 | 589 | static void decon_disable(struct exynos_drm_crtc *crtc) |
96976c3d | 590 | { |
3cecda03 | 591 | struct decon_context *ctx = crtc->ctx; |
c329f667 | 592 | int i; |
3cecda03 | 593 | |
96976c3d | 594 | if (ctx->suspended) |
3cecda03 | 595 | return; |
96976c3d AK |
596 | |
597 | /* | |
598 | * We need to make sure that all windows are disabled before we | |
599 | * suspend that connector. Otherwise we might try to scan from | |
600 | * a destroyed buffer later. | |
601 | */ | |
c329f667 JS |
602 | for (i = 0; i < WINDOWS_NR; i++) |
603 | decon_win_disable(crtc, i); | |
96976c3d AK |
604 | |
605 | clk_disable_unprepare(ctx->vclk); | |
606 | clk_disable_unprepare(ctx->eclk); | |
607 | clk_disable_unprepare(ctx->aclk); | |
608 | clk_disable_unprepare(ctx->pclk); | |
609 | ||
610 | pm_runtime_put_sync(ctx->dev); | |
611 | ||
612 | ctx->suspended = true; | |
96976c3d AK |
613 | } |
614 | ||
f3aaf762 | 615 | static const struct exynos_drm_crtc_ops decon_crtc_ops = { |
3cecda03 GP |
616 | .enable = decon_enable, |
617 | .disable = decon_disable, | |
96976c3d AK |
618 | .mode_fixup = decon_mode_fixup, |
619 | .commit = decon_commit, | |
620 | .enable_vblank = decon_enable_vblank, | |
621 | .disable_vblank = decon_disable_vblank, | |
622 | .wait_for_vblank = decon_wait_for_vblank, | |
96976c3d AK |
623 | .win_commit = decon_win_commit, |
624 | .win_disable = decon_win_disable, | |
fc2e013f | 625 | .clear_channels = decon_clear_channels, |
96976c3d AK |
626 | }; |
627 | ||
628 | ||
629 | static irqreturn_t decon_irq_handler(int irq, void *dev_id) | |
630 | { | |
631 | struct decon_context *ctx = (struct decon_context *)dev_id; | |
632 | u32 val, clear_bit; | |
633 | ||
634 | val = readl(ctx->regs + VIDINTCON1); | |
635 | ||
636 | clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME; | |
637 | if (val & clear_bit) | |
638 | writel(clear_bit, ctx->regs + VIDINTCON1); | |
639 | ||
640 | /* check the crtc is detached already from encoder */ | |
641 | if (ctx->pipe < 0 || !ctx->drm_dev) | |
642 | goto out; | |
643 | ||
644 | if (!ctx->i80_if) { | |
645 | drm_handle_vblank(ctx->drm_dev, ctx->pipe); | |
646 | exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe); | |
647 | ||
648 | /* set wait vsync event to zero and wake up queue. */ | |
649 | if (atomic_read(&ctx->wait_vsync_event)) { | |
650 | atomic_set(&ctx->wait_vsync_event, 0); | |
651 | wake_up(&ctx->wait_vsync_queue); | |
652 | } | |
653 | } | |
654 | out: | |
655 | return IRQ_HANDLED; | |
656 | } | |
657 | ||
658 | static int decon_bind(struct device *dev, struct device *master, void *data) | |
659 | { | |
660 | struct decon_context *ctx = dev_get_drvdata(dev); | |
661 | struct drm_device *drm_dev = data; | |
7ee14cdc GP |
662 | struct exynos_drm_plane *exynos_plane; |
663 | enum drm_plane_type type; | |
6e2a3b66 GP |
664 | unsigned int zpos; |
665 | int ret; | |
96976c3d AK |
666 | |
667 | ret = decon_ctx_initialize(ctx, drm_dev); | |
668 | if (ret) { | |
669 | DRM_ERROR("decon_ctx_initialize failed.\n"); | |
670 | return ret; | |
671 | } | |
672 | ||
7ee14cdc GP |
673 | for (zpos = 0; zpos < WINDOWS_NR; zpos++) { |
674 | type = (zpos == ctx->default_win) ? DRM_PLANE_TYPE_PRIMARY : | |
675 | DRM_PLANE_TYPE_OVERLAY; | |
676 | ret = exynos_plane_init(drm_dev, &ctx->planes[zpos], | |
6e2a3b66 | 677 | 1 << ctx->pipe, type, zpos); |
7ee14cdc GP |
678 | if (ret) |
679 | return ret; | |
680 | } | |
681 | ||
682 | exynos_plane = &ctx->planes[ctx->default_win]; | |
683 | ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, | |
684 | ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD, | |
96976c3d AK |
685 | &decon_crtc_ops, ctx); |
686 | if (IS_ERR(ctx->crtc)) { | |
687 | decon_ctx_remove(ctx); | |
688 | return PTR_ERR(ctx->crtc); | |
689 | } | |
690 | ||
691 | if (ctx->display) | |
692 | exynos_drm_create_enc_conn(drm_dev, ctx->display); | |
693 | ||
694 | return 0; | |
695 | ||
696 | } | |
697 | ||
698 | static void decon_unbind(struct device *dev, struct device *master, | |
699 | void *data) | |
700 | { | |
701 | struct decon_context *ctx = dev_get_drvdata(dev); | |
702 | ||
3cecda03 | 703 | decon_disable(ctx->crtc); |
96976c3d AK |
704 | |
705 | if (ctx->display) | |
706 | exynos_dpi_remove(ctx->display); | |
707 | ||
708 | decon_ctx_remove(ctx); | |
709 | } | |
710 | ||
711 | static const struct component_ops decon_component_ops = { | |
712 | .bind = decon_bind, | |
713 | .unbind = decon_unbind, | |
714 | }; | |
715 | ||
716 | static int decon_probe(struct platform_device *pdev) | |
717 | { | |
718 | struct device *dev = &pdev->dev; | |
719 | struct decon_context *ctx; | |
720 | struct device_node *i80_if_timings; | |
721 | struct resource *res; | |
722 | int ret; | |
723 | ||
724 | if (!dev->of_node) | |
725 | return -ENODEV; | |
726 | ||
727 | ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); | |
728 | if (!ctx) | |
729 | return -ENOMEM; | |
730 | ||
96976c3d AK |
731 | ctx->dev = dev; |
732 | ctx->suspended = true; | |
733 | ||
734 | i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings"); | |
735 | if (i80_if_timings) | |
736 | ctx->i80_if = true; | |
737 | of_node_put(i80_if_timings); | |
738 | ||
739 | ctx->regs = of_iomap(dev->of_node, 0); | |
86650408 AH |
740 | if (!ctx->regs) |
741 | return -ENOMEM; | |
96976c3d AK |
742 | |
743 | ctx->pclk = devm_clk_get(dev, "pclk_decon0"); | |
744 | if (IS_ERR(ctx->pclk)) { | |
745 | dev_err(dev, "failed to get bus clock pclk\n"); | |
746 | ret = PTR_ERR(ctx->pclk); | |
747 | goto err_iounmap; | |
748 | } | |
749 | ||
750 | ctx->aclk = devm_clk_get(dev, "aclk_decon0"); | |
751 | if (IS_ERR(ctx->aclk)) { | |
752 | dev_err(dev, "failed to get bus clock aclk\n"); | |
753 | ret = PTR_ERR(ctx->aclk); | |
754 | goto err_iounmap; | |
755 | } | |
756 | ||
757 | ctx->eclk = devm_clk_get(dev, "decon0_eclk"); | |
758 | if (IS_ERR(ctx->eclk)) { | |
759 | dev_err(dev, "failed to get eclock\n"); | |
760 | ret = PTR_ERR(ctx->eclk); | |
761 | goto err_iounmap; | |
762 | } | |
763 | ||
764 | ctx->vclk = devm_clk_get(dev, "decon0_vclk"); | |
765 | if (IS_ERR(ctx->vclk)) { | |
766 | dev_err(dev, "failed to get vclock\n"); | |
767 | ret = PTR_ERR(ctx->vclk); | |
768 | goto err_iounmap; | |
769 | } | |
770 | ||
771 | res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, | |
772 | ctx->i80_if ? "lcd_sys" : "vsync"); | |
773 | if (!res) { | |
774 | dev_err(dev, "irq request failed.\n"); | |
775 | ret = -ENXIO; | |
776 | goto err_iounmap; | |
777 | } | |
778 | ||
779 | ret = devm_request_irq(dev, res->start, decon_irq_handler, | |
780 | 0, "drm_decon", ctx); | |
781 | if (ret) { | |
782 | dev_err(dev, "irq request failed.\n"); | |
783 | goto err_iounmap; | |
784 | } | |
785 | ||
786 | init_waitqueue_head(&ctx->wait_vsync_queue); | |
787 | atomic_set(&ctx->wait_vsync_event, 0); | |
788 | ||
789 | platform_set_drvdata(pdev, ctx); | |
790 | ||
791 | ctx->display = exynos_dpi_probe(dev); | |
792 | if (IS_ERR(ctx->display)) { | |
793 | ret = PTR_ERR(ctx->display); | |
794 | goto err_iounmap; | |
795 | } | |
796 | ||
797 | pm_runtime_enable(dev); | |
798 | ||
799 | ret = component_add(dev, &decon_component_ops); | |
800 | if (ret) | |
801 | goto err_disable_pm_runtime; | |
802 | ||
803 | return ret; | |
804 | ||
805 | err_disable_pm_runtime: | |
806 | pm_runtime_disable(dev); | |
807 | ||
808 | err_iounmap: | |
809 | iounmap(ctx->regs); | |
810 | ||
96976c3d AK |
811 | return ret; |
812 | } | |
813 | ||
814 | static int decon_remove(struct platform_device *pdev) | |
815 | { | |
816 | struct decon_context *ctx = dev_get_drvdata(&pdev->dev); | |
817 | ||
818 | pm_runtime_disable(&pdev->dev); | |
819 | ||
820 | iounmap(ctx->regs); | |
821 | ||
822 | component_del(&pdev->dev, &decon_component_ops); | |
96976c3d AK |
823 | |
824 | return 0; | |
825 | } | |
826 | ||
827 | struct platform_driver decon_driver = { | |
828 | .probe = decon_probe, | |
829 | .remove = decon_remove, | |
830 | .driver = { | |
831 | .name = "exynos-decon", | |
832 | .of_match_table = decon_driver_dt_match, | |
833 | }, | |
834 | }; |