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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
7eb8f069 AH |
2 | /* |
3 | * Samsung SoC MIPI DSI Master driver. | |
4 | * | |
5 | * Copyright (c) 2014 Samsung Electronics Co., Ltd | |
6 | * | |
7 | * Contacts: Tomasz Figa <t.figa@samsung.com> | |
7eb8f069 AH |
8 | */ |
9 | ||
7eb8f069 | 10 | #include <linux/clk.h> |
2bda34d7 SR |
11 | #include <linux/delay.h> |
12 | #include <linux/component.h> | |
e17ddecc | 13 | #include <linux/gpio/consumer.h> |
7eb8f069 | 14 | #include <linux/irq.h> |
9a320415 | 15 | #include <linux/of_device.h> |
e17ddecc | 16 | #include <linux/of_gpio.h> |
f5f3b9ba | 17 | #include <linux/of_graph.h> |
7eb8f069 AH |
18 | #include <linux/phy/phy.h> |
19 | #include <linux/regulator/consumer.h> | |
2bda34d7 SR |
20 | |
21 | #include <asm/unaligned.h> | |
7eb8f069 AH |
22 | |
23 | #include <video/mipi_display.h> | |
24 | #include <video/videomode.h> | |
25 | ||
2bda34d7 | 26 | #include <drm/drm_atomic_helper.h> |
ee68c743 | 27 | #include <drm/drm_bridge.h> |
2bda34d7 SR |
28 | #include <drm/drm_fb_helper.h> |
29 | #include <drm/drm_mipi_dsi.h> | |
30 | #include <drm/drm_panel.h> | |
31 | #include <drm/drm_print.h> | |
32 | #include <drm/drm_probe_helper.h> | |
33 | ||
e17ddecc | 34 | #include "exynos_drm_crtc.h" |
7eb8f069 AH |
35 | #include "exynos_drm_drv.h" |
36 | ||
37 | /* returns true iff both arguments logically differs */ | |
38 | #define NEQV(a, b) (!(a) ^ !(b)) | |
39 | ||
7eb8f069 AH |
40 | /* DSIM_STATUS */ |
41 | #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0) | |
42 | #define DSIM_STOP_STATE_CLK (1 << 8) | |
43 | #define DSIM_TX_READY_HS_CLK (1 << 10) | |
44 | #define DSIM_PLL_STABLE (1 << 31) | |
45 | ||
46 | /* DSIM_SWRST */ | |
47 | #define DSIM_FUNCRST (1 << 16) | |
48 | #define DSIM_SWRST (1 << 0) | |
49 | ||
50 | /* DSIM_TIMEOUT */ | |
51 | #define DSIM_LPDR_TIMEOUT(x) ((x) << 0) | |
52 | #define DSIM_BTA_TIMEOUT(x) ((x) << 16) | |
53 | ||
54 | /* DSIM_CLKCTRL */ | |
55 | #define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0) | |
56 | #define DSIM_ESC_PRESCALER_MASK (0xffff << 0) | |
57 | #define DSIM_LANE_ESC_CLK_EN_CLK (1 << 19) | |
58 | #define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20) | |
59 | #define DSIM_LANE_ESC_CLK_EN_DATA_MASK (0xf << 20) | |
60 | #define DSIM_BYTE_CLKEN (1 << 24) | |
61 | #define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25) | |
62 | #define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25) | |
63 | #define DSIM_PLL_BYPASS (1 << 27) | |
64 | #define DSIM_ESC_CLKEN (1 << 28) | |
65 | #define DSIM_TX_REQUEST_HSCLK (1 << 31) | |
66 | ||
67 | /* DSIM_CONFIG */ | |
68 | #define DSIM_LANE_EN_CLK (1 << 0) | |
69 | #define DSIM_LANE_EN(x) (((x) & 0xf) << 1) | |
70 | #define DSIM_NUM_OF_DATA_LANE(x) (((x) & 0x3) << 5) | |
71 | #define DSIM_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8) | |
72 | #define DSIM_MAIN_PIX_FORMAT_MASK (0x7 << 12) | |
73 | #define DSIM_MAIN_PIX_FORMAT_RGB888 (0x7 << 12) | |
74 | #define DSIM_MAIN_PIX_FORMAT_RGB666 (0x6 << 12) | |
75 | #define DSIM_MAIN_PIX_FORMAT_RGB666_P (0x5 << 12) | |
76 | #define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12) | |
77 | #define DSIM_SUB_VC (((x) & 0x3) << 16) | |
78 | #define DSIM_MAIN_VC (((x) & 0x3) << 18) | |
79 | #define DSIM_HSA_MODE (1 << 20) | |
80 | #define DSIM_HBP_MODE (1 << 21) | |
81 | #define DSIM_HFP_MODE (1 << 22) | |
82 | #define DSIM_HSE_MODE (1 << 23) | |
83 | #define DSIM_AUTO_MODE (1 << 24) | |
84 | #define DSIM_VIDEO_MODE (1 << 25) | |
85 | #define DSIM_BURST_MODE (1 << 26) | |
86 | #define DSIM_SYNC_INFORM (1 << 27) | |
87 | #define DSIM_EOT_DISABLE (1 << 28) | |
88 | #define DSIM_MFLUSH_VS (1 << 29) | |
6bdc92ee | 89 | /* This flag is valid only for exynos3250/3472/5260/5430 */ |
78d3a8c6 | 90 | #define DSIM_CLKLANE_STOP (1 << 30) |
7eb8f069 AH |
91 | |
92 | /* DSIM_ESCMODE */ | |
93 | #define DSIM_TX_TRIGGER_RST (1 << 4) | |
94 | #define DSIM_TX_LPDT_LP (1 << 6) | |
95 | #define DSIM_CMD_LPDT_LP (1 << 7) | |
96 | #define DSIM_FORCE_BTA (1 << 16) | |
97 | #define DSIM_FORCE_STOP_STATE (1 << 20) | |
98 | #define DSIM_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21) | |
99 | #define DSIM_STOP_STATE_CNT_MASK (0x7ff << 21) | |
100 | ||
101 | /* DSIM_MDRESOL */ | |
102 | #define DSIM_MAIN_STAND_BY (1 << 31) | |
d668e8bf HH |
103 | #define DSIM_MAIN_VRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 16) |
104 | #define DSIM_MAIN_HRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 0) | |
7eb8f069 AH |
105 | |
106 | /* DSIM_MVPORCH */ | |
107 | #define DSIM_CMD_ALLOW(x) ((x) << 28) | |
108 | #define DSIM_STABLE_VFP(x) ((x) << 16) | |
109 | #define DSIM_MAIN_VBP(x) ((x) << 0) | |
110 | #define DSIM_CMD_ALLOW_MASK (0xf << 28) | |
111 | #define DSIM_STABLE_VFP_MASK (0x7ff << 16) | |
112 | #define DSIM_MAIN_VBP_MASK (0x7ff << 0) | |
113 | ||
114 | /* DSIM_MHPORCH */ | |
115 | #define DSIM_MAIN_HFP(x) ((x) << 16) | |
116 | #define DSIM_MAIN_HBP(x) ((x) << 0) | |
117 | #define DSIM_MAIN_HFP_MASK ((0xffff) << 16) | |
118 | #define DSIM_MAIN_HBP_MASK ((0xffff) << 0) | |
119 | ||
120 | /* DSIM_MSYNC */ | |
121 | #define DSIM_MAIN_VSA(x) ((x) << 22) | |
122 | #define DSIM_MAIN_HSA(x) ((x) << 0) | |
123 | #define DSIM_MAIN_VSA_MASK ((0x3ff) << 22) | |
124 | #define DSIM_MAIN_HSA_MASK ((0xffff) << 0) | |
125 | ||
126 | /* DSIM_SDRESOL */ | |
127 | #define DSIM_SUB_STANDY(x) ((x) << 31) | |
128 | #define DSIM_SUB_VRESOL(x) ((x) << 16) | |
129 | #define DSIM_SUB_HRESOL(x) ((x) << 0) | |
130 | #define DSIM_SUB_STANDY_MASK ((0x1) << 31) | |
131 | #define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16) | |
132 | #define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0) | |
133 | ||
134 | /* DSIM_INTSRC */ | |
135 | #define DSIM_INT_PLL_STABLE (1 << 31) | |
136 | #define DSIM_INT_SW_RST_RELEASE (1 << 30) | |
137 | #define DSIM_INT_SFR_FIFO_EMPTY (1 << 29) | |
e6f988a4 | 138 | #define DSIM_INT_SFR_HDR_FIFO_EMPTY (1 << 28) |
7eb8f069 AH |
139 | #define DSIM_INT_BTA (1 << 25) |
140 | #define DSIM_INT_FRAME_DONE (1 << 24) | |
141 | #define DSIM_INT_RX_TIMEOUT (1 << 21) | |
142 | #define DSIM_INT_BTA_TIMEOUT (1 << 20) | |
143 | #define DSIM_INT_RX_DONE (1 << 18) | |
144 | #define DSIM_INT_RX_TE (1 << 17) | |
145 | #define DSIM_INT_RX_ACK (1 << 16) | |
146 | #define DSIM_INT_RX_ECC_ERR (1 << 15) | |
147 | #define DSIM_INT_RX_CRC_ERR (1 << 14) | |
148 | ||
149 | /* DSIM_FIFOCTRL */ | |
150 | #define DSIM_RX_DATA_FULL (1 << 25) | |
151 | #define DSIM_RX_DATA_EMPTY (1 << 24) | |
152 | #define DSIM_SFR_HEADER_FULL (1 << 23) | |
153 | #define DSIM_SFR_HEADER_EMPTY (1 << 22) | |
154 | #define DSIM_SFR_PAYLOAD_FULL (1 << 21) | |
155 | #define DSIM_SFR_PAYLOAD_EMPTY (1 << 20) | |
156 | #define DSIM_I80_HEADER_FULL (1 << 19) | |
157 | #define DSIM_I80_HEADER_EMPTY (1 << 18) | |
158 | #define DSIM_I80_PAYLOAD_FULL (1 << 17) | |
159 | #define DSIM_I80_PAYLOAD_EMPTY (1 << 16) | |
160 | #define DSIM_SD_HEADER_FULL (1 << 15) | |
161 | #define DSIM_SD_HEADER_EMPTY (1 << 14) | |
162 | #define DSIM_SD_PAYLOAD_FULL (1 << 13) | |
163 | #define DSIM_SD_PAYLOAD_EMPTY (1 << 12) | |
164 | #define DSIM_MD_HEADER_FULL (1 << 11) | |
165 | #define DSIM_MD_HEADER_EMPTY (1 << 10) | |
166 | #define DSIM_MD_PAYLOAD_FULL (1 << 9) | |
167 | #define DSIM_MD_PAYLOAD_EMPTY (1 << 8) | |
168 | #define DSIM_RX_FIFO (1 << 4) | |
169 | #define DSIM_SFR_FIFO (1 << 3) | |
170 | #define DSIM_I80_FIFO (1 << 2) | |
171 | #define DSIM_SD_FIFO (1 << 1) | |
172 | #define DSIM_MD_FIFO (1 << 0) | |
173 | ||
174 | /* DSIM_PHYACCHR */ | |
175 | #define DSIM_AFC_EN (1 << 14) | |
176 | #define DSIM_AFC_CTL(x) (((x) & 0x7) << 5) | |
177 | ||
178 | /* DSIM_PLLCTRL */ | |
179 | #define DSIM_FREQ_BAND(x) ((x) << 24) | |
180 | #define DSIM_PLL_EN (1 << 23) | |
181 | #define DSIM_PLL_P(x) ((x) << 13) | |
182 | #define DSIM_PLL_M(x) ((x) << 4) | |
183 | #define DSIM_PLL_S(x) ((x) << 1) | |
184 | ||
9a320415 YC |
185 | /* DSIM_PHYCTRL */ |
186 | #define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) & 0x1ff) << 0) | |
e6f988a4 HH |
187 | #define DSIM_PHYCTRL_B_DPHYCTL_VREG_LP (1 << 30) |
188 | #define DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP (1 << 14) | |
9a320415 YC |
189 | |
190 | /* DSIM_PHYTIMING */ | |
191 | #define DSIM_PHYTIMING_LPX(x) ((x) << 8) | |
192 | #define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0) | |
193 | ||
194 | /* DSIM_PHYTIMING1 */ | |
195 | #define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24) | |
196 | #define DSIM_PHYTIMING1_CLK_ZERO(x) ((x) << 16) | |
197 | #define DSIM_PHYTIMING1_CLK_POST(x) ((x) << 8) | |
198 | #define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0) | |
199 | ||
200 | /* DSIM_PHYTIMING2 */ | |
201 | #define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16) | |
202 | #define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8) | |
203 | #define DSIM_PHYTIMING2_HS_TRAIL(x) ((x) << 0) | |
204 | ||
7eb8f069 AH |
205 | #define DSI_MAX_BUS_WIDTH 4 |
206 | #define DSI_NUM_VIRTUAL_CHANNELS 4 | |
207 | #define DSI_TX_FIFO_SIZE 2048 | |
208 | #define DSI_RX_FIFO_SIZE 256 | |
209 | #define DSI_XFER_TIMEOUT_MS 100 | |
210 | #define DSI_RX_FIFO_EMPTY 0x30800002 | |
211 | ||
26269af9 HH |
212 | #define OLD_SCLK_MIPI_CLK_NAME "pll_clk" |
213 | ||
e6f988a4 HH |
214 | static char *clk_names[5] = { "bus_clk", "sclk_mipi", |
215 | "phyclk_mipidphy0_bitclkdiv8", "phyclk_mipidphy0_rxclkesc0", | |
216 | "sclk_rgb_vclk_to_dsim0" }; | |
0ff03fd1 | 217 | |
7eb8f069 AH |
218 | enum exynos_dsi_transfer_type { |
219 | EXYNOS_DSI_TX, | |
220 | EXYNOS_DSI_RX, | |
221 | }; | |
222 | ||
223 | struct exynos_dsi_transfer { | |
224 | struct list_head list; | |
225 | struct completion completed; | |
226 | int result; | |
6c81e96d | 227 | struct mipi_dsi_packet packet; |
7eb8f069 | 228 | u16 flags; |
7eb8f069 AH |
229 | u16 tx_done; |
230 | ||
231 | u8 *rx_payload; | |
232 | u16 rx_len; | |
233 | u16 rx_done; | |
234 | }; | |
235 | ||
236 | #define DSIM_STATE_ENABLED BIT(0) | |
237 | #define DSIM_STATE_INITIALIZED BIT(1) | |
238 | #define DSIM_STATE_CMD_LPM BIT(2) | |
0e480f6f | 239 | #define DSIM_STATE_VIDOUT_AVAILABLE BIT(3) |
7eb8f069 | 240 | |
9a320415 | 241 | struct exynos_dsi_driver_data { |
b115361e | 242 | const unsigned int *reg_ofs; |
9a320415 | 243 | unsigned int plltmr_reg; |
9a320415 | 244 | unsigned int has_freqband:1; |
78d3a8c6 | 245 | unsigned int has_clklane_stop:1; |
d668e8bf HH |
246 | unsigned int num_clks; |
247 | unsigned int max_freq; | |
248 | unsigned int wait_for_reset; | |
249 | unsigned int num_bits_resol; | |
b115361e | 250 | const unsigned int *reg_values; |
9a320415 YC |
251 | }; |
252 | ||
7eb8f069 | 253 | struct exynos_dsi { |
2b8376c8 | 254 | struct drm_encoder encoder; |
7eb8f069 AH |
255 | struct mipi_dsi_host dsi_host; |
256 | struct drm_connector connector; | |
7eb8f069 | 257 | struct drm_panel *panel; |
05193dc3 | 258 | struct list_head bridge_chain; |
6afb7721 | 259 | struct drm_bridge *out_bridge; |
7eb8f069 AH |
260 | struct device *dev; |
261 | ||
262 | void __iomem *reg_base; | |
263 | struct phy *phy; | |
0ff03fd1 | 264 | struct clk **clks; |
7eb8f069 AH |
265 | struct regulator_bulk_data supplies[2]; |
266 | int irq; | |
e17ddecc | 267 | int te_gpio; |
7eb8f069 AH |
268 | |
269 | u32 pll_clk_rate; | |
270 | u32 burst_clk_rate; | |
271 | u32 esc_clk_rate; | |
272 | u32 lanes; | |
273 | u32 mode_flags; | |
274 | u32 format; | |
7eb8f069 AH |
275 | |
276 | int state; | |
277 | struct drm_property *brightness; | |
278 | struct completion completed; | |
279 | ||
280 | spinlock_t transfer_lock; /* protects transfer_list */ | |
281 | struct list_head transfer_list; | |
9a320415 | 282 | |
2154ac92 | 283 | const struct exynos_dsi_driver_data *driver_data; |
2782622e | 284 | struct device_node *in_bridge_node; |
7eb8f069 AH |
285 | }; |
286 | ||
287 | #define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host) | |
288 | #define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector) | |
289 | ||
2b8376c8 | 290 | static inline struct exynos_dsi *encoder_to_dsi(struct drm_encoder *e) |
5cd5db80 | 291 | { |
cf67cc9a | 292 | return container_of(e, struct exynos_dsi, encoder); |
5cd5db80 AH |
293 | } |
294 | ||
d668e8bf HH |
295 | enum reg_idx { |
296 | DSIM_STATUS_REG, /* Status register */ | |
297 | DSIM_SWRST_REG, /* Software reset register */ | |
298 | DSIM_CLKCTRL_REG, /* Clock control register */ | |
299 | DSIM_TIMEOUT_REG, /* Time out register */ | |
300 | DSIM_CONFIG_REG, /* Configuration register */ | |
301 | DSIM_ESCMODE_REG, /* Escape mode register */ | |
302 | DSIM_MDRESOL_REG, | |
303 | DSIM_MVPORCH_REG, /* Main display Vporch register */ | |
304 | DSIM_MHPORCH_REG, /* Main display Hporch register */ | |
305 | DSIM_MSYNC_REG, /* Main display sync area register */ | |
306 | DSIM_INTSRC_REG, /* Interrupt source register */ | |
307 | DSIM_INTMSK_REG, /* Interrupt mask register */ | |
308 | DSIM_PKTHDR_REG, /* Packet Header FIFO register */ | |
309 | DSIM_PAYLOAD_REG, /* Payload FIFO register */ | |
310 | DSIM_RXFIFO_REG, /* Read FIFO register */ | |
311 | DSIM_FIFOCTRL_REG, /* FIFO status and control register */ | |
312 | DSIM_PLLCTRL_REG, /* PLL control register */ | |
313 | DSIM_PHYCTRL_REG, | |
314 | DSIM_PHYTIMING_REG, | |
315 | DSIM_PHYTIMING1_REG, | |
316 | DSIM_PHYTIMING2_REG, | |
317 | NUM_REGS | |
318 | }; | |
bb32e408 AH |
319 | |
320 | static inline void exynos_dsi_write(struct exynos_dsi *dsi, enum reg_idx idx, | |
321 | u32 val) | |
322 | { | |
6c81e96d | 323 | |
bb32e408 AH |
324 | writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]); |
325 | } | |
326 | ||
327 | static inline u32 exynos_dsi_read(struct exynos_dsi *dsi, enum reg_idx idx) | |
328 | { | |
329 | return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]); | |
330 | } | |
331 | ||
b115361e | 332 | static const unsigned int exynos_reg_ofs[] = { |
d668e8bf HH |
333 | [DSIM_STATUS_REG] = 0x00, |
334 | [DSIM_SWRST_REG] = 0x04, | |
335 | [DSIM_CLKCTRL_REG] = 0x08, | |
336 | [DSIM_TIMEOUT_REG] = 0x0c, | |
337 | [DSIM_CONFIG_REG] = 0x10, | |
338 | [DSIM_ESCMODE_REG] = 0x14, | |
339 | [DSIM_MDRESOL_REG] = 0x18, | |
340 | [DSIM_MVPORCH_REG] = 0x1c, | |
341 | [DSIM_MHPORCH_REG] = 0x20, | |
342 | [DSIM_MSYNC_REG] = 0x24, | |
343 | [DSIM_INTSRC_REG] = 0x2c, | |
344 | [DSIM_INTMSK_REG] = 0x30, | |
345 | [DSIM_PKTHDR_REG] = 0x34, | |
346 | [DSIM_PAYLOAD_REG] = 0x38, | |
347 | [DSIM_RXFIFO_REG] = 0x3c, | |
348 | [DSIM_FIFOCTRL_REG] = 0x44, | |
349 | [DSIM_PLLCTRL_REG] = 0x4c, | |
350 | [DSIM_PHYCTRL_REG] = 0x5c, | |
351 | [DSIM_PHYTIMING_REG] = 0x64, | |
352 | [DSIM_PHYTIMING1_REG] = 0x68, | |
353 | [DSIM_PHYTIMING2_REG] = 0x6c, | |
354 | }; | |
355 | ||
b115361e | 356 | static const unsigned int exynos5433_reg_ofs[] = { |
e6f988a4 HH |
357 | [DSIM_STATUS_REG] = 0x04, |
358 | [DSIM_SWRST_REG] = 0x0C, | |
359 | [DSIM_CLKCTRL_REG] = 0x10, | |
360 | [DSIM_TIMEOUT_REG] = 0x14, | |
361 | [DSIM_CONFIG_REG] = 0x18, | |
362 | [DSIM_ESCMODE_REG] = 0x1C, | |
363 | [DSIM_MDRESOL_REG] = 0x20, | |
364 | [DSIM_MVPORCH_REG] = 0x24, | |
365 | [DSIM_MHPORCH_REG] = 0x28, | |
366 | [DSIM_MSYNC_REG] = 0x2C, | |
367 | [DSIM_INTSRC_REG] = 0x34, | |
368 | [DSIM_INTMSK_REG] = 0x38, | |
369 | [DSIM_PKTHDR_REG] = 0x3C, | |
370 | [DSIM_PAYLOAD_REG] = 0x40, | |
371 | [DSIM_RXFIFO_REG] = 0x44, | |
372 | [DSIM_FIFOCTRL_REG] = 0x4C, | |
373 | [DSIM_PLLCTRL_REG] = 0x94, | |
374 | [DSIM_PHYCTRL_REG] = 0xA4, | |
375 | [DSIM_PHYTIMING_REG] = 0xB4, | |
376 | [DSIM_PHYTIMING1_REG] = 0xB8, | |
377 | [DSIM_PHYTIMING2_REG] = 0xBC, | |
378 | }; | |
379 | ||
d668e8bf HH |
380 | enum reg_value_idx { |
381 | RESET_TYPE, | |
382 | PLL_TIMER, | |
383 | STOP_STATE_CNT, | |
384 | PHYCTRL_ULPS_EXIT, | |
385 | PHYCTRL_VREG_LP, | |
386 | PHYCTRL_SLEW_UP, | |
387 | PHYTIMING_LPX, | |
388 | PHYTIMING_HS_EXIT, | |
389 | PHYTIMING_CLK_PREPARE, | |
390 | PHYTIMING_CLK_ZERO, | |
391 | PHYTIMING_CLK_POST, | |
392 | PHYTIMING_CLK_TRAIL, | |
393 | PHYTIMING_HS_PREPARE, | |
394 | PHYTIMING_HS_ZERO, | |
395 | PHYTIMING_HS_TRAIL | |
396 | }; | |
397 | ||
b115361e | 398 | static const unsigned int reg_values[] = { |
d668e8bf HH |
399 | [RESET_TYPE] = DSIM_SWRST, |
400 | [PLL_TIMER] = 500, | |
401 | [STOP_STATE_CNT] = 0xf, | |
402 | [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af), | |
403 | [PHYCTRL_VREG_LP] = 0, | |
404 | [PHYCTRL_SLEW_UP] = 0, | |
405 | [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06), | |
406 | [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b), | |
407 | [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07), | |
408 | [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27), | |
409 | [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d), | |
410 | [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08), | |
411 | [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09), | |
412 | [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d), | |
413 | [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b), | |
414 | }; | |
415 | ||
b115361e | 416 | static const unsigned int exynos5422_reg_values[] = { |
fdc2e108 CP |
417 | [RESET_TYPE] = DSIM_SWRST, |
418 | [PLL_TIMER] = 500, | |
419 | [STOP_STATE_CNT] = 0xf, | |
420 | [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf), | |
421 | [PHYCTRL_VREG_LP] = 0, | |
422 | [PHYCTRL_SLEW_UP] = 0, | |
423 | [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x08), | |
424 | [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0d), | |
425 | [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), | |
426 | [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x30), | |
427 | [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), | |
428 | [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x0a), | |
429 | [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0c), | |
430 | [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x11), | |
431 | [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d), | |
432 | }; | |
433 | ||
b115361e | 434 | static const unsigned int exynos5433_reg_values[] = { |
e6f988a4 HH |
435 | [RESET_TYPE] = DSIM_FUNCRST, |
436 | [PLL_TIMER] = 22200, | |
437 | [STOP_STATE_CNT] = 0xa, | |
438 | [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190), | |
439 | [PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP, | |
440 | [PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP, | |
441 | [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07), | |
442 | [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c), | |
443 | [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), | |
444 | [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d), | |
445 | [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), | |
446 | [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09), | |
447 | [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b), | |
448 | [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10), | |
449 | [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c), | |
450 | }; | |
451 | ||
b115361e | 452 | static const struct exynos_dsi_driver_data exynos3_dsi_driver_data = { |
d668e8bf | 453 | .reg_ofs = exynos_reg_ofs, |
473462a1 ID |
454 | .plltmr_reg = 0x50, |
455 | .has_freqband = 1, | |
456 | .has_clklane_stop = 1, | |
d668e8bf HH |
457 | .num_clks = 2, |
458 | .max_freq = 1000, | |
459 | .wait_for_reset = 1, | |
460 | .num_bits_resol = 11, | |
461 | .reg_values = reg_values, | |
473462a1 ID |
462 | }; |
463 | ||
b115361e | 464 | static const struct exynos_dsi_driver_data exynos4_dsi_driver_data = { |
d668e8bf | 465 | .reg_ofs = exynos_reg_ofs, |
9a320415 YC |
466 | .plltmr_reg = 0x50, |
467 | .has_freqband = 1, | |
78d3a8c6 | 468 | .has_clklane_stop = 1, |
d668e8bf HH |
469 | .num_clks = 2, |
470 | .max_freq = 1000, | |
471 | .wait_for_reset = 1, | |
472 | .num_bits_resol = 11, | |
473 | .reg_values = reg_values, | |
9a320415 YC |
474 | }; |
475 | ||
b115361e | 476 | static const struct exynos_dsi_driver_data exynos5_dsi_driver_data = { |
d668e8bf | 477 | .reg_ofs = exynos_reg_ofs, |
9a320415 | 478 | .plltmr_reg = 0x58, |
d668e8bf HH |
479 | .num_clks = 2, |
480 | .max_freq = 1000, | |
481 | .wait_for_reset = 1, | |
482 | .num_bits_resol = 11, | |
483 | .reg_values = reg_values, | |
9a320415 YC |
484 | }; |
485 | ||
b115361e | 486 | static const struct exynos_dsi_driver_data exynos5433_dsi_driver_data = { |
e6f988a4 HH |
487 | .reg_ofs = exynos5433_reg_ofs, |
488 | .plltmr_reg = 0xa0, | |
489 | .has_clklane_stop = 1, | |
490 | .num_clks = 5, | |
491 | .max_freq = 1500, | |
492 | .wait_for_reset = 0, | |
493 | .num_bits_resol = 12, | |
494 | .reg_values = exynos5433_reg_values, | |
495 | }; | |
496 | ||
b115361e | 497 | static const struct exynos_dsi_driver_data exynos5422_dsi_driver_data = { |
fdc2e108 CP |
498 | .reg_ofs = exynos5433_reg_ofs, |
499 | .plltmr_reg = 0xa0, | |
500 | .has_clklane_stop = 1, | |
501 | .num_clks = 2, | |
502 | .max_freq = 1500, | |
503 | .wait_for_reset = 1, | |
504 | .num_bits_resol = 12, | |
505 | .reg_values = exynos5422_reg_values, | |
506 | }; | |
507 | ||
b115361e | 508 | static const struct of_device_id exynos_dsi_of_match[] = { |
473462a1 ID |
509 | { .compatible = "samsung,exynos3250-mipi-dsi", |
510 | .data = &exynos3_dsi_driver_data }, | |
9a320415 YC |
511 | { .compatible = "samsung,exynos4210-mipi-dsi", |
512 | .data = &exynos4_dsi_driver_data }, | |
513 | { .compatible = "samsung,exynos5410-mipi-dsi", | |
514 | .data = &exynos5_dsi_driver_data }, | |
fdc2e108 CP |
515 | { .compatible = "samsung,exynos5422-mipi-dsi", |
516 | .data = &exynos5422_dsi_driver_data }, | |
e6f988a4 HH |
517 | { .compatible = "samsung,exynos5433-mipi-dsi", |
518 | .data = &exynos5433_dsi_driver_data }, | |
9a320415 YC |
519 | { } |
520 | }; | |
521 | ||
7eb8f069 AH |
522 | static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi) |
523 | { | |
524 | if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300))) | |
525 | return; | |
526 | ||
527 | dev_err(dsi->dev, "timeout waiting for reset\n"); | |
528 | } | |
529 | ||
530 | static void exynos_dsi_reset(struct exynos_dsi *dsi) | |
531 | { | |
bb32e408 | 532 | u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE]; |
ba12ac2b | 533 | |
7eb8f069 | 534 | reinit_completion(&dsi->completed); |
bb32e408 | 535 | exynos_dsi_write(dsi, DSIM_SWRST_REG, reset_val); |
7eb8f069 AH |
536 | } |
537 | ||
538 | #ifndef MHZ | |
539 | #define MHZ (1000*1000) | |
540 | #endif | |
541 | ||
542 | static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi, | |
543 | unsigned long fin, unsigned long fout, u8 *p, u16 *m, u8 *s) | |
544 | { | |
2154ac92 | 545 | const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; |
7eb8f069 AH |
546 | unsigned long best_freq = 0; |
547 | u32 min_delta = 0xffffffff; | |
548 | u8 p_min, p_max; | |
549 | u8 _p, uninitialized_var(best_p); | |
550 | u16 _m, uninitialized_var(best_m); | |
551 | u8 _s, uninitialized_var(best_s); | |
552 | ||
553 | p_min = DIV_ROUND_UP(fin, (12 * MHZ)); | |
554 | p_max = fin / (6 * MHZ); | |
555 | ||
556 | for (_p = p_min; _p <= p_max; ++_p) { | |
557 | for (_s = 0; _s <= 5; ++_s) { | |
558 | u64 tmp; | |
559 | u32 delta; | |
560 | ||
561 | tmp = (u64)fout * (_p << _s); | |
562 | do_div(tmp, fin); | |
563 | _m = tmp; | |
564 | if (_m < 41 || _m > 125) | |
565 | continue; | |
566 | ||
567 | tmp = (u64)_m * fin; | |
568 | do_div(tmp, _p); | |
d668e8bf HH |
569 | if (tmp < 500 * MHZ || |
570 | tmp > driver_data->max_freq * MHZ) | |
7eb8f069 AH |
571 | continue; |
572 | ||
573 | tmp = (u64)_m * fin; | |
574 | do_div(tmp, _p << _s); | |
575 | ||
576 | delta = abs(fout - tmp); | |
577 | if (delta < min_delta) { | |
578 | best_p = _p; | |
579 | best_m = _m; | |
580 | best_s = _s; | |
581 | min_delta = delta; | |
582 | best_freq = tmp; | |
583 | } | |
584 | } | |
585 | } | |
586 | ||
587 | if (best_freq) { | |
588 | *p = best_p; | |
589 | *m = best_m; | |
590 | *s = best_s; | |
591 | } | |
592 | ||
593 | return best_freq; | |
594 | } | |
595 | ||
596 | static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi, | |
597 | unsigned long freq) | |
598 | { | |
2154ac92 | 599 | const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; |
7eb8f069 | 600 | unsigned long fin, fout; |
9a320415 | 601 | int timeout; |
7eb8f069 AH |
602 | u8 p, s; |
603 | u16 m; | |
604 | u32 reg; | |
605 | ||
26269af9 | 606 | fin = dsi->pll_clk_rate; |
7eb8f069 AH |
607 | fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s); |
608 | if (!fout) { | |
609 | dev_err(dsi->dev, | |
610 | "failed to find PLL PMS for requested frequency\n"); | |
8525b5ec | 611 | return 0; |
7eb8f069 | 612 | } |
9a320415 | 613 | dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s); |
7eb8f069 | 614 | |
d668e8bf HH |
615 | writel(driver_data->reg_values[PLL_TIMER], |
616 | dsi->reg_base + driver_data->plltmr_reg); | |
9a320415 YC |
617 | |
618 | reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s); | |
619 | ||
620 | if (driver_data->has_freqband) { | |
621 | static const unsigned long freq_bands[] = { | |
622 | 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ, | |
623 | 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ, | |
624 | 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ, | |
625 | 770 * MHZ, 870 * MHZ, 950 * MHZ, | |
626 | }; | |
627 | int band; | |
7eb8f069 | 628 | |
9a320415 YC |
629 | for (band = 0; band < ARRAY_SIZE(freq_bands); ++band) |
630 | if (fout < freq_bands[band]) | |
631 | break; | |
7eb8f069 | 632 | |
9a320415 YC |
633 | dev_dbg(dsi->dev, "band %d\n", band); |
634 | ||
635 | reg |= DSIM_FREQ_BAND(band); | |
636 | } | |
7eb8f069 | 637 | |
bb32e408 | 638 | exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg); |
7eb8f069 AH |
639 | |
640 | timeout = 1000; | |
641 | do { | |
642 | if (timeout-- == 0) { | |
643 | dev_err(dsi->dev, "PLL failed to stabilize\n"); | |
8525b5ec | 644 | return 0; |
7eb8f069 | 645 | } |
bb32e408 | 646 | reg = exynos_dsi_read(dsi, DSIM_STATUS_REG); |
7eb8f069 AH |
647 | } while ((reg & DSIM_PLL_STABLE) == 0); |
648 | ||
649 | return fout; | |
650 | } | |
651 | ||
652 | static int exynos_dsi_enable_clock(struct exynos_dsi *dsi) | |
653 | { | |
654 | unsigned long hs_clk, byte_clk, esc_clk; | |
655 | unsigned long esc_div; | |
656 | u32 reg; | |
657 | ||
658 | hs_clk = exynos_dsi_set_pll(dsi, dsi->burst_clk_rate); | |
659 | if (!hs_clk) { | |
660 | dev_err(dsi->dev, "failed to configure DSI PLL\n"); | |
661 | return -EFAULT; | |
662 | } | |
663 | ||
664 | byte_clk = hs_clk / 8; | |
665 | esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate); | |
666 | esc_clk = byte_clk / esc_div; | |
667 | ||
668 | if (esc_clk > 20 * MHZ) { | |
669 | ++esc_div; | |
670 | esc_clk = byte_clk / esc_div; | |
671 | } | |
672 | ||
673 | dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n", | |
674 | hs_clk, byte_clk, esc_clk); | |
675 | ||
bb32e408 | 676 | reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG); |
7eb8f069 AH |
677 | reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK |
678 | | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS | |
679 | | DSIM_BYTE_CLK_SRC_MASK); | |
680 | reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN | |
681 | | DSIM_ESC_PRESCALER(esc_div) | |
682 | | DSIM_LANE_ESC_CLK_EN_CLK | |
683 | | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1) | |
684 | | DSIM_BYTE_CLK_SRC(0) | |
685 | | DSIM_TX_REQUEST_HSCLK; | |
bb32e408 | 686 | exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg); |
7eb8f069 AH |
687 | |
688 | return 0; | |
689 | } | |
690 | ||
9a320415 YC |
691 | static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi) |
692 | { | |
2154ac92 | 693 | const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; |
b115361e | 694 | const unsigned int *reg_values = driver_data->reg_values; |
9a320415 YC |
695 | u32 reg; |
696 | ||
697 | if (driver_data->has_freqband) | |
698 | return; | |
699 | ||
700 | /* B D-PHY: D-PHY Master & Slave Analog Block control */ | |
d668e8bf HH |
701 | reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] | |
702 | reg_values[PHYCTRL_SLEW_UP]; | |
bb32e408 | 703 | exynos_dsi_write(dsi, DSIM_PHYCTRL_REG, reg); |
9a320415 YC |
704 | |
705 | /* | |
706 | * T LPX: Transmitted length of any Low-Power state period | |
707 | * T HS-EXIT: Time that the transmitter drives LP-11 following a HS | |
708 | * burst | |
709 | */ | |
d668e8bf | 710 | reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT]; |
bb32e408 | 711 | exynos_dsi_write(dsi, DSIM_PHYTIMING_REG, reg); |
9a320415 YC |
712 | |
713 | /* | |
714 | * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00 | |
715 | * Line state immediately before the HS-0 Line state starting the | |
716 | * HS transmission | |
717 | * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to | |
718 | * transmitting the Clock. | |
719 | * T CLK_POST: Time that the transmitter continues to send HS clock | |
720 | * after the last associated Data Lane has transitioned to LP Mode | |
721 | * Interval is defined as the period from the end of T HS-TRAIL to | |
722 | * the beginning of T CLK-TRAIL | |
723 | * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after | |
724 | * the last payload clock bit of a HS transmission burst | |
725 | */ | |
d668e8bf HH |
726 | reg = reg_values[PHYTIMING_CLK_PREPARE] | |
727 | reg_values[PHYTIMING_CLK_ZERO] | | |
728 | reg_values[PHYTIMING_CLK_POST] | | |
729 | reg_values[PHYTIMING_CLK_TRAIL]; | |
730 | ||
bb32e408 | 731 | exynos_dsi_write(dsi, DSIM_PHYTIMING1_REG, reg); |
9a320415 YC |
732 | |
733 | /* | |
734 | * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00 | |
735 | * Line state immediately before the HS-0 Line state starting the | |
736 | * HS transmission | |
737 | * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to | |
738 | * transmitting the Sync sequence. | |
739 | * T HS-TRAIL: Time that the transmitter drives the flipped differential | |
740 | * state after last payload data bit of a HS transmission burst | |
741 | */ | |
d668e8bf HH |
742 | reg = reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] | |
743 | reg_values[PHYTIMING_HS_TRAIL]; | |
bb32e408 | 744 | exynos_dsi_write(dsi, DSIM_PHYTIMING2_REG, reg); |
9a320415 YC |
745 | } |
746 | ||
7eb8f069 AH |
747 | static void exynos_dsi_disable_clock(struct exynos_dsi *dsi) |
748 | { | |
749 | u32 reg; | |
750 | ||
bb32e408 | 751 | reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG); |
7eb8f069 AH |
752 | reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK |
753 | | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN); | |
bb32e408 | 754 | exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg); |
7eb8f069 | 755 | |
bb32e408 | 756 | reg = exynos_dsi_read(dsi, DSIM_PLLCTRL_REG); |
7eb8f069 | 757 | reg &= ~DSIM_PLL_EN; |
bb32e408 | 758 | exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg); |
7eb8f069 AH |
759 | } |
760 | ||
e6f988a4 HH |
761 | static void exynos_dsi_enable_lane(struct exynos_dsi *dsi, u32 lane) |
762 | { | |
bb32e408 | 763 | u32 reg = exynos_dsi_read(dsi, DSIM_CONFIG_REG); |
e6f988a4 HH |
764 | reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK | |
765 | DSIM_LANE_EN(lane)); | |
bb32e408 | 766 | exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg); |
e6f988a4 HH |
767 | } |
768 | ||
7eb8f069 AH |
769 | static int exynos_dsi_init_link(struct exynos_dsi *dsi) |
770 | { | |
2154ac92 | 771 | const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; |
7eb8f069 AH |
772 | int timeout; |
773 | u32 reg; | |
774 | u32 lanes_mask; | |
775 | ||
776 | /* Initialize FIFO pointers */ | |
bb32e408 | 777 | reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG); |
7eb8f069 | 778 | reg &= ~0x1f; |
bb32e408 | 779 | exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg); |
7eb8f069 AH |
780 | |
781 | usleep_range(9000, 11000); | |
782 | ||
783 | reg |= 0x1f; | |
bb32e408 | 784 | exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg); |
7eb8f069 AH |
785 | usleep_range(9000, 11000); |
786 | ||
787 | /* DSI configuration */ | |
788 | reg = 0; | |
789 | ||
2f36e33a YC |
790 | /* |
791 | * The first bit of mode_flags specifies display configuration. | |
792 | * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video | |
793 | * mode, otherwise it will support command mode. | |
794 | */ | |
7eb8f069 AH |
795 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { |
796 | reg |= DSIM_VIDEO_MODE; | |
797 | ||
2f36e33a YC |
798 | /* |
799 | * The user manual describes that following bits are ignored in | |
800 | * command mode. | |
801 | */ | |
7eb8f069 AH |
802 | if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH)) |
803 | reg |= DSIM_MFLUSH_VS; | |
7eb8f069 AH |
804 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) |
805 | reg |= DSIM_SYNC_INFORM; | |
806 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) | |
807 | reg |= DSIM_BURST_MODE; | |
808 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT) | |
809 | reg |= DSIM_AUTO_MODE; | |
810 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE) | |
811 | reg |= DSIM_HSE_MODE; | |
812 | if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP)) | |
813 | reg |= DSIM_HFP_MODE; | |
814 | if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP)) | |
815 | reg |= DSIM_HBP_MODE; | |
816 | if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA)) | |
817 | reg |= DSIM_HSA_MODE; | |
818 | } | |
819 | ||
2f36e33a YC |
820 | if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET)) |
821 | reg |= DSIM_EOT_DISABLE; | |
822 | ||
7eb8f069 AH |
823 | switch (dsi->format) { |
824 | case MIPI_DSI_FMT_RGB888: | |
825 | reg |= DSIM_MAIN_PIX_FORMAT_RGB888; | |
826 | break; | |
827 | case MIPI_DSI_FMT_RGB666: | |
828 | reg |= DSIM_MAIN_PIX_FORMAT_RGB666; | |
829 | break; | |
830 | case MIPI_DSI_FMT_RGB666_PACKED: | |
831 | reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P; | |
832 | break; | |
833 | case MIPI_DSI_FMT_RGB565: | |
834 | reg |= DSIM_MAIN_PIX_FORMAT_RGB565; | |
835 | break; | |
836 | default: | |
837 | dev_err(dsi->dev, "invalid pixel format\n"); | |
838 | return -EINVAL; | |
839 | } | |
840 | ||
78d3a8c6 ID |
841 | /* |
842 | * Use non-continuous clock mode if the periparal wants and | |
843 | * host controller supports | |
844 | * | |
845 | * In non-continous clock mode, host controller will turn off | |
846 | * the HS clock between high-speed transmissions to reduce | |
847 | * power consumption. | |
848 | */ | |
849 | if (driver_data->has_clklane_stop && | |
850 | dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { | |
851 | reg |= DSIM_CLKLANE_STOP; | |
78d3a8c6 | 852 | } |
bb32e408 | 853 | exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg); |
e6f988a4 HH |
854 | |
855 | lanes_mask = BIT(dsi->lanes) - 1; | |
856 | exynos_dsi_enable_lane(dsi, lanes_mask); | |
78d3a8c6 | 857 | |
7eb8f069 AH |
858 | /* Check clock and data lane state are stop state */ |
859 | timeout = 100; | |
860 | do { | |
861 | if (timeout-- == 0) { | |
862 | dev_err(dsi->dev, "waiting for bus lanes timed out\n"); | |
863 | return -EFAULT; | |
864 | } | |
865 | ||
bb32e408 | 866 | reg = exynos_dsi_read(dsi, DSIM_STATUS_REG); |
7eb8f069 AH |
867 | if ((reg & DSIM_STOP_STATE_DAT(lanes_mask)) |
868 | != DSIM_STOP_STATE_DAT(lanes_mask)) | |
869 | continue; | |
870 | } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK))); | |
871 | ||
bb32e408 | 872 | reg = exynos_dsi_read(dsi, DSIM_ESCMODE_REG); |
7eb8f069 | 873 | reg &= ~DSIM_STOP_STATE_CNT_MASK; |
d668e8bf | 874 | reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]); |
bb32e408 | 875 | exynos_dsi_write(dsi, DSIM_ESCMODE_REG, reg); |
7eb8f069 AH |
876 | |
877 | reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff); | |
bb32e408 | 878 | exynos_dsi_write(dsi, DSIM_TIMEOUT_REG, reg); |
7eb8f069 AH |
879 | |
880 | return 0; | |
881 | } | |
882 | ||
883 | static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi) | |
884 | { | |
e8929999 | 885 | struct drm_display_mode *m = &dsi->encoder.crtc->state->adjusted_mode; |
d668e8bf | 886 | unsigned int num_bits_resol = dsi->driver_data->num_bits_resol; |
7eb8f069 AH |
887 | u32 reg; |
888 | ||
889 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { | |
890 | reg = DSIM_CMD_ALLOW(0xf) | |
e8929999 AH |
891 | | DSIM_STABLE_VFP(m->vsync_start - m->vdisplay) |
892 | | DSIM_MAIN_VBP(m->vtotal - m->vsync_end); | |
bb32e408 | 893 | exynos_dsi_write(dsi, DSIM_MVPORCH_REG, reg); |
7eb8f069 | 894 | |
e8929999 AH |
895 | reg = DSIM_MAIN_HFP(m->hsync_start - m->hdisplay) |
896 | | DSIM_MAIN_HBP(m->htotal - m->hsync_end); | |
bb32e408 | 897 | exynos_dsi_write(dsi, DSIM_MHPORCH_REG, reg); |
7eb8f069 | 898 | |
e8929999 AH |
899 | reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start) |
900 | | DSIM_MAIN_HSA(m->hsync_end - m->hsync_start); | |
bb32e408 | 901 | exynos_dsi_write(dsi, DSIM_MSYNC_REG, reg); |
7eb8f069 | 902 | } |
e8929999 AH |
903 | reg = DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) | |
904 | DSIM_MAIN_VRESOL(m->vdisplay, num_bits_resol); | |
7eb8f069 | 905 | |
bb32e408 | 906 | exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg); |
7eb8f069 | 907 | |
e8929999 | 908 | dev_dbg(dsi->dev, "LCD size = %dx%d\n", m->hdisplay, m->vdisplay); |
7eb8f069 AH |
909 | } |
910 | ||
911 | static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable) | |
912 | { | |
913 | u32 reg; | |
914 | ||
bb32e408 | 915 | reg = exynos_dsi_read(dsi, DSIM_MDRESOL_REG); |
7eb8f069 AH |
916 | if (enable) |
917 | reg |= DSIM_MAIN_STAND_BY; | |
918 | else | |
919 | reg &= ~DSIM_MAIN_STAND_BY; | |
bb32e408 | 920 | exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg); |
7eb8f069 AH |
921 | } |
922 | ||
923 | static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi) | |
924 | { | |
925 | int timeout = 2000; | |
926 | ||
927 | do { | |
bb32e408 | 928 | u32 reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG); |
7eb8f069 AH |
929 | |
930 | if (!(reg & DSIM_SFR_HEADER_FULL)) | |
931 | return 0; | |
932 | ||
933 | if (!cond_resched()) | |
934 | usleep_range(950, 1050); | |
935 | } while (--timeout); | |
936 | ||
937 | return -ETIMEDOUT; | |
938 | } | |
939 | ||
940 | static void exynos_dsi_set_cmd_lpm(struct exynos_dsi *dsi, bool lpm) | |
941 | { | |
bb32e408 | 942 | u32 v = exynos_dsi_read(dsi, DSIM_ESCMODE_REG); |
7eb8f069 AH |
943 | |
944 | if (lpm) | |
945 | v |= DSIM_CMD_LPDT_LP; | |
946 | else | |
947 | v &= ~DSIM_CMD_LPDT_LP; | |
948 | ||
bb32e408 | 949 | exynos_dsi_write(dsi, DSIM_ESCMODE_REG, v); |
7eb8f069 AH |
950 | } |
951 | ||
952 | static void exynos_dsi_force_bta(struct exynos_dsi *dsi) | |
953 | { | |
bb32e408 | 954 | u32 v = exynos_dsi_read(dsi, DSIM_ESCMODE_REG); |
7eb8f069 | 955 | v |= DSIM_FORCE_BTA; |
bb32e408 | 956 | exynos_dsi_write(dsi, DSIM_ESCMODE_REG, v); |
7eb8f069 AH |
957 | } |
958 | ||
959 | static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi, | |
960 | struct exynos_dsi_transfer *xfer) | |
961 | { | |
962 | struct device *dev = dsi->dev; | |
6c81e96d AH |
963 | struct mipi_dsi_packet *pkt = &xfer->packet; |
964 | const u8 *payload = pkt->payload + xfer->tx_done; | |
965 | u16 length = pkt->payload_length - xfer->tx_done; | |
7eb8f069 AH |
966 | bool first = !xfer->tx_done; |
967 | u32 reg; | |
968 | ||
9cdf0ed2 | 969 | dev_dbg(dev, "< xfer %pK: tx len %u, done %u, rx len %u, done %u\n", |
6c81e96d | 970 | xfer, length, xfer->tx_done, xfer->rx_len, xfer->rx_done); |
7eb8f069 AH |
971 | |
972 | if (length > DSI_TX_FIFO_SIZE) | |
973 | length = DSI_TX_FIFO_SIZE; | |
974 | ||
975 | xfer->tx_done += length; | |
976 | ||
977 | /* Send payload */ | |
978 | while (length >= 4) { | |
6c81e96d | 979 | reg = get_unaligned_le32(payload); |
bb32e408 | 980 | exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg); |
7eb8f069 AH |
981 | payload += 4; |
982 | length -= 4; | |
983 | } | |
984 | ||
985 | reg = 0; | |
986 | switch (length) { | |
987 | case 3: | |
988 | reg |= payload[2] << 16; | |
989 | /* Fall through */ | |
990 | case 2: | |
991 | reg |= payload[1] << 8; | |
992 | /* Fall through */ | |
993 | case 1: | |
994 | reg |= payload[0]; | |
bb32e408 | 995 | exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg); |
7eb8f069 | 996 | break; |
7eb8f069 AH |
997 | } |
998 | ||
999 | /* Send packet header */ | |
1000 | if (!first) | |
1001 | return; | |
1002 | ||
6c81e96d | 1003 | reg = get_unaligned_le32(pkt->header); |
7eb8f069 AH |
1004 | if (exynos_dsi_wait_for_hdr_fifo(dsi)) { |
1005 | dev_err(dev, "waiting for header FIFO timed out\n"); | |
1006 | return; | |
1007 | } | |
1008 | ||
1009 | if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM, | |
1010 | dsi->state & DSIM_STATE_CMD_LPM)) { | |
1011 | exynos_dsi_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM); | |
1012 | dsi->state ^= DSIM_STATE_CMD_LPM; | |
1013 | } | |
1014 | ||
bb32e408 | 1015 | exynos_dsi_write(dsi, DSIM_PKTHDR_REG, reg); |
7eb8f069 AH |
1016 | |
1017 | if (xfer->flags & MIPI_DSI_MSG_REQ_ACK) | |
1018 | exynos_dsi_force_bta(dsi); | |
1019 | } | |
1020 | ||
1021 | static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi, | |
1022 | struct exynos_dsi_transfer *xfer) | |
1023 | { | |
1024 | u8 *payload = xfer->rx_payload + xfer->rx_done; | |
1025 | bool first = !xfer->rx_done; | |
1026 | struct device *dev = dsi->dev; | |
1027 | u16 length; | |
1028 | u32 reg; | |
1029 | ||
1030 | if (first) { | |
bb32e408 | 1031 | reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); |
7eb8f069 AH |
1032 | |
1033 | switch (reg & 0x3f) { | |
1034 | case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: | |
1035 | case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: | |
1036 | if (xfer->rx_len >= 2) { | |
1037 | payload[1] = reg >> 16; | |
1038 | ++xfer->rx_done; | |
1039 | } | |
1040 | /* Fall through */ | |
1041 | case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: | |
1042 | case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: | |
1043 | payload[0] = reg >> 8; | |
1044 | ++xfer->rx_done; | |
1045 | xfer->rx_len = xfer->rx_done; | |
1046 | xfer->result = 0; | |
1047 | goto clear_fifo; | |
1048 | case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: | |
1049 | dev_err(dev, "DSI Error Report: 0x%04x\n", | |
1050 | (reg >> 8) & 0xffff); | |
1051 | xfer->result = 0; | |
1052 | goto clear_fifo; | |
1053 | } | |
1054 | ||
1055 | length = (reg >> 8) & 0xffff; | |
1056 | if (length > xfer->rx_len) { | |
1057 | dev_err(dev, | |
1058 | "response too long (%u > %u bytes), stripping\n", | |
1059 | xfer->rx_len, length); | |
1060 | length = xfer->rx_len; | |
1061 | } else if (length < xfer->rx_len) | |
1062 | xfer->rx_len = length; | |
1063 | } | |
1064 | ||
1065 | length = xfer->rx_len - xfer->rx_done; | |
1066 | xfer->rx_done += length; | |
1067 | ||
1068 | /* Receive payload */ | |
1069 | while (length >= 4) { | |
bb32e408 | 1070 | reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); |
7eb8f069 AH |
1071 | payload[0] = (reg >> 0) & 0xff; |
1072 | payload[1] = (reg >> 8) & 0xff; | |
1073 | payload[2] = (reg >> 16) & 0xff; | |
1074 | payload[3] = (reg >> 24) & 0xff; | |
1075 | payload += 4; | |
1076 | length -= 4; | |
1077 | } | |
1078 | ||
1079 | if (length) { | |
bb32e408 | 1080 | reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); |
7eb8f069 AH |
1081 | switch (length) { |
1082 | case 3: | |
1083 | payload[2] = (reg >> 16) & 0xff; | |
1084 | /* Fall through */ | |
1085 | case 2: | |
1086 | payload[1] = (reg >> 8) & 0xff; | |
1087 | /* Fall through */ | |
1088 | case 1: | |
1089 | payload[0] = reg & 0xff; | |
1090 | } | |
1091 | } | |
1092 | ||
1093 | if (xfer->rx_done == xfer->rx_len) | |
1094 | xfer->result = 0; | |
1095 | ||
1096 | clear_fifo: | |
1097 | length = DSI_RX_FIFO_SIZE / 4; | |
1098 | do { | |
bb32e408 | 1099 | reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); |
7eb8f069 AH |
1100 | if (reg == DSI_RX_FIFO_EMPTY) |
1101 | break; | |
1102 | } while (--length); | |
1103 | } | |
1104 | ||
1105 | static void exynos_dsi_transfer_start(struct exynos_dsi *dsi) | |
1106 | { | |
1107 | unsigned long flags; | |
1108 | struct exynos_dsi_transfer *xfer; | |
1109 | bool start = false; | |
1110 | ||
1111 | again: | |
1112 | spin_lock_irqsave(&dsi->transfer_lock, flags); | |
1113 | ||
1114 | if (list_empty(&dsi->transfer_list)) { | |
1115 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); | |
1116 | return; | |
1117 | } | |
1118 | ||
1119 | xfer = list_first_entry(&dsi->transfer_list, | |
1120 | struct exynos_dsi_transfer, list); | |
1121 | ||
1122 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); | |
1123 | ||
6c81e96d AH |
1124 | if (xfer->packet.payload_length && |
1125 | xfer->tx_done == xfer->packet.payload_length) | |
7eb8f069 AH |
1126 | /* waiting for RX */ |
1127 | return; | |
1128 | ||
1129 | exynos_dsi_send_to_fifo(dsi, xfer); | |
1130 | ||
6c81e96d | 1131 | if (xfer->packet.payload_length || xfer->rx_len) |
7eb8f069 AH |
1132 | return; |
1133 | ||
1134 | xfer->result = 0; | |
1135 | complete(&xfer->completed); | |
1136 | ||
1137 | spin_lock_irqsave(&dsi->transfer_lock, flags); | |
1138 | ||
1139 | list_del_init(&xfer->list); | |
1140 | start = !list_empty(&dsi->transfer_list); | |
1141 | ||
1142 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); | |
1143 | ||
1144 | if (start) | |
1145 | goto again; | |
1146 | } | |
1147 | ||
1148 | static bool exynos_dsi_transfer_finish(struct exynos_dsi *dsi) | |
1149 | { | |
1150 | struct exynos_dsi_transfer *xfer; | |
1151 | unsigned long flags; | |
1152 | bool start = true; | |
1153 | ||
1154 | spin_lock_irqsave(&dsi->transfer_lock, flags); | |
1155 | ||
1156 | if (list_empty(&dsi->transfer_list)) { | |
1157 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); | |
1158 | return false; | |
1159 | } | |
1160 | ||
1161 | xfer = list_first_entry(&dsi->transfer_list, | |
1162 | struct exynos_dsi_transfer, list); | |
1163 | ||
1164 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); | |
1165 | ||
1166 | dev_dbg(dsi->dev, | |
9cdf0ed2 | 1167 | "> xfer %pK, tx_len %zu, tx_done %u, rx_len %u, rx_done %u\n", |
6c81e96d AH |
1168 | xfer, xfer->packet.payload_length, xfer->tx_done, xfer->rx_len, |
1169 | xfer->rx_done); | |
7eb8f069 | 1170 | |
6c81e96d | 1171 | if (xfer->tx_done != xfer->packet.payload_length) |
7eb8f069 AH |
1172 | return true; |
1173 | ||
1174 | if (xfer->rx_done != xfer->rx_len) | |
1175 | exynos_dsi_read_from_fifo(dsi, xfer); | |
1176 | ||
1177 | if (xfer->rx_done != xfer->rx_len) | |
1178 | return true; | |
1179 | ||
1180 | spin_lock_irqsave(&dsi->transfer_lock, flags); | |
1181 | ||
1182 | list_del_init(&xfer->list); | |
1183 | start = !list_empty(&dsi->transfer_list); | |
1184 | ||
1185 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); | |
1186 | ||
1187 | if (!xfer->rx_len) | |
1188 | xfer->result = 0; | |
1189 | complete(&xfer->completed); | |
1190 | ||
1191 | return start; | |
1192 | } | |
1193 | ||
1194 | static void exynos_dsi_remove_transfer(struct exynos_dsi *dsi, | |
1195 | struct exynos_dsi_transfer *xfer) | |
1196 | { | |
1197 | unsigned long flags; | |
1198 | bool start; | |
1199 | ||
1200 | spin_lock_irqsave(&dsi->transfer_lock, flags); | |
1201 | ||
1202 | if (!list_empty(&dsi->transfer_list) && | |
1203 | xfer == list_first_entry(&dsi->transfer_list, | |
1204 | struct exynos_dsi_transfer, list)) { | |
1205 | list_del_init(&xfer->list); | |
1206 | start = !list_empty(&dsi->transfer_list); | |
1207 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); | |
1208 | if (start) | |
1209 | exynos_dsi_transfer_start(dsi); | |
1210 | return; | |
1211 | } | |
1212 | ||
1213 | list_del_init(&xfer->list); | |
1214 | ||
1215 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); | |
1216 | } | |
1217 | ||
1218 | static int exynos_dsi_transfer(struct exynos_dsi *dsi, | |
1219 | struct exynos_dsi_transfer *xfer) | |
1220 | { | |
1221 | unsigned long flags; | |
1222 | bool stopped; | |
1223 | ||
1224 | xfer->tx_done = 0; | |
1225 | xfer->rx_done = 0; | |
1226 | xfer->result = -ETIMEDOUT; | |
1227 | init_completion(&xfer->completed); | |
1228 | ||
1229 | spin_lock_irqsave(&dsi->transfer_lock, flags); | |
1230 | ||
1231 | stopped = list_empty(&dsi->transfer_list); | |
1232 | list_add_tail(&xfer->list, &dsi->transfer_list); | |
1233 | ||
1234 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); | |
1235 | ||
1236 | if (stopped) | |
1237 | exynos_dsi_transfer_start(dsi); | |
1238 | ||
1239 | wait_for_completion_timeout(&xfer->completed, | |
1240 | msecs_to_jiffies(DSI_XFER_TIMEOUT_MS)); | |
1241 | if (xfer->result == -ETIMEDOUT) { | |
6c81e96d | 1242 | struct mipi_dsi_packet *pkt = &xfer->packet; |
7eb8f069 | 1243 | exynos_dsi_remove_transfer(dsi, xfer); |
6c81e96d AH |
1244 | dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 4, pkt->header, |
1245 | (int)pkt->payload_length, pkt->payload); | |
7eb8f069 AH |
1246 | return -ETIMEDOUT; |
1247 | } | |
1248 | ||
1249 | /* Also covers hardware timeout condition */ | |
1250 | return xfer->result; | |
1251 | } | |
1252 | ||
1253 | static irqreturn_t exynos_dsi_irq(int irq, void *dev_id) | |
1254 | { | |
1255 | struct exynos_dsi *dsi = dev_id; | |
1256 | u32 status; | |
1257 | ||
bb32e408 | 1258 | status = exynos_dsi_read(dsi, DSIM_INTSRC_REG); |
7eb8f069 AH |
1259 | if (!status) { |
1260 | static unsigned long int j; | |
1261 | if (printk_timed_ratelimit(&j, 500)) | |
1262 | dev_warn(dsi->dev, "spurious interrupt\n"); | |
1263 | return IRQ_HANDLED; | |
1264 | } | |
bb32e408 | 1265 | exynos_dsi_write(dsi, DSIM_INTSRC_REG, status); |
7eb8f069 AH |
1266 | |
1267 | if (status & DSIM_INT_SW_RST_RELEASE) { | |
e6f988a4 | 1268 | u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY | |
ecf81ed9 AH |
1269 | DSIM_INT_SFR_HDR_FIFO_EMPTY | DSIM_INT_RX_ECC_ERR | |
1270 | DSIM_INT_SW_RST_RELEASE); | |
bb32e408 | 1271 | exynos_dsi_write(dsi, DSIM_INTMSK_REG, mask); |
7eb8f069 AH |
1272 | complete(&dsi->completed); |
1273 | return IRQ_HANDLED; | |
1274 | } | |
1275 | ||
e6f988a4 | 1276 | if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY | |
ecf81ed9 | 1277 | DSIM_INT_PLL_STABLE))) |
7eb8f069 AH |
1278 | return IRQ_HANDLED; |
1279 | ||
1280 | if (exynos_dsi_transfer_finish(dsi)) | |
1281 | exynos_dsi_transfer_start(dsi); | |
1282 | ||
1283 | return IRQ_HANDLED; | |
1284 | } | |
1285 | ||
e17ddecc YC |
1286 | static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id) |
1287 | { | |
1288 | struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id; | |
2b8376c8 | 1289 | struct drm_encoder *encoder = &dsi->encoder; |
e17ddecc | 1290 | |
0e480f6f | 1291 | if (dsi->state & DSIM_STATE_VIDOUT_AVAILABLE) |
e17ddecc YC |
1292 | exynos_drm_crtc_te_handler(encoder->crtc); |
1293 | ||
1294 | return IRQ_HANDLED; | |
1295 | } | |
1296 | ||
1297 | static void exynos_dsi_enable_irq(struct exynos_dsi *dsi) | |
1298 | { | |
1299 | enable_irq(dsi->irq); | |
1300 | ||
1301 | if (gpio_is_valid(dsi->te_gpio)) | |
1302 | enable_irq(gpio_to_irq(dsi->te_gpio)); | |
1303 | } | |
1304 | ||
1305 | static void exynos_dsi_disable_irq(struct exynos_dsi *dsi) | |
1306 | { | |
1307 | if (gpio_is_valid(dsi->te_gpio)) | |
1308 | disable_irq(gpio_to_irq(dsi->te_gpio)); | |
1309 | ||
1310 | disable_irq(dsi->irq); | |
1311 | } | |
1312 | ||
7eb8f069 AH |
1313 | static int exynos_dsi_init(struct exynos_dsi *dsi) |
1314 | { | |
2154ac92 | 1315 | const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; |
d668e8bf | 1316 | |
7eb8f069 | 1317 | exynos_dsi_reset(dsi); |
e17ddecc | 1318 | exynos_dsi_enable_irq(dsi); |
e6f988a4 HH |
1319 | |
1320 | if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST) | |
1321 | exynos_dsi_enable_lane(dsi, BIT(dsi->lanes) - 1); | |
1322 | ||
9a320415 | 1323 | exynos_dsi_enable_clock(dsi); |
d668e8bf HH |
1324 | if (driver_data->wait_for_reset) |
1325 | exynos_dsi_wait_for_reset(dsi); | |
9a320415 | 1326 | exynos_dsi_set_phy_ctrl(dsi); |
7eb8f069 AH |
1327 | exynos_dsi_init_link(dsi); |
1328 | ||
1329 | return 0; | |
1330 | } | |
1331 | ||
295e7954 AH |
1332 | static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi, |
1333 | struct device *panel) | |
e17ddecc YC |
1334 | { |
1335 | int ret; | |
0cef83a5 | 1336 | int te_gpio_irq; |
e17ddecc | 1337 | |
295e7954 | 1338 | dsi->te_gpio = of_get_named_gpio(panel->of_node, "te-gpios", 0); |
22e098da AH |
1339 | if (dsi->te_gpio == -ENOENT) |
1340 | return 0; | |
1341 | ||
e17ddecc | 1342 | if (!gpio_is_valid(dsi->te_gpio)) { |
e17ddecc | 1343 | ret = dsi->te_gpio; |
22e098da | 1344 | dev_err(dsi->dev, "cannot get te-gpios, %d\n", ret); |
e17ddecc YC |
1345 | goto out; |
1346 | } | |
1347 | ||
51d1deca | 1348 | ret = gpio_request(dsi->te_gpio, "te_gpio"); |
e17ddecc YC |
1349 | if (ret) { |
1350 | dev_err(dsi->dev, "gpio request failed with %d\n", ret); | |
1351 | goto out; | |
1352 | } | |
1353 | ||
0cef83a5 | 1354 | te_gpio_irq = gpio_to_irq(dsi->te_gpio); |
0cef83a5 | 1355 | irq_set_status_flags(te_gpio_irq, IRQ_NOAUTOEN); |
51d1deca | 1356 | |
0cef83a5 | 1357 | ret = request_threaded_irq(te_gpio_irq, exynos_dsi_te_irq_handler, NULL, |
e17ddecc YC |
1358 | IRQF_TRIGGER_RISING, "TE", dsi); |
1359 | if (ret) { | |
1360 | dev_err(dsi->dev, "request interrupt failed with %d\n", ret); | |
1361 | gpio_free(dsi->te_gpio); | |
1362 | goto out; | |
1363 | } | |
1364 | ||
1365 | out: | |
1366 | return ret; | |
1367 | } | |
1368 | ||
1369 | static void exynos_dsi_unregister_te_irq(struct exynos_dsi *dsi) | |
1370 | { | |
1371 | if (gpio_is_valid(dsi->te_gpio)) { | |
1372 | free_irq(gpio_to_irq(dsi->te_gpio), dsi); | |
1373 | gpio_free(dsi->te_gpio); | |
1374 | dsi->te_gpio = -ENOENT; | |
1375 | } | |
1376 | } | |
1377 | ||
2b8376c8 | 1378 | static void exynos_dsi_enable(struct drm_encoder *encoder) |
7eb8f069 | 1379 | { |
cf67cc9a | 1380 | struct exynos_dsi *dsi = encoder_to_dsi(encoder); |
f66ff55a | 1381 | struct drm_bridge *iter; |
7eb8f069 AH |
1382 | int ret; |
1383 | ||
1384 | if (dsi->state & DSIM_STATE_ENABLED) | |
b6595dc7 | 1385 | return; |
7eb8f069 | 1386 | |
ba6e4779 | 1387 | pm_runtime_get_sync(dsi->dev); |
0e480f6f HH |
1388 | dsi->state |= DSIM_STATE_ENABLED; |
1389 | ||
8a08f671 MP |
1390 | if (dsi->panel) { |
1391 | ret = drm_panel_prepare(dsi->panel); | |
1392 | if (ret < 0) | |
1393 | goto err_put_sync; | |
1394 | } else { | |
f66ff55a BB |
1395 | list_for_each_entry_reverse(iter, &dsi->bridge_chain, |
1396 | chain_node) { | |
1397 | if (iter->funcs->pre_enable) | |
1398 | iter->funcs->pre_enable(iter); | |
1399 | } | |
7eb8f069 AH |
1400 | } |
1401 | ||
1402 | exynos_dsi_set_display_mode(dsi); | |
1403 | exynos_dsi_set_display_enable(dsi, true); | |
1404 | ||
8a08f671 MP |
1405 | if (dsi->panel) { |
1406 | ret = drm_panel_enable(dsi->panel); | |
1407 | if (ret < 0) | |
1408 | goto err_display_disable; | |
1409 | } else { | |
f66ff55a BB |
1410 | list_for_each_entry(iter, &dsi->bridge_chain, chain_node) { |
1411 | if (iter->funcs->enable) | |
1412 | iter->funcs->enable(iter); | |
1413 | } | |
cdfb8694 AK |
1414 | } |
1415 | ||
0e480f6f | 1416 | dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE; |
8a08f671 MP |
1417 | return; |
1418 | ||
1419 | err_display_disable: | |
1420 | exynos_dsi_set_display_enable(dsi, false); | |
1421 | drm_panel_unprepare(dsi->panel); | |
1422 | ||
1423 | err_put_sync: | |
1424 | dsi->state &= ~DSIM_STATE_ENABLED; | |
1425 | pm_runtime_put(dsi->dev); | |
7eb8f069 AH |
1426 | } |
1427 | ||
2b8376c8 | 1428 | static void exynos_dsi_disable(struct drm_encoder *encoder) |
7eb8f069 | 1429 | { |
cf67cc9a | 1430 | struct exynos_dsi *dsi = encoder_to_dsi(encoder); |
f66ff55a | 1431 | struct drm_bridge *iter; |
b6595dc7 | 1432 | |
7eb8f069 AH |
1433 | if (!(dsi->state & DSIM_STATE_ENABLED)) |
1434 | return; | |
1435 | ||
0e480f6f HH |
1436 | dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE; |
1437 | ||
7eb8f069 | 1438 | drm_panel_disable(dsi->panel); |
f66ff55a BB |
1439 | |
1440 | list_for_each_entry_reverse(iter, &dsi->bridge_chain, chain_node) { | |
1441 | if (iter->funcs->disable) | |
1442 | iter->funcs->disable(iter); | |
1443 | } | |
1444 | ||
cdfb8694 AK |
1445 | exynos_dsi_set_display_enable(dsi, false); |
1446 | drm_panel_unprepare(dsi->panel); | |
f66ff55a BB |
1447 | |
1448 | list_for_each_entry(iter, &dsi->bridge_chain, chain_node) { | |
1449 | if (iter->funcs->post_disable) | |
1450 | iter->funcs->post_disable(iter); | |
1451 | } | |
1452 | ||
7eb8f069 | 1453 | dsi->state &= ~DSIM_STATE_ENABLED; |
ba6e4779 | 1454 | pm_runtime_put_sync(dsi->dev); |
7eb8f069 AH |
1455 | } |
1456 | ||
7eb8f069 AH |
1457 | static enum drm_connector_status |
1458 | exynos_dsi_detect(struct drm_connector *connector, bool force) | |
1459 | { | |
295e7954 | 1460 | return connector->status; |
7eb8f069 AH |
1461 | } |
1462 | ||
1463 | static void exynos_dsi_connector_destroy(struct drm_connector *connector) | |
1464 | { | |
0ae46015 AH |
1465 | drm_connector_unregister(connector); |
1466 | drm_connector_cleanup(connector); | |
1467 | connector->dev = NULL; | |
7eb8f069 AH |
1468 | } |
1469 | ||
800ba2b5 | 1470 | static const struct drm_connector_funcs exynos_dsi_connector_funcs = { |
7eb8f069 AH |
1471 | .detect = exynos_dsi_detect, |
1472 | .fill_modes = drm_helper_probe_single_connector_modes, | |
1473 | .destroy = exynos_dsi_connector_destroy, | |
4ea9526b GP |
1474 | .reset = drm_atomic_helper_connector_reset, |
1475 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, | |
1476 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, | |
7eb8f069 AH |
1477 | }; |
1478 | ||
1479 | static int exynos_dsi_get_modes(struct drm_connector *connector) | |
1480 | { | |
1481 | struct exynos_dsi *dsi = connector_to_dsi(connector); | |
1482 | ||
1483 | if (dsi->panel) | |
06c4a9c2 | 1484 | return drm_panel_get_modes(dsi->panel, connector); |
7eb8f069 AH |
1485 | |
1486 | return 0; | |
1487 | } | |
1488 | ||
800ba2b5 | 1489 | static const struct drm_connector_helper_funcs exynos_dsi_connector_helper_funcs = { |
7eb8f069 | 1490 | .get_modes = exynos_dsi_get_modes, |
7eb8f069 AH |
1491 | }; |
1492 | ||
2b8376c8 | 1493 | static int exynos_dsi_create_connector(struct drm_encoder *encoder) |
7eb8f069 | 1494 | { |
2b8376c8 | 1495 | struct exynos_dsi *dsi = encoder_to_dsi(encoder); |
7eb8f069 | 1496 | struct drm_connector *connector = &dsi->connector; |
deee3284 | 1497 | struct drm_device *drm = encoder->dev; |
7eb8f069 AH |
1498 | int ret; |
1499 | ||
7eb8f069 AH |
1500 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
1501 | ||
deee3284 | 1502 | ret = drm_connector_init(drm, connector, &exynos_dsi_connector_funcs, |
7eb8f069 AH |
1503 | DRM_MODE_CONNECTOR_DSI); |
1504 | if (ret) { | |
6f83d208 ID |
1505 | DRM_DEV_ERROR(dsi->dev, |
1506 | "Failed to initialize connector with drm\n"); | |
7eb8f069 AH |
1507 | return ret; |
1508 | } | |
1509 | ||
295e7954 | 1510 | connector->status = connector_status_disconnected; |
7eb8f069 | 1511 | drm_connector_helper_add(connector, &exynos_dsi_connector_helper_funcs); |
cde4c44d | 1512 | drm_connector_attach_encoder(connector, encoder); |
deee3284 AH |
1513 | if (!drm->registered) |
1514 | return 0; | |
7eb8f069 | 1515 | |
deee3284 AH |
1516 | connector->funcs->reset(connector); |
1517 | drm_fb_helper_add_one_connector(drm->fb_helper, connector); | |
1518 | drm_connector_register(connector); | |
7eb8f069 AH |
1519 | return 0; |
1520 | } | |
1521 | ||
800ba2b5 | 1522 | static const struct drm_encoder_helper_funcs exynos_dsi_encoder_helper_funcs = { |
b6595dc7 GP |
1523 | .enable = exynos_dsi_enable, |
1524 | .disable = exynos_dsi_disable, | |
7eb8f069 AH |
1525 | }; |
1526 | ||
800ba2b5 | 1527 | static const struct drm_encoder_funcs exynos_dsi_encoder_funcs = { |
2b8376c8 GP |
1528 | .destroy = drm_encoder_cleanup, |
1529 | }; | |
1530 | ||
bd024b86 | 1531 | MODULE_DEVICE_TABLE(of, exynos_dsi_of_match); |
7eb8f069 | 1532 | |
295e7954 AH |
1533 | static int exynos_dsi_host_attach(struct mipi_dsi_host *host, |
1534 | struct mipi_dsi_device *device) | |
1535 | { | |
1536 | struct exynos_dsi *dsi = host_to_dsi(host); | |
6afb7721 MP |
1537 | struct drm_encoder *encoder = &dsi->encoder; |
1538 | struct drm_device *drm = encoder->dev; | |
1539 | struct drm_bridge *out_bridge; | |
1540 | ||
1541 | out_bridge = of_drm_find_bridge(device->dev.of_node); | |
1542 | if (out_bridge) { | |
1543 | drm_bridge_attach(encoder, out_bridge, NULL); | |
1544 | dsi->out_bridge = out_bridge; | |
f66ff55a | 1545 | list_splice_init(&encoder->bridge_chain, &dsi->bridge_chain); |
6afb7721 MP |
1546 | } else { |
1547 | int ret = exynos_dsi_create_connector(encoder); | |
1548 | ||
1549 | if (ret) { | |
6f83d208 ID |
1550 | DRM_DEV_ERROR(dsi->dev, |
1551 | "failed to create connector ret = %d\n", | |
1552 | ret); | |
6afb7721 MP |
1553 | drm_encoder_cleanup(encoder); |
1554 | return ret; | |
1555 | } | |
1556 | ||
1557 | dsi->panel = of_drm_find_panel(device->dev.of_node); | |
8727b230 DC |
1558 | if (IS_ERR(dsi->panel)) { |
1559 | dsi->panel = NULL; | |
1560 | } else { | |
6afb7721 MP |
1561 | drm_panel_attach(dsi->panel, &dsi->connector); |
1562 | dsi->connector.status = connector_status_connected; | |
1563 | } | |
1564 | } | |
295e7954 AH |
1565 | |
1566 | /* | |
1567 | * This is a temporary solution and should be made by more generic way. | |
1568 | * | |
1569 | * If attached panel device is for command mode one, dsi should register | |
1570 | * TE interrupt handler. | |
1571 | */ | |
1572 | if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO)) { | |
1573 | int ret = exynos_dsi_register_te_irq(dsi, &device->dev); | |
1574 | if (ret) | |
1575 | return ret; | |
1576 | } | |
1577 | ||
1578 | mutex_lock(&drm->mode_config.mutex); | |
1579 | ||
1580 | dsi->lanes = device->lanes; | |
1581 | dsi->format = device->format; | |
1582 | dsi->mode_flags = device->mode_flags; | |
c038f538 AH |
1583 | exynos_drm_crtc_get_by_type(drm, EXYNOS_DISPLAY_TYPE_LCD)->i80_mode = |
1584 | !(dsi->mode_flags & MIPI_DSI_MODE_VIDEO); | |
295e7954 AH |
1585 | |
1586 | mutex_unlock(&drm->mode_config.mutex); | |
1587 | ||
1588 | if (drm->mode_config.poll_enabled) | |
1589 | drm_kms_helper_hotplug_event(drm); | |
1590 | ||
1591 | return 0; | |
1592 | } | |
1593 | ||
1594 | static int exynos_dsi_host_detach(struct mipi_dsi_host *host, | |
1595 | struct mipi_dsi_device *device) | |
1596 | { | |
1597 | struct exynos_dsi *dsi = host_to_dsi(host); | |
6afb7721 | 1598 | struct drm_device *drm = dsi->encoder.dev; |
295e7954 AH |
1599 | |
1600 | if (dsi->panel) { | |
6afb7721 | 1601 | mutex_lock(&drm->mode_config.mutex); |
295e7954 AH |
1602 | exynos_dsi_disable(&dsi->encoder); |
1603 | drm_panel_detach(dsi->panel); | |
1604 | dsi->panel = NULL; | |
1605 | dsi->connector.status = connector_status_disconnected; | |
6afb7721 MP |
1606 | mutex_unlock(&drm->mode_config.mutex); |
1607 | } else { | |
1608 | if (dsi->out_bridge->funcs->detach) | |
1609 | dsi->out_bridge->funcs->detach(dsi->out_bridge); | |
1610 | dsi->out_bridge = NULL; | |
05193dc3 | 1611 | INIT_LIST_HEAD(&dsi->bridge_chain); |
295e7954 AH |
1612 | } |
1613 | ||
295e7954 AH |
1614 | if (drm->mode_config.poll_enabled) |
1615 | drm_kms_helper_hotplug_event(drm); | |
1616 | ||
1617 | exynos_dsi_unregister_te_irq(dsi); | |
1618 | ||
1619 | return 0; | |
1620 | } | |
1621 | ||
1622 | static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host, | |
1623 | const struct mipi_dsi_msg *msg) | |
1624 | { | |
1625 | struct exynos_dsi *dsi = host_to_dsi(host); | |
1626 | struct exynos_dsi_transfer xfer; | |
1627 | int ret; | |
1628 | ||
1629 | if (!(dsi->state & DSIM_STATE_ENABLED)) | |
1630 | return -EINVAL; | |
1631 | ||
1632 | if (!(dsi->state & DSIM_STATE_INITIALIZED)) { | |
1633 | ret = exynos_dsi_init(dsi); | |
1634 | if (ret) | |
1635 | return ret; | |
1636 | dsi->state |= DSIM_STATE_INITIALIZED; | |
1637 | } | |
1638 | ||
1639 | ret = mipi_dsi_create_packet(&xfer.packet, msg); | |
1640 | if (ret < 0) | |
1641 | return ret; | |
1642 | ||
1643 | xfer.rx_len = msg->rx_len; | |
1644 | xfer.rx_payload = msg->rx_buf; | |
1645 | xfer.flags = msg->flags; | |
1646 | ||
1647 | ret = exynos_dsi_transfer(dsi, &xfer); | |
1648 | return (ret < 0) ? ret : xfer.rx_done; | |
1649 | } | |
1650 | ||
1651 | static const struct mipi_dsi_host_ops exynos_dsi_ops = { | |
1652 | .attach = exynos_dsi_host_attach, | |
1653 | .detach = exynos_dsi_host_detach, | |
1654 | .transfer = exynos_dsi_host_transfer, | |
1655 | }; | |
1656 | ||
7eb8f069 AH |
1657 | static int exynos_dsi_of_read_u32(const struct device_node *np, |
1658 | const char *propname, u32 *out_value) | |
1659 | { | |
1660 | int ret = of_property_read_u32(np, propname, out_value); | |
1661 | ||
1662 | if (ret < 0) | |
4bf99144 | 1663 | pr_err("%pOF: failed to get '%s' property\n", np, propname); |
7eb8f069 AH |
1664 | |
1665 | return ret; | |
1666 | } | |
1667 | ||
1668 | enum { | |
1669 | DSI_PORT_IN, | |
1670 | DSI_PORT_OUT | |
1671 | }; | |
1672 | ||
1673 | static int exynos_dsi_parse_dt(struct exynos_dsi *dsi) | |
1674 | { | |
1675 | struct device *dev = dsi->dev; | |
1676 | struct device_node *node = dev->of_node; | |
7eb8f069 AH |
1677 | int ret; |
1678 | ||
1679 | ret = exynos_dsi_of_read_u32(node, "samsung,pll-clock-frequency", | |
1680 | &dsi->pll_clk_rate); | |
1681 | if (ret < 0) | |
1682 | return ret; | |
1683 | ||
f2921d8c | 1684 | ret = exynos_dsi_of_read_u32(node, "samsung,burst-clock-frequency", |
7eb8f069 AH |
1685 | &dsi->burst_clk_rate); |
1686 | if (ret < 0) | |
f2921d8c | 1687 | return ret; |
7eb8f069 | 1688 | |
f2921d8c | 1689 | ret = exynos_dsi_of_read_u32(node, "samsung,esc-clock-frequency", |
7eb8f069 | 1690 | &dsi->esc_clk_rate); |
f5f3b9ba | 1691 | if (ret < 0) |
f2921d8c | 1692 | return ret; |
f5f3b9ba | 1693 | |
2782622e | 1694 | dsi->in_bridge_node = of_graph_get_remote_node(node, DSI_PORT_IN, 0); |
7eb8f069 | 1695 | |
f2921d8c | 1696 | return 0; |
7eb8f069 AH |
1697 | } |
1698 | ||
f37cd5e8 ID |
1699 | static int exynos_dsi_bind(struct device *dev, struct device *master, |
1700 | void *data) | |
1701 | { | |
2b8376c8 GP |
1702 | struct drm_encoder *encoder = dev_get_drvdata(dev); |
1703 | struct exynos_dsi *dsi = encoder_to_dsi(encoder); | |
f37cd5e8 | 1704 | struct drm_device *drm_dev = data; |
2782622e | 1705 | struct drm_bridge *in_bridge; |
f37cd5e8 ID |
1706 | int ret; |
1707 | ||
2b8376c8 | 1708 | drm_encoder_init(drm_dev, encoder, &exynos_dsi_encoder_funcs, |
13a3d91f | 1709 | DRM_MODE_ENCODER_TMDS, NULL); |
2b8376c8 GP |
1710 | |
1711 | drm_encoder_helper_add(encoder, &exynos_dsi_encoder_helper_funcs); | |
1712 | ||
1ca582f1 AH |
1713 | ret = exynos_drm_set_possible_crtcs(encoder, EXYNOS_DISPLAY_TYPE_LCD); |
1714 | if (ret < 0) | |
1715 | return ret; | |
1716 | ||
2782622e MP |
1717 | if (dsi->in_bridge_node) { |
1718 | in_bridge = of_drm_find_bridge(dsi->in_bridge_node); | |
1719 | if (in_bridge) | |
1720 | drm_bridge_attach(encoder, in_bridge, NULL); | |
c9948920 | 1721 | } |
f5f3b9ba | 1722 | |
f37cd5e8 ID |
1723 | return mipi_dsi_host_register(&dsi->dsi_host); |
1724 | } | |
1725 | ||
1726 | static void exynos_dsi_unbind(struct device *dev, struct device *master, | |
1727 | void *data) | |
1728 | { | |
2b8376c8 | 1729 | struct drm_encoder *encoder = dev_get_drvdata(dev); |
cf67cc9a | 1730 | struct exynos_dsi *dsi = encoder_to_dsi(encoder); |
f37cd5e8 | 1731 | |
cf67cc9a | 1732 | exynos_dsi_disable(encoder); |
f37cd5e8 | 1733 | |
0ae46015 | 1734 | mipi_dsi_host_unregister(&dsi->dsi_host); |
f37cd5e8 ID |
1735 | } |
1736 | ||
f37cd5e8 ID |
1737 | static const struct component_ops exynos_dsi_component_ops = { |
1738 | .bind = exynos_dsi_bind, | |
1739 | .unbind = exynos_dsi_unbind, | |
1740 | }; | |
1741 | ||
7eb8f069 AH |
1742 | static int exynos_dsi_probe(struct platform_device *pdev) |
1743 | { | |
2900c69c | 1744 | struct device *dev = &pdev->dev; |
7eb8f069 AH |
1745 | struct resource *res; |
1746 | struct exynos_dsi *dsi; | |
0ff03fd1 | 1747 | int ret, i; |
7eb8f069 | 1748 | |
2900c69c AH |
1749 | dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); |
1750 | if (!dsi) | |
1751 | return -ENOMEM; | |
1752 | ||
e17ddecc YC |
1753 | /* To be checked as invalid one */ |
1754 | dsi->te_gpio = -ENOENT; | |
1755 | ||
7eb8f069 AH |
1756 | init_completion(&dsi->completed); |
1757 | spin_lock_init(&dsi->transfer_lock); | |
1758 | INIT_LIST_HEAD(&dsi->transfer_list); | |
05193dc3 | 1759 | INIT_LIST_HEAD(&dsi->bridge_chain); |
7eb8f069 AH |
1760 | |
1761 | dsi->dsi_host.ops = &exynos_dsi_ops; | |
e2d2a1e0 | 1762 | dsi->dsi_host.dev = dev; |
7eb8f069 | 1763 | |
e2d2a1e0 | 1764 | dsi->dev = dev; |
2154ac92 | 1765 | dsi->driver_data = of_device_get_match_data(dev); |
7eb8f069 AH |
1766 | |
1767 | ret = exynos_dsi_parse_dt(dsi); | |
1768 | if (ret) | |
86650408 | 1769 | return ret; |
7eb8f069 AH |
1770 | |
1771 | dsi->supplies[0].supply = "vddcore"; | |
1772 | dsi->supplies[1].supply = "vddio"; | |
e2d2a1e0 | 1773 | ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies), |
7eb8f069 AH |
1774 | dsi->supplies); |
1775 | if (ret) { | |
0a9d1e3f MS |
1776 | if (ret != -EPROBE_DEFER) |
1777 | dev_info(dev, "failed to get regulators: %d\n", ret); | |
1778 | return ret; | |
7eb8f069 AH |
1779 | } |
1780 | ||
a86854d0 KC |
1781 | dsi->clks = devm_kcalloc(dev, |
1782 | dsi->driver_data->num_clks, sizeof(*dsi->clks), | |
0ff03fd1 | 1783 | GFP_KERNEL); |
e6f988a4 HH |
1784 | if (!dsi->clks) |
1785 | return -ENOMEM; | |
1786 | ||
0ff03fd1 HH |
1787 | for (i = 0; i < dsi->driver_data->num_clks; i++) { |
1788 | dsi->clks[i] = devm_clk_get(dev, clk_names[i]); | |
1789 | if (IS_ERR(dsi->clks[i])) { | |
1790 | if (strcmp(clk_names[i], "sclk_mipi") == 0) { | |
c0fd99d6 MS |
1791 | dsi->clks[i] = devm_clk_get(dev, |
1792 | OLD_SCLK_MIPI_CLK_NAME); | |
1793 | if (!IS_ERR(dsi->clks[i])) | |
1794 | continue; | |
0ff03fd1 | 1795 | } |
7eb8f069 | 1796 | |
0ff03fd1 HH |
1797 | dev_info(dev, "failed to get the clock: %s\n", |
1798 | clk_names[i]); | |
1799 | return PTR_ERR(dsi->clks[i]); | |
1800 | } | |
7eb8f069 AH |
1801 | } |
1802 | ||
1803 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
e2d2a1e0 | 1804 | dsi->reg_base = devm_ioremap_resource(dev, res); |
293d3f6a | 1805 | if (IS_ERR(dsi->reg_base)) { |
e2d2a1e0 | 1806 | dev_err(dev, "failed to remap io region\n"); |
86650408 | 1807 | return PTR_ERR(dsi->reg_base); |
7eb8f069 AH |
1808 | } |
1809 | ||
e2d2a1e0 | 1810 | dsi->phy = devm_phy_get(dev, "dsim"); |
7eb8f069 | 1811 | if (IS_ERR(dsi->phy)) { |
e2d2a1e0 | 1812 | dev_info(dev, "failed to get dsim phy\n"); |
86650408 | 1813 | return PTR_ERR(dsi->phy); |
7eb8f069 AH |
1814 | } |
1815 | ||
1816 | dsi->irq = platform_get_irq(pdev, 0); | |
1817 | if (dsi->irq < 0) { | |
e2d2a1e0 | 1818 | dev_err(dev, "failed to request dsi irq resource\n"); |
86650408 | 1819 | return dsi->irq; |
7eb8f069 AH |
1820 | } |
1821 | ||
1822 | irq_set_status_flags(dsi->irq, IRQ_NOAUTOEN); | |
e2d2a1e0 | 1823 | ret = devm_request_threaded_irq(dev, dsi->irq, NULL, |
7eb8f069 | 1824 | exynos_dsi_irq, IRQF_ONESHOT, |
e2d2a1e0 | 1825 | dev_name(dev), dsi); |
7eb8f069 | 1826 | if (ret) { |
e2d2a1e0 | 1827 | dev_err(dev, "failed to request dsi irq\n"); |
86650408 | 1828 | return ret; |
7eb8f069 AH |
1829 | } |
1830 | ||
cf67cc9a | 1831 | platform_set_drvdata(pdev, &dsi->encoder); |
7eb8f069 | 1832 | |
ba6e4779 ID |
1833 | pm_runtime_enable(dev); |
1834 | ||
86650408 | 1835 | return component_add(dev, &exynos_dsi_component_ops); |
7eb8f069 AH |
1836 | } |
1837 | ||
1838 | static int exynos_dsi_remove(struct platform_device *pdev) | |
1839 | { | |
70505c2e HK |
1840 | struct exynos_dsi *dsi = platform_get_drvdata(pdev); |
1841 | ||
2782622e | 1842 | of_node_put(dsi->in_bridge_node); |
70505c2e | 1843 | |
ba6e4779 ID |
1844 | pm_runtime_disable(&pdev->dev); |
1845 | ||
df5225bc | 1846 | component_del(&pdev->dev, &exynos_dsi_component_ops); |
df5225bc | 1847 | |
7eb8f069 AH |
1848 | return 0; |
1849 | } | |
1850 | ||
010848a7 | 1851 | static int __maybe_unused exynos_dsi_suspend(struct device *dev) |
ba6e4779 ID |
1852 | { |
1853 | struct drm_encoder *encoder = dev_get_drvdata(dev); | |
1854 | struct exynos_dsi *dsi = encoder_to_dsi(encoder); | |
2154ac92 | 1855 | const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; |
ba6e4779 ID |
1856 | int ret, i; |
1857 | ||
1858 | usleep_range(10000, 20000); | |
1859 | ||
1860 | if (dsi->state & DSIM_STATE_INITIALIZED) { | |
1861 | dsi->state &= ~DSIM_STATE_INITIALIZED; | |
1862 | ||
1863 | exynos_dsi_disable_clock(dsi); | |
1864 | ||
1865 | exynos_dsi_disable_irq(dsi); | |
1866 | } | |
1867 | ||
1868 | dsi->state &= ~DSIM_STATE_CMD_LPM; | |
1869 | ||
1870 | phy_power_off(dsi->phy); | |
1871 | ||
1872 | for (i = driver_data->num_clks - 1; i > -1; i--) | |
1873 | clk_disable_unprepare(dsi->clks[i]); | |
1874 | ||
1875 | ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); | |
1876 | if (ret < 0) | |
1877 | dev_err(dsi->dev, "cannot disable regulators %d\n", ret); | |
1878 | ||
1879 | return 0; | |
1880 | } | |
1881 | ||
010848a7 | 1882 | static int __maybe_unused exynos_dsi_resume(struct device *dev) |
ba6e4779 ID |
1883 | { |
1884 | struct drm_encoder *encoder = dev_get_drvdata(dev); | |
1885 | struct exynos_dsi *dsi = encoder_to_dsi(encoder); | |
2154ac92 | 1886 | const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; |
ba6e4779 ID |
1887 | int ret, i; |
1888 | ||
1889 | ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies); | |
1890 | if (ret < 0) { | |
1891 | dev_err(dsi->dev, "cannot enable regulators %d\n", ret); | |
1892 | return ret; | |
1893 | } | |
1894 | ||
1895 | for (i = 0; i < driver_data->num_clks; i++) { | |
1896 | ret = clk_prepare_enable(dsi->clks[i]); | |
1897 | if (ret < 0) | |
1898 | goto err_clk; | |
1899 | } | |
1900 | ||
1901 | ret = phy_power_on(dsi->phy); | |
1902 | if (ret < 0) { | |
1903 | dev_err(dsi->dev, "cannot enable phy %d\n", ret); | |
1904 | goto err_clk; | |
1905 | } | |
1906 | ||
1907 | return 0; | |
1908 | ||
1909 | err_clk: | |
1910 | while (--i > -1) | |
1911 | clk_disable_unprepare(dsi->clks[i]); | |
1912 | regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); | |
1913 | ||
1914 | return ret; | |
1915 | } | |
ba6e4779 ID |
1916 | |
1917 | static const struct dev_pm_ops exynos_dsi_pm_ops = { | |
1918 | SET_RUNTIME_PM_OPS(exynos_dsi_suspend, exynos_dsi_resume, NULL) | |
7e915746 MS |
1919 | SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, |
1920 | pm_runtime_force_resume) | |
ba6e4779 ID |
1921 | }; |
1922 | ||
7eb8f069 AH |
1923 | struct platform_driver dsi_driver = { |
1924 | .probe = exynos_dsi_probe, | |
1925 | .remove = exynos_dsi_remove, | |
1926 | .driver = { | |
1927 | .name = "exynos-dsi", | |
1928 | .owner = THIS_MODULE, | |
ba6e4779 | 1929 | .pm = &exynos_dsi_pm_ops, |
7eb8f069 AH |
1930 | .of_match_table = exynos_dsi_of_match, |
1931 | }, | |
1932 | }; | |
1933 | ||
1934 | MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>"); | |
1935 | MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>"); | |
1936 | MODULE_DESCRIPTION("Samsung SoC MIPI DSI Master"); | |
1937 | MODULE_LICENSE("GPL v2"); |