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7eb8f069 AH |
1 | /* |
2 | * Samsung SoC MIPI DSI Master driver. | |
3 | * | |
4 | * Copyright (c) 2014 Samsung Electronics Co., Ltd | |
5 | * | |
6 | * Contacts: Tomasz Figa <t.figa@samsung.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <drm/drmP.h> | |
14 | #include <drm/drm_crtc_helper.h> | |
15 | #include <drm/drm_mipi_dsi.h> | |
16 | #include <drm/drm_panel.h> | |
4ea9526b | 17 | #include <drm/drm_atomic_helper.h> |
7eb8f069 AH |
18 | |
19 | #include <linux/clk.h> | |
e17ddecc | 20 | #include <linux/gpio/consumer.h> |
7eb8f069 | 21 | #include <linux/irq.h> |
9a320415 | 22 | #include <linux/of_device.h> |
e17ddecc | 23 | #include <linux/of_gpio.h> |
f5f3b9ba | 24 | #include <linux/of_graph.h> |
7eb8f069 AH |
25 | #include <linux/phy/phy.h> |
26 | #include <linux/regulator/consumer.h> | |
f37cd5e8 | 27 | #include <linux/component.h> |
7eb8f069 AH |
28 | |
29 | #include <video/mipi_display.h> | |
30 | #include <video/videomode.h> | |
31 | ||
e17ddecc | 32 | #include "exynos_drm_crtc.h" |
7eb8f069 AH |
33 | #include "exynos_drm_drv.h" |
34 | ||
35 | /* returns true iff both arguments logically differs */ | |
36 | #define NEQV(a, b) (!(a) ^ !(b)) | |
37 | ||
7eb8f069 AH |
38 | /* DSIM_STATUS */ |
39 | #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0) | |
40 | #define DSIM_STOP_STATE_CLK (1 << 8) | |
41 | #define DSIM_TX_READY_HS_CLK (1 << 10) | |
42 | #define DSIM_PLL_STABLE (1 << 31) | |
43 | ||
44 | /* DSIM_SWRST */ | |
45 | #define DSIM_FUNCRST (1 << 16) | |
46 | #define DSIM_SWRST (1 << 0) | |
47 | ||
48 | /* DSIM_TIMEOUT */ | |
49 | #define DSIM_LPDR_TIMEOUT(x) ((x) << 0) | |
50 | #define DSIM_BTA_TIMEOUT(x) ((x) << 16) | |
51 | ||
52 | /* DSIM_CLKCTRL */ | |
53 | #define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0) | |
54 | #define DSIM_ESC_PRESCALER_MASK (0xffff << 0) | |
55 | #define DSIM_LANE_ESC_CLK_EN_CLK (1 << 19) | |
56 | #define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20) | |
57 | #define DSIM_LANE_ESC_CLK_EN_DATA_MASK (0xf << 20) | |
58 | #define DSIM_BYTE_CLKEN (1 << 24) | |
59 | #define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25) | |
60 | #define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25) | |
61 | #define DSIM_PLL_BYPASS (1 << 27) | |
62 | #define DSIM_ESC_CLKEN (1 << 28) | |
63 | #define DSIM_TX_REQUEST_HSCLK (1 << 31) | |
64 | ||
65 | /* DSIM_CONFIG */ | |
66 | #define DSIM_LANE_EN_CLK (1 << 0) | |
67 | #define DSIM_LANE_EN(x) (((x) & 0xf) << 1) | |
68 | #define DSIM_NUM_OF_DATA_LANE(x) (((x) & 0x3) << 5) | |
69 | #define DSIM_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8) | |
70 | #define DSIM_MAIN_PIX_FORMAT_MASK (0x7 << 12) | |
71 | #define DSIM_MAIN_PIX_FORMAT_RGB888 (0x7 << 12) | |
72 | #define DSIM_MAIN_PIX_FORMAT_RGB666 (0x6 << 12) | |
73 | #define DSIM_MAIN_PIX_FORMAT_RGB666_P (0x5 << 12) | |
74 | #define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12) | |
75 | #define DSIM_SUB_VC (((x) & 0x3) << 16) | |
76 | #define DSIM_MAIN_VC (((x) & 0x3) << 18) | |
77 | #define DSIM_HSA_MODE (1 << 20) | |
78 | #define DSIM_HBP_MODE (1 << 21) | |
79 | #define DSIM_HFP_MODE (1 << 22) | |
80 | #define DSIM_HSE_MODE (1 << 23) | |
81 | #define DSIM_AUTO_MODE (1 << 24) | |
82 | #define DSIM_VIDEO_MODE (1 << 25) | |
83 | #define DSIM_BURST_MODE (1 << 26) | |
84 | #define DSIM_SYNC_INFORM (1 << 27) | |
85 | #define DSIM_EOT_DISABLE (1 << 28) | |
86 | #define DSIM_MFLUSH_VS (1 << 29) | |
78d3a8c6 ID |
87 | /* This flag is valid only for exynos3250/3472/4415/5260/5430 */ |
88 | #define DSIM_CLKLANE_STOP (1 << 30) | |
7eb8f069 AH |
89 | |
90 | /* DSIM_ESCMODE */ | |
91 | #define DSIM_TX_TRIGGER_RST (1 << 4) | |
92 | #define DSIM_TX_LPDT_LP (1 << 6) | |
93 | #define DSIM_CMD_LPDT_LP (1 << 7) | |
94 | #define DSIM_FORCE_BTA (1 << 16) | |
95 | #define DSIM_FORCE_STOP_STATE (1 << 20) | |
96 | #define DSIM_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21) | |
97 | #define DSIM_STOP_STATE_CNT_MASK (0x7ff << 21) | |
98 | ||
99 | /* DSIM_MDRESOL */ | |
100 | #define DSIM_MAIN_STAND_BY (1 << 31) | |
d668e8bf HH |
101 | #define DSIM_MAIN_VRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 16) |
102 | #define DSIM_MAIN_HRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 0) | |
7eb8f069 AH |
103 | |
104 | /* DSIM_MVPORCH */ | |
105 | #define DSIM_CMD_ALLOW(x) ((x) << 28) | |
106 | #define DSIM_STABLE_VFP(x) ((x) << 16) | |
107 | #define DSIM_MAIN_VBP(x) ((x) << 0) | |
108 | #define DSIM_CMD_ALLOW_MASK (0xf << 28) | |
109 | #define DSIM_STABLE_VFP_MASK (0x7ff << 16) | |
110 | #define DSIM_MAIN_VBP_MASK (0x7ff << 0) | |
111 | ||
112 | /* DSIM_MHPORCH */ | |
113 | #define DSIM_MAIN_HFP(x) ((x) << 16) | |
114 | #define DSIM_MAIN_HBP(x) ((x) << 0) | |
115 | #define DSIM_MAIN_HFP_MASK ((0xffff) << 16) | |
116 | #define DSIM_MAIN_HBP_MASK ((0xffff) << 0) | |
117 | ||
118 | /* DSIM_MSYNC */ | |
119 | #define DSIM_MAIN_VSA(x) ((x) << 22) | |
120 | #define DSIM_MAIN_HSA(x) ((x) << 0) | |
121 | #define DSIM_MAIN_VSA_MASK ((0x3ff) << 22) | |
122 | #define DSIM_MAIN_HSA_MASK ((0xffff) << 0) | |
123 | ||
124 | /* DSIM_SDRESOL */ | |
125 | #define DSIM_SUB_STANDY(x) ((x) << 31) | |
126 | #define DSIM_SUB_VRESOL(x) ((x) << 16) | |
127 | #define DSIM_SUB_HRESOL(x) ((x) << 0) | |
128 | #define DSIM_SUB_STANDY_MASK ((0x1) << 31) | |
129 | #define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16) | |
130 | #define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0) | |
131 | ||
132 | /* DSIM_INTSRC */ | |
133 | #define DSIM_INT_PLL_STABLE (1 << 31) | |
134 | #define DSIM_INT_SW_RST_RELEASE (1 << 30) | |
135 | #define DSIM_INT_SFR_FIFO_EMPTY (1 << 29) | |
e6f988a4 | 136 | #define DSIM_INT_SFR_HDR_FIFO_EMPTY (1 << 28) |
7eb8f069 AH |
137 | #define DSIM_INT_BTA (1 << 25) |
138 | #define DSIM_INT_FRAME_DONE (1 << 24) | |
139 | #define DSIM_INT_RX_TIMEOUT (1 << 21) | |
140 | #define DSIM_INT_BTA_TIMEOUT (1 << 20) | |
141 | #define DSIM_INT_RX_DONE (1 << 18) | |
142 | #define DSIM_INT_RX_TE (1 << 17) | |
143 | #define DSIM_INT_RX_ACK (1 << 16) | |
144 | #define DSIM_INT_RX_ECC_ERR (1 << 15) | |
145 | #define DSIM_INT_RX_CRC_ERR (1 << 14) | |
146 | ||
147 | /* DSIM_FIFOCTRL */ | |
148 | #define DSIM_RX_DATA_FULL (1 << 25) | |
149 | #define DSIM_RX_DATA_EMPTY (1 << 24) | |
150 | #define DSIM_SFR_HEADER_FULL (1 << 23) | |
151 | #define DSIM_SFR_HEADER_EMPTY (1 << 22) | |
152 | #define DSIM_SFR_PAYLOAD_FULL (1 << 21) | |
153 | #define DSIM_SFR_PAYLOAD_EMPTY (1 << 20) | |
154 | #define DSIM_I80_HEADER_FULL (1 << 19) | |
155 | #define DSIM_I80_HEADER_EMPTY (1 << 18) | |
156 | #define DSIM_I80_PAYLOAD_FULL (1 << 17) | |
157 | #define DSIM_I80_PAYLOAD_EMPTY (1 << 16) | |
158 | #define DSIM_SD_HEADER_FULL (1 << 15) | |
159 | #define DSIM_SD_HEADER_EMPTY (1 << 14) | |
160 | #define DSIM_SD_PAYLOAD_FULL (1 << 13) | |
161 | #define DSIM_SD_PAYLOAD_EMPTY (1 << 12) | |
162 | #define DSIM_MD_HEADER_FULL (1 << 11) | |
163 | #define DSIM_MD_HEADER_EMPTY (1 << 10) | |
164 | #define DSIM_MD_PAYLOAD_FULL (1 << 9) | |
165 | #define DSIM_MD_PAYLOAD_EMPTY (1 << 8) | |
166 | #define DSIM_RX_FIFO (1 << 4) | |
167 | #define DSIM_SFR_FIFO (1 << 3) | |
168 | #define DSIM_I80_FIFO (1 << 2) | |
169 | #define DSIM_SD_FIFO (1 << 1) | |
170 | #define DSIM_MD_FIFO (1 << 0) | |
171 | ||
172 | /* DSIM_PHYACCHR */ | |
173 | #define DSIM_AFC_EN (1 << 14) | |
174 | #define DSIM_AFC_CTL(x) (((x) & 0x7) << 5) | |
175 | ||
176 | /* DSIM_PLLCTRL */ | |
177 | #define DSIM_FREQ_BAND(x) ((x) << 24) | |
178 | #define DSIM_PLL_EN (1 << 23) | |
179 | #define DSIM_PLL_P(x) ((x) << 13) | |
180 | #define DSIM_PLL_M(x) ((x) << 4) | |
181 | #define DSIM_PLL_S(x) ((x) << 1) | |
182 | ||
9a320415 YC |
183 | /* DSIM_PHYCTRL */ |
184 | #define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) & 0x1ff) << 0) | |
e6f988a4 HH |
185 | #define DSIM_PHYCTRL_B_DPHYCTL_VREG_LP (1 << 30) |
186 | #define DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP (1 << 14) | |
9a320415 YC |
187 | |
188 | /* DSIM_PHYTIMING */ | |
189 | #define DSIM_PHYTIMING_LPX(x) ((x) << 8) | |
190 | #define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0) | |
191 | ||
192 | /* DSIM_PHYTIMING1 */ | |
193 | #define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24) | |
194 | #define DSIM_PHYTIMING1_CLK_ZERO(x) ((x) << 16) | |
195 | #define DSIM_PHYTIMING1_CLK_POST(x) ((x) << 8) | |
196 | #define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0) | |
197 | ||
198 | /* DSIM_PHYTIMING2 */ | |
199 | #define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16) | |
200 | #define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8) | |
201 | #define DSIM_PHYTIMING2_HS_TRAIL(x) ((x) << 0) | |
202 | ||
7eb8f069 AH |
203 | #define DSI_MAX_BUS_WIDTH 4 |
204 | #define DSI_NUM_VIRTUAL_CHANNELS 4 | |
205 | #define DSI_TX_FIFO_SIZE 2048 | |
206 | #define DSI_RX_FIFO_SIZE 256 | |
207 | #define DSI_XFER_TIMEOUT_MS 100 | |
208 | #define DSI_RX_FIFO_EMPTY 0x30800002 | |
209 | ||
26269af9 HH |
210 | #define OLD_SCLK_MIPI_CLK_NAME "pll_clk" |
211 | ||
d668e8bf HH |
212 | #define REG_ADDR(dsi, reg_idx) ((dsi)->reg_base + \ |
213 | dsi->driver_data->reg_ofs[(reg_idx)]) | |
214 | #define DSI_WRITE(dsi, reg_idx, val) writel((val), \ | |
215 | REG_ADDR((dsi), (reg_idx))) | |
216 | #define DSI_READ(dsi, reg_idx) readl(REG_ADDR((dsi), (reg_idx))) | |
ba12ac2b | 217 | |
e6f988a4 HH |
218 | static char *clk_names[5] = { "bus_clk", "sclk_mipi", |
219 | "phyclk_mipidphy0_bitclkdiv8", "phyclk_mipidphy0_rxclkesc0", | |
220 | "sclk_rgb_vclk_to_dsim0" }; | |
0ff03fd1 | 221 | |
7eb8f069 AH |
222 | enum exynos_dsi_transfer_type { |
223 | EXYNOS_DSI_TX, | |
224 | EXYNOS_DSI_RX, | |
225 | }; | |
226 | ||
227 | struct exynos_dsi_transfer { | |
228 | struct list_head list; | |
229 | struct completion completed; | |
230 | int result; | |
231 | u8 data_id; | |
232 | u8 data[2]; | |
233 | u16 flags; | |
234 | ||
235 | const u8 *tx_payload; | |
236 | u16 tx_len; | |
237 | u16 tx_done; | |
238 | ||
239 | u8 *rx_payload; | |
240 | u16 rx_len; | |
241 | u16 rx_done; | |
242 | }; | |
243 | ||
244 | #define DSIM_STATE_ENABLED BIT(0) | |
245 | #define DSIM_STATE_INITIALIZED BIT(1) | |
246 | #define DSIM_STATE_CMD_LPM BIT(2) | |
0e480f6f | 247 | #define DSIM_STATE_VIDOUT_AVAILABLE BIT(3) |
7eb8f069 | 248 | |
9a320415 | 249 | struct exynos_dsi_driver_data { |
d668e8bf | 250 | unsigned int *reg_ofs; |
9a320415 | 251 | unsigned int plltmr_reg; |
9a320415 | 252 | unsigned int has_freqband:1; |
78d3a8c6 | 253 | unsigned int has_clklane_stop:1; |
d668e8bf HH |
254 | unsigned int num_clks; |
255 | unsigned int max_freq; | |
256 | unsigned int wait_for_reset; | |
257 | unsigned int num_bits_resol; | |
258 | unsigned int *reg_values; | |
9a320415 YC |
259 | }; |
260 | ||
7eb8f069 | 261 | struct exynos_dsi { |
2900c69c | 262 | struct exynos_drm_display display; |
7eb8f069 AH |
263 | struct mipi_dsi_host dsi_host; |
264 | struct drm_connector connector; | |
7eb8f069 AH |
265 | struct device_node *panel_node; |
266 | struct drm_panel *panel; | |
267 | struct device *dev; | |
268 | ||
269 | void __iomem *reg_base; | |
270 | struct phy *phy; | |
0ff03fd1 | 271 | struct clk **clks; |
7eb8f069 AH |
272 | struct regulator_bulk_data supplies[2]; |
273 | int irq; | |
e17ddecc | 274 | int te_gpio; |
7eb8f069 AH |
275 | |
276 | u32 pll_clk_rate; | |
277 | u32 burst_clk_rate; | |
278 | u32 esc_clk_rate; | |
279 | u32 lanes; | |
280 | u32 mode_flags; | |
281 | u32 format; | |
282 | struct videomode vm; | |
283 | ||
284 | int state; | |
285 | struct drm_property *brightness; | |
286 | struct completion completed; | |
287 | ||
288 | spinlock_t transfer_lock; /* protects transfer_list */ | |
289 | struct list_head transfer_list; | |
9a320415 YC |
290 | |
291 | struct exynos_dsi_driver_data *driver_data; | |
f5f3b9ba | 292 | struct device_node *bridge_node; |
7eb8f069 AH |
293 | }; |
294 | ||
295 | #define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host) | |
296 | #define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector) | |
297 | ||
5cd5db80 AH |
298 | static inline struct exynos_dsi *display_to_dsi(struct exynos_drm_display *d) |
299 | { | |
300 | return container_of(d, struct exynos_dsi, display); | |
301 | } | |
302 | ||
d668e8bf HH |
303 | enum reg_idx { |
304 | DSIM_STATUS_REG, /* Status register */ | |
305 | DSIM_SWRST_REG, /* Software reset register */ | |
306 | DSIM_CLKCTRL_REG, /* Clock control register */ | |
307 | DSIM_TIMEOUT_REG, /* Time out register */ | |
308 | DSIM_CONFIG_REG, /* Configuration register */ | |
309 | DSIM_ESCMODE_REG, /* Escape mode register */ | |
310 | DSIM_MDRESOL_REG, | |
311 | DSIM_MVPORCH_REG, /* Main display Vporch register */ | |
312 | DSIM_MHPORCH_REG, /* Main display Hporch register */ | |
313 | DSIM_MSYNC_REG, /* Main display sync area register */ | |
314 | DSIM_INTSRC_REG, /* Interrupt source register */ | |
315 | DSIM_INTMSK_REG, /* Interrupt mask register */ | |
316 | DSIM_PKTHDR_REG, /* Packet Header FIFO register */ | |
317 | DSIM_PAYLOAD_REG, /* Payload FIFO register */ | |
318 | DSIM_RXFIFO_REG, /* Read FIFO register */ | |
319 | DSIM_FIFOCTRL_REG, /* FIFO status and control register */ | |
320 | DSIM_PLLCTRL_REG, /* PLL control register */ | |
321 | DSIM_PHYCTRL_REG, | |
322 | DSIM_PHYTIMING_REG, | |
323 | DSIM_PHYTIMING1_REG, | |
324 | DSIM_PHYTIMING2_REG, | |
325 | NUM_REGS | |
326 | }; | |
327 | static unsigned int exynos_reg_ofs[] = { | |
328 | [DSIM_STATUS_REG] = 0x00, | |
329 | [DSIM_SWRST_REG] = 0x04, | |
330 | [DSIM_CLKCTRL_REG] = 0x08, | |
331 | [DSIM_TIMEOUT_REG] = 0x0c, | |
332 | [DSIM_CONFIG_REG] = 0x10, | |
333 | [DSIM_ESCMODE_REG] = 0x14, | |
334 | [DSIM_MDRESOL_REG] = 0x18, | |
335 | [DSIM_MVPORCH_REG] = 0x1c, | |
336 | [DSIM_MHPORCH_REG] = 0x20, | |
337 | [DSIM_MSYNC_REG] = 0x24, | |
338 | [DSIM_INTSRC_REG] = 0x2c, | |
339 | [DSIM_INTMSK_REG] = 0x30, | |
340 | [DSIM_PKTHDR_REG] = 0x34, | |
341 | [DSIM_PAYLOAD_REG] = 0x38, | |
342 | [DSIM_RXFIFO_REG] = 0x3c, | |
343 | [DSIM_FIFOCTRL_REG] = 0x44, | |
344 | [DSIM_PLLCTRL_REG] = 0x4c, | |
345 | [DSIM_PHYCTRL_REG] = 0x5c, | |
346 | [DSIM_PHYTIMING_REG] = 0x64, | |
347 | [DSIM_PHYTIMING1_REG] = 0x68, | |
348 | [DSIM_PHYTIMING2_REG] = 0x6c, | |
349 | }; | |
350 | ||
e6f988a4 HH |
351 | static unsigned int exynos5433_reg_ofs[] = { |
352 | [DSIM_STATUS_REG] = 0x04, | |
353 | [DSIM_SWRST_REG] = 0x0C, | |
354 | [DSIM_CLKCTRL_REG] = 0x10, | |
355 | [DSIM_TIMEOUT_REG] = 0x14, | |
356 | [DSIM_CONFIG_REG] = 0x18, | |
357 | [DSIM_ESCMODE_REG] = 0x1C, | |
358 | [DSIM_MDRESOL_REG] = 0x20, | |
359 | [DSIM_MVPORCH_REG] = 0x24, | |
360 | [DSIM_MHPORCH_REG] = 0x28, | |
361 | [DSIM_MSYNC_REG] = 0x2C, | |
362 | [DSIM_INTSRC_REG] = 0x34, | |
363 | [DSIM_INTMSK_REG] = 0x38, | |
364 | [DSIM_PKTHDR_REG] = 0x3C, | |
365 | [DSIM_PAYLOAD_REG] = 0x40, | |
366 | [DSIM_RXFIFO_REG] = 0x44, | |
367 | [DSIM_FIFOCTRL_REG] = 0x4C, | |
368 | [DSIM_PLLCTRL_REG] = 0x94, | |
369 | [DSIM_PHYCTRL_REG] = 0xA4, | |
370 | [DSIM_PHYTIMING_REG] = 0xB4, | |
371 | [DSIM_PHYTIMING1_REG] = 0xB8, | |
372 | [DSIM_PHYTIMING2_REG] = 0xBC, | |
373 | }; | |
374 | ||
d668e8bf HH |
375 | enum reg_value_idx { |
376 | RESET_TYPE, | |
377 | PLL_TIMER, | |
378 | STOP_STATE_CNT, | |
379 | PHYCTRL_ULPS_EXIT, | |
380 | PHYCTRL_VREG_LP, | |
381 | PHYCTRL_SLEW_UP, | |
382 | PHYTIMING_LPX, | |
383 | PHYTIMING_HS_EXIT, | |
384 | PHYTIMING_CLK_PREPARE, | |
385 | PHYTIMING_CLK_ZERO, | |
386 | PHYTIMING_CLK_POST, | |
387 | PHYTIMING_CLK_TRAIL, | |
388 | PHYTIMING_HS_PREPARE, | |
389 | PHYTIMING_HS_ZERO, | |
390 | PHYTIMING_HS_TRAIL | |
391 | }; | |
392 | ||
393 | static unsigned int reg_values[] = { | |
394 | [RESET_TYPE] = DSIM_SWRST, | |
395 | [PLL_TIMER] = 500, | |
396 | [STOP_STATE_CNT] = 0xf, | |
397 | [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af), | |
398 | [PHYCTRL_VREG_LP] = 0, | |
399 | [PHYCTRL_SLEW_UP] = 0, | |
400 | [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06), | |
401 | [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b), | |
402 | [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07), | |
403 | [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27), | |
404 | [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d), | |
405 | [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08), | |
406 | [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09), | |
407 | [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d), | |
408 | [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b), | |
409 | }; | |
410 | ||
e6f988a4 HH |
411 | static unsigned int exynos5433_reg_values[] = { |
412 | [RESET_TYPE] = DSIM_FUNCRST, | |
413 | [PLL_TIMER] = 22200, | |
414 | [STOP_STATE_CNT] = 0xa, | |
415 | [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190), | |
416 | [PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP, | |
417 | [PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP, | |
418 | [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07), | |
419 | [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c), | |
420 | [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), | |
421 | [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d), | |
422 | [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), | |
423 | [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09), | |
424 | [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b), | |
425 | [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10), | |
426 | [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c), | |
427 | }; | |
428 | ||
473462a1 | 429 | static struct exynos_dsi_driver_data exynos3_dsi_driver_data = { |
d668e8bf | 430 | .reg_ofs = exynos_reg_ofs, |
473462a1 ID |
431 | .plltmr_reg = 0x50, |
432 | .has_freqband = 1, | |
433 | .has_clklane_stop = 1, | |
d668e8bf HH |
434 | .num_clks = 2, |
435 | .max_freq = 1000, | |
436 | .wait_for_reset = 1, | |
437 | .num_bits_resol = 11, | |
438 | .reg_values = reg_values, | |
473462a1 ID |
439 | }; |
440 | ||
9a320415 | 441 | static struct exynos_dsi_driver_data exynos4_dsi_driver_data = { |
d668e8bf | 442 | .reg_ofs = exynos_reg_ofs, |
9a320415 YC |
443 | .plltmr_reg = 0x50, |
444 | .has_freqband = 1, | |
78d3a8c6 | 445 | .has_clklane_stop = 1, |
d668e8bf HH |
446 | .num_clks = 2, |
447 | .max_freq = 1000, | |
448 | .wait_for_reset = 1, | |
449 | .num_bits_resol = 11, | |
450 | .reg_values = reg_values, | |
9a320415 YC |
451 | }; |
452 | ||
4bc6d644 | 453 | static struct exynos_dsi_driver_data exynos4415_dsi_driver_data = { |
d668e8bf | 454 | .reg_ofs = exynos_reg_ofs, |
4bc6d644 YC |
455 | .plltmr_reg = 0x58, |
456 | .has_clklane_stop = 1, | |
d668e8bf HH |
457 | .num_clks = 2, |
458 | .max_freq = 1000, | |
459 | .wait_for_reset = 1, | |
460 | .num_bits_resol = 11, | |
461 | .reg_values = reg_values, | |
4bc6d644 YC |
462 | }; |
463 | ||
9a320415 | 464 | static struct exynos_dsi_driver_data exynos5_dsi_driver_data = { |
d668e8bf | 465 | .reg_ofs = exynos_reg_ofs, |
9a320415 | 466 | .plltmr_reg = 0x58, |
d668e8bf HH |
467 | .num_clks = 2, |
468 | .max_freq = 1000, | |
469 | .wait_for_reset = 1, | |
470 | .num_bits_resol = 11, | |
471 | .reg_values = reg_values, | |
9a320415 YC |
472 | }; |
473 | ||
e6f988a4 HH |
474 | static struct exynos_dsi_driver_data exynos5433_dsi_driver_data = { |
475 | .reg_ofs = exynos5433_reg_ofs, | |
476 | .plltmr_reg = 0xa0, | |
477 | .has_clklane_stop = 1, | |
478 | .num_clks = 5, | |
479 | .max_freq = 1500, | |
480 | .wait_for_reset = 0, | |
481 | .num_bits_resol = 12, | |
482 | .reg_values = exynos5433_reg_values, | |
483 | }; | |
484 | ||
9a320415 | 485 | static struct of_device_id exynos_dsi_of_match[] = { |
473462a1 ID |
486 | { .compatible = "samsung,exynos3250-mipi-dsi", |
487 | .data = &exynos3_dsi_driver_data }, | |
9a320415 YC |
488 | { .compatible = "samsung,exynos4210-mipi-dsi", |
489 | .data = &exynos4_dsi_driver_data }, | |
4bc6d644 YC |
490 | { .compatible = "samsung,exynos4415-mipi-dsi", |
491 | .data = &exynos4415_dsi_driver_data }, | |
9a320415 YC |
492 | { .compatible = "samsung,exynos5410-mipi-dsi", |
493 | .data = &exynos5_dsi_driver_data }, | |
e6f988a4 HH |
494 | { .compatible = "samsung,exynos5433-mipi-dsi", |
495 | .data = &exynos5433_dsi_driver_data }, | |
9a320415 YC |
496 | { } |
497 | }; | |
498 | ||
499 | static inline struct exynos_dsi_driver_data *exynos_dsi_get_driver_data( | |
500 | struct platform_device *pdev) | |
501 | { | |
502 | const struct of_device_id *of_id = | |
503 | of_match_device(exynos_dsi_of_match, &pdev->dev); | |
504 | ||
505 | return (struct exynos_dsi_driver_data *)of_id->data; | |
506 | } | |
507 | ||
7eb8f069 AH |
508 | static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi) |
509 | { | |
510 | if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300))) | |
511 | return; | |
512 | ||
513 | dev_err(dsi->dev, "timeout waiting for reset\n"); | |
514 | } | |
515 | ||
516 | static void exynos_dsi_reset(struct exynos_dsi *dsi) | |
517 | { | |
ba12ac2b HH |
518 | struct exynos_dsi_driver_data *driver_data = dsi->driver_data; |
519 | ||
7eb8f069 | 520 | reinit_completion(&dsi->completed); |
d668e8bf | 521 | DSI_WRITE(dsi, DSIM_SWRST_REG, driver_data->reg_values[RESET_TYPE]); |
7eb8f069 AH |
522 | } |
523 | ||
524 | #ifndef MHZ | |
525 | #define MHZ (1000*1000) | |
526 | #endif | |
527 | ||
528 | static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi, | |
529 | unsigned long fin, unsigned long fout, u8 *p, u16 *m, u8 *s) | |
530 | { | |
ba12ac2b | 531 | struct exynos_dsi_driver_data *driver_data = dsi->driver_data; |
7eb8f069 AH |
532 | unsigned long best_freq = 0; |
533 | u32 min_delta = 0xffffffff; | |
534 | u8 p_min, p_max; | |
535 | u8 _p, uninitialized_var(best_p); | |
536 | u16 _m, uninitialized_var(best_m); | |
537 | u8 _s, uninitialized_var(best_s); | |
538 | ||
539 | p_min = DIV_ROUND_UP(fin, (12 * MHZ)); | |
540 | p_max = fin / (6 * MHZ); | |
541 | ||
542 | for (_p = p_min; _p <= p_max; ++_p) { | |
543 | for (_s = 0; _s <= 5; ++_s) { | |
544 | u64 tmp; | |
545 | u32 delta; | |
546 | ||
547 | tmp = (u64)fout * (_p << _s); | |
548 | do_div(tmp, fin); | |
549 | _m = tmp; | |
550 | if (_m < 41 || _m > 125) | |
551 | continue; | |
552 | ||
553 | tmp = (u64)_m * fin; | |
554 | do_div(tmp, _p); | |
d668e8bf HH |
555 | if (tmp < 500 * MHZ || |
556 | tmp > driver_data->max_freq * MHZ) | |
7eb8f069 AH |
557 | continue; |
558 | ||
559 | tmp = (u64)_m * fin; | |
560 | do_div(tmp, _p << _s); | |
561 | ||
562 | delta = abs(fout - tmp); | |
563 | if (delta < min_delta) { | |
564 | best_p = _p; | |
565 | best_m = _m; | |
566 | best_s = _s; | |
567 | min_delta = delta; | |
568 | best_freq = tmp; | |
569 | } | |
570 | } | |
571 | } | |
572 | ||
573 | if (best_freq) { | |
574 | *p = best_p; | |
575 | *m = best_m; | |
576 | *s = best_s; | |
577 | } | |
578 | ||
579 | return best_freq; | |
580 | } | |
581 | ||
582 | static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi, | |
583 | unsigned long freq) | |
584 | { | |
9a320415 | 585 | struct exynos_dsi_driver_data *driver_data = dsi->driver_data; |
7eb8f069 | 586 | unsigned long fin, fout; |
9a320415 | 587 | int timeout; |
7eb8f069 AH |
588 | u8 p, s; |
589 | u16 m; | |
590 | u32 reg; | |
591 | ||
26269af9 | 592 | fin = dsi->pll_clk_rate; |
7eb8f069 AH |
593 | fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s); |
594 | if (!fout) { | |
595 | dev_err(dsi->dev, | |
596 | "failed to find PLL PMS for requested frequency\n"); | |
8525b5ec | 597 | return 0; |
7eb8f069 | 598 | } |
9a320415 | 599 | dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s); |
7eb8f069 | 600 | |
d668e8bf HH |
601 | writel(driver_data->reg_values[PLL_TIMER], |
602 | dsi->reg_base + driver_data->plltmr_reg); | |
9a320415 YC |
603 | |
604 | reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s); | |
605 | ||
606 | if (driver_data->has_freqband) { | |
607 | static const unsigned long freq_bands[] = { | |
608 | 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ, | |
609 | 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ, | |
610 | 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ, | |
611 | 770 * MHZ, 870 * MHZ, 950 * MHZ, | |
612 | }; | |
613 | int band; | |
7eb8f069 | 614 | |
9a320415 YC |
615 | for (band = 0; band < ARRAY_SIZE(freq_bands); ++band) |
616 | if (fout < freq_bands[band]) | |
617 | break; | |
7eb8f069 | 618 | |
9a320415 YC |
619 | dev_dbg(dsi->dev, "band %d\n", band); |
620 | ||
621 | reg |= DSIM_FREQ_BAND(band); | |
622 | } | |
7eb8f069 | 623 | |
ba12ac2b | 624 | DSI_WRITE(dsi, DSIM_PLLCTRL_REG, reg); |
7eb8f069 AH |
625 | |
626 | timeout = 1000; | |
627 | do { | |
628 | if (timeout-- == 0) { | |
629 | dev_err(dsi->dev, "PLL failed to stabilize\n"); | |
8525b5ec | 630 | return 0; |
7eb8f069 | 631 | } |
ba12ac2b | 632 | reg = DSI_READ(dsi, DSIM_STATUS_REG); |
7eb8f069 AH |
633 | } while ((reg & DSIM_PLL_STABLE) == 0); |
634 | ||
635 | return fout; | |
636 | } | |
637 | ||
638 | static int exynos_dsi_enable_clock(struct exynos_dsi *dsi) | |
639 | { | |
640 | unsigned long hs_clk, byte_clk, esc_clk; | |
641 | unsigned long esc_div; | |
642 | u32 reg; | |
643 | ||
644 | hs_clk = exynos_dsi_set_pll(dsi, dsi->burst_clk_rate); | |
645 | if (!hs_clk) { | |
646 | dev_err(dsi->dev, "failed to configure DSI PLL\n"); | |
647 | return -EFAULT; | |
648 | } | |
649 | ||
650 | byte_clk = hs_clk / 8; | |
651 | esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate); | |
652 | esc_clk = byte_clk / esc_div; | |
653 | ||
654 | if (esc_clk > 20 * MHZ) { | |
655 | ++esc_div; | |
656 | esc_clk = byte_clk / esc_div; | |
657 | } | |
658 | ||
659 | dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n", | |
660 | hs_clk, byte_clk, esc_clk); | |
661 | ||
ba12ac2b | 662 | reg = DSI_READ(dsi, DSIM_CLKCTRL_REG); |
7eb8f069 AH |
663 | reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK |
664 | | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS | |
665 | | DSIM_BYTE_CLK_SRC_MASK); | |
666 | reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN | |
667 | | DSIM_ESC_PRESCALER(esc_div) | |
668 | | DSIM_LANE_ESC_CLK_EN_CLK | |
669 | | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1) | |
670 | | DSIM_BYTE_CLK_SRC(0) | |
671 | | DSIM_TX_REQUEST_HSCLK; | |
ba12ac2b | 672 | DSI_WRITE(dsi, DSIM_CLKCTRL_REG, reg); |
7eb8f069 AH |
673 | |
674 | return 0; | |
675 | } | |
676 | ||
9a320415 YC |
677 | static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi) |
678 | { | |
679 | struct exynos_dsi_driver_data *driver_data = dsi->driver_data; | |
d668e8bf | 680 | unsigned int *reg_values = driver_data->reg_values; |
9a320415 YC |
681 | u32 reg; |
682 | ||
683 | if (driver_data->has_freqband) | |
684 | return; | |
685 | ||
686 | /* B D-PHY: D-PHY Master & Slave Analog Block control */ | |
d668e8bf HH |
687 | reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] | |
688 | reg_values[PHYCTRL_SLEW_UP]; | |
ba12ac2b | 689 | DSI_WRITE(dsi, DSIM_PHYCTRL_REG, reg); |
9a320415 YC |
690 | |
691 | /* | |
692 | * T LPX: Transmitted length of any Low-Power state period | |
693 | * T HS-EXIT: Time that the transmitter drives LP-11 following a HS | |
694 | * burst | |
695 | */ | |
d668e8bf | 696 | reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT]; |
ba12ac2b | 697 | DSI_WRITE(dsi, DSIM_PHYTIMING_REG, reg); |
9a320415 YC |
698 | |
699 | /* | |
700 | * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00 | |
701 | * Line state immediately before the HS-0 Line state starting the | |
702 | * HS transmission | |
703 | * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to | |
704 | * transmitting the Clock. | |
705 | * T CLK_POST: Time that the transmitter continues to send HS clock | |
706 | * after the last associated Data Lane has transitioned to LP Mode | |
707 | * Interval is defined as the period from the end of T HS-TRAIL to | |
708 | * the beginning of T CLK-TRAIL | |
709 | * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after | |
710 | * the last payload clock bit of a HS transmission burst | |
711 | */ | |
d668e8bf HH |
712 | reg = reg_values[PHYTIMING_CLK_PREPARE] | |
713 | reg_values[PHYTIMING_CLK_ZERO] | | |
714 | reg_values[PHYTIMING_CLK_POST] | | |
715 | reg_values[PHYTIMING_CLK_TRAIL]; | |
716 | ||
ba12ac2b | 717 | DSI_WRITE(dsi, DSIM_PHYTIMING1_REG, reg); |
9a320415 YC |
718 | |
719 | /* | |
720 | * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00 | |
721 | * Line state immediately before the HS-0 Line state starting the | |
722 | * HS transmission | |
723 | * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to | |
724 | * transmitting the Sync sequence. | |
725 | * T HS-TRAIL: Time that the transmitter drives the flipped differential | |
726 | * state after last payload data bit of a HS transmission burst | |
727 | */ | |
d668e8bf HH |
728 | reg = reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] | |
729 | reg_values[PHYTIMING_HS_TRAIL]; | |
ba12ac2b | 730 | DSI_WRITE(dsi, DSIM_PHYTIMING2_REG, reg); |
9a320415 YC |
731 | } |
732 | ||
7eb8f069 AH |
733 | static void exynos_dsi_disable_clock(struct exynos_dsi *dsi) |
734 | { | |
735 | u32 reg; | |
736 | ||
ba12ac2b | 737 | reg = DSI_READ(dsi, DSIM_CLKCTRL_REG); |
7eb8f069 AH |
738 | reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK |
739 | | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN); | |
ba12ac2b | 740 | DSI_WRITE(dsi, DSIM_CLKCTRL_REG, reg); |
7eb8f069 | 741 | |
ba12ac2b | 742 | reg = DSI_READ(dsi, DSIM_PLLCTRL_REG); |
7eb8f069 | 743 | reg &= ~DSIM_PLL_EN; |
ba12ac2b | 744 | DSI_WRITE(dsi, DSIM_PLLCTRL_REG, reg); |
7eb8f069 AH |
745 | } |
746 | ||
e6f988a4 HH |
747 | static void exynos_dsi_enable_lane(struct exynos_dsi *dsi, u32 lane) |
748 | { | |
749 | u32 reg = DSI_READ(dsi, DSIM_CONFIG_REG); | |
750 | reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK | | |
751 | DSIM_LANE_EN(lane)); | |
752 | DSI_WRITE(dsi, DSIM_CONFIG_REG, reg); | |
753 | } | |
754 | ||
7eb8f069 AH |
755 | static int exynos_dsi_init_link(struct exynos_dsi *dsi) |
756 | { | |
78d3a8c6 | 757 | struct exynos_dsi_driver_data *driver_data = dsi->driver_data; |
7eb8f069 AH |
758 | int timeout; |
759 | u32 reg; | |
760 | u32 lanes_mask; | |
761 | ||
762 | /* Initialize FIFO pointers */ | |
ba12ac2b | 763 | reg = DSI_READ(dsi, DSIM_FIFOCTRL_REG); |
7eb8f069 | 764 | reg &= ~0x1f; |
ba12ac2b | 765 | DSI_WRITE(dsi, DSIM_FIFOCTRL_REG, reg); |
7eb8f069 AH |
766 | |
767 | usleep_range(9000, 11000); | |
768 | ||
769 | reg |= 0x1f; | |
ba12ac2b | 770 | DSI_WRITE(dsi, DSIM_FIFOCTRL_REG, reg); |
7eb8f069 AH |
771 | usleep_range(9000, 11000); |
772 | ||
773 | /* DSI configuration */ | |
774 | reg = 0; | |
775 | ||
2f36e33a YC |
776 | /* |
777 | * The first bit of mode_flags specifies display configuration. | |
778 | * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video | |
779 | * mode, otherwise it will support command mode. | |
780 | */ | |
7eb8f069 AH |
781 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { |
782 | reg |= DSIM_VIDEO_MODE; | |
783 | ||
2f36e33a YC |
784 | /* |
785 | * The user manual describes that following bits are ignored in | |
786 | * command mode. | |
787 | */ | |
7eb8f069 AH |
788 | if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH)) |
789 | reg |= DSIM_MFLUSH_VS; | |
7eb8f069 AH |
790 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) |
791 | reg |= DSIM_SYNC_INFORM; | |
792 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) | |
793 | reg |= DSIM_BURST_MODE; | |
794 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT) | |
795 | reg |= DSIM_AUTO_MODE; | |
796 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE) | |
797 | reg |= DSIM_HSE_MODE; | |
798 | if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP)) | |
799 | reg |= DSIM_HFP_MODE; | |
800 | if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP)) | |
801 | reg |= DSIM_HBP_MODE; | |
802 | if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA)) | |
803 | reg |= DSIM_HSA_MODE; | |
804 | } | |
805 | ||
2f36e33a YC |
806 | if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET)) |
807 | reg |= DSIM_EOT_DISABLE; | |
808 | ||
7eb8f069 AH |
809 | switch (dsi->format) { |
810 | case MIPI_DSI_FMT_RGB888: | |
811 | reg |= DSIM_MAIN_PIX_FORMAT_RGB888; | |
812 | break; | |
813 | case MIPI_DSI_FMT_RGB666: | |
814 | reg |= DSIM_MAIN_PIX_FORMAT_RGB666; | |
815 | break; | |
816 | case MIPI_DSI_FMT_RGB666_PACKED: | |
817 | reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P; | |
818 | break; | |
819 | case MIPI_DSI_FMT_RGB565: | |
820 | reg |= DSIM_MAIN_PIX_FORMAT_RGB565; | |
821 | break; | |
822 | default: | |
823 | dev_err(dsi->dev, "invalid pixel format\n"); | |
824 | return -EINVAL; | |
825 | } | |
826 | ||
78d3a8c6 ID |
827 | /* |
828 | * Use non-continuous clock mode if the periparal wants and | |
829 | * host controller supports | |
830 | * | |
831 | * In non-continous clock mode, host controller will turn off | |
832 | * the HS clock between high-speed transmissions to reduce | |
833 | * power consumption. | |
834 | */ | |
835 | if (driver_data->has_clklane_stop && | |
836 | dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { | |
837 | reg |= DSIM_CLKLANE_STOP; | |
78d3a8c6 | 838 | } |
e6f988a4 HH |
839 | DSI_WRITE(dsi, DSIM_CONFIG_REG, reg); |
840 | ||
841 | lanes_mask = BIT(dsi->lanes) - 1; | |
842 | exynos_dsi_enable_lane(dsi, lanes_mask); | |
78d3a8c6 | 843 | |
7eb8f069 AH |
844 | /* Check clock and data lane state are stop state */ |
845 | timeout = 100; | |
846 | do { | |
847 | if (timeout-- == 0) { | |
848 | dev_err(dsi->dev, "waiting for bus lanes timed out\n"); | |
849 | return -EFAULT; | |
850 | } | |
851 | ||
ba12ac2b | 852 | reg = DSI_READ(dsi, DSIM_STATUS_REG); |
7eb8f069 AH |
853 | if ((reg & DSIM_STOP_STATE_DAT(lanes_mask)) |
854 | != DSIM_STOP_STATE_DAT(lanes_mask)) | |
855 | continue; | |
856 | } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK))); | |
857 | ||
ba12ac2b | 858 | reg = DSI_READ(dsi, DSIM_ESCMODE_REG); |
7eb8f069 | 859 | reg &= ~DSIM_STOP_STATE_CNT_MASK; |
d668e8bf | 860 | reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]); |
ba12ac2b | 861 | DSI_WRITE(dsi, DSIM_ESCMODE_REG, reg); |
7eb8f069 AH |
862 | |
863 | reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff); | |
ba12ac2b | 864 | DSI_WRITE(dsi, DSIM_TIMEOUT_REG, reg); |
7eb8f069 AH |
865 | |
866 | return 0; | |
867 | } | |
868 | ||
869 | static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi) | |
870 | { | |
871 | struct videomode *vm = &dsi->vm; | |
d668e8bf | 872 | unsigned int num_bits_resol = dsi->driver_data->num_bits_resol; |
7eb8f069 AH |
873 | u32 reg; |
874 | ||
875 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { | |
876 | reg = DSIM_CMD_ALLOW(0xf) | |
877 | | DSIM_STABLE_VFP(vm->vfront_porch) | |
878 | | DSIM_MAIN_VBP(vm->vback_porch); | |
ba12ac2b | 879 | DSI_WRITE(dsi, DSIM_MVPORCH_REG, reg); |
7eb8f069 AH |
880 | |
881 | reg = DSIM_MAIN_HFP(vm->hfront_porch) | |
882 | | DSIM_MAIN_HBP(vm->hback_porch); | |
ba12ac2b | 883 | DSI_WRITE(dsi, DSIM_MHPORCH_REG, reg); |
7eb8f069 AH |
884 | |
885 | reg = DSIM_MAIN_VSA(vm->vsync_len) | |
886 | | DSIM_MAIN_HSA(vm->hsync_len); | |
ba12ac2b | 887 | DSI_WRITE(dsi, DSIM_MSYNC_REG, reg); |
7eb8f069 | 888 | } |
d668e8bf HH |
889 | reg = DSIM_MAIN_HRESOL(vm->hactive, num_bits_resol) | |
890 | DSIM_MAIN_VRESOL(vm->vactive, num_bits_resol); | |
7eb8f069 | 891 | |
ba12ac2b | 892 | DSI_WRITE(dsi, DSIM_MDRESOL_REG, reg); |
7eb8f069 AH |
893 | |
894 | dev_dbg(dsi->dev, "LCD size = %dx%d\n", vm->hactive, vm->vactive); | |
895 | } | |
896 | ||
897 | static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable) | |
898 | { | |
899 | u32 reg; | |
900 | ||
ba12ac2b | 901 | reg = DSI_READ(dsi, DSIM_MDRESOL_REG); |
7eb8f069 AH |
902 | if (enable) |
903 | reg |= DSIM_MAIN_STAND_BY; | |
904 | else | |
905 | reg &= ~DSIM_MAIN_STAND_BY; | |
ba12ac2b | 906 | DSI_WRITE(dsi, DSIM_MDRESOL_REG, reg); |
7eb8f069 AH |
907 | } |
908 | ||
909 | static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi) | |
910 | { | |
911 | int timeout = 2000; | |
912 | ||
913 | do { | |
ba12ac2b | 914 | u32 reg = DSI_READ(dsi, DSIM_FIFOCTRL_REG); |
7eb8f069 AH |
915 | |
916 | if (!(reg & DSIM_SFR_HEADER_FULL)) | |
917 | return 0; | |
918 | ||
919 | if (!cond_resched()) | |
920 | usleep_range(950, 1050); | |
921 | } while (--timeout); | |
922 | ||
923 | return -ETIMEDOUT; | |
924 | } | |
925 | ||
926 | static void exynos_dsi_set_cmd_lpm(struct exynos_dsi *dsi, bool lpm) | |
927 | { | |
ba12ac2b | 928 | u32 v = DSI_READ(dsi, DSIM_ESCMODE_REG); |
7eb8f069 AH |
929 | |
930 | if (lpm) | |
931 | v |= DSIM_CMD_LPDT_LP; | |
932 | else | |
933 | v &= ~DSIM_CMD_LPDT_LP; | |
934 | ||
ba12ac2b | 935 | DSI_WRITE(dsi, DSIM_ESCMODE_REG, v); |
7eb8f069 AH |
936 | } |
937 | ||
938 | static void exynos_dsi_force_bta(struct exynos_dsi *dsi) | |
939 | { | |
ba12ac2b | 940 | u32 v = DSI_READ(dsi, DSIM_ESCMODE_REG); |
7eb8f069 | 941 | v |= DSIM_FORCE_BTA; |
ba12ac2b | 942 | DSI_WRITE(dsi, DSIM_ESCMODE_REG, v); |
7eb8f069 AH |
943 | } |
944 | ||
945 | static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi, | |
946 | struct exynos_dsi_transfer *xfer) | |
947 | { | |
948 | struct device *dev = dsi->dev; | |
949 | const u8 *payload = xfer->tx_payload + xfer->tx_done; | |
950 | u16 length = xfer->tx_len - xfer->tx_done; | |
951 | bool first = !xfer->tx_done; | |
952 | u32 reg; | |
953 | ||
954 | dev_dbg(dev, "< xfer %p: tx len %u, done %u, rx len %u, done %u\n", | |
955 | xfer, xfer->tx_len, xfer->tx_done, xfer->rx_len, xfer->rx_done); | |
956 | ||
957 | if (length > DSI_TX_FIFO_SIZE) | |
958 | length = DSI_TX_FIFO_SIZE; | |
959 | ||
960 | xfer->tx_done += length; | |
961 | ||
962 | /* Send payload */ | |
963 | while (length >= 4) { | |
964 | reg = (payload[3] << 24) | (payload[2] << 16) | |
965 | | (payload[1] << 8) | payload[0]; | |
ba12ac2b | 966 | DSI_WRITE(dsi, DSIM_PAYLOAD_REG, reg); |
7eb8f069 AH |
967 | payload += 4; |
968 | length -= 4; | |
969 | } | |
970 | ||
971 | reg = 0; | |
972 | switch (length) { | |
973 | case 3: | |
974 | reg |= payload[2] << 16; | |
975 | /* Fall through */ | |
976 | case 2: | |
977 | reg |= payload[1] << 8; | |
978 | /* Fall through */ | |
979 | case 1: | |
980 | reg |= payload[0]; | |
ba12ac2b | 981 | DSI_WRITE(dsi, DSIM_PAYLOAD_REG, reg); |
7eb8f069 AH |
982 | break; |
983 | case 0: | |
984 | /* Do nothing */ | |
985 | break; | |
986 | } | |
987 | ||
988 | /* Send packet header */ | |
989 | if (!first) | |
990 | return; | |
991 | ||
992 | reg = (xfer->data[1] << 16) | (xfer->data[0] << 8) | xfer->data_id; | |
993 | if (exynos_dsi_wait_for_hdr_fifo(dsi)) { | |
994 | dev_err(dev, "waiting for header FIFO timed out\n"); | |
995 | return; | |
996 | } | |
997 | ||
998 | if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM, | |
999 | dsi->state & DSIM_STATE_CMD_LPM)) { | |
1000 | exynos_dsi_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM); | |
1001 | dsi->state ^= DSIM_STATE_CMD_LPM; | |
1002 | } | |
1003 | ||
ba12ac2b | 1004 | DSI_WRITE(dsi, DSIM_PKTHDR_REG, reg); |
7eb8f069 AH |
1005 | |
1006 | if (xfer->flags & MIPI_DSI_MSG_REQ_ACK) | |
1007 | exynos_dsi_force_bta(dsi); | |
1008 | } | |
1009 | ||
1010 | static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi, | |
1011 | struct exynos_dsi_transfer *xfer) | |
1012 | { | |
1013 | u8 *payload = xfer->rx_payload + xfer->rx_done; | |
1014 | bool first = !xfer->rx_done; | |
1015 | struct device *dev = dsi->dev; | |
1016 | u16 length; | |
1017 | u32 reg; | |
1018 | ||
1019 | if (first) { | |
ba12ac2b | 1020 | reg = DSI_READ(dsi, DSIM_RXFIFO_REG); |
7eb8f069 AH |
1021 | |
1022 | switch (reg & 0x3f) { | |
1023 | case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: | |
1024 | case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: | |
1025 | if (xfer->rx_len >= 2) { | |
1026 | payload[1] = reg >> 16; | |
1027 | ++xfer->rx_done; | |
1028 | } | |
1029 | /* Fall through */ | |
1030 | case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: | |
1031 | case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: | |
1032 | payload[0] = reg >> 8; | |
1033 | ++xfer->rx_done; | |
1034 | xfer->rx_len = xfer->rx_done; | |
1035 | xfer->result = 0; | |
1036 | goto clear_fifo; | |
1037 | case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: | |
1038 | dev_err(dev, "DSI Error Report: 0x%04x\n", | |
1039 | (reg >> 8) & 0xffff); | |
1040 | xfer->result = 0; | |
1041 | goto clear_fifo; | |
1042 | } | |
1043 | ||
1044 | length = (reg >> 8) & 0xffff; | |
1045 | if (length > xfer->rx_len) { | |
1046 | dev_err(dev, | |
1047 | "response too long (%u > %u bytes), stripping\n", | |
1048 | xfer->rx_len, length); | |
1049 | length = xfer->rx_len; | |
1050 | } else if (length < xfer->rx_len) | |
1051 | xfer->rx_len = length; | |
1052 | } | |
1053 | ||
1054 | length = xfer->rx_len - xfer->rx_done; | |
1055 | xfer->rx_done += length; | |
1056 | ||
1057 | /* Receive payload */ | |
1058 | while (length >= 4) { | |
ba12ac2b | 1059 | reg = DSI_READ(dsi, DSIM_RXFIFO_REG); |
7eb8f069 AH |
1060 | payload[0] = (reg >> 0) & 0xff; |
1061 | payload[1] = (reg >> 8) & 0xff; | |
1062 | payload[2] = (reg >> 16) & 0xff; | |
1063 | payload[3] = (reg >> 24) & 0xff; | |
1064 | payload += 4; | |
1065 | length -= 4; | |
1066 | } | |
1067 | ||
1068 | if (length) { | |
ba12ac2b | 1069 | reg = DSI_READ(dsi, DSIM_RXFIFO_REG); |
7eb8f069 AH |
1070 | switch (length) { |
1071 | case 3: | |
1072 | payload[2] = (reg >> 16) & 0xff; | |
1073 | /* Fall through */ | |
1074 | case 2: | |
1075 | payload[1] = (reg >> 8) & 0xff; | |
1076 | /* Fall through */ | |
1077 | case 1: | |
1078 | payload[0] = reg & 0xff; | |
1079 | } | |
1080 | } | |
1081 | ||
1082 | if (xfer->rx_done == xfer->rx_len) | |
1083 | xfer->result = 0; | |
1084 | ||
1085 | clear_fifo: | |
1086 | length = DSI_RX_FIFO_SIZE / 4; | |
1087 | do { | |
ba12ac2b | 1088 | reg = DSI_READ(dsi, DSIM_RXFIFO_REG); |
7eb8f069 AH |
1089 | if (reg == DSI_RX_FIFO_EMPTY) |
1090 | break; | |
1091 | } while (--length); | |
1092 | } | |
1093 | ||
1094 | static void exynos_dsi_transfer_start(struct exynos_dsi *dsi) | |
1095 | { | |
1096 | unsigned long flags; | |
1097 | struct exynos_dsi_transfer *xfer; | |
1098 | bool start = false; | |
1099 | ||
1100 | again: | |
1101 | spin_lock_irqsave(&dsi->transfer_lock, flags); | |
1102 | ||
1103 | if (list_empty(&dsi->transfer_list)) { | |
1104 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); | |
1105 | return; | |
1106 | } | |
1107 | ||
1108 | xfer = list_first_entry(&dsi->transfer_list, | |
1109 | struct exynos_dsi_transfer, list); | |
1110 | ||
1111 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); | |
1112 | ||
1113 | if (xfer->tx_len && xfer->tx_done == xfer->tx_len) | |
1114 | /* waiting for RX */ | |
1115 | return; | |
1116 | ||
1117 | exynos_dsi_send_to_fifo(dsi, xfer); | |
1118 | ||
1119 | if (xfer->tx_len || xfer->rx_len) | |
1120 | return; | |
1121 | ||
1122 | xfer->result = 0; | |
1123 | complete(&xfer->completed); | |
1124 | ||
1125 | spin_lock_irqsave(&dsi->transfer_lock, flags); | |
1126 | ||
1127 | list_del_init(&xfer->list); | |
1128 | start = !list_empty(&dsi->transfer_list); | |
1129 | ||
1130 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); | |
1131 | ||
1132 | if (start) | |
1133 | goto again; | |
1134 | } | |
1135 | ||
1136 | static bool exynos_dsi_transfer_finish(struct exynos_dsi *dsi) | |
1137 | { | |
1138 | struct exynos_dsi_transfer *xfer; | |
1139 | unsigned long flags; | |
1140 | bool start = true; | |
1141 | ||
1142 | spin_lock_irqsave(&dsi->transfer_lock, flags); | |
1143 | ||
1144 | if (list_empty(&dsi->transfer_list)) { | |
1145 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); | |
1146 | return false; | |
1147 | } | |
1148 | ||
1149 | xfer = list_first_entry(&dsi->transfer_list, | |
1150 | struct exynos_dsi_transfer, list); | |
1151 | ||
1152 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); | |
1153 | ||
1154 | dev_dbg(dsi->dev, | |
1155 | "> xfer %p, tx_len %u, tx_done %u, rx_len %u, rx_done %u\n", | |
1156 | xfer, xfer->tx_len, xfer->tx_done, xfer->rx_len, xfer->rx_done); | |
1157 | ||
1158 | if (xfer->tx_done != xfer->tx_len) | |
1159 | return true; | |
1160 | ||
1161 | if (xfer->rx_done != xfer->rx_len) | |
1162 | exynos_dsi_read_from_fifo(dsi, xfer); | |
1163 | ||
1164 | if (xfer->rx_done != xfer->rx_len) | |
1165 | return true; | |
1166 | ||
1167 | spin_lock_irqsave(&dsi->transfer_lock, flags); | |
1168 | ||
1169 | list_del_init(&xfer->list); | |
1170 | start = !list_empty(&dsi->transfer_list); | |
1171 | ||
1172 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); | |
1173 | ||
1174 | if (!xfer->rx_len) | |
1175 | xfer->result = 0; | |
1176 | complete(&xfer->completed); | |
1177 | ||
1178 | return start; | |
1179 | } | |
1180 | ||
1181 | static void exynos_dsi_remove_transfer(struct exynos_dsi *dsi, | |
1182 | struct exynos_dsi_transfer *xfer) | |
1183 | { | |
1184 | unsigned long flags; | |
1185 | bool start; | |
1186 | ||
1187 | spin_lock_irqsave(&dsi->transfer_lock, flags); | |
1188 | ||
1189 | if (!list_empty(&dsi->transfer_list) && | |
1190 | xfer == list_first_entry(&dsi->transfer_list, | |
1191 | struct exynos_dsi_transfer, list)) { | |
1192 | list_del_init(&xfer->list); | |
1193 | start = !list_empty(&dsi->transfer_list); | |
1194 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); | |
1195 | if (start) | |
1196 | exynos_dsi_transfer_start(dsi); | |
1197 | return; | |
1198 | } | |
1199 | ||
1200 | list_del_init(&xfer->list); | |
1201 | ||
1202 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); | |
1203 | } | |
1204 | ||
1205 | static int exynos_dsi_transfer(struct exynos_dsi *dsi, | |
1206 | struct exynos_dsi_transfer *xfer) | |
1207 | { | |
1208 | unsigned long flags; | |
1209 | bool stopped; | |
1210 | ||
1211 | xfer->tx_done = 0; | |
1212 | xfer->rx_done = 0; | |
1213 | xfer->result = -ETIMEDOUT; | |
1214 | init_completion(&xfer->completed); | |
1215 | ||
1216 | spin_lock_irqsave(&dsi->transfer_lock, flags); | |
1217 | ||
1218 | stopped = list_empty(&dsi->transfer_list); | |
1219 | list_add_tail(&xfer->list, &dsi->transfer_list); | |
1220 | ||
1221 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); | |
1222 | ||
1223 | if (stopped) | |
1224 | exynos_dsi_transfer_start(dsi); | |
1225 | ||
1226 | wait_for_completion_timeout(&xfer->completed, | |
1227 | msecs_to_jiffies(DSI_XFER_TIMEOUT_MS)); | |
1228 | if (xfer->result == -ETIMEDOUT) { | |
1229 | exynos_dsi_remove_transfer(dsi, xfer); | |
1230 | dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 2, xfer->data, | |
1231 | xfer->tx_len, xfer->tx_payload); | |
1232 | return -ETIMEDOUT; | |
1233 | } | |
1234 | ||
1235 | /* Also covers hardware timeout condition */ | |
1236 | return xfer->result; | |
1237 | } | |
1238 | ||
1239 | static irqreturn_t exynos_dsi_irq(int irq, void *dev_id) | |
1240 | { | |
1241 | struct exynos_dsi *dsi = dev_id; | |
1242 | u32 status; | |
1243 | ||
ba12ac2b | 1244 | status = DSI_READ(dsi, DSIM_INTSRC_REG); |
7eb8f069 AH |
1245 | if (!status) { |
1246 | static unsigned long int j; | |
1247 | if (printk_timed_ratelimit(&j, 500)) | |
1248 | dev_warn(dsi->dev, "spurious interrupt\n"); | |
1249 | return IRQ_HANDLED; | |
1250 | } | |
ba12ac2b | 1251 | DSI_WRITE(dsi, DSIM_INTSRC_REG, status); |
7eb8f069 AH |
1252 | |
1253 | if (status & DSIM_INT_SW_RST_RELEASE) { | |
e6f988a4 HH |
1254 | u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY | |
1255 | DSIM_INT_SFR_HDR_FIFO_EMPTY | DSIM_INT_FRAME_DONE | | |
1256 | DSIM_INT_RX_ECC_ERR | DSIM_INT_SW_RST_RELEASE); | |
ba12ac2b | 1257 | DSI_WRITE(dsi, DSIM_INTMSK_REG, mask); |
7eb8f069 AH |
1258 | complete(&dsi->completed); |
1259 | return IRQ_HANDLED; | |
1260 | } | |
1261 | ||
e6f988a4 HH |
1262 | if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY | |
1263 | DSIM_INT_FRAME_DONE | DSIM_INT_PLL_STABLE))) | |
7eb8f069 AH |
1264 | return IRQ_HANDLED; |
1265 | ||
1266 | if (exynos_dsi_transfer_finish(dsi)) | |
1267 | exynos_dsi_transfer_start(dsi); | |
1268 | ||
1269 | return IRQ_HANDLED; | |
1270 | } | |
1271 | ||
e17ddecc YC |
1272 | static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id) |
1273 | { | |
1274 | struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id; | |
e5169723 | 1275 | struct drm_encoder *encoder = dsi->display.encoder; |
e17ddecc | 1276 | |
0e480f6f | 1277 | if (dsi->state & DSIM_STATE_VIDOUT_AVAILABLE) |
e17ddecc YC |
1278 | exynos_drm_crtc_te_handler(encoder->crtc); |
1279 | ||
1280 | return IRQ_HANDLED; | |
1281 | } | |
1282 | ||
1283 | static void exynos_dsi_enable_irq(struct exynos_dsi *dsi) | |
1284 | { | |
1285 | enable_irq(dsi->irq); | |
1286 | ||
1287 | if (gpio_is_valid(dsi->te_gpio)) | |
1288 | enable_irq(gpio_to_irq(dsi->te_gpio)); | |
1289 | } | |
1290 | ||
1291 | static void exynos_dsi_disable_irq(struct exynos_dsi *dsi) | |
1292 | { | |
1293 | if (gpio_is_valid(dsi->te_gpio)) | |
1294 | disable_irq(gpio_to_irq(dsi->te_gpio)); | |
1295 | ||
1296 | disable_irq(dsi->irq); | |
1297 | } | |
1298 | ||
7eb8f069 AH |
1299 | static int exynos_dsi_init(struct exynos_dsi *dsi) |
1300 | { | |
d668e8bf HH |
1301 | struct exynos_dsi_driver_data *driver_data = dsi->driver_data; |
1302 | ||
7eb8f069 | 1303 | exynos_dsi_reset(dsi); |
e17ddecc | 1304 | exynos_dsi_enable_irq(dsi); |
e6f988a4 HH |
1305 | |
1306 | if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST) | |
1307 | exynos_dsi_enable_lane(dsi, BIT(dsi->lanes) - 1); | |
1308 | ||
9a320415 | 1309 | exynos_dsi_enable_clock(dsi); |
d668e8bf HH |
1310 | if (driver_data->wait_for_reset) |
1311 | exynos_dsi_wait_for_reset(dsi); | |
9a320415 | 1312 | exynos_dsi_set_phy_ctrl(dsi); |
7eb8f069 AH |
1313 | exynos_dsi_init_link(dsi); |
1314 | ||
1315 | return 0; | |
1316 | } | |
1317 | ||
e17ddecc YC |
1318 | static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi) |
1319 | { | |
1320 | int ret; | |
0cef83a5 | 1321 | int te_gpio_irq; |
e17ddecc YC |
1322 | |
1323 | dsi->te_gpio = of_get_named_gpio(dsi->panel_node, "te-gpios", 0); | |
1324 | if (!gpio_is_valid(dsi->te_gpio)) { | |
1325 | dev_err(dsi->dev, "no te-gpios specified\n"); | |
1326 | ret = dsi->te_gpio; | |
1327 | goto out; | |
1328 | } | |
1329 | ||
51d1deca | 1330 | ret = gpio_request(dsi->te_gpio, "te_gpio"); |
e17ddecc YC |
1331 | if (ret) { |
1332 | dev_err(dsi->dev, "gpio request failed with %d\n", ret); | |
1333 | goto out; | |
1334 | } | |
1335 | ||
0cef83a5 | 1336 | te_gpio_irq = gpio_to_irq(dsi->te_gpio); |
0cef83a5 | 1337 | irq_set_status_flags(te_gpio_irq, IRQ_NOAUTOEN); |
51d1deca | 1338 | |
0cef83a5 | 1339 | ret = request_threaded_irq(te_gpio_irq, exynos_dsi_te_irq_handler, NULL, |
e17ddecc YC |
1340 | IRQF_TRIGGER_RISING, "TE", dsi); |
1341 | if (ret) { | |
1342 | dev_err(dsi->dev, "request interrupt failed with %d\n", ret); | |
1343 | gpio_free(dsi->te_gpio); | |
1344 | goto out; | |
1345 | } | |
1346 | ||
1347 | out: | |
1348 | return ret; | |
1349 | } | |
1350 | ||
1351 | static void exynos_dsi_unregister_te_irq(struct exynos_dsi *dsi) | |
1352 | { | |
1353 | if (gpio_is_valid(dsi->te_gpio)) { | |
1354 | free_irq(gpio_to_irq(dsi->te_gpio), dsi); | |
1355 | gpio_free(dsi->te_gpio); | |
1356 | dsi->te_gpio = -ENOENT; | |
1357 | } | |
1358 | } | |
1359 | ||
7eb8f069 AH |
1360 | static int exynos_dsi_host_attach(struct mipi_dsi_host *host, |
1361 | struct mipi_dsi_device *device) | |
1362 | { | |
1363 | struct exynos_dsi *dsi = host_to_dsi(host); | |
1364 | ||
1365 | dsi->lanes = device->lanes; | |
1366 | dsi->format = device->format; | |
1367 | dsi->mode_flags = device->mode_flags; | |
1368 | dsi->panel_node = device->dev.of_node; | |
1369 | ||
e17ddecc YC |
1370 | /* |
1371 | * This is a temporary solution and should be made by more generic way. | |
1372 | * | |
1373 | * If attached panel device is for command mode one, dsi should register | |
1374 | * TE interrupt handler. | |
1375 | */ | |
1376 | if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) { | |
1377 | int ret = exynos_dsi_register_te_irq(dsi); | |
1378 | ||
1379 | if (ret) | |
1380 | return ret; | |
1381 | } | |
1382 | ||
ecb84157 YC |
1383 | if (dsi->connector.dev) |
1384 | drm_helper_hpd_irq_event(dsi->connector.dev); | |
1385 | ||
7eb8f069 AH |
1386 | return 0; |
1387 | } | |
1388 | ||
1389 | static int exynos_dsi_host_detach(struct mipi_dsi_host *host, | |
1390 | struct mipi_dsi_device *device) | |
1391 | { | |
1392 | struct exynos_dsi *dsi = host_to_dsi(host); | |
1393 | ||
e17ddecc YC |
1394 | exynos_dsi_unregister_te_irq(dsi); |
1395 | ||
7eb8f069 AH |
1396 | dsi->panel_node = NULL; |
1397 | ||
1398 | if (dsi->connector.dev) | |
1399 | drm_helper_hpd_irq_event(dsi->connector.dev); | |
1400 | ||
1401 | return 0; | |
1402 | } | |
1403 | ||
1404 | /* distinguish between short and long DSI packet types */ | |
1405 | static bool exynos_dsi_is_short_dsi_type(u8 type) | |
1406 | { | |
1407 | return (type & 0x0f) <= 8; | |
1408 | } | |
1409 | ||
1410 | static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host, | |
ed6ff40e | 1411 | const struct mipi_dsi_msg *msg) |
7eb8f069 AH |
1412 | { |
1413 | struct exynos_dsi *dsi = host_to_dsi(host); | |
1414 | struct exynos_dsi_transfer xfer; | |
1415 | int ret; | |
1416 | ||
0e480f6f HH |
1417 | if (!(dsi->state & DSIM_STATE_ENABLED)) |
1418 | return -EINVAL; | |
1419 | ||
7eb8f069 AH |
1420 | if (!(dsi->state & DSIM_STATE_INITIALIZED)) { |
1421 | ret = exynos_dsi_init(dsi); | |
1422 | if (ret) | |
1423 | return ret; | |
1424 | dsi->state |= DSIM_STATE_INITIALIZED; | |
1425 | } | |
1426 | ||
1427 | if (msg->tx_len == 0) | |
1428 | return -EINVAL; | |
1429 | ||
1430 | xfer.data_id = msg->type | (msg->channel << 6); | |
1431 | ||
1432 | if (exynos_dsi_is_short_dsi_type(msg->type)) { | |
1433 | const char *tx_buf = msg->tx_buf; | |
1434 | ||
1435 | if (msg->tx_len > 2) | |
1436 | return -EINVAL; | |
1437 | xfer.tx_len = 0; | |
1438 | xfer.data[0] = tx_buf[0]; | |
1439 | xfer.data[1] = (msg->tx_len == 2) ? tx_buf[1] : 0; | |
1440 | } else { | |
1441 | xfer.tx_len = msg->tx_len; | |
1442 | xfer.data[0] = msg->tx_len & 0xff; | |
1443 | xfer.data[1] = msg->tx_len >> 8; | |
1444 | xfer.tx_payload = msg->tx_buf; | |
1445 | } | |
1446 | ||
1447 | xfer.rx_len = msg->rx_len; | |
1448 | xfer.rx_payload = msg->rx_buf; | |
1449 | xfer.flags = msg->flags; | |
1450 | ||
1451 | ret = exynos_dsi_transfer(dsi, &xfer); | |
1452 | return (ret < 0) ? ret : xfer.rx_done; | |
1453 | } | |
1454 | ||
1455 | static const struct mipi_dsi_host_ops exynos_dsi_ops = { | |
1456 | .attach = exynos_dsi_host_attach, | |
1457 | .detach = exynos_dsi_host_detach, | |
1458 | .transfer = exynos_dsi_host_transfer, | |
1459 | }; | |
1460 | ||
1461 | static int exynos_dsi_poweron(struct exynos_dsi *dsi) | |
1462 | { | |
0ff03fd1 HH |
1463 | struct exynos_dsi_driver_data *driver_data = dsi->driver_data; |
1464 | int ret, i; | |
7eb8f069 AH |
1465 | |
1466 | ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies); | |
1467 | if (ret < 0) { | |
1468 | dev_err(dsi->dev, "cannot enable regulators %d\n", ret); | |
1469 | return ret; | |
1470 | } | |
1471 | ||
0ff03fd1 HH |
1472 | for (i = 0; i < driver_data->num_clks; i++) { |
1473 | ret = clk_prepare_enable(dsi->clks[i]); | |
1474 | if (ret < 0) | |
1475 | goto err_clk; | |
7eb8f069 AH |
1476 | } |
1477 | ||
1478 | ret = phy_power_on(dsi->phy); | |
1479 | if (ret < 0) { | |
1480 | dev_err(dsi->dev, "cannot enable phy %d\n", ret); | |
0ff03fd1 | 1481 | goto err_clk; |
7eb8f069 AH |
1482 | } |
1483 | ||
1484 | return 0; | |
1485 | ||
0ff03fd1 HH |
1486 | err_clk: |
1487 | while (--i > -1) | |
1488 | clk_disable_unprepare(dsi->clks[i]); | |
7eb8f069 AH |
1489 | regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); |
1490 | ||
1491 | return ret; | |
1492 | } | |
1493 | ||
1494 | static void exynos_dsi_poweroff(struct exynos_dsi *dsi) | |
1495 | { | |
0ff03fd1 HH |
1496 | struct exynos_dsi_driver_data *driver_data = dsi->driver_data; |
1497 | int ret, i; | |
7eb8f069 AH |
1498 | |
1499 | usleep_range(10000, 20000); | |
1500 | ||
1501 | if (dsi->state & DSIM_STATE_INITIALIZED) { | |
1502 | dsi->state &= ~DSIM_STATE_INITIALIZED; | |
1503 | ||
1504 | exynos_dsi_disable_clock(dsi); | |
1505 | ||
e17ddecc | 1506 | exynos_dsi_disable_irq(dsi); |
7eb8f069 AH |
1507 | } |
1508 | ||
1509 | dsi->state &= ~DSIM_STATE_CMD_LPM; | |
1510 | ||
1511 | phy_power_off(dsi->phy); | |
1512 | ||
0ff03fd1 HH |
1513 | for (i = driver_data->num_clks - 1; i > -1; i--) |
1514 | clk_disable_unprepare(dsi->clks[i]); | |
7eb8f069 AH |
1515 | |
1516 | ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); | |
1517 | if (ret < 0) | |
1518 | dev_err(dsi->dev, "cannot disable regulators %d\n", ret); | |
1519 | } | |
1520 | ||
1521 | static int exynos_dsi_enable(struct exynos_dsi *dsi) | |
1522 | { | |
1523 | int ret; | |
1524 | ||
1525 | if (dsi->state & DSIM_STATE_ENABLED) | |
1526 | return 0; | |
1527 | ||
1528 | ret = exynos_dsi_poweron(dsi); | |
1529 | if (ret < 0) | |
1530 | return ret; | |
1531 | ||
0e480f6f HH |
1532 | dsi->state |= DSIM_STATE_ENABLED; |
1533 | ||
cdfb8694 | 1534 | ret = drm_panel_prepare(dsi->panel); |
7eb8f069 | 1535 | if (ret < 0) { |
0e480f6f | 1536 | dsi->state &= ~DSIM_STATE_ENABLED; |
7eb8f069 AH |
1537 | exynos_dsi_poweroff(dsi); |
1538 | return ret; | |
1539 | } | |
1540 | ||
1541 | exynos_dsi_set_display_mode(dsi); | |
1542 | exynos_dsi_set_display_enable(dsi, true); | |
1543 | ||
cdfb8694 AK |
1544 | ret = drm_panel_enable(dsi->panel); |
1545 | if (ret < 0) { | |
d41bb38f | 1546 | dsi->state &= ~DSIM_STATE_ENABLED; |
cdfb8694 AK |
1547 | exynos_dsi_set_display_enable(dsi, false); |
1548 | drm_panel_unprepare(dsi->panel); | |
1549 | exynos_dsi_poweroff(dsi); | |
1550 | return ret; | |
1551 | } | |
1552 | ||
0e480f6f HH |
1553 | dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE; |
1554 | ||
7eb8f069 AH |
1555 | return 0; |
1556 | } | |
1557 | ||
1558 | static void exynos_dsi_disable(struct exynos_dsi *dsi) | |
1559 | { | |
1560 | if (!(dsi->state & DSIM_STATE_ENABLED)) | |
1561 | return; | |
1562 | ||
0e480f6f HH |
1563 | dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE; |
1564 | ||
7eb8f069 | 1565 | drm_panel_disable(dsi->panel); |
cdfb8694 AK |
1566 | exynos_dsi_set_display_enable(dsi, false); |
1567 | drm_panel_unprepare(dsi->panel); | |
7eb8f069 AH |
1568 | |
1569 | dsi->state &= ~DSIM_STATE_ENABLED; | |
0e480f6f HH |
1570 | |
1571 | exynos_dsi_poweroff(dsi); | |
7eb8f069 AH |
1572 | } |
1573 | ||
1574 | static void exynos_dsi_dpms(struct exynos_drm_display *display, int mode) | |
1575 | { | |
5cd5db80 | 1576 | struct exynos_dsi *dsi = display_to_dsi(display); |
7eb8f069 AH |
1577 | |
1578 | if (dsi->panel) { | |
1579 | switch (mode) { | |
1580 | case DRM_MODE_DPMS_ON: | |
1581 | exynos_dsi_enable(dsi); | |
1582 | break; | |
1583 | case DRM_MODE_DPMS_STANDBY: | |
1584 | case DRM_MODE_DPMS_SUSPEND: | |
1585 | case DRM_MODE_DPMS_OFF: | |
1586 | exynos_dsi_disable(dsi); | |
1587 | break; | |
1588 | default: | |
1589 | break; | |
1590 | } | |
1591 | } | |
1592 | } | |
1593 | ||
1594 | static enum drm_connector_status | |
1595 | exynos_dsi_detect(struct drm_connector *connector, bool force) | |
1596 | { | |
1597 | struct exynos_dsi *dsi = connector_to_dsi(connector); | |
1598 | ||
1599 | if (!dsi->panel) { | |
1600 | dsi->panel = of_drm_find_panel(dsi->panel_node); | |
1601 | if (dsi->panel) | |
1602 | drm_panel_attach(dsi->panel, &dsi->connector); | |
1603 | } else if (!dsi->panel_node) { | |
1604 | struct exynos_drm_display *display; | |
1605 | ||
1606 | display = platform_get_drvdata(to_platform_device(dsi->dev)); | |
1607 | exynos_dsi_dpms(display, DRM_MODE_DPMS_OFF); | |
1608 | drm_panel_detach(dsi->panel); | |
1609 | dsi->panel = NULL; | |
1610 | } | |
1611 | ||
1612 | if (dsi->panel) | |
1613 | return connector_status_connected; | |
1614 | ||
1615 | return connector_status_disconnected; | |
1616 | } | |
1617 | ||
1618 | static void exynos_dsi_connector_destroy(struct drm_connector *connector) | |
1619 | { | |
0ae46015 AH |
1620 | drm_connector_unregister(connector); |
1621 | drm_connector_cleanup(connector); | |
1622 | connector->dev = NULL; | |
7eb8f069 AH |
1623 | } |
1624 | ||
1625 | static struct drm_connector_funcs exynos_dsi_connector_funcs = { | |
63498e30 | 1626 | .dpms = drm_atomic_helper_connector_dpms, |
7eb8f069 AH |
1627 | .detect = exynos_dsi_detect, |
1628 | .fill_modes = drm_helper_probe_single_connector_modes, | |
1629 | .destroy = exynos_dsi_connector_destroy, | |
4ea9526b GP |
1630 | .reset = drm_atomic_helper_connector_reset, |
1631 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, | |
1632 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, | |
7eb8f069 AH |
1633 | }; |
1634 | ||
1635 | static int exynos_dsi_get_modes(struct drm_connector *connector) | |
1636 | { | |
1637 | struct exynos_dsi *dsi = connector_to_dsi(connector); | |
1638 | ||
1639 | if (dsi->panel) | |
1640 | return dsi->panel->funcs->get_modes(dsi->panel); | |
1641 | ||
1642 | return 0; | |
1643 | } | |
1644 | ||
7eb8f069 AH |
1645 | static struct drm_encoder * |
1646 | exynos_dsi_best_encoder(struct drm_connector *connector) | |
1647 | { | |
1648 | struct exynos_dsi *dsi = connector_to_dsi(connector); | |
1649 | ||
e5169723 | 1650 | return dsi->display.encoder; |
7eb8f069 AH |
1651 | } |
1652 | ||
1653 | static struct drm_connector_helper_funcs exynos_dsi_connector_helper_funcs = { | |
1654 | .get_modes = exynos_dsi_get_modes, | |
7eb8f069 AH |
1655 | .best_encoder = exynos_dsi_best_encoder, |
1656 | }; | |
1657 | ||
1658 | static int exynos_dsi_create_connector(struct exynos_drm_display *display, | |
1659 | struct drm_encoder *encoder) | |
1660 | { | |
5cd5db80 | 1661 | struct exynos_dsi *dsi = display_to_dsi(display); |
7eb8f069 AH |
1662 | struct drm_connector *connector = &dsi->connector; |
1663 | int ret; | |
1664 | ||
7eb8f069 AH |
1665 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
1666 | ||
1667 | ret = drm_connector_init(encoder->dev, connector, | |
1668 | &exynos_dsi_connector_funcs, | |
1669 | DRM_MODE_CONNECTOR_DSI); | |
1670 | if (ret) { | |
1671 | DRM_ERROR("Failed to initialize connector with drm\n"); | |
1672 | return ret; | |
1673 | } | |
1674 | ||
1675 | drm_connector_helper_add(connector, &exynos_dsi_connector_helper_funcs); | |
34ea3d38 | 1676 | drm_connector_register(connector); |
7eb8f069 AH |
1677 | drm_mode_connector_attach_encoder(connector, encoder); |
1678 | ||
1679 | return 0; | |
1680 | } | |
1681 | ||
1682 | static void exynos_dsi_mode_set(struct exynos_drm_display *display, | |
1683 | struct drm_display_mode *mode) | |
1684 | { | |
5cd5db80 | 1685 | struct exynos_dsi *dsi = display_to_dsi(display); |
7eb8f069 AH |
1686 | struct videomode *vm = &dsi->vm; |
1687 | ||
1688 | vm->hactive = mode->hdisplay; | |
1689 | vm->vactive = mode->vdisplay; | |
1690 | vm->vfront_porch = mode->vsync_start - mode->vdisplay; | |
1691 | vm->vback_porch = mode->vtotal - mode->vsync_end; | |
1692 | vm->vsync_len = mode->vsync_end - mode->vsync_start; | |
1693 | vm->hfront_porch = mode->hsync_start - mode->hdisplay; | |
1694 | vm->hback_porch = mode->htotal - mode->hsync_end; | |
1695 | vm->hsync_len = mode->hsync_end - mode->hsync_start; | |
1696 | } | |
1697 | ||
1698 | static struct exynos_drm_display_ops exynos_dsi_display_ops = { | |
1699 | .create_connector = exynos_dsi_create_connector, | |
1700 | .mode_set = exynos_dsi_mode_set, | |
1701 | .dpms = exynos_dsi_dpms | |
1702 | }; | |
1703 | ||
bd024b86 | 1704 | MODULE_DEVICE_TABLE(of, exynos_dsi_of_match); |
7eb8f069 AH |
1705 | |
1706 | /* of_* functions will be removed after merge of of_graph patches */ | |
1707 | static struct device_node * | |
1708 | of_get_child_by_name_reg(struct device_node *parent, const char *name, u32 reg) | |
1709 | { | |
1710 | struct device_node *np; | |
1711 | ||
1712 | for_each_child_of_node(parent, np) { | |
1713 | u32 r; | |
1714 | ||
1715 | if (!np->name || of_node_cmp(np->name, name)) | |
1716 | continue; | |
1717 | ||
1718 | if (of_property_read_u32(np, "reg", &r) < 0) | |
1719 | r = 0; | |
1720 | ||
1721 | if (reg == r) | |
1722 | break; | |
1723 | } | |
1724 | ||
1725 | return np; | |
1726 | } | |
1727 | ||
1728 | static struct device_node *of_graph_get_port_by_reg(struct device_node *parent, | |
1729 | u32 reg) | |
1730 | { | |
1731 | struct device_node *ports, *port; | |
1732 | ||
1733 | ports = of_get_child_by_name(parent, "ports"); | |
1734 | if (ports) | |
1735 | parent = ports; | |
1736 | ||
1737 | port = of_get_child_by_name_reg(parent, "port", reg); | |
1738 | ||
1739 | of_node_put(ports); | |
1740 | ||
1741 | return port; | |
1742 | } | |
1743 | ||
1744 | static struct device_node * | |
1745 | of_graph_get_endpoint_by_reg(struct device_node *port, u32 reg) | |
1746 | { | |
1747 | return of_get_child_by_name_reg(port, "endpoint", reg); | |
1748 | } | |
1749 | ||
1750 | static int exynos_dsi_of_read_u32(const struct device_node *np, | |
1751 | const char *propname, u32 *out_value) | |
1752 | { | |
1753 | int ret = of_property_read_u32(np, propname, out_value); | |
1754 | ||
1755 | if (ret < 0) | |
1756 | pr_err("%s: failed to get '%s' property\n", np->full_name, | |
1757 | propname); | |
1758 | ||
1759 | return ret; | |
1760 | } | |
1761 | ||
1762 | enum { | |
1763 | DSI_PORT_IN, | |
1764 | DSI_PORT_OUT | |
1765 | }; | |
1766 | ||
1767 | static int exynos_dsi_parse_dt(struct exynos_dsi *dsi) | |
1768 | { | |
1769 | struct device *dev = dsi->dev; | |
1770 | struct device_node *node = dev->of_node; | |
1771 | struct device_node *port, *ep; | |
1772 | int ret; | |
1773 | ||
1774 | ret = exynos_dsi_of_read_u32(node, "samsung,pll-clock-frequency", | |
1775 | &dsi->pll_clk_rate); | |
1776 | if (ret < 0) | |
1777 | return ret; | |
1778 | ||
1779 | port = of_graph_get_port_by_reg(node, DSI_PORT_OUT); | |
1780 | if (!port) { | |
1781 | dev_err(dev, "no output port specified\n"); | |
1782 | return -EINVAL; | |
1783 | } | |
1784 | ||
1785 | ep = of_graph_get_endpoint_by_reg(port, 0); | |
1786 | of_node_put(port); | |
1787 | if (!ep) { | |
1788 | dev_err(dev, "no endpoint specified in output port\n"); | |
1789 | return -EINVAL; | |
1790 | } | |
1791 | ||
1792 | ret = exynos_dsi_of_read_u32(ep, "samsung,burst-clock-frequency", | |
1793 | &dsi->burst_clk_rate); | |
1794 | if (ret < 0) | |
1795 | goto end; | |
1796 | ||
1797 | ret = exynos_dsi_of_read_u32(ep, "samsung,esc-clock-frequency", | |
1798 | &dsi->esc_clk_rate); | |
f5f3b9ba HH |
1799 | if (ret < 0) |
1800 | goto end; | |
1801 | ||
1802 | of_node_put(ep); | |
1803 | ||
1804 | ep = of_graph_get_next_endpoint(node, NULL); | |
1805 | if (!ep) { | |
1806 | ret = -ENXIO; | |
1807 | goto end; | |
1808 | } | |
7eb8f069 | 1809 | |
f5f3b9ba HH |
1810 | dsi->bridge_node = of_graph_get_remote_port_parent(ep); |
1811 | if (!dsi->bridge_node) { | |
1812 | ret = -ENXIO; | |
1813 | goto end; | |
1814 | } | |
7eb8f069 AH |
1815 | end: |
1816 | of_node_put(ep); | |
1817 | ||
1818 | return ret; | |
1819 | } | |
1820 | ||
f37cd5e8 ID |
1821 | static int exynos_dsi_bind(struct device *dev, struct device *master, |
1822 | void *data) | |
1823 | { | |
2900c69c | 1824 | struct exynos_drm_display *display = dev_get_drvdata(dev); |
5cd5db80 | 1825 | struct exynos_dsi *dsi = display_to_dsi(display); |
f37cd5e8 | 1826 | struct drm_device *drm_dev = data; |
f5f3b9ba | 1827 | struct drm_bridge *bridge; |
f37cd5e8 ID |
1828 | int ret; |
1829 | ||
2900c69c | 1830 | ret = exynos_drm_create_enc_conn(drm_dev, display); |
f37cd5e8 ID |
1831 | if (ret) { |
1832 | DRM_ERROR("Encoder create [%d] failed with %d\n", | |
2900c69c | 1833 | display->type, ret); |
f37cd5e8 ID |
1834 | return ret; |
1835 | } | |
1836 | ||
f5f3b9ba HH |
1837 | bridge = of_drm_find_bridge(dsi->bridge_node); |
1838 | if (bridge) { | |
1839 | display->encoder->bridge = bridge; | |
1840 | drm_bridge_attach(drm_dev, bridge); | |
1841 | } | |
1842 | ||
f37cd5e8 ID |
1843 | return mipi_dsi_host_register(&dsi->dsi_host); |
1844 | } | |
1845 | ||
1846 | static void exynos_dsi_unbind(struct device *dev, struct device *master, | |
1847 | void *data) | |
1848 | { | |
2900c69c | 1849 | struct exynos_drm_display *display = dev_get_drvdata(dev); |
5cd5db80 | 1850 | struct exynos_dsi *dsi = display_to_dsi(display); |
f37cd5e8 | 1851 | |
2900c69c | 1852 | exynos_dsi_dpms(display, DRM_MODE_DPMS_OFF); |
f37cd5e8 | 1853 | |
0ae46015 | 1854 | mipi_dsi_host_unregister(&dsi->dsi_host); |
f37cd5e8 ID |
1855 | } |
1856 | ||
f37cd5e8 ID |
1857 | static const struct component_ops exynos_dsi_component_ops = { |
1858 | .bind = exynos_dsi_bind, | |
1859 | .unbind = exynos_dsi_unbind, | |
1860 | }; | |
1861 | ||
7eb8f069 AH |
1862 | static int exynos_dsi_probe(struct platform_device *pdev) |
1863 | { | |
2900c69c | 1864 | struct device *dev = &pdev->dev; |
7eb8f069 AH |
1865 | struct resource *res; |
1866 | struct exynos_dsi *dsi; | |
0ff03fd1 | 1867 | int ret, i; |
7eb8f069 | 1868 | |
2900c69c AH |
1869 | dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); |
1870 | if (!dsi) | |
1871 | return -ENOMEM; | |
1872 | ||
1873 | dsi->display.type = EXYNOS_DISPLAY_TYPE_LCD; | |
1874 | dsi->display.ops = &exynos_dsi_display_ops; | |
1875 | ||
e17ddecc YC |
1876 | /* To be checked as invalid one */ |
1877 | dsi->te_gpio = -ENOENT; | |
1878 | ||
7eb8f069 AH |
1879 | init_completion(&dsi->completed); |
1880 | spin_lock_init(&dsi->transfer_lock); | |
1881 | INIT_LIST_HEAD(&dsi->transfer_list); | |
1882 | ||
1883 | dsi->dsi_host.ops = &exynos_dsi_ops; | |
e2d2a1e0 | 1884 | dsi->dsi_host.dev = dev; |
7eb8f069 | 1885 | |
e2d2a1e0 | 1886 | dsi->dev = dev; |
9a320415 | 1887 | dsi->driver_data = exynos_dsi_get_driver_data(pdev); |
7eb8f069 AH |
1888 | |
1889 | ret = exynos_dsi_parse_dt(dsi); | |
1890 | if (ret) | |
86650408 | 1891 | return ret; |
7eb8f069 AH |
1892 | |
1893 | dsi->supplies[0].supply = "vddcore"; | |
1894 | dsi->supplies[1].supply = "vddio"; | |
e2d2a1e0 | 1895 | ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies), |
7eb8f069 AH |
1896 | dsi->supplies); |
1897 | if (ret) { | |
e2d2a1e0 | 1898 | dev_info(dev, "failed to get regulators: %d\n", ret); |
7eb8f069 AH |
1899 | return -EPROBE_DEFER; |
1900 | } | |
1901 | ||
0ff03fd1 HH |
1902 | dsi->clks = devm_kzalloc(dev, |
1903 | sizeof(*dsi->clks) * dsi->driver_data->num_clks, | |
1904 | GFP_KERNEL); | |
e6f988a4 HH |
1905 | if (!dsi->clks) |
1906 | return -ENOMEM; | |
1907 | ||
0ff03fd1 HH |
1908 | for (i = 0; i < dsi->driver_data->num_clks; i++) { |
1909 | dsi->clks[i] = devm_clk_get(dev, clk_names[i]); | |
1910 | if (IS_ERR(dsi->clks[i])) { | |
1911 | if (strcmp(clk_names[i], "sclk_mipi") == 0) { | |
1912 | strcpy(clk_names[i], OLD_SCLK_MIPI_CLK_NAME); | |
1913 | i--; | |
1914 | continue; | |
1915 | } | |
7eb8f069 | 1916 | |
0ff03fd1 HH |
1917 | dev_info(dev, "failed to get the clock: %s\n", |
1918 | clk_names[i]); | |
1919 | return PTR_ERR(dsi->clks[i]); | |
1920 | } | |
7eb8f069 AH |
1921 | } |
1922 | ||
1923 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
e2d2a1e0 | 1924 | dsi->reg_base = devm_ioremap_resource(dev, res); |
293d3f6a | 1925 | if (IS_ERR(dsi->reg_base)) { |
e2d2a1e0 | 1926 | dev_err(dev, "failed to remap io region\n"); |
86650408 | 1927 | return PTR_ERR(dsi->reg_base); |
7eb8f069 AH |
1928 | } |
1929 | ||
e2d2a1e0 | 1930 | dsi->phy = devm_phy_get(dev, "dsim"); |
7eb8f069 | 1931 | if (IS_ERR(dsi->phy)) { |
e2d2a1e0 | 1932 | dev_info(dev, "failed to get dsim phy\n"); |
86650408 | 1933 | return PTR_ERR(dsi->phy); |
7eb8f069 AH |
1934 | } |
1935 | ||
1936 | dsi->irq = platform_get_irq(pdev, 0); | |
1937 | if (dsi->irq < 0) { | |
e2d2a1e0 | 1938 | dev_err(dev, "failed to request dsi irq resource\n"); |
86650408 | 1939 | return dsi->irq; |
7eb8f069 AH |
1940 | } |
1941 | ||
1942 | irq_set_status_flags(dsi->irq, IRQ_NOAUTOEN); | |
e2d2a1e0 | 1943 | ret = devm_request_threaded_irq(dev, dsi->irq, NULL, |
7eb8f069 | 1944 | exynos_dsi_irq, IRQF_ONESHOT, |
e2d2a1e0 | 1945 | dev_name(dev), dsi); |
7eb8f069 | 1946 | if (ret) { |
e2d2a1e0 | 1947 | dev_err(dev, "failed to request dsi irq\n"); |
86650408 | 1948 | return ret; |
7eb8f069 AH |
1949 | } |
1950 | ||
e2d2a1e0 | 1951 | platform_set_drvdata(pdev, &dsi->display); |
7eb8f069 | 1952 | |
86650408 | 1953 | return component_add(dev, &exynos_dsi_component_ops); |
7eb8f069 AH |
1954 | } |
1955 | ||
1956 | static int exynos_dsi_remove(struct platform_device *pdev) | |
1957 | { | |
df5225bc | 1958 | component_del(&pdev->dev, &exynos_dsi_component_ops); |
df5225bc | 1959 | |
7eb8f069 AH |
1960 | return 0; |
1961 | } | |
1962 | ||
7eb8f069 AH |
1963 | struct platform_driver dsi_driver = { |
1964 | .probe = exynos_dsi_probe, | |
1965 | .remove = exynos_dsi_remove, | |
1966 | .driver = { | |
1967 | .name = "exynos-dsi", | |
1968 | .owner = THIS_MODULE, | |
7eb8f069 AH |
1969 | .of_match_table = exynos_dsi_of_match, |
1970 | }, | |
1971 | }; | |
1972 | ||
1973 | MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>"); | |
1974 | MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>"); | |
1975 | MODULE_DESCRIPTION("Samsung SoC MIPI DSI Master"); | |
1976 | MODULE_LICENSE("GPL v2"); |