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7eb8f069 AH |
1 | /* |
2 | * Samsung SoC MIPI DSI Master driver. | |
3 | * | |
4 | * Copyright (c) 2014 Samsung Electronics Co., Ltd | |
5 | * | |
6 | * Contacts: Tomasz Figa <t.figa@samsung.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <drm/drmP.h> | |
14 | #include <drm/drm_crtc_helper.h> | |
15 | #include <drm/drm_mipi_dsi.h> | |
16 | #include <drm/drm_panel.h> | |
17 | ||
18 | #include <linux/clk.h> | |
e17ddecc | 19 | #include <linux/gpio/consumer.h> |
7eb8f069 | 20 | #include <linux/irq.h> |
e17ddecc | 21 | #include <linux/of_gpio.h> |
7eb8f069 AH |
22 | #include <linux/phy/phy.h> |
23 | #include <linux/regulator/consumer.h> | |
f37cd5e8 | 24 | #include <linux/component.h> |
7eb8f069 AH |
25 | |
26 | #include <video/mipi_display.h> | |
27 | #include <video/videomode.h> | |
28 | ||
e17ddecc | 29 | #include "exynos_drm_crtc.h" |
7eb8f069 AH |
30 | #include "exynos_drm_drv.h" |
31 | ||
32 | /* returns true iff both arguments logically differs */ | |
33 | #define NEQV(a, b) (!(a) ^ !(b)) | |
34 | ||
35 | #define DSIM_STATUS_REG 0x0 /* Status register */ | |
36 | #define DSIM_SWRST_REG 0x4 /* Software reset register */ | |
37 | #define DSIM_CLKCTRL_REG 0x8 /* Clock control register */ | |
38 | #define DSIM_TIMEOUT_REG 0xc /* Time out register */ | |
39 | #define DSIM_CONFIG_REG 0x10 /* Configuration register */ | |
40 | #define DSIM_ESCMODE_REG 0x14 /* Escape mode register */ | |
41 | ||
42 | /* Main display image resolution register */ | |
43 | #define DSIM_MDRESOL_REG 0x18 | |
44 | #define DSIM_MVPORCH_REG 0x1c /* Main display Vporch register */ | |
45 | #define DSIM_MHPORCH_REG 0x20 /* Main display Hporch register */ | |
46 | #define DSIM_MSYNC_REG 0x24 /* Main display sync area register */ | |
47 | ||
48 | /* Sub display image resolution register */ | |
49 | #define DSIM_SDRESOL_REG 0x28 | |
50 | #define DSIM_INTSRC_REG 0x2c /* Interrupt source register */ | |
51 | #define DSIM_INTMSK_REG 0x30 /* Interrupt mask register */ | |
52 | #define DSIM_PKTHDR_REG 0x34 /* Packet Header FIFO register */ | |
53 | #define DSIM_PAYLOAD_REG 0x38 /* Payload FIFO register */ | |
54 | #define DSIM_RXFIFO_REG 0x3c /* Read FIFO register */ | |
55 | #define DSIM_FIFOTHLD_REG 0x40 /* FIFO threshold level register */ | |
56 | #define DSIM_FIFOCTRL_REG 0x44 /* FIFO status and control register */ | |
57 | ||
58 | /* FIFO memory AC characteristic register */ | |
59 | #define DSIM_PLLCTRL_REG 0x4c /* PLL control register */ | |
60 | #define DSIM_PLLTMR_REG 0x50 /* PLL timer register */ | |
61 | #define DSIM_PHYACCHR_REG 0x54 /* D-PHY AC characteristic register */ | |
62 | #define DSIM_PHYACCHR1_REG 0x58 /* D-PHY AC characteristic register1 */ | |
63 | ||
64 | /* DSIM_STATUS */ | |
65 | #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0) | |
66 | #define DSIM_STOP_STATE_CLK (1 << 8) | |
67 | #define DSIM_TX_READY_HS_CLK (1 << 10) | |
68 | #define DSIM_PLL_STABLE (1 << 31) | |
69 | ||
70 | /* DSIM_SWRST */ | |
71 | #define DSIM_FUNCRST (1 << 16) | |
72 | #define DSIM_SWRST (1 << 0) | |
73 | ||
74 | /* DSIM_TIMEOUT */ | |
75 | #define DSIM_LPDR_TIMEOUT(x) ((x) << 0) | |
76 | #define DSIM_BTA_TIMEOUT(x) ((x) << 16) | |
77 | ||
78 | /* DSIM_CLKCTRL */ | |
79 | #define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0) | |
80 | #define DSIM_ESC_PRESCALER_MASK (0xffff << 0) | |
81 | #define DSIM_LANE_ESC_CLK_EN_CLK (1 << 19) | |
82 | #define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20) | |
83 | #define DSIM_LANE_ESC_CLK_EN_DATA_MASK (0xf << 20) | |
84 | #define DSIM_BYTE_CLKEN (1 << 24) | |
85 | #define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25) | |
86 | #define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25) | |
87 | #define DSIM_PLL_BYPASS (1 << 27) | |
88 | #define DSIM_ESC_CLKEN (1 << 28) | |
89 | #define DSIM_TX_REQUEST_HSCLK (1 << 31) | |
90 | ||
91 | /* DSIM_CONFIG */ | |
92 | #define DSIM_LANE_EN_CLK (1 << 0) | |
93 | #define DSIM_LANE_EN(x) (((x) & 0xf) << 1) | |
94 | #define DSIM_NUM_OF_DATA_LANE(x) (((x) & 0x3) << 5) | |
95 | #define DSIM_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8) | |
96 | #define DSIM_MAIN_PIX_FORMAT_MASK (0x7 << 12) | |
97 | #define DSIM_MAIN_PIX_FORMAT_RGB888 (0x7 << 12) | |
98 | #define DSIM_MAIN_PIX_FORMAT_RGB666 (0x6 << 12) | |
99 | #define DSIM_MAIN_PIX_FORMAT_RGB666_P (0x5 << 12) | |
100 | #define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12) | |
101 | #define DSIM_SUB_VC (((x) & 0x3) << 16) | |
102 | #define DSIM_MAIN_VC (((x) & 0x3) << 18) | |
103 | #define DSIM_HSA_MODE (1 << 20) | |
104 | #define DSIM_HBP_MODE (1 << 21) | |
105 | #define DSIM_HFP_MODE (1 << 22) | |
106 | #define DSIM_HSE_MODE (1 << 23) | |
107 | #define DSIM_AUTO_MODE (1 << 24) | |
108 | #define DSIM_VIDEO_MODE (1 << 25) | |
109 | #define DSIM_BURST_MODE (1 << 26) | |
110 | #define DSIM_SYNC_INFORM (1 << 27) | |
111 | #define DSIM_EOT_DISABLE (1 << 28) | |
112 | #define DSIM_MFLUSH_VS (1 << 29) | |
113 | ||
114 | /* DSIM_ESCMODE */ | |
115 | #define DSIM_TX_TRIGGER_RST (1 << 4) | |
116 | #define DSIM_TX_LPDT_LP (1 << 6) | |
117 | #define DSIM_CMD_LPDT_LP (1 << 7) | |
118 | #define DSIM_FORCE_BTA (1 << 16) | |
119 | #define DSIM_FORCE_STOP_STATE (1 << 20) | |
120 | #define DSIM_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21) | |
121 | #define DSIM_STOP_STATE_CNT_MASK (0x7ff << 21) | |
122 | ||
123 | /* DSIM_MDRESOL */ | |
124 | #define DSIM_MAIN_STAND_BY (1 << 31) | |
125 | #define DSIM_MAIN_VRESOL(x) (((x) & 0x7ff) << 16) | |
126 | #define DSIM_MAIN_HRESOL(x) (((x) & 0X7ff) << 0) | |
127 | ||
128 | /* DSIM_MVPORCH */ | |
129 | #define DSIM_CMD_ALLOW(x) ((x) << 28) | |
130 | #define DSIM_STABLE_VFP(x) ((x) << 16) | |
131 | #define DSIM_MAIN_VBP(x) ((x) << 0) | |
132 | #define DSIM_CMD_ALLOW_MASK (0xf << 28) | |
133 | #define DSIM_STABLE_VFP_MASK (0x7ff << 16) | |
134 | #define DSIM_MAIN_VBP_MASK (0x7ff << 0) | |
135 | ||
136 | /* DSIM_MHPORCH */ | |
137 | #define DSIM_MAIN_HFP(x) ((x) << 16) | |
138 | #define DSIM_MAIN_HBP(x) ((x) << 0) | |
139 | #define DSIM_MAIN_HFP_MASK ((0xffff) << 16) | |
140 | #define DSIM_MAIN_HBP_MASK ((0xffff) << 0) | |
141 | ||
142 | /* DSIM_MSYNC */ | |
143 | #define DSIM_MAIN_VSA(x) ((x) << 22) | |
144 | #define DSIM_MAIN_HSA(x) ((x) << 0) | |
145 | #define DSIM_MAIN_VSA_MASK ((0x3ff) << 22) | |
146 | #define DSIM_MAIN_HSA_MASK ((0xffff) << 0) | |
147 | ||
148 | /* DSIM_SDRESOL */ | |
149 | #define DSIM_SUB_STANDY(x) ((x) << 31) | |
150 | #define DSIM_SUB_VRESOL(x) ((x) << 16) | |
151 | #define DSIM_SUB_HRESOL(x) ((x) << 0) | |
152 | #define DSIM_SUB_STANDY_MASK ((0x1) << 31) | |
153 | #define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16) | |
154 | #define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0) | |
155 | ||
156 | /* DSIM_INTSRC */ | |
157 | #define DSIM_INT_PLL_STABLE (1 << 31) | |
158 | #define DSIM_INT_SW_RST_RELEASE (1 << 30) | |
159 | #define DSIM_INT_SFR_FIFO_EMPTY (1 << 29) | |
160 | #define DSIM_INT_BTA (1 << 25) | |
161 | #define DSIM_INT_FRAME_DONE (1 << 24) | |
162 | #define DSIM_INT_RX_TIMEOUT (1 << 21) | |
163 | #define DSIM_INT_BTA_TIMEOUT (1 << 20) | |
164 | #define DSIM_INT_RX_DONE (1 << 18) | |
165 | #define DSIM_INT_RX_TE (1 << 17) | |
166 | #define DSIM_INT_RX_ACK (1 << 16) | |
167 | #define DSIM_INT_RX_ECC_ERR (1 << 15) | |
168 | #define DSIM_INT_RX_CRC_ERR (1 << 14) | |
169 | ||
170 | /* DSIM_FIFOCTRL */ | |
171 | #define DSIM_RX_DATA_FULL (1 << 25) | |
172 | #define DSIM_RX_DATA_EMPTY (1 << 24) | |
173 | #define DSIM_SFR_HEADER_FULL (1 << 23) | |
174 | #define DSIM_SFR_HEADER_EMPTY (1 << 22) | |
175 | #define DSIM_SFR_PAYLOAD_FULL (1 << 21) | |
176 | #define DSIM_SFR_PAYLOAD_EMPTY (1 << 20) | |
177 | #define DSIM_I80_HEADER_FULL (1 << 19) | |
178 | #define DSIM_I80_HEADER_EMPTY (1 << 18) | |
179 | #define DSIM_I80_PAYLOAD_FULL (1 << 17) | |
180 | #define DSIM_I80_PAYLOAD_EMPTY (1 << 16) | |
181 | #define DSIM_SD_HEADER_FULL (1 << 15) | |
182 | #define DSIM_SD_HEADER_EMPTY (1 << 14) | |
183 | #define DSIM_SD_PAYLOAD_FULL (1 << 13) | |
184 | #define DSIM_SD_PAYLOAD_EMPTY (1 << 12) | |
185 | #define DSIM_MD_HEADER_FULL (1 << 11) | |
186 | #define DSIM_MD_HEADER_EMPTY (1 << 10) | |
187 | #define DSIM_MD_PAYLOAD_FULL (1 << 9) | |
188 | #define DSIM_MD_PAYLOAD_EMPTY (1 << 8) | |
189 | #define DSIM_RX_FIFO (1 << 4) | |
190 | #define DSIM_SFR_FIFO (1 << 3) | |
191 | #define DSIM_I80_FIFO (1 << 2) | |
192 | #define DSIM_SD_FIFO (1 << 1) | |
193 | #define DSIM_MD_FIFO (1 << 0) | |
194 | ||
195 | /* DSIM_PHYACCHR */ | |
196 | #define DSIM_AFC_EN (1 << 14) | |
197 | #define DSIM_AFC_CTL(x) (((x) & 0x7) << 5) | |
198 | ||
199 | /* DSIM_PLLCTRL */ | |
200 | #define DSIM_FREQ_BAND(x) ((x) << 24) | |
201 | #define DSIM_PLL_EN (1 << 23) | |
202 | #define DSIM_PLL_P(x) ((x) << 13) | |
203 | #define DSIM_PLL_M(x) ((x) << 4) | |
204 | #define DSIM_PLL_S(x) ((x) << 1) | |
205 | ||
206 | #define DSI_MAX_BUS_WIDTH 4 | |
207 | #define DSI_NUM_VIRTUAL_CHANNELS 4 | |
208 | #define DSI_TX_FIFO_SIZE 2048 | |
209 | #define DSI_RX_FIFO_SIZE 256 | |
210 | #define DSI_XFER_TIMEOUT_MS 100 | |
211 | #define DSI_RX_FIFO_EMPTY 0x30800002 | |
212 | ||
213 | enum exynos_dsi_transfer_type { | |
214 | EXYNOS_DSI_TX, | |
215 | EXYNOS_DSI_RX, | |
216 | }; | |
217 | ||
218 | struct exynos_dsi_transfer { | |
219 | struct list_head list; | |
220 | struct completion completed; | |
221 | int result; | |
222 | u8 data_id; | |
223 | u8 data[2]; | |
224 | u16 flags; | |
225 | ||
226 | const u8 *tx_payload; | |
227 | u16 tx_len; | |
228 | u16 tx_done; | |
229 | ||
230 | u8 *rx_payload; | |
231 | u16 rx_len; | |
232 | u16 rx_done; | |
233 | }; | |
234 | ||
235 | #define DSIM_STATE_ENABLED BIT(0) | |
236 | #define DSIM_STATE_INITIALIZED BIT(1) | |
237 | #define DSIM_STATE_CMD_LPM BIT(2) | |
238 | ||
239 | struct exynos_dsi { | |
240 | struct mipi_dsi_host dsi_host; | |
241 | struct drm_connector connector; | |
242 | struct drm_encoder *encoder; | |
243 | struct device_node *panel_node; | |
244 | struct drm_panel *panel; | |
245 | struct device *dev; | |
246 | ||
247 | void __iomem *reg_base; | |
248 | struct phy *phy; | |
249 | struct clk *pll_clk; | |
250 | struct clk *bus_clk; | |
251 | struct regulator_bulk_data supplies[2]; | |
252 | int irq; | |
e17ddecc | 253 | int te_gpio; |
7eb8f069 AH |
254 | |
255 | u32 pll_clk_rate; | |
256 | u32 burst_clk_rate; | |
257 | u32 esc_clk_rate; | |
258 | u32 lanes; | |
259 | u32 mode_flags; | |
260 | u32 format; | |
261 | struct videomode vm; | |
262 | ||
263 | int state; | |
264 | struct drm_property *brightness; | |
265 | struct completion completed; | |
266 | ||
267 | spinlock_t transfer_lock; /* protects transfer_list */ | |
268 | struct list_head transfer_list; | |
269 | }; | |
270 | ||
271 | #define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host) | |
272 | #define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector) | |
273 | ||
274 | static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi) | |
275 | { | |
276 | if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300))) | |
277 | return; | |
278 | ||
279 | dev_err(dsi->dev, "timeout waiting for reset\n"); | |
280 | } | |
281 | ||
282 | static void exynos_dsi_reset(struct exynos_dsi *dsi) | |
283 | { | |
284 | reinit_completion(&dsi->completed); | |
285 | writel(DSIM_SWRST, dsi->reg_base + DSIM_SWRST_REG); | |
286 | } | |
287 | ||
288 | #ifndef MHZ | |
289 | #define MHZ (1000*1000) | |
290 | #endif | |
291 | ||
292 | static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi, | |
293 | unsigned long fin, unsigned long fout, u8 *p, u16 *m, u8 *s) | |
294 | { | |
295 | unsigned long best_freq = 0; | |
296 | u32 min_delta = 0xffffffff; | |
297 | u8 p_min, p_max; | |
298 | u8 _p, uninitialized_var(best_p); | |
299 | u16 _m, uninitialized_var(best_m); | |
300 | u8 _s, uninitialized_var(best_s); | |
301 | ||
302 | p_min = DIV_ROUND_UP(fin, (12 * MHZ)); | |
303 | p_max = fin / (6 * MHZ); | |
304 | ||
305 | for (_p = p_min; _p <= p_max; ++_p) { | |
306 | for (_s = 0; _s <= 5; ++_s) { | |
307 | u64 tmp; | |
308 | u32 delta; | |
309 | ||
310 | tmp = (u64)fout * (_p << _s); | |
311 | do_div(tmp, fin); | |
312 | _m = tmp; | |
313 | if (_m < 41 || _m > 125) | |
314 | continue; | |
315 | ||
316 | tmp = (u64)_m * fin; | |
317 | do_div(tmp, _p); | |
318 | if (tmp < 500 * MHZ || tmp > 1000 * MHZ) | |
319 | continue; | |
320 | ||
321 | tmp = (u64)_m * fin; | |
322 | do_div(tmp, _p << _s); | |
323 | ||
324 | delta = abs(fout - tmp); | |
325 | if (delta < min_delta) { | |
326 | best_p = _p; | |
327 | best_m = _m; | |
328 | best_s = _s; | |
329 | min_delta = delta; | |
330 | best_freq = tmp; | |
331 | } | |
332 | } | |
333 | } | |
334 | ||
335 | if (best_freq) { | |
336 | *p = best_p; | |
337 | *m = best_m; | |
338 | *s = best_s; | |
339 | } | |
340 | ||
341 | return best_freq; | |
342 | } | |
343 | ||
344 | static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi, | |
345 | unsigned long freq) | |
346 | { | |
347 | static const unsigned long freq_bands[] = { | |
348 | 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ, | |
349 | 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ, | |
350 | 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ, | |
351 | 770 * MHZ, 870 * MHZ, 950 * MHZ, | |
352 | }; | |
353 | unsigned long fin, fout; | |
354 | int timeout, band; | |
355 | u8 p, s; | |
356 | u16 m; | |
357 | u32 reg; | |
358 | ||
359 | clk_set_rate(dsi->pll_clk, dsi->pll_clk_rate); | |
360 | ||
361 | fin = clk_get_rate(dsi->pll_clk); | |
362 | if (!fin) { | |
363 | dev_err(dsi->dev, "failed to get PLL clock frequency\n"); | |
364 | return 0; | |
365 | } | |
366 | ||
367 | dev_dbg(dsi->dev, "PLL input frequency: %lu\n", fin); | |
368 | ||
369 | fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s); | |
370 | if (!fout) { | |
371 | dev_err(dsi->dev, | |
372 | "failed to find PLL PMS for requested frequency\n"); | |
373 | return -EFAULT; | |
374 | } | |
375 | ||
376 | for (band = 0; band < ARRAY_SIZE(freq_bands); ++band) | |
377 | if (fout < freq_bands[band]) | |
378 | break; | |
379 | ||
380 | dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d), band %d\n", fout, | |
381 | p, m, s, band); | |
382 | ||
383 | writel(500, dsi->reg_base + DSIM_PLLTMR_REG); | |
384 | ||
385 | reg = DSIM_FREQ_BAND(band) | DSIM_PLL_EN | |
386 | | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s); | |
387 | writel(reg, dsi->reg_base + DSIM_PLLCTRL_REG); | |
388 | ||
389 | timeout = 1000; | |
390 | do { | |
391 | if (timeout-- == 0) { | |
392 | dev_err(dsi->dev, "PLL failed to stabilize\n"); | |
393 | return -EFAULT; | |
394 | } | |
395 | reg = readl(dsi->reg_base + DSIM_STATUS_REG); | |
396 | } while ((reg & DSIM_PLL_STABLE) == 0); | |
397 | ||
398 | return fout; | |
399 | } | |
400 | ||
401 | static int exynos_dsi_enable_clock(struct exynos_dsi *dsi) | |
402 | { | |
403 | unsigned long hs_clk, byte_clk, esc_clk; | |
404 | unsigned long esc_div; | |
405 | u32 reg; | |
406 | ||
407 | hs_clk = exynos_dsi_set_pll(dsi, dsi->burst_clk_rate); | |
408 | if (!hs_clk) { | |
409 | dev_err(dsi->dev, "failed to configure DSI PLL\n"); | |
410 | return -EFAULT; | |
411 | } | |
412 | ||
413 | byte_clk = hs_clk / 8; | |
414 | esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate); | |
415 | esc_clk = byte_clk / esc_div; | |
416 | ||
417 | if (esc_clk > 20 * MHZ) { | |
418 | ++esc_div; | |
419 | esc_clk = byte_clk / esc_div; | |
420 | } | |
421 | ||
422 | dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n", | |
423 | hs_clk, byte_clk, esc_clk); | |
424 | ||
425 | reg = readl(dsi->reg_base + DSIM_CLKCTRL_REG); | |
426 | reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK | |
427 | | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS | |
428 | | DSIM_BYTE_CLK_SRC_MASK); | |
429 | reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN | |
430 | | DSIM_ESC_PRESCALER(esc_div) | |
431 | | DSIM_LANE_ESC_CLK_EN_CLK | |
432 | | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1) | |
433 | | DSIM_BYTE_CLK_SRC(0) | |
434 | | DSIM_TX_REQUEST_HSCLK; | |
435 | writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG); | |
436 | ||
437 | return 0; | |
438 | } | |
439 | ||
440 | static void exynos_dsi_disable_clock(struct exynos_dsi *dsi) | |
441 | { | |
442 | u32 reg; | |
443 | ||
444 | reg = readl(dsi->reg_base + DSIM_CLKCTRL_REG); | |
445 | reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK | |
446 | | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN); | |
447 | writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG); | |
448 | ||
449 | reg = readl(dsi->reg_base + DSIM_PLLCTRL_REG); | |
450 | reg &= ~DSIM_PLL_EN; | |
451 | writel(reg, dsi->reg_base + DSIM_PLLCTRL_REG); | |
452 | } | |
453 | ||
454 | static int exynos_dsi_init_link(struct exynos_dsi *dsi) | |
455 | { | |
456 | int timeout; | |
457 | u32 reg; | |
458 | u32 lanes_mask; | |
459 | ||
460 | /* Initialize FIFO pointers */ | |
461 | reg = readl(dsi->reg_base + DSIM_FIFOCTRL_REG); | |
462 | reg &= ~0x1f; | |
463 | writel(reg, dsi->reg_base + DSIM_FIFOCTRL_REG); | |
464 | ||
465 | usleep_range(9000, 11000); | |
466 | ||
467 | reg |= 0x1f; | |
468 | writel(reg, dsi->reg_base + DSIM_FIFOCTRL_REG); | |
469 | ||
470 | usleep_range(9000, 11000); | |
471 | ||
472 | /* DSI configuration */ | |
473 | reg = 0; | |
474 | ||
2f36e33a YC |
475 | /* |
476 | * The first bit of mode_flags specifies display configuration. | |
477 | * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video | |
478 | * mode, otherwise it will support command mode. | |
479 | */ | |
7eb8f069 AH |
480 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { |
481 | reg |= DSIM_VIDEO_MODE; | |
482 | ||
2f36e33a YC |
483 | /* |
484 | * The user manual describes that following bits are ignored in | |
485 | * command mode. | |
486 | */ | |
7eb8f069 AH |
487 | if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH)) |
488 | reg |= DSIM_MFLUSH_VS; | |
7eb8f069 AH |
489 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) |
490 | reg |= DSIM_SYNC_INFORM; | |
491 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) | |
492 | reg |= DSIM_BURST_MODE; | |
493 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT) | |
494 | reg |= DSIM_AUTO_MODE; | |
495 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE) | |
496 | reg |= DSIM_HSE_MODE; | |
497 | if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP)) | |
498 | reg |= DSIM_HFP_MODE; | |
499 | if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP)) | |
500 | reg |= DSIM_HBP_MODE; | |
501 | if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA)) | |
502 | reg |= DSIM_HSA_MODE; | |
503 | } | |
504 | ||
2f36e33a YC |
505 | if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET)) |
506 | reg |= DSIM_EOT_DISABLE; | |
507 | ||
7eb8f069 AH |
508 | switch (dsi->format) { |
509 | case MIPI_DSI_FMT_RGB888: | |
510 | reg |= DSIM_MAIN_PIX_FORMAT_RGB888; | |
511 | break; | |
512 | case MIPI_DSI_FMT_RGB666: | |
513 | reg |= DSIM_MAIN_PIX_FORMAT_RGB666; | |
514 | break; | |
515 | case MIPI_DSI_FMT_RGB666_PACKED: | |
516 | reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P; | |
517 | break; | |
518 | case MIPI_DSI_FMT_RGB565: | |
519 | reg |= DSIM_MAIN_PIX_FORMAT_RGB565; | |
520 | break; | |
521 | default: | |
522 | dev_err(dsi->dev, "invalid pixel format\n"); | |
523 | return -EINVAL; | |
524 | } | |
525 | ||
526 | reg |= DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1); | |
527 | ||
528 | writel(reg, dsi->reg_base + DSIM_CONFIG_REG); | |
529 | ||
530 | reg |= DSIM_LANE_EN_CLK; | |
531 | writel(reg, dsi->reg_base + DSIM_CONFIG_REG); | |
532 | ||
533 | lanes_mask = BIT(dsi->lanes) - 1; | |
534 | reg |= DSIM_LANE_EN(lanes_mask); | |
535 | writel(reg, dsi->reg_base + DSIM_CONFIG_REG); | |
536 | ||
537 | /* Check clock and data lane state are stop state */ | |
538 | timeout = 100; | |
539 | do { | |
540 | if (timeout-- == 0) { | |
541 | dev_err(dsi->dev, "waiting for bus lanes timed out\n"); | |
542 | return -EFAULT; | |
543 | } | |
544 | ||
545 | reg = readl(dsi->reg_base + DSIM_STATUS_REG); | |
546 | if ((reg & DSIM_STOP_STATE_DAT(lanes_mask)) | |
547 | != DSIM_STOP_STATE_DAT(lanes_mask)) | |
548 | continue; | |
549 | } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK))); | |
550 | ||
551 | reg = readl(dsi->reg_base + DSIM_ESCMODE_REG); | |
552 | reg &= ~DSIM_STOP_STATE_CNT_MASK; | |
553 | reg |= DSIM_STOP_STATE_CNT(0xf); | |
554 | writel(reg, dsi->reg_base + DSIM_ESCMODE_REG); | |
555 | ||
556 | reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff); | |
557 | writel(reg, dsi->reg_base + DSIM_TIMEOUT_REG); | |
558 | ||
559 | return 0; | |
560 | } | |
561 | ||
562 | static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi) | |
563 | { | |
564 | struct videomode *vm = &dsi->vm; | |
565 | u32 reg; | |
566 | ||
567 | if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { | |
568 | reg = DSIM_CMD_ALLOW(0xf) | |
569 | | DSIM_STABLE_VFP(vm->vfront_porch) | |
570 | | DSIM_MAIN_VBP(vm->vback_porch); | |
571 | writel(reg, dsi->reg_base + DSIM_MVPORCH_REG); | |
572 | ||
573 | reg = DSIM_MAIN_HFP(vm->hfront_porch) | |
574 | | DSIM_MAIN_HBP(vm->hback_porch); | |
575 | writel(reg, dsi->reg_base + DSIM_MHPORCH_REG); | |
576 | ||
577 | reg = DSIM_MAIN_VSA(vm->vsync_len) | |
578 | | DSIM_MAIN_HSA(vm->hsync_len); | |
579 | writel(reg, dsi->reg_base + DSIM_MSYNC_REG); | |
580 | } | |
581 | ||
582 | reg = DSIM_MAIN_HRESOL(vm->hactive) | DSIM_MAIN_VRESOL(vm->vactive); | |
583 | writel(reg, dsi->reg_base + DSIM_MDRESOL_REG); | |
584 | ||
585 | dev_dbg(dsi->dev, "LCD size = %dx%d\n", vm->hactive, vm->vactive); | |
586 | } | |
587 | ||
588 | static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable) | |
589 | { | |
590 | u32 reg; | |
591 | ||
592 | reg = readl(dsi->reg_base + DSIM_MDRESOL_REG); | |
593 | if (enable) | |
594 | reg |= DSIM_MAIN_STAND_BY; | |
595 | else | |
596 | reg &= ~DSIM_MAIN_STAND_BY; | |
597 | writel(reg, dsi->reg_base + DSIM_MDRESOL_REG); | |
598 | } | |
599 | ||
600 | static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi) | |
601 | { | |
602 | int timeout = 2000; | |
603 | ||
604 | do { | |
605 | u32 reg = readl(dsi->reg_base + DSIM_FIFOCTRL_REG); | |
606 | ||
607 | if (!(reg & DSIM_SFR_HEADER_FULL)) | |
608 | return 0; | |
609 | ||
610 | if (!cond_resched()) | |
611 | usleep_range(950, 1050); | |
612 | } while (--timeout); | |
613 | ||
614 | return -ETIMEDOUT; | |
615 | } | |
616 | ||
617 | static void exynos_dsi_set_cmd_lpm(struct exynos_dsi *dsi, bool lpm) | |
618 | { | |
619 | u32 v = readl(dsi->reg_base + DSIM_ESCMODE_REG); | |
620 | ||
621 | if (lpm) | |
622 | v |= DSIM_CMD_LPDT_LP; | |
623 | else | |
624 | v &= ~DSIM_CMD_LPDT_LP; | |
625 | ||
626 | writel(v, dsi->reg_base + DSIM_ESCMODE_REG); | |
627 | } | |
628 | ||
629 | static void exynos_dsi_force_bta(struct exynos_dsi *dsi) | |
630 | { | |
631 | u32 v = readl(dsi->reg_base + DSIM_ESCMODE_REG); | |
632 | ||
633 | v |= DSIM_FORCE_BTA; | |
634 | writel(v, dsi->reg_base + DSIM_ESCMODE_REG); | |
635 | } | |
636 | ||
637 | static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi, | |
638 | struct exynos_dsi_transfer *xfer) | |
639 | { | |
640 | struct device *dev = dsi->dev; | |
641 | const u8 *payload = xfer->tx_payload + xfer->tx_done; | |
642 | u16 length = xfer->tx_len - xfer->tx_done; | |
643 | bool first = !xfer->tx_done; | |
644 | u32 reg; | |
645 | ||
646 | dev_dbg(dev, "< xfer %p: tx len %u, done %u, rx len %u, done %u\n", | |
647 | xfer, xfer->tx_len, xfer->tx_done, xfer->rx_len, xfer->rx_done); | |
648 | ||
649 | if (length > DSI_TX_FIFO_SIZE) | |
650 | length = DSI_TX_FIFO_SIZE; | |
651 | ||
652 | xfer->tx_done += length; | |
653 | ||
654 | /* Send payload */ | |
655 | while (length >= 4) { | |
656 | reg = (payload[3] << 24) | (payload[2] << 16) | |
657 | | (payload[1] << 8) | payload[0]; | |
658 | writel(reg, dsi->reg_base + DSIM_PAYLOAD_REG); | |
659 | payload += 4; | |
660 | length -= 4; | |
661 | } | |
662 | ||
663 | reg = 0; | |
664 | switch (length) { | |
665 | case 3: | |
666 | reg |= payload[2] << 16; | |
667 | /* Fall through */ | |
668 | case 2: | |
669 | reg |= payload[1] << 8; | |
670 | /* Fall through */ | |
671 | case 1: | |
672 | reg |= payload[0]; | |
673 | writel(reg, dsi->reg_base + DSIM_PAYLOAD_REG); | |
674 | break; | |
675 | case 0: | |
676 | /* Do nothing */ | |
677 | break; | |
678 | } | |
679 | ||
680 | /* Send packet header */ | |
681 | if (!first) | |
682 | return; | |
683 | ||
684 | reg = (xfer->data[1] << 16) | (xfer->data[0] << 8) | xfer->data_id; | |
685 | if (exynos_dsi_wait_for_hdr_fifo(dsi)) { | |
686 | dev_err(dev, "waiting for header FIFO timed out\n"); | |
687 | return; | |
688 | } | |
689 | ||
690 | if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM, | |
691 | dsi->state & DSIM_STATE_CMD_LPM)) { | |
692 | exynos_dsi_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM); | |
693 | dsi->state ^= DSIM_STATE_CMD_LPM; | |
694 | } | |
695 | ||
696 | writel(reg, dsi->reg_base + DSIM_PKTHDR_REG); | |
697 | ||
698 | if (xfer->flags & MIPI_DSI_MSG_REQ_ACK) | |
699 | exynos_dsi_force_bta(dsi); | |
700 | } | |
701 | ||
702 | static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi, | |
703 | struct exynos_dsi_transfer *xfer) | |
704 | { | |
705 | u8 *payload = xfer->rx_payload + xfer->rx_done; | |
706 | bool first = !xfer->rx_done; | |
707 | struct device *dev = dsi->dev; | |
708 | u16 length; | |
709 | u32 reg; | |
710 | ||
711 | if (first) { | |
712 | reg = readl(dsi->reg_base + DSIM_RXFIFO_REG); | |
713 | ||
714 | switch (reg & 0x3f) { | |
715 | case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: | |
716 | case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: | |
717 | if (xfer->rx_len >= 2) { | |
718 | payload[1] = reg >> 16; | |
719 | ++xfer->rx_done; | |
720 | } | |
721 | /* Fall through */ | |
722 | case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: | |
723 | case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: | |
724 | payload[0] = reg >> 8; | |
725 | ++xfer->rx_done; | |
726 | xfer->rx_len = xfer->rx_done; | |
727 | xfer->result = 0; | |
728 | goto clear_fifo; | |
729 | case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: | |
730 | dev_err(dev, "DSI Error Report: 0x%04x\n", | |
731 | (reg >> 8) & 0xffff); | |
732 | xfer->result = 0; | |
733 | goto clear_fifo; | |
734 | } | |
735 | ||
736 | length = (reg >> 8) & 0xffff; | |
737 | if (length > xfer->rx_len) { | |
738 | dev_err(dev, | |
739 | "response too long (%u > %u bytes), stripping\n", | |
740 | xfer->rx_len, length); | |
741 | length = xfer->rx_len; | |
742 | } else if (length < xfer->rx_len) | |
743 | xfer->rx_len = length; | |
744 | } | |
745 | ||
746 | length = xfer->rx_len - xfer->rx_done; | |
747 | xfer->rx_done += length; | |
748 | ||
749 | /* Receive payload */ | |
750 | while (length >= 4) { | |
751 | reg = readl(dsi->reg_base + DSIM_RXFIFO_REG); | |
752 | payload[0] = (reg >> 0) & 0xff; | |
753 | payload[1] = (reg >> 8) & 0xff; | |
754 | payload[2] = (reg >> 16) & 0xff; | |
755 | payload[3] = (reg >> 24) & 0xff; | |
756 | payload += 4; | |
757 | length -= 4; | |
758 | } | |
759 | ||
760 | if (length) { | |
761 | reg = readl(dsi->reg_base + DSIM_RXFIFO_REG); | |
762 | switch (length) { | |
763 | case 3: | |
764 | payload[2] = (reg >> 16) & 0xff; | |
765 | /* Fall through */ | |
766 | case 2: | |
767 | payload[1] = (reg >> 8) & 0xff; | |
768 | /* Fall through */ | |
769 | case 1: | |
770 | payload[0] = reg & 0xff; | |
771 | } | |
772 | } | |
773 | ||
774 | if (xfer->rx_done == xfer->rx_len) | |
775 | xfer->result = 0; | |
776 | ||
777 | clear_fifo: | |
778 | length = DSI_RX_FIFO_SIZE / 4; | |
779 | do { | |
780 | reg = readl(dsi->reg_base + DSIM_RXFIFO_REG); | |
781 | if (reg == DSI_RX_FIFO_EMPTY) | |
782 | break; | |
783 | } while (--length); | |
784 | } | |
785 | ||
786 | static void exynos_dsi_transfer_start(struct exynos_dsi *dsi) | |
787 | { | |
788 | unsigned long flags; | |
789 | struct exynos_dsi_transfer *xfer; | |
790 | bool start = false; | |
791 | ||
792 | again: | |
793 | spin_lock_irqsave(&dsi->transfer_lock, flags); | |
794 | ||
795 | if (list_empty(&dsi->transfer_list)) { | |
796 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); | |
797 | return; | |
798 | } | |
799 | ||
800 | xfer = list_first_entry(&dsi->transfer_list, | |
801 | struct exynos_dsi_transfer, list); | |
802 | ||
803 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); | |
804 | ||
805 | if (xfer->tx_len && xfer->tx_done == xfer->tx_len) | |
806 | /* waiting for RX */ | |
807 | return; | |
808 | ||
809 | exynos_dsi_send_to_fifo(dsi, xfer); | |
810 | ||
811 | if (xfer->tx_len || xfer->rx_len) | |
812 | return; | |
813 | ||
814 | xfer->result = 0; | |
815 | complete(&xfer->completed); | |
816 | ||
817 | spin_lock_irqsave(&dsi->transfer_lock, flags); | |
818 | ||
819 | list_del_init(&xfer->list); | |
820 | start = !list_empty(&dsi->transfer_list); | |
821 | ||
822 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); | |
823 | ||
824 | if (start) | |
825 | goto again; | |
826 | } | |
827 | ||
828 | static bool exynos_dsi_transfer_finish(struct exynos_dsi *dsi) | |
829 | { | |
830 | struct exynos_dsi_transfer *xfer; | |
831 | unsigned long flags; | |
832 | bool start = true; | |
833 | ||
834 | spin_lock_irqsave(&dsi->transfer_lock, flags); | |
835 | ||
836 | if (list_empty(&dsi->transfer_list)) { | |
837 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); | |
838 | return false; | |
839 | } | |
840 | ||
841 | xfer = list_first_entry(&dsi->transfer_list, | |
842 | struct exynos_dsi_transfer, list); | |
843 | ||
844 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); | |
845 | ||
846 | dev_dbg(dsi->dev, | |
847 | "> xfer %p, tx_len %u, tx_done %u, rx_len %u, rx_done %u\n", | |
848 | xfer, xfer->tx_len, xfer->tx_done, xfer->rx_len, xfer->rx_done); | |
849 | ||
850 | if (xfer->tx_done != xfer->tx_len) | |
851 | return true; | |
852 | ||
853 | if (xfer->rx_done != xfer->rx_len) | |
854 | exynos_dsi_read_from_fifo(dsi, xfer); | |
855 | ||
856 | if (xfer->rx_done != xfer->rx_len) | |
857 | return true; | |
858 | ||
859 | spin_lock_irqsave(&dsi->transfer_lock, flags); | |
860 | ||
861 | list_del_init(&xfer->list); | |
862 | start = !list_empty(&dsi->transfer_list); | |
863 | ||
864 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); | |
865 | ||
866 | if (!xfer->rx_len) | |
867 | xfer->result = 0; | |
868 | complete(&xfer->completed); | |
869 | ||
870 | return start; | |
871 | } | |
872 | ||
873 | static void exynos_dsi_remove_transfer(struct exynos_dsi *dsi, | |
874 | struct exynos_dsi_transfer *xfer) | |
875 | { | |
876 | unsigned long flags; | |
877 | bool start; | |
878 | ||
879 | spin_lock_irqsave(&dsi->transfer_lock, flags); | |
880 | ||
881 | if (!list_empty(&dsi->transfer_list) && | |
882 | xfer == list_first_entry(&dsi->transfer_list, | |
883 | struct exynos_dsi_transfer, list)) { | |
884 | list_del_init(&xfer->list); | |
885 | start = !list_empty(&dsi->transfer_list); | |
886 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); | |
887 | if (start) | |
888 | exynos_dsi_transfer_start(dsi); | |
889 | return; | |
890 | } | |
891 | ||
892 | list_del_init(&xfer->list); | |
893 | ||
894 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); | |
895 | } | |
896 | ||
897 | static int exynos_dsi_transfer(struct exynos_dsi *dsi, | |
898 | struct exynos_dsi_transfer *xfer) | |
899 | { | |
900 | unsigned long flags; | |
901 | bool stopped; | |
902 | ||
903 | xfer->tx_done = 0; | |
904 | xfer->rx_done = 0; | |
905 | xfer->result = -ETIMEDOUT; | |
906 | init_completion(&xfer->completed); | |
907 | ||
908 | spin_lock_irqsave(&dsi->transfer_lock, flags); | |
909 | ||
910 | stopped = list_empty(&dsi->transfer_list); | |
911 | list_add_tail(&xfer->list, &dsi->transfer_list); | |
912 | ||
913 | spin_unlock_irqrestore(&dsi->transfer_lock, flags); | |
914 | ||
915 | if (stopped) | |
916 | exynos_dsi_transfer_start(dsi); | |
917 | ||
918 | wait_for_completion_timeout(&xfer->completed, | |
919 | msecs_to_jiffies(DSI_XFER_TIMEOUT_MS)); | |
920 | if (xfer->result == -ETIMEDOUT) { | |
921 | exynos_dsi_remove_transfer(dsi, xfer); | |
922 | dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 2, xfer->data, | |
923 | xfer->tx_len, xfer->tx_payload); | |
924 | return -ETIMEDOUT; | |
925 | } | |
926 | ||
927 | /* Also covers hardware timeout condition */ | |
928 | return xfer->result; | |
929 | } | |
930 | ||
931 | static irqreturn_t exynos_dsi_irq(int irq, void *dev_id) | |
932 | { | |
933 | struct exynos_dsi *dsi = dev_id; | |
934 | u32 status; | |
935 | ||
936 | status = readl(dsi->reg_base + DSIM_INTSRC_REG); | |
937 | if (!status) { | |
938 | static unsigned long int j; | |
939 | if (printk_timed_ratelimit(&j, 500)) | |
940 | dev_warn(dsi->dev, "spurious interrupt\n"); | |
941 | return IRQ_HANDLED; | |
942 | } | |
943 | writel(status, dsi->reg_base + DSIM_INTSRC_REG); | |
944 | ||
945 | if (status & DSIM_INT_SW_RST_RELEASE) { | |
946 | u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY); | |
947 | writel(mask, dsi->reg_base + DSIM_INTMSK_REG); | |
948 | complete(&dsi->completed); | |
949 | return IRQ_HANDLED; | |
950 | } | |
951 | ||
952 | if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY))) | |
953 | return IRQ_HANDLED; | |
954 | ||
955 | if (exynos_dsi_transfer_finish(dsi)) | |
956 | exynos_dsi_transfer_start(dsi); | |
957 | ||
958 | return IRQ_HANDLED; | |
959 | } | |
960 | ||
e17ddecc YC |
961 | static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id) |
962 | { | |
963 | struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id; | |
964 | struct drm_encoder *encoder = dsi->encoder; | |
965 | ||
966 | if (dsi->state & DSIM_STATE_ENABLED) | |
967 | exynos_drm_crtc_te_handler(encoder->crtc); | |
968 | ||
969 | return IRQ_HANDLED; | |
970 | } | |
971 | ||
972 | static void exynos_dsi_enable_irq(struct exynos_dsi *dsi) | |
973 | { | |
974 | enable_irq(dsi->irq); | |
975 | ||
976 | if (gpio_is_valid(dsi->te_gpio)) | |
977 | enable_irq(gpio_to_irq(dsi->te_gpio)); | |
978 | } | |
979 | ||
980 | static void exynos_dsi_disable_irq(struct exynos_dsi *dsi) | |
981 | { | |
982 | if (gpio_is_valid(dsi->te_gpio)) | |
983 | disable_irq(gpio_to_irq(dsi->te_gpio)); | |
984 | ||
985 | disable_irq(dsi->irq); | |
986 | } | |
987 | ||
7eb8f069 AH |
988 | static int exynos_dsi_init(struct exynos_dsi *dsi) |
989 | { | |
990 | exynos_dsi_enable_clock(dsi); | |
991 | exynos_dsi_reset(dsi); | |
e17ddecc | 992 | exynos_dsi_enable_irq(dsi); |
7eb8f069 AH |
993 | exynos_dsi_wait_for_reset(dsi); |
994 | exynos_dsi_init_link(dsi); | |
995 | ||
996 | return 0; | |
997 | } | |
998 | ||
e17ddecc YC |
999 | static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi) |
1000 | { | |
1001 | int ret; | |
1002 | ||
1003 | dsi->te_gpio = of_get_named_gpio(dsi->panel_node, "te-gpios", 0); | |
1004 | if (!gpio_is_valid(dsi->te_gpio)) { | |
1005 | dev_err(dsi->dev, "no te-gpios specified\n"); | |
1006 | ret = dsi->te_gpio; | |
1007 | goto out; | |
1008 | } | |
1009 | ||
1010 | ret = gpio_request_one(dsi->te_gpio, GPIOF_IN, "te_gpio"); | |
1011 | if (ret) { | |
1012 | dev_err(dsi->dev, "gpio request failed with %d\n", ret); | |
1013 | goto out; | |
1014 | } | |
1015 | ||
1016 | /* | |
1017 | * This TE GPIO IRQ should not be set to IRQ_NOAUTOEN, because panel | |
1018 | * calls drm_panel_init() first then calls mipi_dsi_attach() in probe(). | |
1019 | * It means that te_gpio is invalid when exynos_dsi_enable_irq() is | |
1020 | * called by drm_panel_init() before panel is attached. | |
1021 | */ | |
1022 | ret = request_threaded_irq(gpio_to_irq(dsi->te_gpio), | |
1023 | exynos_dsi_te_irq_handler, NULL, | |
1024 | IRQF_TRIGGER_RISING, "TE", dsi); | |
1025 | if (ret) { | |
1026 | dev_err(dsi->dev, "request interrupt failed with %d\n", ret); | |
1027 | gpio_free(dsi->te_gpio); | |
1028 | goto out; | |
1029 | } | |
1030 | ||
1031 | out: | |
1032 | return ret; | |
1033 | } | |
1034 | ||
1035 | static void exynos_dsi_unregister_te_irq(struct exynos_dsi *dsi) | |
1036 | { | |
1037 | if (gpio_is_valid(dsi->te_gpio)) { | |
1038 | free_irq(gpio_to_irq(dsi->te_gpio), dsi); | |
1039 | gpio_free(dsi->te_gpio); | |
1040 | dsi->te_gpio = -ENOENT; | |
1041 | } | |
1042 | } | |
1043 | ||
7eb8f069 AH |
1044 | static int exynos_dsi_host_attach(struct mipi_dsi_host *host, |
1045 | struct mipi_dsi_device *device) | |
1046 | { | |
1047 | struct exynos_dsi *dsi = host_to_dsi(host); | |
1048 | ||
1049 | dsi->lanes = device->lanes; | |
1050 | dsi->format = device->format; | |
1051 | dsi->mode_flags = device->mode_flags; | |
1052 | dsi->panel_node = device->dev.of_node; | |
1053 | ||
1054 | if (dsi->connector.dev) | |
1055 | drm_helper_hpd_irq_event(dsi->connector.dev); | |
1056 | ||
e17ddecc YC |
1057 | /* |
1058 | * This is a temporary solution and should be made by more generic way. | |
1059 | * | |
1060 | * If attached panel device is for command mode one, dsi should register | |
1061 | * TE interrupt handler. | |
1062 | */ | |
1063 | if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) { | |
1064 | int ret = exynos_dsi_register_te_irq(dsi); | |
1065 | ||
1066 | if (ret) | |
1067 | return ret; | |
1068 | } | |
1069 | ||
7eb8f069 AH |
1070 | return 0; |
1071 | } | |
1072 | ||
1073 | static int exynos_dsi_host_detach(struct mipi_dsi_host *host, | |
1074 | struct mipi_dsi_device *device) | |
1075 | { | |
1076 | struct exynos_dsi *dsi = host_to_dsi(host); | |
1077 | ||
e17ddecc YC |
1078 | exynos_dsi_unregister_te_irq(dsi); |
1079 | ||
7eb8f069 AH |
1080 | dsi->panel_node = NULL; |
1081 | ||
1082 | if (dsi->connector.dev) | |
1083 | drm_helper_hpd_irq_event(dsi->connector.dev); | |
1084 | ||
1085 | return 0; | |
1086 | } | |
1087 | ||
1088 | /* distinguish between short and long DSI packet types */ | |
1089 | static bool exynos_dsi_is_short_dsi_type(u8 type) | |
1090 | { | |
1091 | return (type & 0x0f) <= 8; | |
1092 | } | |
1093 | ||
1094 | static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host, | |
1095 | struct mipi_dsi_msg *msg) | |
1096 | { | |
1097 | struct exynos_dsi *dsi = host_to_dsi(host); | |
1098 | struct exynos_dsi_transfer xfer; | |
1099 | int ret; | |
1100 | ||
1101 | if (!(dsi->state & DSIM_STATE_INITIALIZED)) { | |
1102 | ret = exynos_dsi_init(dsi); | |
1103 | if (ret) | |
1104 | return ret; | |
1105 | dsi->state |= DSIM_STATE_INITIALIZED; | |
1106 | } | |
1107 | ||
1108 | if (msg->tx_len == 0) | |
1109 | return -EINVAL; | |
1110 | ||
1111 | xfer.data_id = msg->type | (msg->channel << 6); | |
1112 | ||
1113 | if (exynos_dsi_is_short_dsi_type(msg->type)) { | |
1114 | const char *tx_buf = msg->tx_buf; | |
1115 | ||
1116 | if (msg->tx_len > 2) | |
1117 | return -EINVAL; | |
1118 | xfer.tx_len = 0; | |
1119 | xfer.data[0] = tx_buf[0]; | |
1120 | xfer.data[1] = (msg->tx_len == 2) ? tx_buf[1] : 0; | |
1121 | } else { | |
1122 | xfer.tx_len = msg->tx_len; | |
1123 | xfer.data[0] = msg->tx_len & 0xff; | |
1124 | xfer.data[1] = msg->tx_len >> 8; | |
1125 | xfer.tx_payload = msg->tx_buf; | |
1126 | } | |
1127 | ||
1128 | xfer.rx_len = msg->rx_len; | |
1129 | xfer.rx_payload = msg->rx_buf; | |
1130 | xfer.flags = msg->flags; | |
1131 | ||
1132 | ret = exynos_dsi_transfer(dsi, &xfer); | |
1133 | return (ret < 0) ? ret : xfer.rx_done; | |
1134 | } | |
1135 | ||
1136 | static const struct mipi_dsi_host_ops exynos_dsi_ops = { | |
1137 | .attach = exynos_dsi_host_attach, | |
1138 | .detach = exynos_dsi_host_detach, | |
1139 | .transfer = exynos_dsi_host_transfer, | |
1140 | }; | |
1141 | ||
1142 | static int exynos_dsi_poweron(struct exynos_dsi *dsi) | |
1143 | { | |
1144 | int ret; | |
1145 | ||
1146 | ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies); | |
1147 | if (ret < 0) { | |
1148 | dev_err(dsi->dev, "cannot enable regulators %d\n", ret); | |
1149 | return ret; | |
1150 | } | |
1151 | ||
1152 | ret = clk_prepare_enable(dsi->bus_clk); | |
1153 | if (ret < 0) { | |
1154 | dev_err(dsi->dev, "cannot enable bus clock %d\n", ret); | |
1155 | goto err_bus_clk; | |
1156 | } | |
1157 | ||
1158 | ret = clk_prepare_enable(dsi->pll_clk); | |
1159 | if (ret < 0) { | |
1160 | dev_err(dsi->dev, "cannot enable pll clock %d\n", ret); | |
1161 | goto err_pll_clk; | |
1162 | } | |
1163 | ||
1164 | ret = phy_power_on(dsi->phy); | |
1165 | if (ret < 0) { | |
1166 | dev_err(dsi->dev, "cannot enable phy %d\n", ret); | |
1167 | goto err_phy; | |
1168 | } | |
1169 | ||
1170 | return 0; | |
1171 | ||
1172 | err_phy: | |
1173 | clk_disable_unprepare(dsi->pll_clk); | |
1174 | err_pll_clk: | |
1175 | clk_disable_unprepare(dsi->bus_clk); | |
1176 | err_bus_clk: | |
1177 | regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); | |
1178 | ||
1179 | return ret; | |
1180 | } | |
1181 | ||
1182 | static void exynos_dsi_poweroff(struct exynos_dsi *dsi) | |
1183 | { | |
1184 | int ret; | |
1185 | ||
1186 | usleep_range(10000, 20000); | |
1187 | ||
1188 | if (dsi->state & DSIM_STATE_INITIALIZED) { | |
1189 | dsi->state &= ~DSIM_STATE_INITIALIZED; | |
1190 | ||
1191 | exynos_dsi_disable_clock(dsi); | |
1192 | ||
e17ddecc | 1193 | exynos_dsi_disable_irq(dsi); |
7eb8f069 AH |
1194 | } |
1195 | ||
1196 | dsi->state &= ~DSIM_STATE_CMD_LPM; | |
1197 | ||
1198 | phy_power_off(dsi->phy); | |
1199 | ||
1200 | clk_disable_unprepare(dsi->pll_clk); | |
1201 | clk_disable_unprepare(dsi->bus_clk); | |
1202 | ||
1203 | ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); | |
1204 | if (ret < 0) | |
1205 | dev_err(dsi->dev, "cannot disable regulators %d\n", ret); | |
1206 | } | |
1207 | ||
1208 | static int exynos_dsi_enable(struct exynos_dsi *dsi) | |
1209 | { | |
1210 | int ret; | |
1211 | ||
1212 | if (dsi->state & DSIM_STATE_ENABLED) | |
1213 | return 0; | |
1214 | ||
1215 | ret = exynos_dsi_poweron(dsi); | |
1216 | if (ret < 0) | |
1217 | return ret; | |
1218 | ||
1219 | ret = drm_panel_enable(dsi->panel); | |
1220 | if (ret < 0) { | |
1221 | exynos_dsi_poweroff(dsi); | |
1222 | return ret; | |
1223 | } | |
1224 | ||
1225 | exynos_dsi_set_display_mode(dsi); | |
1226 | exynos_dsi_set_display_enable(dsi, true); | |
1227 | ||
1228 | dsi->state |= DSIM_STATE_ENABLED; | |
1229 | ||
1230 | return 0; | |
1231 | } | |
1232 | ||
1233 | static void exynos_dsi_disable(struct exynos_dsi *dsi) | |
1234 | { | |
1235 | if (!(dsi->state & DSIM_STATE_ENABLED)) | |
1236 | return; | |
1237 | ||
1238 | exynos_dsi_set_display_enable(dsi, false); | |
1239 | drm_panel_disable(dsi->panel); | |
1240 | exynos_dsi_poweroff(dsi); | |
1241 | ||
1242 | dsi->state &= ~DSIM_STATE_ENABLED; | |
1243 | } | |
1244 | ||
1245 | static void exynos_dsi_dpms(struct exynos_drm_display *display, int mode) | |
1246 | { | |
1247 | struct exynos_dsi *dsi = display->ctx; | |
1248 | ||
1249 | if (dsi->panel) { | |
1250 | switch (mode) { | |
1251 | case DRM_MODE_DPMS_ON: | |
1252 | exynos_dsi_enable(dsi); | |
1253 | break; | |
1254 | case DRM_MODE_DPMS_STANDBY: | |
1255 | case DRM_MODE_DPMS_SUSPEND: | |
1256 | case DRM_MODE_DPMS_OFF: | |
1257 | exynos_dsi_disable(dsi); | |
1258 | break; | |
1259 | default: | |
1260 | break; | |
1261 | } | |
1262 | } | |
1263 | } | |
1264 | ||
1265 | static enum drm_connector_status | |
1266 | exynos_dsi_detect(struct drm_connector *connector, bool force) | |
1267 | { | |
1268 | struct exynos_dsi *dsi = connector_to_dsi(connector); | |
1269 | ||
1270 | if (!dsi->panel) { | |
1271 | dsi->panel = of_drm_find_panel(dsi->panel_node); | |
1272 | if (dsi->panel) | |
1273 | drm_panel_attach(dsi->panel, &dsi->connector); | |
1274 | } else if (!dsi->panel_node) { | |
1275 | struct exynos_drm_display *display; | |
1276 | ||
1277 | display = platform_get_drvdata(to_platform_device(dsi->dev)); | |
1278 | exynos_dsi_dpms(display, DRM_MODE_DPMS_OFF); | |
1279 | drm_panel_detach(dsi->panel); | |
1280 | dsi->panel = NULL; | |
1281 | } | |
1282 | ||
1283 | if (dsi->panel) | |
1284 | return connector_status_connected; | |
1285 | ||
1286 | return connector_status_disconnected; | |
1287 | } | |
1288 | ||
1289 | static void exynos_dsi_connector_destroy(struct drm_connector *connector) | |
1290 | { | |
1291 | } | |
1292 | ||
1293 | static struct drm_connector_funcs exynos_dsi_connector_funcs = { | |
1294 | .dpms = drm_helper_connector_dpms, | |
1295 | .detect = exynos_dsi_detect, | |
1296 | .fill_modes = drm_helper_probe_single_connector_modes, | |
1297 | .destroy = exynos_dsi_connector_destroy, | |
1298 | }; | |
1299 | ||
1300 | static int exynos_dsi_get_modes(struct drm_connector *connector) | |
1301 | { | |
1302 | struct exynos_dsi *dsi = connector_to_dsi(connector); | |
1303 | ||
1304 | if (dsi->panel) | |
1305 | return dsi->panel->funcs->get_modes(dsi->panel); | |
1306 | ||
1307 | return 0; | |
1308 | } | |
1309 | ||
1310 | static int exynos_dsi_mode_valid(struct drm_connector *connector, | |
1311 | struct drm_display_mode *mode) | |
1312 | { | |
1313 | return MODE_OK; | |
1314 | } | |
1315 | ||
1316 | static struct drm_encoder * | |
1317 | exynos_dsi_best_encoder(struct drm_connector *connector) | |
1318 | { | |
1319 | struct exynos_dsi *dsi = connector_to_dsi(connector); | |
1320 | ||
1321 | return dsi->encoder; | |
1322 | } | |
1323 | ||
1324 | static struct drm_connector_helper_funcs exynos_dsi_connector_helper_funcs = { | |
1325 | .get_modes = exynos_dsi_get_modes, | |
1326 | .mode_valid = exynos_dsi_mode_valid, | |
1327 | .best_encoder = exynos_dsi_best_encoder, | |
1328 | }; | |
1329 | ||
1330 | static int exynos_dsi_create_connector(struct exynos_drm_display *display, | |
1331 | struct drm_encoder *encoder) | |
1332 | { | |
1333 | struct exynos_dsi *dsi = display->ctx; | |
1334 | struct drm_connector *connector = &dsi->connector; | |
1335 | int ret; | |
1336 | ||
1337 | dsi->encoder = encoder; | |
1338 | ||
1339 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
1340 | ||
1341 | ret = drm_connector_init(encoder->dev, connector, | |
1342 | &exynos_dsi_connector_funcs, | |
1343 | DRM_MODE_CONNECTOR_DSI); | |
1344 | if (ret) { | |
1345 | DRM_ERROR("Failed to initialize connector with drm\n"); | |
1346 | return ret; | |
1347 | } | |
1348 | ||
1349 | drm_connector_helper_add(connector, &exynos_dsi_connector_helper_funcs); | |
34ea3d38 | 1350 | drm_connector_register(connector); |
7eb8f069 AH |
1351 | drm_mode_connector_attach_encoder(connector, encoder); |
1352 | ||
1353 | return 0; | |
1354 | } | |
1355 | ||
1356 | static void exynos_dsi_mode_set(struct exynos_drm_display *display, | |
1357 | struct drm_display_mode *mode) | |
1358 | { | |
1359 | struct exynos_dsi *dsi = display->ctx; | |
1360 | struct videomode *vm = &dsi->vm; | |
1361 | ||
1362 | vm->hactive = mode->hdisplay; | |
1363 | vm->vactive = mode->vdisplay; | |
1364 | vm->vfront_porch = mode->vsync_start - mode->vdisplay; | |
1365 | vm->vback_porch = mode->vtotal - mode->vsync_end; | |
1366 | vm->vsync_len = mode->vsync_end - mode->vsync_start; | |
1367 | vm->hfront_porch = mode->hsync_start - mode->hdisplay; | |
1368 | vm->hback_porch = mode->htotal - mode->hsync_end; | |
1369 | vm->hsync_len = mode->hsync_end - mode->hsync_start; | |
1370 | } | |
1371 | ||
1372 | static struct exynos_drm_display_ops exynos_dsi_display_ops = { | |
1373 | .create_connector = exynos_dsi_create_connector, | |
1374 | .mode_set = exynos_dsi_mode_set, | |
1375 | .dpms = exynos_dsi_dpms | |
1376 | }; | |
1377 | ||
1378 | static struct exynos_drm_display exynos_dsi_display = { | |
1379 | .type = EXYNOS_DISPLAY_TYPE_LCD, | |
1380 | .ops = &exynos_dsi_display_ops, | |
1381 | }; | |
1382 | ||
1383 | /* of_* functions will be removed after merge of of_graph patches */ | |
1384 | static struct device_node * | |
1385 | of_get_child_by_name_reg(struct device_node *parent, const char *name, u32 reg) | |
1386 | { | |
1387 | struct device_node *np; | |
1388 | ||
1389 | for_each_child_of_node(parent, np) { | |
1390 | u32 r; | |
1391 | ||
1392 | if (!np->name || of_node_cmp(np->name, name)) | |
1393 | continue; | |
1394 | ||
1395 | if (of_property_read_u32(np, "reg", &r) < 0) | |
1396 | r = 0; | |
1397 | ||
1398 | if (reg == r) | |
1399 | break; | |
1400 | } | |
1401 | ||
1402 | return np; | |
1403 | } | |
1404 | ||
1405 | static struct device_node *of_graph_get_port_by_reg(struct device_node *parent, | |
1406 | u32 reg) | |
1407 | { | |
1408 | struct device_node *ports, *port; | |
1409 | ||
1410 | ports = of_get_child_by_name(parent, "ports"); | |
1411 | if (ports) | |
1412 | parent = ports; | |
1413 | ||
1414 | port = of_get_child_by_name_reg(parent, "port", reg); | |
1415 | ||
1416 | of_node_put(ports); | |
1417 | ||
1418 | return port; | |
1419 | } | |
1420 | ||
1421 | static struct device_node * | |
1422 | of_graph_get_endpoint_by_reg(struct device_node *port, u32 reg) | |
1423 | { | |
1424 | return of_get_child_by_name_reg(port, "endpoint", reg); | |
1425 | } | |
1426 | ||
1427 | static int exynos_dsi_of_read_u32(const struct device_node *np, | |
1428 | const char *propname, u32 *out_value) | |
1429 | { | |
1430 | int ret = of_property_read_u32(np, propname, out_value); | |
1431 | ||
1432 | if (ret < 0) | |
1433 | pr_err("%s: failed to get '%s' property\n", np->full_name, | |
1434 | propname); | |
1435 | ||
1436 | return ret; | |
1437 | } | |
1438 | ||
1439 | enum { | |
1440 | DSI_PORT_IN, | |
1441 | DSI_PORT_OUT | |
1442 | }; | |
1443 | ||
1444 | static int exynos_dsi_parse_dt(struct exynos_dsi *dsi) | |
1445 | { | |
1446 | struct device *dev = dsi->dev; | |
1447 | struct device_node *node = dev->of_node; | |
1448 | struct device_node *port, *ep; | |
1449 | int ret; | |
1450 | ||
1451 | ret = exynos_dsi_of_read_u32(node, "samsung,pll-clock-frequency", | |
1452 | &dsi->pll_clk_rate); | |
1453 | if (ret < 0) | |
1454 | return ret; | |
1455 | ||
1456 | port = of_graph_get_port_by_reg(node, DSI_PORT_OUT); | |
1457 | if (!port) { | |
1458 | dev_err(dev, "no output port specified\n"); | |
1459 | return -EINVAL; | |
1460 | } | |
1461 | ||
1462 | ep = of_graph_get_endpoint_by_reg(port, 0); | |
1463 | of_node_put(port); | |
1464 | if (!ep) { | |
1465 | dev_err(dev, "no endpoint specified in output port\n"); | |
1466 | return -EINVAL; | |
1467 | } | |
1468 | ||
1469 | ret = exynos_dsi_of_read_u32(ep, "samsung,burst-clock-frequency", | |
1470 | &dsi->burst_clk_rate); | |
1471 | if (ret < 0) | |
1472 | goto end; | |
1473 | ||
1474 | ret = exynos_dsi_of_read_u32(ep, "samsung,esc-clock-frequency", | |
1475 | &dsi->esc_clk_rate); | |
1476 | ||
1477 | end: | |
1478 | of_node_put(ep); | |
1479 | ||
1480 | return ret; | |
1481 | } | |
1482 | ||
f37cd5e8 ID |
1483 | static int exynos_dsi_bind(struct device *dev, struct device *master, |
1484 | void *data) | |
1485 | { | |
1486 | struct drm_device *drm_dev = data; | |
1487 | struct exynos_dsi *dsi; | |
1488 | int ret; | |
1489 | ||
1490 | ret = exynos_drm_create_enc_conn(drm_dev, &exynos_dsi_display); | |
1491 | if (ret) { | |
1492 | DRM_ERROR("Encoder create [%d] failed with %d\n", | |
1493 | exynos_dsi_display.type, ret); | |
1494 | return ret; | |
1495 | } | |
1496 | ||
1497 | dsi = exynos_dsi_display.ctx; | |
1498 | ||
1499 | return mipi_dsi_host_register(&dsi->dsi_host); | |
1500 | } | |
1501 | ||
1502 | static void exynos_dsi_unbind(struct device *dev, struct device *master, | |
1503 | void *data) | |
1504 | { | |
1505 | struct exynos_dsi *dsi = exynos_dsi_display.ctx; | |
1506 | struct drm_encoder *encoder = dsi->encoder; | |
1507 | ||
1508 | exynos_dsi_dpms(&exynos_dsi_display, DRM_MODE_DPMS_OFF); | |
1509 | ||
1510 | mipi_dsi_host_unregister(&dsi->dsi_host); | |
1511 | ||
1512 | encoder->funcs->destroy(encoder); | |
1513 | drm_connector_cleanup(&dsi->connector); | |
1514 | } | |
1515 | ||
f37cd5e8 ID |
1516 | static const struct component_ops exynos_dsi_component_ops = { |
1517 | .bind = exynos_dsi_bind, | |
1518 | .unbind = exynos_dsi_unbind, | |
1519 | }; | |
1520 | ||
7eb8f069 AH |
1521 | static int exynos_dsi_probe(struct platform_device *pdev) |
1522 | { | |
1523 | struct resource *res; | |
1524 | struct exynos_dsi *dsi; | |
1525 | int ret; | |
1526 | ||
df5225bc ID |
1527 | ret = exynos_drm_component_add(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR, |
1528 | exynos_dsi_display.type); | |
1529 | if (ret) | |
1530 | return ret; | |
1531 | ||
7eb8f069 AH |
1532 | dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL); |
1533 | if (!dsi) { | |
1534 | dev_err(&pdev->dev, "failed to allocate dsi object.\n"); | |
df5225bc ID |
1535 | ret = -ENOMEM; |
1536 | goto err_del_component; | |
7eb8f069 AH |
1537 | } |
1538 | ||
e17ddecc YC |
1539 | /* To be checked as invalid one */ |
1540 | dsi->te_gpio = -ENOENT; | |
1541 | ||
7eb8f069 AH |
1542 | init_completion(&dsi->completed); |
1543 | spin_lock_init(&dsi->transfer_lock); | |
1544 | INIT_LIST_HEAD(&dsi->transfer_list); | |
1545 | ||
1546 | dsi->dsi_host.ops = &exynos_dsi_ops; | |
1547 | dsi->dsi_host.dev = &pdev->dev; | |
1548 | ||
1549 | dsi->dev = &pdev->dev; | |
1550 | ||
1551 | ret = exynos_dsi_parse_dt(dsi); | |
1552 | if (ret) | |
df5225bc | 1553 | goto err_del_component; |
7eb8f069 AH |
1554 | |
1555 | dsi->supplies[0].supply = "vddcore"; | |
1556 | dsi->supplies[1].supply = "vddio"; | |
1557 | ret = devm_regulator_bulk_get(&pdev->dev, ARRAY_SIZE(dsi->supplies), | |
1558 | dsi->supplies); | |
1559 | if (ret) { | |
1560 | dev_info(&pdev->dev, "failed to get regulators: %d\n", ret); | |
1561 | return -EPROBE_DEFER; | |
1562 | } | |
1563 | ||
1564 | dsi->pll_clk = devm_clk_get(&pdev->dev, "pll_clk"); | |
1565 | if (IS_ERR(dsi->pll_clk)) { | |
1566 | dev_info(&pdev->dev, "failed to get dsi pll input clock\n"); | |
df5225bc ID |
1567 | ret = PTR_ERR(dsi->pll_clk); |
1568 | goto err_del_component; | |
7eb8f069 AH |
1569 | } |
1570 | ||
1571 | dsi->bus_clk = devm_clk_get(&pdev->dev, "bus_clk"); | |
1572 | if (IS_ERR(dsi->bus_clk)) { | |
1573 | dev_info(&pdev->dev, "failed to get dsi bus clock\n"); | |
df5225bc ID |
1574 | ret = PTR_ERR(dsi->bus_clk); |
1575 | goto err_del_component; | |
7eb8f069 AH |
1576 | } |
1577 | ||
1578 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1579 | dsi->reg_base = devm_ioremap_resource(&pdev->dev, res); | |
293d3f6a | 1580 | if (IS_ERR(dsi->reg_base)) { |
7eb8f069 | 1581 | dev_err(&pdev->dev, "failed to remap io region\n"); |
df5225bc ID |
1582 | ret = PTR_ERR(dsi->reg_base); |
1583 | goto err_del_component; | |
7eb8f069 AH |
1584 | } |
1585 | ||
1586 | dsi->phy = devm_phy_get(&pdev->dev, "dsim"); | |
1587 | if (IS_ERR(dsi->phy)) { | |
1588 | dev_info(&pdev->dev, "failed to get dsim phy\n"); | |
df5225bc ID |
1589 | ret = PTR_ERR(dsi->phy); |
1590 | goto err_del_component; | |
7eb8f069 AH |
1591 | } |
1592 | ||
1593 | dsi->irq = platform_get_irq(pdev, 0); | |
1594 | if (dsi->irq < 0) { | |
1595 | dev_err(&pdev->dev, "failed to request dsi irq resource\n"); | |
df5225bc ID |
1596 | ret = dsi->irq; |
1597 | goto err_del_component; | |
7eb8f069 AH |
1598 | } |
1599 | ||
1600 | irq_set_status_flags(dsi->irq, IRQ_NOAUTOEN); | |
1601 | ret = devm_request_threaded_irq(&pdev->dev, dsi->irq, NULL, | |
1602 | exynos_dsi_irq, IRQF_ONESHOT, | |
1603 | dev_name(&pdev->dev), dsi); | |
1604 | if (ret) { | |
1605 | dev_err(&pdev->dev, "failed to request dsi irq\n"); | |
df5225bc | 1606 | goto err_del_component; |
7eb8f069 AH |
1607 | } |
1608 | ||
1609 | exynos_dsi_display.ctx = dsi; | |
1610 | ||
1611 | platform_set_drvdata(pdev, &exynos_dsi_display); | |
7eb8f069 | 1612 | |
df5225bc ID |
1613 | ret = component_add(&pdev->dev, &exynos_dsi_component_ops); |
1614 | if (ret) | |
1615 | goto err_del_component; | |
1616 | ||
1617 | return ret; | |
1618 | ||
1619 | err_del_component: | |
1620 | exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR); | |
1621 | return ret; | |
7eb8f069 AH |
1622 | } |
1623 | ||
1624 | static int exynos_dsi_remove(struct platform_device *pdev) | |
1625 | { | |
df5225bc ID |
1626 | component_del(&pdev->dev, &exynos_dsi_component_ops); |
1627 | exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR); | |
1628 | ||
7eb8f069 AH |
1629 | return 0; |
1630 | } | |
1631 | ||
7eb8f069 AH |
1632 | static struct of_device_id exynos_dsi_of_match[] = { |
1633 | { .compatible = "samsung,exynos4210-mipi-dsi" }, | |
1634 | { } | |
1635 | }; | |
1636 | ||
7eb8f069 AH |
1637 | struct platform_driver dsi_driver = { |
1638 | .probe = exynos_dsi_probe, | |
1639 | .remove = exynos_dsi_remove, | |
1640 | .driver = { | |
1641 | .name = "exynos-dsi", | |
1642 | .owner = THIS_MODULE, | |
7eb8f069 AH |
1643 | .of_match_table = exynos_dsi_of_match, |
1644 | }, | |
1645 | }; | |
1646 | ||
1647 | MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>"); | |
1648 | MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>"); | |
1649 | MODULE_DESCRIPTION("Samsung SoC MIPI DSI Master"); | |
1650 | MODULE_LICENSE("GPL v2"); |