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16102edb EK |
1 | /* |
2 | * Copyright (C) 2012 Samsung Electronics Co.Ltd | |
3 | * Authors: | |
4 | * Eunchul Kim <chulspro.kim@samsung.com> | |
5 | * Jinyoung Jeon <jy0.jeon@samsung.com> | |
6 | * Sangmin Lee <lsmin.lee@samsung.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | */ | |
14 | #include <linux/kernel.h> | |
7a2d5c77 | 15 | #include <linux/component.h> |
16102edb | 16 | #include <linux/platform_device.h> |
a3ad6976 | 17 | #include <linux/mfd/syscon.h> |
5186fc5e | 18 | #include <linux/regmap.h> |
16102edb EK |
19 | #include <linux/clk.h> |
20 | #include <linux/pm_runtime.h> | |
3f1c781d | 21 | #include <linux/of.h> |
72d465aa | 22 | #include <linux/spinlock.h> |
16102edb EK |
23 | |
24 | #include <drm/drmP.h> | |
25 | #include <drm/exynos_drm.h> | |
26 | #include "regs-fimc.h" | |
e30655d0 | 27 | #include "exynos_drm_drv.h" |
7a2d5c77 | 28 | #include "exynos_drm_iommu.h" |
16102edb | 29 | #include "exynos_drm_ipp.h" |
16102edb EK |
30 | |
31 | /* | |
6fe891f6 | 32 | * FIMC stands for Fully Interactive Mobile Camera and |
16102edb EK |
33 | * supports image scaler/rotator and input/output DMA operations. |
34 | * input DMA reads image data from the memory. | |
35 | * output DMA writes image data to memory. | |
36 | * FIMC supports image rotation and image effect functions. | |
16102edb EK |
37 | */ |
38 | ||
39 | #define FIMC_MAX_DEVS 4 | |
40 | #define FIMC_MAX_SRC 2 | |
41 | #define FIMC_MAX_DST 32 | |
42 | #define FIMC_SHFACTOR 10 | |
43 | #define FIMC_BUF_STOP 1 | |
44 | #define FIMC_BUF_START 2 | |
16102edb | 45 | #define FIMC_WIDTH_ITU_709 1280 |
7a2d5c77 MS |
46 | #define FIMC_AUTOSUSPEND_DELAY 2000 |
47 | ||
48 | static unsigned int fimc_mask = 0xc; | |
49 | module_param_named(fimc_devs, fimc_mask, uint, 0644); | |
50 | MODULE_PARM_DESC(fimc_devs, "Alias mask for assigning FIMC devices to Exynos DRM"); | |
16102edb EK |
51 | |
52 | #define get_fimc_context(dev) platform_get_drvdata(to_platform_device(dev)) | |
16102edb | 53 | |
e5f86839 SN |
54 | enum { |
55 | FIMC_CLK_LCLK, | |
56 | FIMC_CLK_GATE, | |
57 | FIMC_CLK_WB_A, | |
58 | FIMC_CLK_WB_B, | |
e5f86839 SN |
59 | FIMC_CLKS_MAX |
60 | }; | |
61 | ||
62 | static const char * const fimc_clock_names[] = { | |
63 | [FIMC_CLK_LCLK] = "sclk_fimc", | |
64 | [FIMC_CLK_GATE] = "fimc", | |
65 | [FIMC_CLK_WB_A] = "pxl_async0", | |
66 | [FIMC_CLK_WB_B] = "pxl_async1", | |
e5f86839 SN |
67 | }; |
68 | ||
16102edb EK |
69 | /* |
70 | * A structure of scaler. | |
71 | * | |
72 | * @range: narrow, wide. | |
73 | * @bypass: unused scaler path. | |
74 | * @up_h: horizontal scale up. | |
75 | * @up_v: vertical scale up. | |
76 | * @hratio: horizontal ratio. | |
77 | * @vratio: vertical ratio. | |
78 | */ | |
79 | struct fimc_scaler { | |
7a2d5c77 | 80 | bool range; |
16102edb EK |
81 | bool bypass; |
82 | bool up_h; | |
83 | bool up_v; | |
84 | u32 hratio; | |
85 | u32 vratio; | |
86 | }; | |
87 | ||
16102edb EK |
88 | /* |
89 | * A structure of fimc context. | |
90 | * | |
16102edb EK |
91 | * @regs_res: register resources. |
92 | * @regs: memory mapped io registers. | |
93 | * @lock: locking of operations. | |
e5f86839 | 94 | * @clocks: fimc clocks. |
16102edb | 95 | * @sc: scaler infomations. |
16102edb EK |
96 | * @pol: porarity of writeback. |
97 | * @id: fimc id. | |
98 | * @irq: irq number. | |
16102edb EK |
99 | */ |
100 | struct fimc_context { | |
7a2d5c77 MS |
101 | struct exynos_drm_ipp ipp; |
102 | struct drm_device *drm_dev; | |
103 | struct device *dev; | |
104 | struct exynos_drm_ipp_task *task; | |
105 | struct exynos_drm_ipp_formats *formats; | |
106 | unsigned int num_formats; | |
107 | ||
16102edb EK |
108 | struct resource *regs_res; |
109 | void __iomem *regs; | |
72d465aa | 110 | spinlock_t lock; |
e5f86839 | 111 | struct clk *clocks[FIMC_CLKS_MAX]; |
16102edb | 112 | struct fimc_scaler sc; |
16102edb EK |
113 | int id; |
114 | int irq; | |
16102edb EK |
115 | }; |
116 | ||
acd8afa8 AH |
117 | static u32 fimc_read(struct fimc_context *ctx, u32 reg) |
118 | { | |
119 | return readl(ctx->regs + reg); | |
120 | } | |
121 | ||
122 | static void fimc_write(struct fimc_context *ctx, u32 val, u32 reg) | |
123 | { | |
124 | writel(val, ctx->regs + reg); | |
125 | } | |
126 | ||
127 | static void fimc_set_bits(struct fimc_context *ctx, u32 reg, u32 bits) | |
128 | { | |
129 | void __iomem *r = ctx->regs + reg; | |
130 | ||
131 | writel(readl(r) | bits, r); | |
132 | } | |
133 | ||
134 | static void fimc_clear_bits(struct fimc_context *ctx, u32 reg, u32 bits) | |
135 | { | |
136 | void __iomem *r = ctx->regs + reg; | |
137 | ||
138 | writel(readl(r) & ~bits, r); | |
139 | } | |
140 | ||
b5c0b552 | 141 | static void fimc_sw_reset(struct fimc_context *ctx) |
16102edb EK |
142 | { |
143 | u32 cfg; | |
144 | ||
e39d5ce1 | 145 | /* stop dma operation */ |
acd8afa8 AH |
146 | cfg = fimc_read(ctx, EXYNOS_CISTATUS); |
147 | if (EXYNOS_CISTATUS_GET_ENVID_STATUS(cfg)) | |
148 | fimc_clear_bits(ctx, EXYNOS_MSCTRL, EXYNOS_MSCTRL_ENVID); | |
16102edb | 149 | |
acd8afa8 | 150 | fimc_set_bits(ctx, EXYNOS_CISRCFMT, EXYNOS_CISRCFMT_ITU601_8BIT); |
16102edb | 151 | |
e39d5ce1 | 152 | /* disable image capture */ |
acd8afa8 AH |
153 | fimc_clear_bits(ctx, EXYNOS_CIIMGCPT, |
154 | EXYNOS_CIIMGCPT_IMGCPTEN_SC | EXYNOS_CIIMGCPT_IMGCPTEN); | |
e39d5ce1 | 155 | |
16102edb | 156 | /* s/w reset */ |
acd8afa8 | 157 | fimc_set_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_SWRST); |
16102edb EK |
158 | |
159 | /* s/w reset complete */ | |
acd8afa8 | 160 | fimc_clear_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_SWRST); |
16102edb EK |
161 | |
162 | /* reset sequence */ | |
acd8afa8 | 163 | fimc_write(ctx, 0x0, EXYNOS_CIFCNTSEQ); |
16102edb EK |
164 | } |
165 | ||
7a2d5c77 | 166 | static void fimc_set_type_ctrl(struct fimc_context *ctx) |
16102edb EK |
167 | { |
168 | u32 cfg; | |
169 | ||
acd8afa8 | 170 | cfg = fimc_read(ctx, EXYNOS_CIGCTRL); |
16102edb EK |
171 | cfg &= ~(EXYNOS_CIGCTRL_TESTPATTERN_MASK | |
172 | EXYNOS_CIGCTRL_SELCAM_ITU_MASK | | |
173 | EXYNOS_CIGCTRL_SELCAM_MIPI_MASK | | |
174 | EXYNOS_CIGCTRL_SELCAM_FIMC_MASK | | |
175 | EXYNOS_CIGCTRL_SELWB_CAMIF_MASK | | |
176 | EXYNOS_CIGCTRL_SELWRITEBACK_MASK); | |
177 | ||
7a2d5c77 MS |
178 | cfg |= (EXYNOS_CIGCTRL_SELCAM_ITU_A | |
179 | EXYNOS_CIGCTRL_SELWRITEBACK_A | | |
180 | EXYNOS_CIGCTRL_SELCAM_MIPI_A | | |
181 | EXYNOS_CIGCTRL_SELCAM_FIMC_ITU); | |
16102edb | 182 | |
acd8afa8 | 183 | fimc_write(ctx, cfg, EXYNOS_CIGCTRL); |
16102edb EK |
184 | } |
185 | ||
16102edb EK |
186 | static void fimc_handle_jpeg(struct fimc_context *ctx, bool enable) |
187 | { | |
188 | u32 cfg; | |
189 | ||
cbc4c33d | 190 | DRM_DEBUG_KMS("enable[%d]\n", enable); |
16102edb | 191 | |
acd8afa8 | 192 | cfg = fimc_read(ctx, EXYNOS_CIGCTRL); |
16102edb EK |
193 | if (enable) |
194 | cfg |= EXYNOS_CIGCTRL_CAM_JPEG; | |
195 | else | |
196 | cfg &= ~EXYNOS_CIGCTRL_CAM_JPEG; | |
197 | ||
acd8afa8 | 198 | fimc_write(ctx, cfg, EXYNOS_CIGCTRL); |
16102edb EK |
199 | } |
200 | ||
8b4609cd | 201 | static void fimc_mask_irq(struct fimc_context *ctx, bool enable) |
16102edb EK |
202 | { |
203 | u32 cfg; | |
204 | ||
8b4609cd | 205 | DRM_DEBUG_KMS("enable[%d]\n", enable); |
16102edb | 206 | |
acd8afa8 | 207 | cfg = fimc_read(ctx, EXYNOS_CIGCTRL); |
16102edb | 208 | if (enable) { |
8b4609cd AH |
209 | cfg &= ~EXYNOS_CIGCTRL_IRQ_OVFEN; |
210 | cfg |= EXYNOS_CIGCTRL_IRQ_ENABLE | EXYNOS_CIGCTRL_IRQ_LEVEL; | |
16102edb | 211 | } else |
8b4609cd | 212 | cfg &= ~EXYNOS_CIGCTRL_IRQ_ENABLE; |
acd8afa8 | 213 | fimc_write(ctx, cfg, EXYNOS_CIGCTRL); |
16102edb EK |
214 | } |
215 | ||
216 | static void fimc_clear_irq(struct fimc_context *ctx) | |
217 | { | |
acd8afa8 | 218 | fimc_set_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_IRQ_CLR); |
16102edb EK |
219 | } |
220 | ||
221 | static bool fimc_check_ovf(struct fimc_context *ctx) | |
222 | { | |
acd8afa8 | 223 | u32 status, flag; |
16102edb | 224 | |
acd8afa8 | 225 | status = fimc_read(ctx, EXYNOS_CISTATUS); |
16102edb EK |
226 | flag = EXYNOS_CISTATUS_OVFIY | EXYNOS_CISTATUS_OVFICB | |
227 | EXYNOS_CISTATUS_OVFICR; | |
228 | ||
cbc4c33d | 229 | DRM_DEBUG_KMS("flag[0x%x]\n", flag); |
16102edb EK |
230 | |
231 | if (status & flag) { | |
acd8afa8 AH |
232 | fimc_set_bits(ctx, EXYNOS_CIWDOFST, |
233 | EXYNOS_CIWDOFST_CLROVFIY | EXYNOS_CIWDOFST_CLROVFICB | | |
16102edb | 234 | EXYNOS_CIWDOFST_CLROVFICR); |
16102edb | 235 | |
7a2d5c77 | 236 | dev_err(ctx->dev, "occurred overflow at %d, status 0x%x.\n", |
16102edb EK |
237 | ctx->id, status); |
238 | return true; | |
239 | } | |
240 | ||
241 | return false; | |
242 | } | |
243 | ||
244 | static bool fimc_check_frame_end(struct fimc_context *ctx) | |
245 | { | |
246 | u32 cfg; | |
247 | ||
acd8afa8 | 248 | cfg = fimc_read(ctx, EXYNOS_CISTATUS); |
16102edb | 249 | |
cbc4c33d | 250 | DRM_DEBUG_KMS("cfg[0x%x]\n", cfg); |
16102edb EK |
251 | |
252 | if (!(cfg & EXYNOS_CISTATUS_FRAMEEND)) | |
253 | return false; | |
254 | ||
255 | cfg &= ~(EXYNOS_CISTATUS_FRAMEEND); | |
acd8afa8 | 256 | fimc_write(ctx, cfg, EXYNOS_CISTATUS); |
16102edb EK |
257 | |
258 | return true; | |
259 | } | |
260 | ||
261 | static int fimc_get_buf_id(struct fimc_context *ctx) | |
262 | { | |
263 | u32 cfg; | |
264 | int frame_cnt, buf_id; | |
265 | ||
acd8afa8 | 266 | cfg = fimc_read(ctx, EXYNOS_CISTATUS2); |
16102edb EK |
267 | frame_cnt = EXYNOS_CISTATUS2_GET_FRAMECOUNT_BEFORE(cfg); |
268 | ||
269 | if (frame_cnt == 0) | |
270 | frame_cnt = EXYNOS_CISTATUS2_GET_FRAMECOUNT_PRESENT(cfg); | |
271 | ||
cbc4c33d | 272 | DRM_DEBUG_KMS("present[%d]before[%d]\n", |
16102edb EK |
273 | EXYNOS_CISTATUS2_GET_FRAMECOUNT_PRESENT(cfg), |
274 | EXYNOS_CISTATUS2_GET_FRAMECOUNT_BEFORE(cfg)); | |
275 | ||
276 | if (frame_cnt == 0) { | |
277 | DRM_ERROR("failed to get frame count.\n"); | |
278 | return -EIO; | |
279 | } | |
280 | ||
281 | buf_id = frame_cnt - 1; | |
cbc4c33d | 282 | DRM_DEBUG_KMS("buf_id[%d]\n", buf_id); |
16102edb EK |
283 | |
284 | return buf_id; | |
285 | } | |
286 | ||
287 | static void fimc_handle_lastend(struct fimc_context *ctx, bool enable) | |
288 | { | |
289 | u32 cfg; | |
290 | ||
cbc4c33d | 291 | DRM_DEBUG_KMS("enable[%d]\n", enable); |
16102edb | 292 | |
acd8afa8 | 293 | cfg = fimc_read(ctx, EXYNOS_CIOCTRL); |
16102edb EK |
294 | if (enable) |
295 | cfg |= EXYNOS_CIOCTRL_LASTENDEN; | |
296 | else | |
297 | cfg &= ~EXYNOS_CIOCTRL_LASTENDEN; | |
298 | ||
acd8afa8 | 299 | fimc_write(ctx, cfg, EXYNOS_CIOCTRL); |
16102edb EK |
300 | } |
301 | ||
7a2d5c77 | 302 | static void fimc_src_set_fmt_order(struct fimc_context *ctx, u32 fmt) |
16102edb | 303 | { |
16102edb EK |
304 | u32 cfg; |
305 | ||
cbc4c33d | 306 | DRM_DEBUG_KMS("fmt[0x%x]\n", fmt); |
16102edb EK |
307 | |
308 | /* RGB */ | |
acd8afa8 | 309 | cfg = fimc_read(ctx, EXYNOS_CISCCTRL); |
16102edb EK |
310 | cfg &= ~EXYNOS_CISCCTRL_INRGB_FMT_RGB_MASK; |
311 | ||
312 | switch (fmt) { | |
313 | case DRM_FORMAT_RGB565: | |
314 | cfg |= EXYNOS_CISCCTRL_INRGB_FMT_RGB565; | |
acd8afa8 | 315 | fimc_write(ctx, cfg, EXYNOS_CISCCTRL); |
7a2d5c77 | 316 | return; |
16102edb EK |
317 | case DRM_FORMAT_RGB888: |
318 | case DRM_FORMAT_XRGB8888: | |
319 | cfg |= EXYNOS_CISCCTRL_INRGB_FMT_RGB888; | |
acd8afa8 | 320 | fimc_write(ctx, cfg, EXYNOS_CISCCTRL); |
7a2d5c77 | 321 | return; |
16102edb EK |
322 | default: |
323 | /* bypass */ | |
324 | break; | |
325 | } | |
326 | ||
327 | /* YUV */ | |
acd8afa8 | 328 | cfg = fimc_read(ctx, EXYNOS_MSCTRL); |
16102edb EK |
329 | cfg &= ~(EXYNOS_MSCTRL_ORDER2P_SHIFT_MASK | |
330 | EXYNOS_MSCTRL_C_INT_IN_2PLANE | | |
331 | EXYNOS_MSCTRL_ORDER422_YCBYCR); | |
332 | ||
333 | switch (fmt) { | |
334 | case DRM_FORMAT_YUYV: | |
335 | cfg |= EXYNOS_MSCTRL_ORDER422_YCBYCR; | |
336 | break; | |
337 | case DRM_FORMAT_YVYU: | |
338 | cfg |= EXYNOS_MSCTRL_ORDER422_YCRYCB; | |
339 | break; | |
340 | case DRM_FORMAT_UYVY: | |
341 | cfg |= EXYNOS_MSCTRL_ORDER422_CBYCRY; | |
342 | break; | |
343 | case DRM_FORMAT_VYUY: | |
344 | case DRM_FORMAT_YUV444: | |
345 | cfg |= EXYNOS_MSCTRL_ORDER422_CRYCBY; | |
346 | break; | |
347 | case DRM_FORMAT_NV21: | |
348 | case DRM_FORMAT_NV61: | |
349 | cfg |= (EXYNOS_MSCTRL_ORDER2P_LSB_CRCB | | |
350 | EXYNOS_MSCTRL_C_INT_IN_2PLANE); | |
351 | break; | |
352 | case DRM_FORMAT_YUV422: | |
353 | case DRM_FORMAT_YUV420: | |
354 | case DRM_FORMAT_YVU420: | |
355 | cfg |= EXYNOS_MSCTRL_C_INT_IN_3PLANE; | |
356 | break; | |
357 | case DRM_FORMAT_NV12: | |
16102edb EK |
358 | case DRM_FORMAT_NV16: |
359 | cfg |= (EXYNOS_MSCTRL_ORDER2P_LSB_CBCR | | |
360 | EXYNOS_MSCTRL_C_INT_IN_2PLANE); | |
361 | break; | |
16102edb EK |
362 | } |
363 | ||
acd8afa8 | 364 | fimc_write(ctx, cfg, EXYNOS_MSCTRL); |
16102edb EK |
365 | } |
366 | ||
7a2d5c77 | 367 | static void fimc_src_set_fmt(struct fimc_context *ctx, u32 fmt, bool tiled) |
16102edb | 368 | { |
16102edb EK |
369 | u32 cfg; |
370 | ||
cbc4c33d | 371 | DRM_DEBUG_KMS("fmt[0x%x]\n", fmt); |
16102edb | 372 | |
acd8afa8 | 373 | cfg = fimc_read(ctx, EXYNOS_MSCTRL); |
16102edb EK |
374 | cfg &= ~EXYNOS_MSCTRL_INFORMAT_RGB; |
375 | ||
376 | switch (fmt) { | |
377 | case DRM_FORMAT_RGB565: | |
378 | case DRM_FORMAT_RGB888: | |
379 | case DRM_FORMAT_XRGB8888: | |
380 | cfg |= EXYNOS_MSCTRL_INFORMAT_RGB; | |
381 | break; | |
382 | case DRM_FORMAT_YUV444: | |
383 | cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR420; | |
384 | break; | |
385 | case DRM_FORMAT_YUYV: | |
386 | case DRM_FORMAT_YVYU: | |
387 | case DRM_FORMAT_UYVY: | |
388 | case DRM_FORMAT_VYUY: | |
389 | cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR422_1PLANE; | |
390 | break; | |
391 | case DRM_FORMAT_NV16: | |
392 | case DRM_FORMAT_NV61: | |
393 | case DRM_FORMAT_YUV422: | |
394 | cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR422; | |
395 | break; | |
396 | case DRM_FORMAT_YUV420: | |
397 | case DRM_FORMAT_YVU420: | |
398 | case DRM_FORMAT_NV12: | |
399 | case DRM_FORMAT_NV21: | |
16102edb EK |
400 | cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR420; |
401 | break; | |
16102edb EK |
402 | } |
403 | ||
acd8afa8 | 404 | fimc_write(ctx, cfg, EXYNOS_MSCTRL); |
16102edb | 405 | |
acd8afa8 | 406 | cfg = fimc_read(ctx, EXYNOS_CIDMAPARAM); |
16102edb EK |
407 | cfg &= ~EXYNOS_CIDMAPARAM_R_MODE_MASK; |
408 | ||
7a2d5c77 MS |
409 | if (tiled) |
410 | cfg |= EXYNOS_CIDMAPARAM_R_MODE_64X32; | |
411 | else | |
412 | cfg |= EXYNOS_CIDMAPARAM_R_MODE_LINEAR; | |
16102edb | 413 | |
acd8afa8 | 414 | fimc_write(ctx, cfg, EXYNOS_CIDMAPARAM); |
16102edb | 415 | |
7a2d5c77 | 416 | fimc_src_set_fmt_order(ctx, fmt); |
16102edb EK |
417 | } |
418 | ||
7a2d5c77 | 419 | static void fimc_src_set_transf(struct fimc_context *ctx, unsigned int rotation) |
16102edb | 420 | { |
7a2d5c77 | 421 | unsigned int degree = rotation & DRM_MODE_ROTATE_MASK; |
16102edb EK |
422 | u32 cfg1, cfg2; |
423 | ||
7a2d5c77 | 424 | DRM_DEBUG_KMS("rotation[%x]\n", rotation); |
16102edb | 425 | |
acd8afa8 | 426 | cfg1 = fimc_read(ctx, EXYNOS_MSCTRL); |
16102edb EK |
427 | cfg1 &= ~(EXYNOS_MSCTRL_FLIP_X_MIRROR | |
428 | EXYNOS_MSCTRL_FLIP_Y_MIRROR); | |
429 | ||
acd8afa8 | 430 | cfg2 = fimc_read(ctx, EXYNOS_CITRGFMT); |
16102edb EK |
431 | cfg2 &= ~EXYNOS_CITRGFMT_INROT90_CLOCKWISE; |
432 | ||
433 | switch (degree) { | |
7a2d5c77 MS |
434 | case DRM_MODE_ROTATE_0: |
435 | if (rotation & DRM_MODE_REFLECT_X) | |
16102edb | 436 | cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR; |
7a2d5c77 | 437 | if (rotation & DRM_MODE_REFLECT_Y) |
16102edb EK |
438 | cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR; |
439 | break; | |
7a2d5c77 | 440 | case DRM_MODE_ROTATE_90: |
16102edb | 441 | cfg2 |= EXYNOS_CITRGFMT_INROT90_CLOCKWISE; |
7a2d5c77 | 442 | if (rotation & DRM_MODE_REFLECT_X) |
16102edb | 443 | cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR; |
7a2d5c77 | 444 | if (rotation & DRM_MODE_REFLECT_Y) |
16102edb EK |
445 | cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR; |
446 | break; | |
7a2d5c77 | 447 | case DRM_MODE_ROTATE_180: |
16102edb EK |
448 | cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR | |
449 | EXYNOS_MSCTRL_FLIP_Y_MIRROR); | |
7a2d5c77 | 450 | if (rotation & DRM_MODE_REFLECT_X) |
16102edb | 451 | cfg1 &= ~EXYNOS_MSCTRL_FLIP_X_MIRROR; |
7a2d5c77 | 452 | if (rotation & DRM_MODE_REFLECT_Y) |
16102edb EK |
453 | cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR; |
454 | break; | |
7a2d5c77 | 455 | case DRM_MODE_ROTATE_270: |
16102edb EK |
456 | cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR | |
457 | EXYNOS_MSCTRL_FLIP_Y_MIRROR); | |
458 | cfg2 |= EXYNOS_CITRGFMT_INROT90_CLOCKWISE; | |
7a2d5c77 | 459 | if (rotation & DRM_MODE_REFLECT_X) |
16102edb | 460 | cfg1 &= ~EXYNOS_MSCTRL_FLIP_X_MIRROR; |
7a2d5c77 | 461 | if (rotation & DRM_MODE_REFLECT_Y) |
16102edb EK |
462 | cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR; |
463 | break; | |
16102edb EK |
464 | } |
465 | ||
acd8afa8 AH |
466 | fimc_write(ctx, cfg1, EXYNOS_MSCTRL); |
467 | fimc_write(ctx, cfg2, EXYNOS_CITRGFMT); | |
16102edb EK |
468 | } |
469 | ||
7a2d5c77 MS |
470 | static void fimc_set_window(struct fimc_context *ctx, |
471 | struct exynos_drm_ipp_buffer *buf) | |
16102edb EK |
472 | { |
473 | u32 cfg, h1, h2, v1, v2; | |
474 | ||
475 | /* cropped image */ | |
7a2d5c77 MS |
476 | h1 = buf->rect.x; |
477 | h2 = buf->buf.width - buf->rect.w - buf->rect.x; | |
478 | v1 = buf->rect.y; | |
479 | v2 = buf->buf.height - buf->rect.h - buf->rect.y; | |
16102edb | 480 | |
cbc4c33d | 481 | DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]hsize[%d]vsize[%d]\n", |
7a2d5c77 MS |
482 | buf->rect.x, buf->rect.y, buf->rect.w, buf->rect.h, |
483 | buf->buf.width, buf->buf.height); | |
cbc4c33d | 484 | DRM_DEBUG_KMS("h1[%d]h2[%d]v1[%d]v2[%d]\n", h1, h2, v1, v2); |
16102edb EK |
485 | |
486 | /* | |
487 | * set window offset 1, 2 size | |
488 | * check figure 43-21 in user manual | |
489 | */ | |
acd8afa8 | 490 | cfg = fimc_read(ctx, EXYNOS_CIWDOFST); |
16102edb EK |
491 | cfg &= ~(EXYNOS_CIWDOFST_WINHOROFST_MASK | |
492 | EXYNOS_CIWDOFST_WINVEROFST_MASK); | |
493 | cfg |= (EXYNOS_CIWDOFST_WINHOROFST(h1) | | |
494 | EXYNOS_CIWDOFST_WINVEROFST(v1)); | |
495 | cfg |= EXYNOS_CIWDOFST_WINOFSEN; | |
acd8afa8 | 496 | fimc_write(ctx, cfg, EXYNOS_CIWDOFST); |
16102edb EK |
497 | |
498 | cfg = (EXYNOS_CIWDOFST2_WINHOROFST2(h2) | | |
499 | EXYNOS_CIWDOFST2_WINVEROFST2(v2)); | |
acd8afa8 | 500 | fimc_write(ctx, cfg, EXYNOS_CIWDOFST2); |
16102edb EK |
501 | } |
502 | ||
7a2d5c77 MS |
503 | static void fimc_src_set_size(struct fimc_context *ctx, |
504 | struct exynos_drm_ipp_buffer *buf) | |
16102edb | 505 | { |
16102edb EK |
506 | u32 cfg; |
507 | ||
7a2d5c77 | 508 | DRM_DEBUG_KMS("hsize[%d]vsize[%d]\n", buf->buf.width, buf->buf.height); |
16102edb EK |
509 | |
510 | /* original size */ | |
7a2d5c77 MS |
511 | cfg = (EXYNOS_ORGISIZE_HORIZONTAL(buf->buf.width) | |
512 | EXYNOS_ORGISIZE_VERTICAL(buf->buf.height)); | |
16102edb | 513 | |
acd8afa8 | 514 | fimc_write(ctx, cfg, EXYNOS_ORGISIZE); |
16102edb | 515 | |
7a2d5c77 MS |
516 | DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]\n", buf->rect.x, buf->rect.y, |
517 | buf->rect.w, buf->rect.h); | |
16102edb EK |
518 | |
519 | /* set input DMA image size */ | |
acd8afa8 | 520 | cfg = fimc_read(ctx, EXYNOS_CIREAL_ISIZE); |
16102edb EK |
521 | cfg &= ~(EXYNOS_CIREAL_ISIZE_HEIGHT_MASK | |
522 | EXYNOS_CIREAL_ISIZE_WIDTH_MASK); | |
7a2d5c77 MS |
523 | cfg |= (EXYNOS_CIREAL_ISIZE_WIDTH(buf->rect.w) | |
524 | EXYNOS_CIREAL_ISIZE_HEIGHT(buf->rect.h)); | |
acd8afa8 | 525 | fimc_write(ctx, cfg, EXYNOS_CIREAL_ISIZE); |
16102edb EK |
526 | |
527 | /* | |
528 | * set input FIFO image size | |
529 | * for now, we support only ITU601 8 bit mode | |
530 | */ | |
531 | cfg = (EXYNOS_CISRCFMT_ITU601_8BIT | | |
7a2d5c77 MS |
532 | EXYNOS_CISRCFMT_SOURCEHSIZE(buf->buf.width) | |
533 | EXYNOS_CISRCFMT_SOURCEVSIZE(buf->buf.height)); | |
acd8afa8 | 534 | fimc_write(ctx, cfg, EXYNOS_CISRCFMT); |
16102edb EK |
535 | |
536 | /* offset Y(RGB), Cb, Cr */ | |
7a2d5c77 MS |
537 | cfg = (EXYNOS_CIIYOFF_HORIZONTAL(buf->rect.x) | |
538 | EXYNOS_CIIYOFF_VERTICAL(buf->rect.y)); | |
acd8afa8 | 539 | fimc_write(ctx, cfg, EXYNOS_CIIYOFF); |
7a2d5c77 MS |
540 | cfg = (EXYNOS_CIICBOFF_HORIZONTAL(buf->rect.x) | |
541 | EXYNOS_CIICBOFF_VERTICAL(buf->rect.y)); | |
acd8afa8 | 542 | fimc_write(ctx, cfg, EXYNOS_CIICBOFF); |
7a2d5c77 MS |
543 | cfg = (EXYNOS_CIICROFF_HORIZONTAL(buf->rect.x) | |
544 | EXYNOS_CIICROFF_VERTICAL(buf->rect.y)); | |
acd8afa8 | 545 | fimc_write(ctx, cfg, EXYNOS_CIICROFF); |
16102edb | 546 | |
7a2d5c77 | 547 | fimc_set_window(ctx, buf); |
16102edb EK |
548 | } |
549 | ||
7a2d5c77 MS |
550 | static void fimc_src_set_addr(struct fimc_context *ctx, |
551 | struct exynos_drm_ipp_buffer *buf) | |
16102edb | 552 | { |
7a2d5c77 MS |
553 | fimc_write(ctx, buf->dma_addr[0], EXYNOS_CIIYSA(0)); |
554 | fimc_write(ctx, buf->dma_addr[1], EXYNOS_CIICBSA(0)); | |
555 | fimc_write(ctx, buf->dma_addr[2], EXYNOS_CIICRSA(0)); | |
16102edb EK |
556 | } |
557 | ||
7a2d5c77 | 558 | static void fimc_dst_set_fmt_order(struct fimc_context *ctx, u32 fmt) |
16102edb | 559 | { |
16102edb EK |
560 | u32 cfg; |
561 | ||
cbc4c33d | 562 | DRM_DEBUG_KMS("fmt[0x%x]\n", fmt); |
16102edb EK |
563 | |
564 | /* RGB */ | |
acd8afa8 | 565 | cfg = fimc_read(ctx, EXYNOS_CISCCTRL); |
16102edb EK |
566 | cfg &= ~EXYNOS_CISCCTRL_OUTRGB_FMT_RGB_MASK; |
567 | ||
568 | switch (fmt) { | |
569 | case DRM_FORMAT_RGB565: | |
570 | cfg |= EXYNOS_CISCCTRL_OUTRGB_FMT_RGB565; | |
acd8afa8 | 571 | fimc_write(ctx, cfg, EXYNOS_CISCCTRL); |
7a2d5c77 | 572 | return; |
16102edb EK |
573 | case DRM_FORMAT_RGB888: |
574 | cfg |= EXYNOS_CISCCTRL_OUTRGB_FMT_RGB888; | |
acd8afa8 | 575 | fimc_write(ctx, cfg, EXYNOS_CISCCTRL); |
7a2d5c77 | 576 | return; |
16102edb EK |
577 | case DRM_FORMAT_XRGB8888: |
578 | cfg |= (EXYNOS_CISCCTRL_OUTRGB_FMT_RGB888 | | |
579 | EXYNOS_CISCCTRL_EXTRGB_EXTENSION); | |
acd8afa8 | 580 | fimc_write(ctx, cfg, EXYNOS_CISCCTRL); |
16102edb EK |
581 | break; |
582 | default: | |
583 | /* bypass */ | |
584 | break; | |
585 | } | |
586 | ||
587 | /* YUV */ | |
acd8afa8 | 588 | cfg = fimc_read(ctx, EXYNOS_CIOCTRL); |
16102edb EK |
589 | cfg &= ~(EXYNOS_CIOCTRL_ORDER2P_MASK | |
590 | EXYNOS_CIOCTRL_ORDER422_MASK | | |
591 | EXYNOS_CIOCTRL_YCBCR_PLANE_MASK); | |
592 | ||
593 | switch (fmt) { | |
594 | case DRM_FORMAT_XRGB8888: | |
595 | cfg |= EXYNOS_CIOCTRL_ALPHA_OUT; | |
596 | break; | |
597 | case DRM_FORMAT_YUYV: | |
598 | cfg |= EXYNOS_CIOCTRL_ORDER422_YCBYCR; | |
599 | break; | |
600 | case DRM_FORMAT_YVYU: | |
601 | cfg |= EXYNOS_CIOCTRL_ORDER422_YCRYCB; | |
602 | break; | |
603 | case DRM_FORMAT_UYVY: | |
604 | cfg |= EXYNOS_CIOCTRL_ORDER422_CBYCRY; | |
605 | break; | |
606 | case DRM_FORMAT_VYUY: | |
607 | cfg |= EXYNOS_CIOCTRL_ORDER422_CRYCBY; | |
608 | break; | |
609 | case DRM_FORMAT_NV21: | |
610 | case DRM_FORMAT_NV61: | |
611 | cfg |= EXYNOS_CIOCTRL_ORDER2P_LSB_CRCB; | |
612 | cfg |= EXYNOS_CIOCTRL_YCBCR_2PLANE; | |
613 | break; | |
614 | case DRM_FORMAT_YUV422: | |
615 | case DRM_FORMAT_YUV420: | |
616 | case DRM_FORMAT_YVU420: | |
617 | cfg |= EXYNOS_CIOCTRL_YCBCR_3PLANE; | |
618 | break; | |
619 | case DRM_FORMAT_NV12: | |
16102edb EK |
620 | case DRM_FORMAT_NV16: |
621 | cfg |= EXYNOS_CIOCTRL_ORDER2P_LSB_CBCR; | |
622 | cfg |= EXYNOS_CIOCTRL_YCBCR_2PLANE; | |
623 | break; | |
16102edb EK |
624 | } |
625 | ||
acd8afa8 | 626 | fimc_write(ctx, cfg, EXYNOS_CIOCTRL); |
16102edb EK |
627 | } |
628 | ||
7a2d5c77 | 629 | static void fimc_dst_set_fmt(struct fimc_context *ctx, u32 fmt, bool tiled) |
16102edb | 630 | { |
16102edb EK |
631 | u32 cfg; |
632 | ||
cbc4c33d | 633 | DRM_DEBUG_KMS("fmt[0x%x]\n", fmt); |
16102edb | 634 | |
acd8afa8 | 635 | cfg = fimc_read(ctx, EXYNOS_CIEXTEN); |
16102edb EK |
636 | |
637 | if (fmt == DRM_FORMAT_AYUV) { | |
638 | cfg |= EXYNOS_CIEXTEN_YUV444_OUT; | |
acd8afa8 | 639 | fimc_write(ctx, cfg, EXYNOS_CIEXTEN); |
16102edb EK |
640 | } else { |
641 | cfg &= ~EXYNOS_CIEXTEN_YUV444_OUT; | |
acd8afa8 | 642 | fimc_write(ctx, cfg, EXYNOS_CIEXTEN); |
16102edb | 643 | |
acd8afa8 | 644 | cfg = fimc_read(ctx, EXYNOS_CITRGFMT); |
16102edb EK |
645 | cfg &= ~EXYNOS_CITRGFMT_OUTFORMAT_MASK; |
646 | ||
647 | switch (fmt) { | |
648 | case DRM_FORMAT_RGB565: | |
649 | case DRM_FORMAT_RGB888: | |
650 | case DRM_FORMAT_XRGB8888: | |
651 | cfg |= EXYNOS_CITRGFMT_OUTFORMAT_RGB; | |
652 | break; | |
653 | case DRM_FORMAT_YUYV: | |
654 | case DRM_FORMAT_YVYU: | |
655 | case DRM_FORMAT_UYVY: | |
656 | case DRM_FORMAT_VYUY: | |
657 | cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422_1PLANE; | |
658 | break; | |
659 | case DRM_FORMAT_NV16: | |
660 | case DRM_FORMAT_NV61: | |
661 | case DRM_FORMAT_YUV422: | |
662 | cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422; | |
663 | break; | |
664 | case DRM_FORMAT_YUV420: | |
665 | case DRM_FORMAT_YVU420: | |
666 | case DRM_FORMAT_NV12: | |
16102edb EK |
667 | case DRM_FORMAT_NV21: |
668 | cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR420; | |
669 | break; | |
16102edb EK |
670 | } |
671 | ||
acd8afa8 | 672 | fimc_write(ctx, cfg, EXYNOS_CITRGFMT); |
16102edb EK |
673 | } |
674 | ||
acd8afa8 | 675 | cfg = fimc_read(ctx, EXYNOS_CIDMAPARAM); |
16102edb EK |
676 | cfg &= ~EXYNOS_CIDMAPARAM_W_MODE_MASK; |
677 | ||
7a2d5c77 MS |
678 | if (tiled) |
679 | cfg |= EXYNOS_CIDMAPARAM_W_MODE_64X32; | |
680 | else | |
681 | cfg |= EXYNOS_CIDMAPARAM_W_MODE_LINEAR; | |
16102edb | 682 | |
acd8afa8 | 683 | fimc_write(ctx, cfg, EXYNOS_CIDMAPARAM); |
16102edb | 684 | |
7a2d5c77 | 685 | fimc_dst_set_fmt_order(ctx, fmt); |
16102edb EK |
686 | } |
687 | ||
7a2d5c77 | 688 | static void fimc_dst_set_transf(struct fimc_context *ctx, unsigned int rotation) |
16102edb | 689 | { |
7a2d5c77 | 690 | unsigned int degree = rotation & DRM_MODE_ROTATE_MASK; |
16102edb EK |
691 | u32 cfg; |
692 | ||
7a2d5c77 | 693 | DRM_DEBUG_KMS("rotation[0x%x]\n", rotation); |
16102edb | 694 | |
acd8afa8 | 695 | cfg = fimc_read(ctx, EXYNOS_CITRGFMT); |
16102edb EK |
696 | cfg &= ~EXYNOS_CITRGFMT_FLIP_MASK; |
697 | cfg &= ~EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE; | |
698 | ||
699 | switch (degree) { | |
7a2d5c77 MS |
700 | case DRM_MODE_ROTATE_0: |
701 | if (rotation & DRM_MODE_REFLECT_X) | |
16102edb | 702 | cfg |= EXYNOS_CITRGFMT_FLIP_X_MIRROR; |
7a2d5c77 | 703 | if (rotation & DRM_MODE_REFLECT_Y) |
16102edb EK |
704 | cfg |= EXYNOS_CITRGFMT_FLIP_Y_MIRROR; |
705 | break; | |
7a2d5c77 | 706 | case DRM_MODE_ROTATE_90: |
16102edb | 707 | cfg |= EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE; |
7a2d5c77 | 708 | if (rotation & DRM_MODE_REFLECT_X) |
16102edb | 709 | cfg |= EXYNOS_CITRGFMT_FLIP_X_MIRROR; |
7a2d5c77 | 710 | if (rotation & DRM_MODE_REFLECT_Y) |
16102edb EK |
711 | cfg |= EXYNOS_CITRGFMT_FLIP_Y_MIRROR; |
712 | break; | |
7a2d5c77 | 713 | case DRM_MODE_ROTATE_180: |
16102edb EK |
714 | cfg |= (EXYNOS_CITRGFMT_FLIP_X_MIRROR | |
715 | EXYNOS_CITRGFMT_FLIP_Y_MIRROR); | |
7a2d5c77 | 716 | if (rotation & DRM_MODE_REFLECT_X) |
16102edb | 717 | cfg &= ~EXYNOS_CITRGFMT_FLIP_X_MIRROR; |
7a2d5c77 | 718 | if (rotation & DRM_MODE_REFLECT_Y) |
16102edb EK |
719 | cfg &= ~EXYNOS_CITRGFMT_FLIP_Y_MIRROR; |
720 | break; | |
7a2d5c77 | 721 | case DRM_MODE_ROTATE_270: |
16102edb EK |
722 | cfg |= (EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE | |
723 | EXYNOS_CITRGFMT_FLIP_X_MIRROR | | |
724 | EXYNOS_CITRGFMT_FLIP_Y_MIRROR); | |
7a2d5c77 | 725 | if (rotation & DRM_MODE_REFLECT_X) |
16102edb | 726 | cfg &= ~EXYNOS_CITRGFMT_FLIP_X_MIRROR; |
7a2d5c77 | 727 | if (rotation & DRM_MODE_REFLECT_Y) |
16102edb EK |
728 | cfg &= ~EXYNOS_CITRGFMT_FLIP_Y_MIRROR; |
729 | break; | |
16102edb EK |
730 | } |
731 | ||
acd8afa8 | 732 | fimc_write(ctx, cfg, EXYNOS_CITRGFMT); |
16102edb EK |
733 | } |
734 | ||
16102edb | 735 | static int fimc_set_prescaler(struct fimc_context *ctx, struct fimc_scaler *sc, |
7a2d5c77 MS |
736 | struct drm_exynos_ipp_task_rect *src, |
737 | struct drm_exynos_ipp_task_rect *dst) | |
16102edb | 738 | { |
16102edb EK |
739 | u32 cfg, cfg_ext, shfactor; |
740 | u32 pre_dst_width, pre_dst_height; | |
be6cdfd1 | 741 | u32 hfactor, vfactor; |
16102edb EK |
742 | int ret = 0; |
743 | u32 src_w, src_h, dst_w, dst_h; | |
744 | ||
acd8afa8 | 745 | cfg_ext = fimc_read(ctx, EXYNOS_CITRGFMT); |
16102edb EK |
746 | if (cfg_ext & EXYNOS_CITRGFMT_INROT90_CLOCKWISE) { |
747 | src_w = src->h; | |
748 | src_h = src->w; | |
749 | } else { | |
750 | src_w = src->w; | |
751 | src_h = src->h; | |
752 | } | |
753 | ||
754 | if (cfg_ext & EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE) { | |
755 | dst_w = dst->h; | |
756 | dst_h = dst->w; | |
757 | } else { | |
758 | dst_w = dst->w; | |
759 | dst_h = dst->h; | |
760 | } | |
761 | ||
be6cdfd1 AH |
762 | /* fimc_ippdrv_check_property assures that dividers are not null */ |
763 | hfactor = fls(src_w / dst_w / 2); | |
764 | if (hfactor > FIMC_SHFACTOR / 2) { | |
7a2d5c77 | 765 | dev_err(ctx->dev, "failed to get ratio horizontal.\n"); |
be6cdfd1 | 766 | return -EINVAL; |
16102edb EK |
767 | } |
768 | ||
be6cdfd1 AH |
769 | vfactor = fls(src_h / dst_h / 2); |
770 | if (vfactor > FIMC_SHFACTOR / 2) { | |
7a2d5c77 | 771 | dev_err(ctx->dev, "failed to get ratio vertical.\n"); |
be6cdfd1 | 772 | return -EINVAL; |
16102edb EK |
773 | } |
774 | ||
be6cdfd1 AH |
775 | pre_dst_width = src_w >> hfactor; |
776 | pre_dst_height = src_h >> vfactor; | |
cbc4c33d | 777 | DRM_DEBUG_KMS("pre_dst_width[%d]pre_dst_height[%d]\n", |
16102edb | 778 | pre_dst_width, pre_dst_height); |
be6cdfd1 | 779 | DRM_DEBUG_KMS("hfactor[%d]vfactor[%d]\n", hfactor, vfactor); |
16102edb EK |
780 | |
781 | sc->hratio = (src_w << 14) / (dst_w << hfactor); | |
782 | sc->vratio = (src_h << 14) / (dst_h << vfactor); | |
783 | sc->up_h = (dst_w >= src_w) ? true : false; | |
784 | sc->up_v = (dst_h >= src_h) ? true : false; | |
cbc4c33d YC |
785 | DRM_DEBUG_KMS("hratio[%d]vratio[%d]up_h[%d]up_v[%d]\n", |
786 | sc->hratio, sc->vratio, sc->up_h, sc->up_v); | |
16102edb EK |
787 | |
788 | shfactor = FIMC_SHFACTOR - (hfactor + vfactor); | |
cbc4c33d | 789 | DRM_DEBUG_KMS("shfactor[%d]\n", shfactor); |
16102edb EK |
790 | |
791 | cfg = (EXYNOS_CISCPRERATIO_SHFACTOR(shfactor) | | |
be6cdfd1 AH |
792 | EXYNOS_CISCPRERATIO_PREHORRATIO(1 << hfactor) | |
793 | EXYNOS_CISCPRERATIO_PREVERRATIO(1 << vfactor)); | |
acd8afa8 | 794 | fimc_write(ctx, cfg, EXYNOS_CISCPRERATIO); |
16102edb EK |
795 | |
796 | cfg = (EXYNOS_CISCPREDST_PREDSTWIDTH(pre_dst_width) | | |
797 | EXYNOS_CISCPREDST_PREDSTHEIGHT(pre_dst_height)); | |
acd8afa8 | 798 | fimc_write(ctx, cfg, EXYNOS_CISCPREDST); |
16102edb EK |
799 | |
800 | return ret; | |
801 | } | |
802 | ||
803 | static void fimc_set_scaler(struct fimc_context *ctx, struct fimc_scaler *sc) | |
804 | { | |
805 | u32 cfg, cfg_ext; | |
806 | ||
cbc4c33d YC |
807 | DRM_DEBUG_KMS("range[%d]bypass[%d]up_h[%d]up_v[%d]\n", |
808 | sc->range, sc->bypass, sc->up_h, sc->up_v); | |
809 | DRM_DEBUG_KMS("hratio[%d]vratio[%d]\n", | |
810 | sc->hratio, sc->vratio); | |
16102edb | 811 | |
acd8afa8 | 812 | cfg = fimc_read(ctx, EXYNOS_CISCCTRL); |
16102edb EK |
813 | cfg &= ~(EXYNOS_CISCCTRL_SCALERBYPASS | |
814 | EXYNOS_CISCCTRL_SCALEUP_H | EXYNOS_CISCCTRL_SCALEUP_V | | |
815 | EXYNOS_CISCCTRL_MAIN_V_RATIO_MASK | | |
816 | EXYNOS_CISCCTRL_MAIN_H_RATIO_MASK | | |
817 | EXYNOS_CISCCTRL_CSCR2Y_WIDE | | |
818 | EXYNOS_CISCCTRL_CSCY2R_WIDE); | |
819 | ||
820 | if (sc->range) | |
821 | cfg |= (EXYNOS_CISCCTRL_CSCR2Y_WIDE | | |
822 | EXYNOS_CISCCTRL_CSCY2R_WIDE); | |
823 | if (sc->bypass) | |
824 | cfg |= EXYNOS_CISCCTRL_SCALERBYPASS; | |
825 | if (sc->up_h) | |
826 | cfg |= EXYNOS_CISCCTRL_SCALEUP_H; | |
827 | if (sc->up_v) | |
828 | cfg |= EXYNOS_CISCCTRL_SCALEUP_V; | |
829 | ||
830 | cfg |= (EXYNOS_CISCCTRL_MAINHORRATIO((sc->hratio >> 6)) | | |
831 | EXYNOS_CISCCTRL_MAINVERRATIO((sc->vratio >> 6))); | |
acd8afa8 | 832 | fimc_write(ctx, cfg, EXYNOS_CISCCTRL); |
16102edb | 833 | |
acd8afa8 | 834 | cfg_ext = fimc_read(ctx, EXYNOS_CIEXTEN); |
16102edb EK |
835 | cfg_ext &= ~EXYNOS_CIEXTEN_MAINHORRATIO_EXT_MASK; |
836 | cfg_ext &= ~EXYNOS_CIEXTEN_MAINVERRATIO_EXT_MASK; | |
837 | cfg_ext |= (EXYNOS_CIEXTEN_MAINHORRATIO_EXT(sc->hratio) | | |
838 | EXYNOS_CIEXTEN_MAINVERRATIO_EXT(sc->vratio)); | |
acd8afa8 | 839 | fimc_write(ctx, cfg_ext, EXYNOS_CIEXTEN); |
16102edb EK |
840 | } |
841 | ||
7a2d5c77 MS |
842 | static void fimc_dst_set_size(struct fimc_context *ctx, |
843 | struct exynos_drm_ipp_buffer *buf) | |
16102edb | 844 | { |
7a2d5c77 | 845 | u32 cfg, cfg_ext; |
16102edb | 846 | |
7a2d5c77 | 847 | DRM_DEBUG_KMS("hsize[%d]vsize[%d]\n", buf->buf.width, buf->buf.height); |
16102edb EK |
848 | |
849 | /* original size */ | |
7a2d5c77 MS |
850 | cfg = (EXYNOS_ORGOSIZE_HORIZONTAL(buf->buf.width) | |
851 | EXYNOS_ORGOSIZE_VERTICAL(buf->buf.height)); | |
16102edb | 852 | |
acd8afa8 | 853 | fimc_write(ctx, cfg, EXYNOS_ORGOSIZE); |
16102edb | 854 | |
7a2d5c77 MS |
855 | DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]\n", buf->rect.x, buf->rect.y, |
856 | buf->rect.w, buf->rect.h); | |
16102edb EK |
857 | |
858 | /* CSC ITU */ | |
acd8afa8 | 859 | cfg = fimc_read(ctx, EXYNOS_CIGCTRL); |
16102edb EK |
860 | cfg &= ~EXYNOS_CIGCTRL_CSC_MASK; |
861 | ||
7a2d5c77 | 862 | if (buf->buf.width >= FIMC_WIDTH_ITU_709) |
16102edb EK |
863 | cfg |= EXYNOS_CIGCTRL_CSC_ITU709; |
864 | else | |
865 | cfg |= EXYNOS_CIGCTRL_CSC_ITU601; | |
866 | ||
acd8afa8 | 867 | fimc_write(ctx, cfg, EXYNOS_CIGCTRL); |
16102edb | 868 | |
7a2d5c77 | 869 | cfg_ext = fimc_read(ctx, EXYNOS_CITRGFMT); |
16102edb EK |
870 | |
871 | /* target image size */ | |
acd8afa8 | 872 | cfg = fimc_read(ctx, EXYNOS_CITRGFMT); |
16102edb EK |
873 | cfg &= ~(EXYNOS_CITRGFMT_TARGETH_MASK | |
874 | EXYNOS_CITRGFMT_TARGETV_MASK); | |
7a2d5c77 MS |
875 | if (cfg_ext & EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE) |
876 | cfg |= (EXYNOS_CITRGFMT_TARGETHSIZE(buf->rect.h) | | |
877 | EXYNOS_CITRGFMT_TARGETVSIZE(buf->rect.w)); | |
878 | else | |
879 | cfg |= (EXYNOS_CITRGFMT_TARGETHSIZE(buf->rect.w) | | |
880 | EXYNOS_CITRGFMT_TARGETVSIZE(buf->rect.h)); | |
acd8afa8 | 881 | fimc_write(ctx, cfg, EXYNOS_CITRGFMT); |
16102edb EK |
882 | |
883 | /* target area */ | |
7a2d5c77 | 884 | cfg = EXYNOS_CITAREA_TARGET_AREA(buf->rect.w * buf->rect.h); |
acd8afa8 | 885 | fimc_write(ctx, cfg, EXYNOS_CITAREA); |
16102edb EK |
886 | |
887 | /* offset Y(RGB), Cb, Cr */ | |
7a2d5c77 MS |
888 | cfg = (EXYNOS_CIOYOFF_HORIZONTAL(buf->rect.x) | |
889 | EXYNOS_CIOYOFF_VERTICAL(buf->rect.y)); | |
acd8afa8 | 890 | fimc_write(ctx, cfg, EXYNOS_CIOYOFF); |
7a2d5c77 MS |
891 | cfg = (EXYNOS_CIOCBOFF_HORIZONTAL(buf->rect.x) | |
892 | EXYNOS_CIOCBOFF_VERTICAL(buf->rect.y)); | |
acd8afa8 | 893 | fimc_write(ctx, cfg, EXYNOS_CIOCBOFF); |
7a2d5c77 MS |
894 | cfg = (EXYNOS_CIOCROFF_HORIZONTAL(buf->rect.x) | |
895 | EXYNOS_CIOCROFF_VERTICAL(buf->rect.y)); | |
acd8afa8 | 896 | fimc_write(ctx, cfg, EXYNOS_CIOCROFF); |
16102edb EK |
897 | } |
898 | ||
56442d83 | 899 | static void fimc_dst_set_buf_seq(struct fimc_context *ctx, u32 buf_id, |
7a2d5c77 | 900 | bool enqueue) |
16102edb | 901 | { |
72d465aa | 902 | unsigned long flags; |
56442d83 AH |
903 | u32 buf_num; |
904 | u32 cfg; | |
16102edb | 905 | |
7a2d5c77 | 906 | DRM_DEBUG_KMS("buf_id[%d]enqueu[%d]\n", buf_id, enqueue); |
16102edb | 907 | |
72d465aa | 908 | spin_lock_irqsave(&ctx->lock, flags); |
16102edb | 909 | |
acd8afa8 | 910 | cfg = fimc_read(ctx, EXYNOS_CIFCNTSEQ); |
16102edb | 911 | |
7a2d5c77 | 912 | if (enqueue) |
56442d83 AH |
913 | cfg |= (1 << buf_id); |
914 | else | |
915 | cfg &= ~(1 << buf_id); | |
16102edb | 916 | |
acd8afa8 | 917 | fimc_write(ctx, cfg, EXYNOS_CIFCNTSEQ); |
16102edb | 918 | |
56442d83 | 919 | buf_num = hweight32(cfg); |
16102edb | 920 | |
7a2d5c77 | 921 | if (enqueue && buf_num >= FIMC_BUF_START) |
56442d83 | 922 | fimc_mask_irq(ctx, true); |
7a2d5c77 | 923 | else if (!enqueue && buf_num <= FIMC_BUF_STOP) |
8b4609cd | 924 | fimc_mask_irq(ctx, false); |
16102edb | 925 | |
72d465aa | 926 | spin_unlock_irqrestore(&ctx->lock, flags); |
16102edb EK |
927 | } |
928 | ||
7a2d5c77 MS |
929 | static void fimc_dst_set_addr(struct fimc_context *ctx, |
930 | struct exynos_drm_ipp_buffer *buf) | |
16102edb | 931 | { |
7a2d5c77 MS |
932 | fimc_write(ctx, buf->dma_addr[0], EXYNOS_CIOYSA(0)); |
933 | fimc_write(ctx, buf->dma_addr[1], EXYNOS_CIOCBSA(0)); | |
934 | fimc_write(ctx, buf->dma_addr[2], EXYNOS_CIOCRSA(0)); | |
16102edb | 935 | |
7a2d5c77 | 936 | fimc_dst_set_buf_seq(ctx, 0, true); |
16102edb EK |
937 | } |
938 | ||
7a2d5c77 | 939 | static void fimc_stop(struct fimc_context *ctx); |
16102edb | 940 | |
16102edb EK |
941 | static irqreturn_t fimc_irq_handler(int irq, void *dev_id) |
942 | { | |
943 | struct fimc_context *ctx = dev_id; | |
16102edb EK |
944 | int buf_id; |
945 | ||
cbc4c33d | 946 | DRM_DEBUG_KMS("fimc id[%d]\n", ctx->id); |
16102edb EK |
947 | |
948 | fimc_clear_irq(ctx); | |
949 | if (fimc_check_ovf(ctx)) | |
950 | return IRQ_NONE; | |
951 | ||
952 | if (!fimc_check_frame_end(ctx)) | |
953 | return IRQ_NONE; | |
954 | ||
955 | buf_id = fimc_get_buf_id(ctx); | |
956 | if (buf_id < 0) | |
957 | return IRQ_HANDLED; | |
958 | ||
cbc4c33d | 959 | DRM_DEBUG_KMS("buf_id[%d]\n", buf_id); |
16102edb | 960 | |
7a2d5c77 MS |
961 | if (ctx->task) { |
962 | struct exynos_drm_ipp_task *task = ctx->task; | |
16102edb | 963 | |
7a2d5c77 MS |
964 | ctx->task = NULL; |
965 | pm_runtime_mark_last_busy(ctx->dev); | |
966 | pm_runtime_put_autosuspend(ctx->dev); | |
967 | exynos_drm_ipp_task_done(task, 0); | |
16102edb EK |
968 | } |
969 | ||
7a2d5c77 MS |
970 | fimc_dst_set_buf_seq(ctx, buf_id, false); |
971 | fimc_stop(ctx); | |
16102edb | 972 | |
7a2d5c77 | 973 | return IRQ_HANDLED; |
16102edb EK |
974 | } |
975 | ||
976 | static void fimc_clear_addr(struct fimc_context *ctx) | |
977 | { | |
978 | int i; | |
979 | ||
16102edb | 980 | for (i = 0; i < FIMC_MAX_SRC; i++) { |
acd8afa8 AH |
981 | fimc_write(ctx, 0, EXYNOS_CIIYSA(i)); |
982 | fimc_write(ctx, 0, EXYNOS_CIICBSA(i)); | |
983 | fimc_write(ctx, 0, EXYNOS_CIICRSA(i)); | |
16102edb EK |
984 | } |
985 | ||
986 | for (i = 0; i < FIMC_MAX_DST; i++) { | |
acd8afa8 AH |
987 | fimc_write(ctx, 0, EXYNOS_CIOYSA(i)); |
988 | fimc_write(ctx, 0, EXYNOS_CIOCBSA(i)); | |
989 | fimc_write(ctx, 0, EXYNOS_CIOCRSA(i)); | |
16102edb EK |
990 | } |
991 | } | |
992 | ||
7a2d5c77 | 993 | static void fimc_reset(struct fimc_context *ctx) |
16102edb | 994 | { |
16102edb | 995 | /* reset h/w block */ |
b5c0b552 | 996 | fimc_sw_reset(ctx); |
16102edb EK |
997 | |
998 | /* reset scaler capability */ | |
999 | memset(&ctx->sc, 0x0, sizeof(ctx->sc)); | |
1000 | ||
1001 | fimc_clear_addr(ctx); | |
16102edb EK |
1002 | } |
1003 | ||
7a2d5c77 | 1004 | static void fimc_start(struct fimc_context *ctx) |
16102edb | 1005 | { |
16102edb EK |
1006 | u32 cfg0, cfg1; |
1007 | ||
8b4609cd | 1008 | fimc_mask_irq(ctx, true); |
16102edb | 1009 | |
7a2d5c77 | 1010 | /* If set true, we can save jpeg about screen */ |
16102edb EK |
1011 | fimc_handle_jpeg(ctx, false); |
1012 | fimc_set_scaler(ctx, &ctx->sc); | |
16102edb | 1013 | |
7a2d5c77 MS |
1014 | fimc_set_type_ctrl(ctx); |
1015 | fimc_handle_lastend(ctx, false); | |
16102edb | 1016 | |
7a2d5c77 MS |
1017 | /* setup dma */ |
1018 | cfg0 = fimc_read(ctx, EXYNOS_MSCTRL); | |
1019 | cfg0 &= ~EXYNOS_MSCTRL_INPUT_MASK; | |
1020 | cfg0 |= EXYNOS_MSCTRL_INPUT_MEMORY; | |
1021 | fimc_write(ctx, cfg0, EXYNOS_MSCTRL); | |
16102edb EK |
1022 | |
1023 | /* Reset status */ | |
acd8afa8 | 1024 | fimc_write(ctx, 0x0, EXYNOS_CISTATUS); |
16102edb | 1025 | |
acd8afa8 | 1026 | cfg0 = fimc_read(ctx, EXYNOS_CIIMGCPT); |
16102edb EK |
1027 | cfg0 &= ~EXYNOS_CIIMGCPT_IMGCPTEN_SC; |
1028 | cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN_SC; | |
1029 | ||
1030 | /* Scaler */ | |
acd8afa8 | 1031 | cfg1 = fimc_read(ctx, EXYNOS_CISCCTRL); |
16102edb EK |
1032 | cfg1 &= ~EXYNOS_CISCCTRL_SCAN_MASK; |
1033 | cfg1 |= (EXYNOS_CISCCTRL_PROGRESSIVE | | |
1034 | EXYNOS_CISCCTRL_SCALERSTART); | |
1035 | ||
acd8afa8 | 1036 | fimc_write(ctx, cfg1, EXYNOS_CISCCTRL); |
16102edb EK |
1037 | |
1038 | /* Enable image capture*/ | |
1039 | cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN; | |
acd8afa8 | 1040 | fimc_write(ctx, cfg0, EXYNOS_CIIMGCPT); |
16102edb EK |
1041 | |
1042 | /* Disable frame end irq */ | |
acd8afa8 | 1043 | fimc_clear_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_IRQ_END_DISABLE); |
16102edb | 1044 | |
acd8afa8 | 1045 | fimc_clear_bits(ctx, EXYNOS_CIOCTRL, EXYNOS_CIOCTRL_WEAVE_MASK); |
16102edb | 1046 | |
7a2d5c77 | 1047 | fimc_set_bits(ctx, EXYNOS_MSCTRL, EXYNOS_MSCTRL_ENVID); |
16102edb EK |
1048 | } |
1049 | ||
7a2d5c77 | 1050 | static void fimc_stop(struct fimc_context *ctx) |
16102edb | 1051 | { |
16102edb EK |
1052 | u32 cfg; |
1053 | ||
7a2d5c77 MS |
1054 | /* Source clear */ |
1055 | cfg = fimc_read(ctx, EXYNOS_MSCTRL); | |
1056 | cfg &= ~EXYNOS_MSCTRL_INPUT_MASK; | |
1057 | cfg &= ~EXYNOS_MSCTRL_ENVID; | |
1058 | fimc_write(ctx, cfg, EXYNOS_MSCTRL); | |
16102edb | 1059 | |
8b4609cd | 1060 | fimc_mask_irq(ctx, false); |
16102edb EK |
1061 | |
1062 | /* reset sequence */ | |
acd8afa8 | 1063 | fimc_write(ctx, 0x0, EXYNOS_CIFCNTSEQ); |
16102edb EK |
1064 | |
1065 | /* Scaler disable */ | |
acd8afa8 | 1066 | fimc_clear_bits(ctx, EXYNOS_CISCCTRL, EXYNOS_CISCCTRL_SCALERSTART); |
16102edb EK |
1067 | |
1068 | /* Disable image capture */ | |
acd8afa8 AH |
1069 | fimc_clear_bits(ctx, EXYNOS_CIIMGCPT, |
1070 | EXYNOS_CIIMGCPT_IMGCPTEN_SC | EXYNOS_CIIMGCPT_IMGCPTEN); | |
16102edb EK |
1071 | |
1072 | /* Enable frame end irq */ | |
acd8afa8 | 1073 | fimc_set_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_IRQ_END_DISABLE); |
16102edb EK |
1074 | } |
1075 | ||
7a2d5c77 MS |
1076 | static int fimc_commit(struct exynos_drm_ipp *ipp, |
1077 | struct exynos_drm_ipp_task *task) | |
1078 | { | |
1079 | struct fimc_context *ctx = | |
1080 | container_of(ipp, struct fimc_context, ipp); | |
1081 | ||
1082 | pm_runtime_get_sync(ctx->dev); | |
1083 | ctx->task = task; | |
1084 | ||
1085 | fimc_src_set_fmt(ctx, task->src.buf.fourcc, task->src.buf.modifier); | |
1086 | fimc_src_set_size(ctx, &task->src); | |
1087 | fimc_src_set_transf(ctx, DRM_MODE_ROTATE_0); | |
1088 | fimc_src_set_addr(ctx, &task->src); | |
1089 | fimc_dst_set_fmt(ctx, task->dst.buf.fourcc, task->dst.buf.modifier); | |
1090 | fimc_dst_set_transf(ctx, task->transform.rotation); | |
1091 | fimc_dst_set_size(ctx, &task->dst); | |
1092 | fimc_dst_set_addr(ctx, &task->dst); | |
1093 | fimc_set_prescaler(ctx, &ctx->sc, &task->src.rect, &task->dst.rect); | |
1094 | fimc_start(ctx); | |
1095 | ||
1096 | return 0; | |
1097 | } | |
1098 | ||
1099 | static void fimc_abort(struct exynos_drm_ipp *ipp, | |
1100 | struct exynos_drm_ipp_task *task) | |
1101 | { | |
1102 | struct fimc_context *ctx = | |
1103 | container_of(ipp, struct fimc_context, ipp); | |
1104 | ||
1105 | fimc_reset(ctx); | |
1106 | ||
1107 | if (ctx->task) { | |
1108 | struct exynos_drm_ipp_task *task = ctx->task; | |
1109 | ||
1110 | ctx->task = NULL; | |
1111 | pm_runtime_mark_last_busy(ctx->dev); | |
1112 | pm_runtime_put_autosuspend(ctx->dev); | |
1113 | exynos_drm_ipp_task_done(task, -EIO); | |
1114 | } | |
1115 | } | |
1116 | ||
1117 | static struct exynos_drm_ipp_funcs ipp_funcs = { | |
1118 | .commit = fimc_commit, | |
1119 | .abort = fimc_abort, | |
1120 | }; | |
1121 | ||
1122 | static int fimc_bind(struct device *dev, struct device *master, void *data) | |
1123 | { | |
1124 | struct fimc_context *ctx = dev_get_drvdata(dev); | |
1125 | struct drm_device *drm_dev = data; | |
1126 | struct exynos_drm_ipp *ipp = &ctx->ipp; | |
1127 | ||
1128 | ctx->drm_dev = drm_dev; | |
1129 | drm_iommu_attach_device(drm_dev, dev); | |
1130 | ||
1131 | exynos_drm_ipp_register(drm_dev, ipp, &ipp_funcs, | |
1132 | DRM_EXYNOS_IPP_CAP_CROP | DRM_EXYNOS_IPP_CAP_ROTATE | | |
1133 | DRM_EXYNOS_IPP_CAP_SCALE | DRM_EXYNOS_IPP_CAP_CONVERT, | |
1134 | ctx->formats, ctx->num_formats, "fimc"); | |
1135 | ||
1136 | dev_info(dev, "The exynos fimc has been probed successfully\n"); | |
1137 | ||
1138 | return 0; | |
1139 | } | |
1140 | ||
1141 | static void fimc_unbind(struct device *dev, struct device *master, | |
1142 | void *data) | |
1143 | { | |
1144 | struct fimc_context *ctx = dev_get_drvdata(dev); | |
1145 | struct drm_device *drm_dev = data; | |
1146 | struct exynos_drm_ipp *ipp = &ctx->ipp; | |
1147 | ||
1148 | exynos_drm_ipp_unregister(drm_dev, ipp); | |
1149 | drm_iommu_detach_device(drm_dev, dev); | |
1150 | } | |
1151 | ||
1152 | static const struct component_ops fimc_component_ops = { | |
1153 | .bind = fimc_bind, | |
1154 | .unbind = fimc_unbind, | |
1155 | }; | |
1156 | ||
e5f86839 SN |
1157 | static void fimc_put_clocks(struct fimc_context *ctx) |
1158 | { | |
1159 | int i; | |
1160 | ||
1161 | for (i = 0; i < FIMC_CLKS_MAX; i++) { | |
1162 | if (IS_ERR(ctx->clocks[i])) | |
1163 | continue; | |
1164 | clk_put(ctx->clocks[i]); | |
1165 | ctx->clocks[i] = ERR_PTR(-EINVAL); | |
1166 | } | |
1167 | } | |
1168 | ||
1169 | static int fimc_setup_clocks(struct fimc_context *ctx) | |
1170 | { | |
7a2d5c77 | 1171 | struct device *fimc_dev = ctx->dev; |
e5f86839 SN |
1172 | struct device *dev; |
1173 | int ret, i; | |
1174 | ||
1175 | for (i = 0; i < FIMC_CLKS_MAX; i++) | |
1176 | ctx->clocks[i] = ERR_PTR(-EINVAL); | |
1177 | ||
1178 | for (i = 0; i < FIMC_CLKS_MAX; i++) { | |
1179 | if (i == FIMC_CLK_WB_A || i == FIMC_CLK_WB_B) | |
1180 | dev = fimc_dev->parent; | |
1181 | else | |
1182 | dev = fimc_dev; | |
1183 | ||
1184 | ctx->clocks[i] = clk_get(dev, fimc_clock_names[i]); | |
1185 | if (IS_ERR(ctx->clocks[i])) { | |
e5f86839 SN |
1186 | ret = PTR_ERR(ctx->clocks[i]); |
1187 | dev_err(fimc_dev, "failed to get clock: %s\n", | |
1188 | fimc_clock_names[i]); | |
1189 | goto e_clk_free; | |
1190 | } | |
1191 | } | |
1192 | ||
e5f86839 SN |
1193 | ret = clk_prepare_enable(ctx->clocks[FIMC_CLK_LCLK]); |
1194 | if (!ret) | |
1195 | return ret; | |
1196 | e_clk_free: | |
1197 | fimc_put_clocks(ctx); | |
1198 | return ret; | |
1199 | } | |
1200 | ||
7a2d5c77 | 1201 | int exynos_drm_check_fimc_device(struct device *dev) |
5186fc5e | 1202 | { |
19832055 | 1203 | int id = of_alias_get_id(dev->of_node, "fimc"); |
5186fc5e | 1204 | |
7a2d5c77 MS |
1205 | if (id >= 0 && (BIT(id) & fimc_mask)) |
1206 | return 0; | |
1207 | return -ENODEV; | |
1208 | } | |
5186fc5e | 1209 | |
7a2d5c77 MS |
1210 | static const unsigned int fimc_formats[] = { |
1211 | DRM_FORMAT_XRGB8888, DRM_FORMAT_RGB565, | |
1212 | DRM_FORMAT_NV12, DRM_FORMAT_NV16, DRM_FORMAT_NV21, DRM_FORMAT_NV61, | |
1213 | DRM_FORMAT_UYVY, DRM_FORMAT_VYUY, DRM_FORMAT_YUYV, DRM_FORMAT_YVYU, | |
1214 | DRM_FORMAT_YUV420, DRM_FORMAT_YVU420, DRM_FORMAT_YUV422, | |
1215 | DRM_FORMAT_YUV444, | |
1216 | }; | |
5186fc5e | 1217 | |
7a2d5c77 MS |
1218 | static const unsigned int fimc_tiled_formats[] = { |
1219 | DRM_FORMAT_NV12, DRM_FORMAT_NV21, | |
1220 | }; | |
5186fc5e | 1221 | |
7a2d5c77 MS |
1222 | static const struct drm_exynos_ipp_limit fimc_4210_limits_v1[] = { |
1223 | { IPP_SIZE_LIMIT(BUFFER, .h = { 16, 8192, 8 }, .v = { 16, 8192, 2 }) }, | |
1224 | { IPP_SIZE_LIMIT(AREA, .h = { 16, 4224, 2 }, .v = { 16, 0, 2 }) }, | |
1225 | { IPP_SIZE_LIMIT(ROTATED, .h = { 128, 1920 }, .v = { 128, 0 }) }, | |
1226 | { IPP_SCALE_LIMIT(.h = { (1 << 16) / 64, (1 << 16) * 64 }, | |
1227 | .v = { (1 << 16) / 64, (1 << 16) * 64 }) }, | |
1228 | }; | |
5186fc5e | 1229 | |
7a2d5c77 MS |
1230 | static const struct drm_exynos_ipp_limit fimc_4210_limits_v2[] = { |
1231 | { IPP_SIZE_LIMIT(BUFFER, .h = { 16, 8192, 8 }, .v = { 16, 8192, 2 }) }, | |
1232 | { IPP_SIZE_LIMIT(AREA, .h = { 16, 1920, 2 }, .v = { 16, 0, 2 }) }, | |
1233 | { IPP_SIZE_LIMIT(ROTATED, .h = { 128, 1366 }, .v = { 128, 0 }) }, | |
1234 | { IPP_SCALE_LIMIT(.h = { (1 << 16) / 64, (1 << 16) * 64 }, | |
1235 | .v = { (1 << 16) / 64, (1 << 16) * 64 }) }, | |
1236 | }; | |
1237 | ||
1238 | static const struct drm_exynos_ipp_limit fimc_4210_limits_tiled_v1[] = { | |
1239 | { IPP_SIZE_LIMIT(BUFFER, .h = { 128, 1920, 128 }, .v = { 32, 1920, 32 }) }, | |
1240 | { IPP_SIZE_LIMIT(AREA, .h = { 128, 1920, 2 }, .v = { 128, 0, 2 }) }, | |
1241 | { IPP_SCALE_LIMIT(.h = { (1 << 16) / 64, (1 << 16) * 64 }, | |
1242 | .v = { (1 << 16) / 64, (1 << 16) * 64 }) }, | |
1243 | }; | |
1244 | ||
1245 | static const struct drm_exynos_ipp_limit fimc_4210_limits_tiled_v2[] = { | |
1246 | { IPP_SIZE_LIMIT(BUFFER, .h = { 128, 1920, 128 }, .v = { 32, 1920, 32 }) }, | |
1247 | { IPP_SIZE_LIMIT(AREA, .h = { 128, 1366, 2 }, .v = { 128, 0, 2 }) }, | |
1248 | { IPP_SCALE_LIMIT(.h = { (1 << 16) / 64, (1 << 16) * 64 }, | |
1249 | .v = { (1 << 16) / 64, (1 << 16) * 64 }) }, | |
1250 | }; | |
5186fc5e | 1251 | |
56550d94 | 1252 | static int fimc_probe(struct platform_device *pdev) |
16102edb | 1253 | { |
7a2d5c77 MS |
1254 | const struct drm_exynos_ipp_limit *limits; |
1255 | struct exynos_drm_ipp_formats *formats; | |
16102edb EK |
1256 | struct device *dev = &pdev->dev; |
1257 | struct fimc_context *ctx; | |
16102edb | 1258 | struct resource *res; |
16102edb | 1259 | int ret; |
7a2d5c77 | 1260 | int i, j, num_limits, num_formats; |
16102edb | 1261 | |
7a2d5c77 | 1262 | if (exynos_drm_check_fimc_device(dev) != 0) |
5186fc5e | 1263 | return -ENODEV; |
16102edb EK |
1264 | |
1265 | ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); | |
1266 | if (!ctx) | |
1267 | return -ENOMEM; | |
1268 | ||
7a2d5c77 MS |
1269 | ctx->dev = dev; |
1270 | ctx->id = of_alias_get_id(dev->of_node, "fimc"); | |
5186fc5e | 1271 | |
7a2d5c77 MS |
1272 | /* construct formats/limits array */ |
1273 | num_formats = ARRAY_SIZE(fimc_formats) + ARRAY_SIZE(fimc_tiled_formats); | |
a86854d0 KC |
1274 | formats = devm_kcalloc(dev, num_formats, sizeof(*formats), |
1275 | GFP_KERNEL); | |
7a2d5c77 MS |
1276 | if (!formats) |
1277 | return -ENOMEM; | |
1278 | ||
1279 | /* linear formats */ | |
1280 | if (ctx->id < 3) { | |
1281 | limits = fimc_4210_limits_v1; | |
1282 | num_limits = ARRAY_SIZE(fimc_4210_limits_v1); | |
1283 | } else { | |
1284 | limits = fimc_4210_limits_v2; | |
1285 | num_limits = ARRAY_SIZE(fimc_4210_limits_v2); | |
1286 | } | |
1287 | for (i = 0; i < ARRAY_SIZE(fimc_formats); i++) { | |
1288 | formats[i].fourcc = fimc_formats[i]; | |
1289 | formats[i].type = DRM_EXYNOS_IPP_FORMAT_SOURCE | | |
1290 | DRM_EXYNOS_IPP_FORMAT_DESTINATION; | |
1291 | formats[i].limits = limits; | |
1292 | formats[i].num_limits = num_limits; | |
1293 | } | |
5186fc5e | 1294 | |
7a2d5c77 MS |
1295 | /* tiled formats */ |
1296 | if (ctx->id < 3) { | |
1297 | limits = fimc_4210_limits_tiled_v1; | |
1298 | num_limits = ARRAY_SIZE(fimc_4210_limits_tiled_v1); | |
1299 | } else { | |
1300 | limits = fimc_4210_limits_tiled_v2; | |
1301 | num_limits = ARRAY_SIZE(fimc_4210_limits_tiled_v2); | |
5186fc5e | 1302 | } |
7a2d5c77 MS |
1303 | for (j = i, i = 0; i < ARRAY_SIZE(fimc_tiled_formats); j++, i++) { |
1304 | formats[j].fourcc = fimc_tiled_formats[i]; | |
1305 | formats[j].modifier = DRM_FORMAT_MOD_SAMSUNG_64_32_TILE; | |
1306 | formats[j].type = DRM_EXYNOS_IPP_FORMAT_SOURCE | | |
1307 | DRM_EXYNOS_IPP_FORMAT_DESTINATION; | |
1308 | formats[j].limits = limits; | |
1309 | formats[j].num_limits = num_limits; | |
1310 | } | |
1311 | ||
1312 | ctx->formats = formats; | |
1313 | ctx->num_formats = num_formats; | |
5186fc5e | 1314 | |
16102edb EK |
1315 | /* resource memory */ |
1316 | ctx->regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
d4ed6025 TR |
1317 | ctx->regs = devm_ioremap_resource(dev, ctx->regs_res); |
1318 | if (IS_ERR(ctx->regs)) | |
1319 | return PTR_ERR(ctx->regs); | |
16102edb EK |
1320 | |
1321 | /* resource irq */ | |
1322 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
1323 | if (!res) { | |
1324 | dev_err(dev, "failed to request irq resource.\n"); | |
15b3263e | 1325 | return -ENOENT; |
16102edb EK |
1326 | } |
1327 | ||
7a2d5c77 MS |
1328 | ret = devm_request_irq(dev, res->start, fimc_irq_handler, |
1329 | 0, dev_name(dev), ctx); | |
16102edb EK |
1330 | if (ret < 0) { |
1331 | dev_err(dev, "failed to request irq.\n"); | |
15b3263e | 1332 | return ret; |
16102edb EK |
1333 | } |
1334 | ||
e5f86839 SN |
1335 | ret = fimc_setup_clocks(ctx); |
1336 | if (ret < 0) | |
dcb9a7c7 | 1337 | return ret; |
16102edb | 1338 | |
72d465aa | 1339 | spin_lock_init(&ctx->lock); |
16102edb EK |
1340 | platform_set_drvdata(pdev, ctx); |
1341 | ||
7a2d5c77 MS |
1342 | pm_runtime_use_autosuspend(dev); |
1343 | pm_runtime_set_autosuspend_delay(dev, FIMC_AUTOSUSPEND_DELAY); | |
16102edb EK |
1344 | pm_runtime_enable(dev); |
1345 | ||
7a2d5c77 MS |
1346 | ret = component_add(dev, &fimc_component_ops); |
1347 | if (ret) | |
e5f86839 | 1348 | goto err_pm_dis; |
16102edb | 1349 | |
d873ab99 | 1350 | dev_info(dev, "drm fimc registered successfully.\n"); |
16102edb EK |
1351 | |
1352 | return 0; | |
1353 | ||
e5f86839 | 1354 | err_pm_dis: |
7a2d5c77 | 1355 | pm_runtime_dont_use_autosuspend(dev); |
16102edb | 1356 | pm_runtime_disable(dev); |
e5f86839 | 1357 | fimc_put_clocks(ctx); |
87acdde5 | 1358 | |
16102edb EK |
1359 | return ret; |
1360 | } | |
1361 | ||
56550d94 | 1362 | static int fimc_remove(struct platform_device *pdev) |
16102edb EK |
1363 | { |
1364 | struct device *dev = &pdev->dev; | |
1365 | struct fimc_context *ctx = get_fimc_context(dev); | |
16102edb | 1366 | |
7a2d5c77 MS |
1367 | component_del(dev, &fimc_component_ops); |
1368 | pm_runtime_dont_use_autosuspend(dev); | |
1369 | pm_runtime_disable(dev); | |
16102edb | 1370 | |
e5f86839 | 1371 | fimc_put_clocks(ctx); |
16102edb | 1372 | |
16102edb EK |
1373 | return 0; |
1374 | } | |
1375 | ||
641a2fef | 1376 | #ifdef CONFIG_PM |
16102edb EK |
1377 | static int fimc_runtime_suspend(struct device *dev) |
1378 | { | |
1379 | struct fimc_context *ctx = get_fimc_context(dev); | |
1380 | ||
cbc4c33d | 1381 | DRM_DEBUG_KMS("id[%d]\n", ctx->id); |
7a2d5c77 MS |
1382 | clk_disable_unprepare(ctx->clocks[FIMC_CLK_GATE]); |
1383 | return 0; | |
16102edb EK |
1384 | } |
1385 | ||
1386 | static int fimc_runtime_resume(struct device *dev) | |
1387 | { | |
1388 | struct fimc_context *ctx = get_fimc_context(dev); | |
1389 | ||
cbc4c33d | 1390 | DRM_DEBUG_KMS("id[%d]\n", ctx->id); |
7a2d5c77 | 1391 | return clk_prepare_enable(ctx->clocks[FIMC_CLK_GATE]); |
16102edb EK |
1392 | } |
1393 | #endif | |
1394 | ||
16102edb | 1395 | static const struct dev_pm_ops fimc_pm_ops = { |
479f1254 MS |
1396 | SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, |
1397 | pm_runtime_force_resume) | |
16102edb EK |
1398 | SET_RUNTIME_PM_OPS(fimc_runtime_suspend, fimc_runtime_resume, NULL) |
1399 | }; | |
1400 | ||
5186fc5e SN |
1401 | static const struct of_device_id fimc_of_match[] = { |
1402 | { .compatible = "samsung,exynos4210-fimc" }, | |
1403 | { .compatible = "samsung,exynos4212-fimc" }, | |
1404 | { }, | |
1405 | }; | |
39b58a39 | 1406 | MODULE_DEVICE_TABLE(of, fimc_of_match); |
5186fc5e | 1407 | |
16102edb EK |
1408 | struct platform_driver fimc_driver = { |
1409 | .probe = fimc_probe, | |
56550d94 | 1410 | .remove = fimc_remove, |
16102edb | 1411 | .driver = { |
5186fc5e | 1412 | .of_match_table = fimc_of_match, |
16102edb EK |
1413 | .name = "exynos-drm-fimc", |
1414 | .owner = THIS_MODULE, | |
1415 | .pm = &fimc_pm_ops, | |
1416 | }, | |
1417 | }; |