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1c248b7d ID |
1 | /* exynos_drm_fimd.c |
2 | * | |
3 | * Copyright (C) 2011 Samsung Electronics Co.Ltd | |
4 | * Authors: | |
5 | * Joonyoung Shim <jy0922.shim@samsung.com> | |
6 | * Inki Dae <inki.dae@samsung.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | */ | |
760285e7 | 14 | #include <drm/drmP.h> |
1c248b7d ID |
15 | |
16 | #include <linux/kernel.h> | |
1c248b7d ID |
17 | #include <linux/platform_device.h> |
18 | #include <linux/clk.h> | |
3f1c781d | 19 | #include <linux/of.h> |
d636ead8 | 20 | #include <linux/of_device.h> |
cb91f6a0 | 21 | #include <linux/pm_runtime.h> |
1c248b7d | 22 | |
7f4596f4 | 23 | #include <video/of_display_timing.h> |
111e6055 | 24 | #include <video/of_videomode.h> |
5a213a55 | 25 | #include <video/samsung_fimd.h> |
1c248b7d | 26 | #include <drm/exynos_drm.h> |
1c248b7d ID |
27 | |
28 | #include "exynos_drm_drv.h" | |
29 | #include "exynos_drm_fbdev.h" | |
30 | #include "exynos_drm_crtc.h" | |
bcc5cd1c | 31 | #include "exynos_drm_iommu.h" |
1c248b7d ID |
32 | |
33 | /* | |
b8654b37 | 34 | * FIMD stands for Fully Interactive Mobile Display and |
1c248b7d ID |
35 | * as a display controller, it transfers contents drawn on memory |
36 | * to a LCD Panel through Display Interfaces such as RGB or | |
37 | * CPU Interface. | |
38 | */ | |
39 | ||
111e6055 AH |
40 | #define FIMD_DEFAULT_FRAMERATE 60 |
41 | ||
1c248b7d ID |
42 | /* position control register for hardware window 0, 2 ~ 4.*/ |
43 | #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16) | |
44 | #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16) | |
0f10cf14 LKA |
45 | /* |
46 | * size control register for hardware windows 0 and alpha control register | |
47 | * for hardware windows 1 ~ 4 | |
48 | */ | |
49 | #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16) | |
50 | /* size control register for hardware windows 1 ~ 2. */ | |
1c248b7d ID |
51 | #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16) |
52 | ||
53 | #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8) | |
54 | #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8) | |
55 | #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4) | |
56 | ||
57 | /* color key control register for hardware window 1 ~ 4. */ | |
0f10cf14 | 58 | #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8)) |
1c248b7d | 59 | /* color key value register for hardware window 1 ~ 4. */ |
0f10cf14 | 60 | #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8)) |
1c248b7d ID |
61 | |
62 | /* FIMD has totally five hardware windows. */ | |
63 | #define WINDOWS_NR 5 | |
64 | ||
bb7704d6 | 65 | #define get_fimd_manager(mgr) platform_get_drvdata(to_platform_device(dev)) |
1c248b7d | 66 | |
e2e13389 LKA |
67 | struct fimd_driver_data { |
68 | unsigned int timing_base; | |
de7af100 TF |
69 | |
70 | unsigned int has_shadowcon:1; | |
411d9ed4 | 71 | unsigned int has_clksel:1; |
5cc4621a | 72 | unsigned int has_limited_fmt:1; |
e2e13389 LKA |
73 | }; |
74 | ||
725ddead TF |
75 | static struct fimd_driver_data s3c64xx_fimd_driver_data = { |
76 | .timing_base = 0x0, | |
77 | .has_clksel = 1, | |
5cc4621a | 78 | .has_limited_fmt = 1, |
725ddead TF |
79 | }; |
80 | ||
6ecf18f9 | 81 | static struct fimd_driver_data exynos4_fimd_driver_data = { |
e2e13389 | 82 | .timing_base = 0x0, |
de7af100 | 83 | .has_shadowcon = 1, |
e2e13389 LKA |
84 | }; |
85 | ||
6ecf18f9 | 86 | static struct fimd_driver_data exynos5_fimd_driver_data = { |
e2e13389 | 87 | .timing_base = 0x20000, |
de7af100 | 88 | .has_shadowcon = 1, |
e2e13389 LKA |
89 | }; |
90 | ||
1c248b7d ID |
91 | struct fimd_win_data { |
92 | unsigned int offset_x; | |
93 | unsigned int offset_y; | |
19c8b834 ID |
94 | unsigned int ovl_width; |
95 | unsigned int ovl_height; | |
96 | unsigned int fb_width; | |
97 | unsigned int fb_height; | |
1c248b7d | 98 | unsigned int bpp; |
a4f38a80 | 99 | unsigned int pixel_format; |
2c871127 | 100 | dma_addr_t dma_addr; |
1c248b7d ID |
101 | unsigned int buf_offsize; |
102 | unsigned int line_size; /* bytes */ | |
ec05da95 | 103 | bool enabled; |
db7e55ae | 104 | bool resume; |
1c248b7d ID |
105 | }; |
106 | ||
107 | struct fimd_context { | |
bb7704d6 | 108 | struct device *dev; |
40c8ab4b | 109 | struct drm_device *drm_dev; |
1c248b7d ID |
110 | struct clk *bus_clk; |
111 | struct clk *lcd_clk; | |
1c248b7d | 112 | void __iomem *regs; |
a968e727 | 113 | struct drm_display_mode mode; |
1c248b7d | 114 | struct fimd_win_data win_data[WINDOWS_NR]; |
1c248b7d ID |
115 | unsigned int default_win; |
116 | unsigned long irq_flags; | |
117 | u32 vidcon0; | |
118 | u32 vidcon1; | |
cb91f6a0 | 119 | bool suspended; |
080be03d | 120 | int pipe; |
01ce113c P |
121 | wait_queue_head_t wait_vsync_queue; |
122 | atomic_t wait_vsync_event; | |
1c248b7d | 123 | |
562ad9f4 | 124 | struct exynos_drm_panel_info panel; |
18873465 | 125 | struct fimd_driver_data *driver_data; |
1c248b7d ID |
126 | }; |
127 | ||
d636ead8 | 128 | static const struct of_device_id fimd_driver_dt_match[] = { |
725ddead TF |
129 | { .compatible = "samsung,s3c6400-fimd", |
130 | .data = &s3c64xx_fimd_driver_data }, | |
5830daf8 | 131 | { .compatible = "samsung,exynos4210-fimd", |
d636ead8 | 132 | .data = &exynos4_fimd_driver_data }, |
5830daf8 | 133 | { .compatible = "samsung,exynos5250-fimd", |
d636ead8 JS |
134 | .data = &exynos5_fimd_driver_data }, |
135 | {}, | |
136 | }; | |
d636ead8 | 137 | |
e2e13389 LKA |
138 | static inline struct fimd_driver_data *drm_fimd_get_driver_data( |
139 | struct platform_device *pdev) | |
140 | { | |
d636ead8 JS |
141 | const struct of_device_id *of_id = |
142 | of_match_device(fimd_driver_dt_match, &pdev->dev); | |
143 | ||
2d3f173c | 144 | return (struct fimd_driver_data *)of_id->data; |
e2e13389 LKA |
145 | } |
146 | ||
bb7704d6 | 147 | static int fimd_mgr_initialize(struct exynos_drm_manager *mgr, |
080be03d | 148 | struct drm_device *drm_dev, int pipe) |
40c8ab4b | 149 | { |
bb7704d6 | 150 | struct fimd_context *ctx = mgr->ctx; |
40c8ab4b SP |
151 | |
152 | ctx->drm_dev = drm_dev; | |
080be03d | 153 | ctx->pipe = pipe; |
40c8ab4b | 154 | |
080be03d SP |
155 | /* |
156 | * enable drm irq mode. | |
157 | * - with irq_enabled = true, we can use the vblank feature. | |
158 | * | |
159 | * P.S. note that we wouldn't use drm irq handler but | |
160 | * just specific driver own one instead because | |
161 | * drm framework supports only one irq handler. | |
162 | */ | |
163 | drm_dev->irq_enabled = true; | |
ec05da95 | 164 | |
080be03d SP |
165 | /* |
166 | * with vblank_disable_allowed = true, vblank interrupt will be disabled | |
167 | * by drm timer once a current process gives up ownership of | |
168 | * vblank event.(after drm_vblank_put function is called) | |
169 | */ | |
170 | drm_dev->vblank_disable_allowed = true; | |
c32b06ef | 171 | |
080be03d SP |
172 | /* attach this sub driver to iommu mapping if supported. */ |
173 | if (is_drm_iommu_supported(ctx->drm_dev)) | |
174 | drm_iommu_attach_device(ctx->drm_dev, ctx->dev); | |
c32b06ef | 175 | |
080be03d | 176 | return 0; |
ec05da95 ID |
177 | } |
178 | ||
080be03d | 179 | static void fimd_mgr_remove(struct exynos_drm_manager *mgr) |
ec05da95 | 180 | { |
bb7704d6 | 181 | struct fimd_context *ctx = mgr->ctx; |
ec05da95 | 182 | |
080be03d SP |
183 | /* detach this sub driver from iommu mapping if supported. */ |
184 | if (is_drm_iommu_supported(ctx->drm_dev)) | |
185 | drm_iommu_detach_device(ctx->drm_dev, ctx->dev); | |
ec05da95 ID |
186 | } |
187 | ||
a968e727 SP |
188 | static u32 fimd_calc_clkdiv(struct fimd_context *ctx, |
189 | const struct drm_display_mode *mode) | |
190 | { | |
191 | unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh; | |
192 | u32 clkdiv; | |
193 | ||
194 | /* Find the clock divider value that gets us closest to ideal_clk */ | |
195 | clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk); | |
196 | ||
197 | return (clkdiv < 0x100) ? clkdiv : 0xff; | |
198 | } | |
199 | ||
200 | static bool fimd_mode_fixup(struct exynos_drm_manager *mgr, | |
201 | const struct drm_display_mode *mode, | |
202 | struct drm_display_mode *adjusted_mode) | |
203 | { | |
204 | if (adjusted_mode->vrefresh == 0) | |
205 | adjusted_mode->vrefresh = FIMD_DEFAULT_FRAMERATE; | |
206 | ||
207 | return true; | |
208 | } | |
209 | ||
210 | static void fimd_mode_set(struct exynos_drm_manager *mgr, | |
211 | const struct drm_display_mode *in_mode) | |
212 | { | |
213 | struct fimd_context *ctx = mgr->ctx; | |
214 | ||
215 | drm_mode_copy(&ctx->mode, in_mode); | |
216 | } | |
217 | ||
bb7704d6 | 218 | static void fimd_commit(struct exynos_drm_manager *mgr) |
1c248b7d | 219 | { |
bb7704d6 | 220 | struct fimd_context *ctx = mgr->ctx; |
a968e727 | 221 | struct drm_display_mode *mode = &ctx->mode; |
e2e13389 | 222 | struct fimd_driver_data *driver_data; |
1417f109 | 223 | u32 val, clkdiv, vidcon1; |
a968e727 | 224 | int hblank, vblank, vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd; |
1c248b7d | 225 | |
18873465 | 226 | driver_data = ctx->driver_data; |
e30d4bcf ID |
227 | if (ctx->suspended) |
228 | return; | |
229 | ||
a968e727 SP |
230 | /* nothing to do if we haven't set the mode yet */ |
231 | if (mode->htotal == 0 || mode->vtotal == 0) | |
232 | return; | |
233 | ||
1417f109 SP |
234 | /* setup polarity values */ |
235 | vidcon1 = ctx->vidcon1; | |
236 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
237 | vidcon1 |= VIDCON1_INV_VSYNC; | |
238 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
239 | vidcon1 |= VIDCON1_INV_HSYNC; | |
240 | writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1); | |
1c248b7d ID |
241 | |
242 | /* setup vertical timing values. */ | |
a968e727 SP |
243 | vblank = mode->crtc_vblank_end - mode->crtc_vblank_start; |
244 | vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; | |
245 | vbpd = (vblank - vsync_len) / 2; | |
246 | vfpd = vblank - vsync_len - vbpd; | |
247 | ||
248 | val = VIDTCON0_VBPD(vbpd - 1) | | |
249 | VIDTCON0_VFPD(vfpd - 1) | | |
250 | VIDTCON0_VSPW(vsync_len - 1); | |
e2e13389 | 251 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON0); |
1c248b7d ID |
252 | |
253 | /* setup horizontal timing values. */ | |
a968e727 SP |
254 | hblank = mode->crtc_hblank_end - mode->crtc_hblank_start; |
255 | hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; | |
256 | hbpd = (hblank - hsync_len) / 2; | |
257 | hfpd = hblank - hsync_len - hbpd; | |
258 | ||
259 | val = VIDTCON1_HBPD(hbpd - 1) | | |
260 | VIDTCON1_HFPD(hfpd - 1) | | |
261 | VIDTCON1_HSPW(hsync_len - 1); | |
e2e13389 | 262 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON1); |
1c248b7d ID |
263 | |
264 | /* setup horizontal and vertical display size. */ | |
a968e727 SP |
265 | val = VIDTCON2_LINEVAL(mode->vdisplay - 1) | |
266 | VIDTCON2_HOZVAL(mode->hdisplay - 1) | | |
267 | VIDTCON2_LINEVAL_E(mode->vdisplay - 1) | | |
268 | VIDTCON2_HOZVAL_E(mode->hdisplay - 1); | |
e2e13389 | 269 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON2); |
1c248b7d ID |
270 | |
271 | /* setup clock source, clock divider, enable dma. */ | |
272 | val = ctx->vidcon0; | |
273 | val &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR); | |
274 | ||
411d9ed4 TF |
275 | if (ctx->driver_data->has_clksel) { |
276 | val &= ~VIDCON0_CLKSEL_MASK; | |
277 | val |= VIDCON0_CLKSEL_LCD; | |
278 | } | |
279 | ||
a968e727 SP |
280 | clkdiv = fimd_calc_clkdiv(ctx, mode); |
281 | if (clkdiv > 1) | |
282 | val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR; | |
1c248b7d ID |
283 | else |
284 | val &= ~VIDCON0_CLKDIR; /* 1:1 clock */ | |
285 | ||
286 | /* | |
287 | * fields of register with prefix '_F' would be updated | |
288 | * at vsync(same as dma start) | |
289 | */ | |
290 | val |= VIDCON0_ENVID | VIDCON0_ENVID_F; | |
291 | writel(val, ctx->regs + VIDCON0); | |
292 | } | |
293 | ||
bb7704d6 | 294 | static int fimd_enable_vblank(struct exynos_drm_manager *mgr) |
1c248b7d | 295 | { |
bb7704d6 | 296 | struct fimd_context *ctx = mgr->ctx; |
1c248b7d ID |
297 | u32 val; |
298 | ||
cb91f6a0 JS |
299 | if (ctx->suspended) |
300 | return -EPERM; | |
301 | ||
1c248b7d ID |
302 | if (!test_and_set_bit(0, &ctx->irq_flags)) { |
303 | val = readl(ctx->regs + VIDINTCON0); | |
304 | ||
305 | val |= VIDINTCON0_INT_ENABLE; | |
306 | val |= VIDINTCON0_INT_FRAME; | |
307 | ||
308 | val &= ~VIDINTCON0_FRAMESEL0_MASK; | |
309 | val |= VIDINTCON0_FRAMESEL0_VSYNC; | |
310 | val &= ~VIDINTCON0_FRAMESEL1_MASK; | |
311 | val |= VIDINTCON0_FRAMESEL1_NONE; | |
312 | ||
313 | writel(val, ctx->regs + VIDINTCON0); | |
314 | } | |
315 | ||
316 | return 0; | |
317 | } | |
318 | ||
bb7704d6 | 319 | static void fimd_disable_vblank(struct exynos_drm_manager *mgr) |
1c248b7d | 320 | { |
bb7704d6 | 321 | struct fimd_context *ctx = mgr->ctx; |
1c248b7d ID |
322 | u32 val; |
323 | ||
cb91f6a0 JS |
324 | if (ctx->suspended) |
325 | return; | |
326 | ||
1c248b7d ID |
327 | if (test_and_clear_bit(0, &ctx->irq_flags)) { |
328 | val = readl(ctx->regs + VIDINTCON0); | |
329 | ||
330 | val &= ~VIDINTCON0_INT_FRAME; | |
331 | val &= ~VIDINTCON0_INT_ENABLE; | |
332 | ||
333 | writel(val, ctx->regs + VIDINTCON0); | |
334 | } | |
335 | } | |
336 | ||
bb7704d6 | 337 | static void fimd_wait_for_vblank(struct exynos_drm_manager *mgr) |
07033970 | 338 | { |
bb7704d6 | 339 | struct fimd_context *ctx = mgr->ctx; |
07033970 | 340 | |
01ce113c P |
341 | if (ctx->suspended) |
342 | return; | |
343 | ||
344 | atomic_set(&ctx->wait_vsync_event, 1); | |
345 | ||
346 | /* | |
347 | * wait for FIMD to signal VSYNC interrupt or return after | |
348 | * timeout which is set to 50ms (refresh rate of 20). | |
349 | */ | |
350 | if (!wait_event_timeout(ctx->wait_vsync_queue, | |
351 | !atomic_read(&ctx->wait_vsync_event), | |
8dd9ad5d | 352 | HZ/20)) |
07033970 P |
353 | DRM_DEBUG_KMS("vblank wait timed out.\n"); |
354 | } | |
355 | ||
bb7704d6 SP |
356 | static void fimd_win_mode_set(struct exynos_drm_manager *mgr, |
357 | struct exynos_drm_overlay *overlay) | |
1c248b7d | 358 | { |
bb7704d6 | 359 | struct fimd_context *ctx = mgr->ctx; |
1c248b7d | 360 | struct fimd_win_data *win_data; |
864ee9e6 | 361 | int win; |
19c8b834 | 362 | unsigned long offset; |
1c248b7d | 363 | |
1c248b7d | 364 | if (!overlay) { |
bb7704d6 | 365 | DRM_ERROR("overlay is NULL\n"); |
1c248b7d ID |
366 | return; |
367 | } | |
368 | ||
864ee9e6 JS |
369 | win = overlay->zpos; |
370 | if (win == DEFAULT_ZPOS) | |
371 | win = ctx->default_win; | |
372 | ||
37b006e8 | 373 | if (win < 0 || win >= WINDOWS_NR) |
864ee9e6 JS |
374 | return; |
375 | ||
19c8b834 ID |
376 | offset = overlay->fb_x * (overlay->bpp >> 3); |
377 | offset += overlay->fb_y * overlay->pitch; | |
378 | ||
379 | DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch); | |
380 | ||
864ee9e6 | 381 | win_data = &ctx->win_data[win]; |
1c248b7d | 382 | |
19c8b834 ID |
383 | win_data->offset_x = overlay->crtc_x; |
384 | win_data->offset_y = overlay->crtc_y; | |
385 | win_data->ovl_width = overlay->crtc_width; | |
386 | win_data->ovl_height = overlay->crtc_height; | |
387 | win_data->fb_width = overlay->fb_width; | |
388 | win_data->fb_height = overlay->fb_height; | |
229d3534 | 389 | win_data->dma_addr = overlay->dma_addr[0] + offset; |
1c248b7d | 390 | win_data->bpp = overlay->bpp; |
a4f38a80 | 391 | win_data->pixel_format = overlay->pixel_format; |
19c8b834 ID |
392 | win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) * |
393 | (overlay->bpp >> 3); | |
394 | win_data->line_size = overlay->crtc_width * (overlay->bpp >> 3); | |
395 | ||
396 | DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n", | |
397 | win_data->offset_x, win_data->offset_y); | |
398 | DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", | |
399 | win_data->ovl_width, win_data->ovl_height); | |
ddd8e959 | 400 | DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data->dma_addr); |
19c8b834 ID |
401 | DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n", |
402 | overlay->fb_width, overlay->crtc_width); | |
1c248b7d ID |
403 | } |
404 | ||
bb7704d6 | 405 | static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win) |
1c248b7d | 406 | { |
1c248b7d ID |
407 | struct fimd_win_data *win_data = &ctx->win_data[win]; |
408 | unsigned long val; | |
409 | ||
1c248b7d ID |
410 | val = WINCONx_ENWIN; |
411 | ||
5cc4621a ID |
412 | /* |
413 | * In case of s3c64xx, window 0 doesn't support alpha channel. | |
414 | * So the request format is ARGB8888 then change it to XRGB8888. | |
415 | */ | |
416 | if (ctx->driver_data->has_limited_fmt && !win) { | |
417 | if (win_data->pixel_format == DRM_FORMAT_ARGB8888) | |
418 | win_data->pixel_format = DRM_FORMAT_XRGB8888; | |
419 | } | |
420 | ||
a4f38a80 ID |
421 | switch (win_data->pixel_format) { |
422 | case DRM_FORMAT_C8: | |
1c248b7d ID |
423 | val |= WINCON0_BPPMODE_8BPP_PALETTE; |
424 | val |= WINCONx_BURSTLEN_8WORD; | |
425 | val |= WINCONx_BYTSWP; | |
426 | break; | |
a4f38a80 ID |
427 | case DRM_FORMAT_XRGB1555: |
428 | val |= WINCON0_BPPMODE_16BPP_1555; | |
429 | val |= WINCONx_HAWSWP; | |
430 | val |= WINCONx_BURSTLEN_16WORD; | |
431 | break; | |
432 | case DRM_FORMAT_RGB565: | |
1c248b7d ID |
433 | val |= WINCON0_BPPMODE_16BPP_565; |
434 | val |= WINCONx_HAWSWP; | |
435 | val |= WINCONx_BURSTLEN_16WORD; | |
436 | break; | |
a4f38a80 | 437 | case DRM_FORMAT_XRGB8888: |
1c248b7d ID |
438 | val |= WINCON0_BPPMODE_24BPP_888; |
439 | val |= WINCONx_WSWP; | |
440 | val |= WINCONx_BURSTLEN_16WORD; | |
441 | break; | |
a4f38a80 ID |
442 | case DRM_FORMAT_ARGB8888: |
443 | val |= WINCON1_BPPMODE_25BPP_A1888 | |
1c248b7d ID |
444 | | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL; |
445 | val |= WINCONx_WSWP; | |
446 | val |= WINCONx_BURSTLEN_16WORD; | |
447 | break; | |
448 | default: | |
449 | DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n"); | |
450 | ||
451 | val |= WINCON0_BPPMODE_24BPP_888; | |
452 | val |= WINCONx_WSWP; | |
453 | val |= WINCONx_BURSTLEN_16WORD; | |
454 | break; | |
455 | } | |
456 | ||
457 | DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp); | |
458 | ||
459 | writel(val, ctx->regs + WINCON(win)); | |
460 | } | |
461 | ||
bb7704d6 | 462 | static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win) |
1c248b7d | 463 | { |
1c248b7d ID |
464 | unsigned int keycon0 = 0, keycon1 = 0; |
465 | ||
1c248b7d ID |
466 | keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F | |
467 | WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); | |
468 | ||
469 | keycon1 = WxKEYCON1_COLVAL(0xffffffff); | |
470 | ||
471 | writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); | |
472 | writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); | |
473 | } | |
474 | ||
de7af100 TF |
475 | /** |
476 | * shadow_protect_win() - disable updating values from shadow registers at vsync | |
477 | * | |
478 | * @win: window to protect registers for | |
479 | * @protect: 1 to protect (disable updates) | |
480 | */ | |
481 | static void fimd_shadow_protect_win(struct fimd_context *ctx, | |
482 | int win, bool protect) | |
483 | { | |
484 | u32 reg, bits, val; | |
485 | ||
486 | if (ctx->driver_data->has_shadowcon) { | |
487 | reg = SHADOWCON; | |
488 | bits = SHADOWCON_WINx_PROTECT(win); | |
489 | } else { | |
490 | reg = PRTCON; | |
491 | bits = PRTCON_PROTECT; | |
492 | } | |
493 | ||
494 | val = readl(ctx->regs + reg); | |
495 | if (protect) | |
496 | val |= bits; | |
497 | else | |
498 | val &= ~bits; | |
499 | writel(val, ctx->regs + reg); | |
500 | } | |
501 | ||
bb7704d6 | 502 | static void fimd_win_commit(struct exynos_drm_manager *mgr, int zpos) |
1c248b7d | 503 | { |
bb7704d6 | 504 | struct fimd_context *ctx = mgr->ctx; |
1c248b7d | 505 | struct fimd_win_data *win_data; |
864ee9e6 | 506 | int win = zpos; |
1c248b7d | 507 | unsigned long val, alpha, size; |
f56aad3a JS |
508 | unsigned int last_x; |
509 | unsigned int last_y; | |
1c248b7d | 510 | |
e30d4bcf ID |
511 | if (ctx->suspended) |
512 | return; | |
513 | ||
864ee9e6 JS |
514 | if (win == DEFAULT_ZPOS) |
515 | win = ctx->default_win; | |
516 | ||
37b006e8 | 517 | if (win < 0 || win >= WINDOWS_NR) |
1c248b7d ID |
518 | return; |
519 | ||
520 | win_data = &ctx->win_data[win]; | |
521 | ||
522 | /* | |
de7af100 | 523 | * SHADOWCON/PRTCON register is used for enabling timing. |
1c248b7d ID |
524 | * |
525 | * for example, once only width value of a register is set, | |
526 | * if the dma is started then fimd hardware could malfunction so | |
527 | * with protect window setting, the register fields with prefix '_F' | |
528 | * wouldn't be updated at vsync also but updated once unprotect window | |
529 | * is set. | |
530 | */ | |
531 | ||
532 | /* protect windows */ | |
de7af100 | 533 | fimd_shadow_protect_win(ctx, win, true); |
1c248b7d ID |
534 | |
535 | /* buffer start address */ | |
2c871127 | 536 | val = (unsigned long)win_data->dma_addr; |
1c248b7d ID |
537 | writel(val, ctx->regs + VIDWx_BUF_START(win, 0)); |
538 | ||
539 | /* buffer end address */ | |
19c8b834 | 540 | size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3); |
2c871127 | 541 | val = (unsigned long)(win_data->dma_addr + size); |
1c248b7d ID |
542 | writel(val, ctx->regs + VIDWx_BUF_END(win, 0)); |
543 | ||
544 | DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n", | |
2c871127 | 545 | (unsigned long)win_data->dma_addr, val, size); |
19c8b834 ID |
546 | DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", |
547 | win_data->ovl_width, win_data->ovl_height); | |
1c248b7d ID |
548 | |
549 | /* buffer size */ | |
550 | val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) | | |
ca555e5a JS |
551 | VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size) | |
552 | VIDW_BUF_SIZE_OFFSET_E(win_data->buf_offsize) | | |
553 | VIDW_BUF_SIZE_PAGEWIDTH_E(win_data->line_size); | |
1c248b7d ID |
554 | writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0)); |
555 | ||
556 | /* OSD position */ | |
557 | val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) | | |
ca555e5a JS |
558 | VIDOSDxA_TOPLEFT_Y(win_data->offset_y) | |
559 | VIDOSDxA_TOPLEFT_X_E(win_data->offset_x) | | |
560 | VIDOSDxA_TOPLEFT_Y_E(win_data->offset_y); | |
1c248b7d ID |
561 | writel(val, ctx->regs + VIDOSD_A(win)); |
562 | ||
f56aad3a JS |
563 | last_x = win_data->offset_x + win_data->ovl_width; |
564 | if (last_x) | |
565 | last_x--; | |
566 | last_y = win_data->offset_y + win_data->ovl_height; | |
567 | if (last_y) | |
568 | last_y--; | |
569 | ||
ca555e5a JS |
570 | val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) | |
571 | VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y); | |
572 | ||
1c248b7d ID |
573 | writel(val, ctx->regs + VIDOSD_B(win)); |
574 | ||
19c8b834 | 575 | DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", |
f56aad3a | 576 | win_data->offset_x, win_data->offset_y, last_x, last_y); |
1c248b7d ID |
577 | |
578 | /* hardware window 0 doesn't support alpha channel. */ | |
579 | if (win != 0) { | |
580 | /* OSD alpha */ | |
581 | alpha = VIDISD14C_ALPHA1_R(0xf) | | |
582 | VIDISD14C_ALPHA1_G(0xf) | | |
583 | VIDISD14C_ALPHA1_B(0xf); | |
584 | ||
585 | writel(alpha, ctx->regs + VIDOSD_C(win)); | |
586 | } | |
587 | ||
588 | /* OSD size */ | |
589 | if (win != 3 && win != 4) { | |
590 | u32 offset = VIDOSD_D(win); | |
591 | if (win == 0) | |
0f10cf14 | 592 | offset = VIDOSD_C(win); |
19c8b834 | 593 | val = win_data->ovl_width * win_data->ovl_height; |
1c248b7d ID |
594 | writel(val, ctx->regs + offset); |
595 | ||
596 | DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val); | |
597 | } | |
598 | ||
bb7704d6 | 599 | fimd_win_set_pixfmt(ctx, win); |
1c248b7d ID |
600 | |
601 | /* hardware window 0 doesn't support color key. */ | |
602 | if (win != 0) | |
bb7704d6 | 603 | fimd_win_set_colkey(ctx, win); |
1c248b7d | 604 | |
ec05da95 ID |
605 | /* wincon */ |
606 | val = readl(ctx->regs + WINCON(win)); | |
607 | val |= WINCONx_ENWIN; | |
608 | writel(val, ctx->regs + WINCON(win)); | |
609 | ||
1c248b7d | 610 | /* Enable DMA channel and unprotect windows */ |
de7af100 TF |
611 | fimd_shadow_protect_win(ctx, win, false); |
612 | ||
613 | if (ctx->driver_data->has_shadowcon) { | |
614 | val = readl(ctx->regs + SHADOWCON); | |
615 | val |= SHADOWCON_CHx_ENABLE(win); | |
616 | writel(val, ctx->regs + SHADOWCON); | |
617 | } | |
ec05da95 ID |
618 | |
619 | win_data->enabled = true; | |
1c248b7d ID |
620 | } |
621 | ||
bb7704d6 | 622 | static void fimd_win_disable(struct exynos_drm_manager *mgr, int zpos) |
1c248b7d | 623 | { |
bb7704d6 | 624 | struct fimd_context *ctx = mgr->ctx; |
ec05da95 | 625 | struct fimd_win_data *win_data; |
864ee9e6 | 626 | int win = zpos; |
1c248b7d ID |
627 | u32 val; |
628 | ||
864ee9e6 JS |
629 | if (win == DEFAULT_ZPOS) |
630 | win = ctx->default_win; | |
631 | ||
37b006e8 | 632 | if (win < 0 || win >= WINDOWS_NR) |
1c248b7d ID |
633 | return; |
634 | ||
ec05da95 ID |
635 | win_data = &ctx->win_data[win]; |
636 | ||
db7e55ae P |
637 | if (ctx->suspended) { |
638 | /* do not resume this window*/ | |
639 | win_data->resume = false; | |
640 | return; | |
641 | } | |
642 | ||
1c248b7d | 643 | /* protect windows */ |
de7af100 | 644 | fimd_shadow_protect_win(ctx, win, true); |
1c248b7d ID |
645 | |
646 | /* wincon */ | |
647 | val = readl(ctx->regs + WINCON(win)); | |
648 | val &= ~WINCONx_ENWIN; | |
649 | writel(val, ctx->regs + WINCON(win)); | |
650 | ||
651 | /* unprotect windows */ | |
de7af100 TF |
652 | if (ctx->driver_data->has_shadowcon) { |
653 | val = readl(ctx->regs + SHADOWCON); | |
654 | val &= ~SHADOWCON_CHx_ENABLE(win); | |
655 | writel(val, ctx->regs + SHADOWCON); | |
656 | } | |
657 | ||
658 | fimd_shadow_protect_win(ctx, win, false); | |
ec05da95 ID |
659 | |
660 | win_data->enabled = false; | |
1c248b7d ID |
661 | } |
662 | ||
080be03d SP |
663 | static void fimd_dpms(struct exynos_drm_manager *mgr, int mode) |
664 | { | |
665 | struct fimd_context *ctx = mgr->ctx; | |
666 | ||
667 | DRM_DEBUG_KMS("%d\n", mode); | |
668 | ||
080be03d SP |
669 | switch (mode) { |
670 | case DRM_MODE_DPMS_ON: | |
671 | /* | |
672 | * enable fimd hardware only if suspended status. | |
673 | * | |
674 | * P.S. fimd_dpms function would be called at booting time so | |
675 | * clk_enable could be called double time. | |
676 | */ | |
677 | if (ctx->suspended) | |
678 | pm_runtime_get_sync(ctx->dev); | |
679 | break; | |
680 | case DRM_MODE_DPMS_STANDBY: | |
681 | case DRM_MODE_DPMS_SUSPEND: | |
682 | case DRM_MODE_DPMS_OFF: | |
683 | if (!ctx->suspended) | |
684 | pm_runtime_put_sync(ctx->dev); | |
685 | break; | |
686 | default: | |
687 | DRM_DEBUG_KMS("unspecified mode %d\n", mode); | |
688 | break; | |
689 | } | |
080be03d SP |
690 | } |
691 | ||
1c6244c3 | 692 | static struct exynos_drm_manager_ops fimd_manager_ops = { |
40c8ab4b | 693 | .initialize = fimd_mgr_initialize, |
080be03d | 694 | .remove = fimd_mgr_remove, |
1c6244c3 | 695 | .dpms = fimd_dpms, |
a968e727 SP |
696 | .mode_fixup = fimd_mode_fixup, |
697 | .mode_set = fimd_mode_set, | |
1c6244c3 SP |
698 | .commit = fimd_commit, |
699 | .enable_vblank = fimd_enable_vblank, | |
700 | .disable_vblank = fimd_disable_vblank, | |
701 | .wait_for_vblank = fimd_wait_for_vblank, | |
702 | .win_mode_set = fimd_win_mode_set, | |
703 | .win_commit = fimd_win_commit, | |
704 | .win_disable = fimd_win_disable, | |
1c248b7d ID |
705 | }; |
706 | ||
677e84c1 | 707 | static struct exynos_drm_manager fimd_manager = { |
080be03d SP |
708 | .type = EXYNOS_DISPLAY_TYPE_LCD, |
709 | .ops = &fimd_manager_ops, | |
677e84c1 JS |
710 | }; |
711 | ||
1c248b7d ID |
712 | static irqreturn_t fimd_irq_handler(int irq, void *dev_id) |
713 | { | |
714 | struct fimd_context *ctx = (struct fimd_context *)dev_id; | |
1c248b7d ID |
715 | u32 val; |
716 | ||
717 | val = readl(ctx->regs + VIDINTCON1); | |
718 | ||
719 | if (val & VIDINTCON1_INT_FRAME) | |
720 | /* VSYNC interrupt */ | |
721 | writel(VIDINTCON1_INT_FRAME, ctx->regs + VIDINTCON1); | |
722 | ||
ec05da95 | 723 | /* check the crtc is detached already from encoder */ |
080be03d | 724 | if (ctx->pipe < 0 || !ctx->drm_dev) |
ec05da95 | 725 | goto out; |
483b88f8 | 726 | |
080be03d SP |
727 | drm_handle_vblank(ctx->drm_dev, ctx->pipe); |
728 | exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe); | |
1c248b7d | 729 | |
01ce113c P |
730 | /* set wait vsync event to zero and wake up queue. */ |
731 | if (atomic_read(&ctx->wait_vsync_event)) { | |
732 | atomic_set(&ctx->wait_vsync_event, 0); | |
8dd9ad5d | 733 | wake_up(&ctx->wait_vsync_queue); |
01ce113c | 734 | } |
ec05da95 | 735 | out: |
1c248b7d ID |
736 | return IRQ_HANDLED; |
737 | } | |
738 | ||
1c248b7d ID |
739 | static void fimd_clear_win(struct fimd_context *ctx, int win) |
740 | { | |
1c248b7d ID |
741 | writel(0, ctx->regs + WINCON(win)); |
742 | writel(0, ctx->regs + VIDOSD_A(win)); | |
743 | writel(0, ctx->regs + VIDOSD_B(win)); | |
744 | writel(0, ctx->regs + VIDOSD_C(win)); | |
745 | ||
746 | if (win == 1 || win == 2) | |
747 | writel(0, ctx->regs + VIDOSD_D(win)); | |
748 | ||
de7af100 | 749 | fimd_shadow_protect_win(ctx, win, false); |
1c248b7d ID |
750 | } |
751 | ||
5d55393a | 752 | static int fimd_clock(struct fimd_context *ctx, bool enable) |
373af0c0 | 753 | { |
373af0c0 ID |
754 | if (enable) { |
755 | int ret; | |
756 | ||
11963a63 | 757 | ret = clk_prepare_enable(ctx->bus_clk); |
373af0c0 ID |
758 | if (ret < 0) |
759 | return ret; | |
760 | ||
11963a63 | 761 | ret = clk_prepare_enable(ctx->lcd_clk); |
373af0c0 | 762 | if (ret < 0) { |
11963a63 | 763 | clk_disable_unprepare(ctx->bus_clk); |
373af0c0 ID |
764 | return ret; |
765 | } | |
5d55393a | 766 | } else { |
11963a63 VS |
767 | clk_disable_unprepare(ctx->lcd_clk); |
768 | clk_disable_unprepare(ctx->bus_clk); | |
5d55393a ID |
769 | } |
770 | ||
771 | return 0; | |
772 | } | |
773 | ||
080be03d | 774 | static void fimd_window_suspend(struct exynos_drm_manager *mgr) |
db7e55ae | 775 | { |
bb7704d6 | 776 | struct fimd_context *ctx = mgr->ctx; |
db7e55ae P |
777 | struct fimd_win_data *win_data; |
778 | int i; | |
779 | ||
780 | for (i = 0; i < WINDOWS_NR; i++) { | |
781 | win_data = &ctx->win_data[i]; | |
782 | win_data->resume = win_data->enabled; | |
bb7704d6 | 783 | fimd_win_disable(mgr, i); |
db7e55ae | 784 | } |
bb7704d6 | 785 | fimd_wait_for_vblank(mgr); |
db7e55ae P |
786 | } |
787 | ||
080be03d | 788 | static void fimd_window_resume(struct exynos_drm_manager *mgr) |
db7e55ae | 789 | { |
bb7704d6 | 790 | struct fimd_context *ctx = mgr->ctx; |
db7e55ae P |
791 | struct fimd_win_data *win_data; |
792 | int i; | |
793 | ||
794 | for (i = 0; i < WINDOWS_NR; i++) { | |
795 | win_data = &ctx->win_data[i]; | |
796 | win_data->enabled = win_data->resume; | |
797 | win_data->resume = false; | |
798 | } | |
799 | } | |
800 | ||
080be03d SP |
801 | static void fimd_apply(struct exynos_drm_manager *mgr) |
802 | { | |
803 | struct fimd_context *ctx = mgr->ctx; | |
804 | struct fimd_win_data *win_data; | |
805 | int i; | |
806 | ||
807 | for (i = 0; i < WINDOWS_NR; i++) { | |
808 | win_data = &ctx->win_data[i]; | |
809 | if (win_data->enabled) | |
810 | fimd_win_commit(mgr, i); | |
811 | } | |
812 | ||
813 | fimd_commit(mgr); | |
814 | } | |
815 | ||
bb7704d6 | 816 | static int fimd_activate(struct exynos_drm_manager *mgr, bool enable) |
5d55393a | 817 | { |
bb7704d6 | 818 | struct fimd_context *ctx = mgr->ctx; |
bb7704d6 | 819 | |
5d55393a ID |
820 | if (enable) { |
821 | int ret; | |
5d55393a ID |
822 | |
823 | ret = fimd_clock(ctx, true); | |
824 | if (ret < 0) | |
825 | return ret; | |
373af0c0 ID |
826 | |
827 | ctx->suspended = false; | |
828 | ||
829 | /* if vblank was enabled status, enable it again. */ | |
830 | if (test_and_clear_bit(0, &ctx->irq_flags)) | |
bb7704d6 | 831 | fimd_enable_vblank(mgr); |
db7e55ae | 832 | |
080be03d | 833 | fimd_window_resume(mgr); |
87244fa6 SP |
834 | |
835 | fimd_apply(mgr); | |
373af0c0 | 836 | } else { |
080be03d | 837 | fimd_window_suspend(mgr); |
db7e55ae | 838 | |
5d55393a | 839 | fimd_clock(ctx, false); |
373af0c0 ID |
840 | ctx->suspended = true; |
841 | } | |
842 | ||
843 | return 0; | |
844 | } | |
845 | ||
562ad9f4 AH |
846 | static int fimd_probe(struct platform_device *pdev) |
847 | { | |
848 | struct device *dev = &pdev->dev; | |
849 | struct fimd_context *ctx; | |
562ad9f4 AH |
850 | struct resource *res; |
851 | int win; | |
852 | int ret = -EINVAL; | |
1c248b7d | 853 | |
2d3f173c SK |
854 | if (!dev->of_node) |
855 | return -ENODEV; | |
856 | ||
d873ab99 | 857 | ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); |
1c248b7d ID |
858 | if (!ctx) |
859 | return -ENOMEM; | |
860 | ||
bb7704d6 SP |
861 | ctx->dev = dev; |
862 | ||
1417f109 SP |
863 | if (of_property_read_bool(dev->of_node, "samsung,invert-vden")) |
864 | ctx->vidcon1 |= VIDCON1_INV_VDEN; | |
865 | if (of_property_read_bool(dev->of_node, "samsung,invert-vclk")) | |
866 | ctx->vidcon1 |= VIDCON1_INV_VCLK; | |
562ad9f4 | 867 | |
a968e727 SP |
868 | ctx->bus_clk = devm_clk_get(dev, "fimd"); |
869 | if (IS_ERR(ctx->bus_clk)) { | |
870 | dev_err(dev, "failed to get bus clock\n"); | |
871 | return PTR_ERR(ctx->bus_clk); | |
872 | } | |
873 | ||
874 | ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd"); | |
875 | if (IS_ERR(ctx->lcd_clk)) { | |
876 | dev_err(dev, "failed to get lcd clock\n"); | |
877 | return PTR_ERR(ctx->lcd_clk); | |
878 | } | |
1c248b7d | 879 | |
1c248b7d | 880 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1c248b7d | 881 | |
d873ab99 | 882 | ctx->regs = devm_ioremap_resource(dev, res); |
d4ed6025 TR |
883 | if (IS_ERR(ctx->regs)) |
884 | return PTR_ERR(ctx->regs); | |
1c248b7d | 885 | |
1977e6d8 | 886 | res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "vsync"); |
1c248b7d ID |
887 | if (!res) { |
888 | dev_err(dev, "irq request failed.\n"); | |
a4d8de5f | 889 | return -ENXIO; |
1c248b7d ID |
890 | } |
891 | ||
055e0c06 | 892 | ret = devm_request_irq(dev, res->start, fimd_irq_handler, |
edc57266 SK |
893 | 0, "drm_fimd", ctx); |
894 | if (ret) { | |
1c248b7d | 895 | dev_err(dev, "irq request failed.\n"); |
a4d8de5f | 896 | return ret; |
1c248b7d ID |
897 | } |
898 | ||
18873465 | 899 | ctx->driver_data = drm_fimd_get_driver_data(pdev); |
57ed0f7b | 900 | init_waitqueue_head(&ctx->wait_vsync_queue); |
01ce113c | 901 | atomic_set(&ctx->wait_vsync_event, 0); |
1c248b7d | 902 | |
bb7704d6 | 903 | platform_set_drvdata(pdev, &fimd_manager); |
c32b06ef | 904 | |
080be03d SP |
905 | fimd_manager.ctx = ctx; |
906 | exynos_drm_manager_register(&fimd_manager); | |
907 | ||
c32b06ef ID |
908 | pm_runtime_enable(dev); |
909 | pm_runtime_get_sync(dev); | |
910 | ||
911 | for (win = 0; win < WINDOWS_NR; win++) | |
912 | fimd_clear_win(ctx, win); | |
913 | ||
1c248b7d | 914 | return 0; |
1c248b7d ID |
915 | } |
916 | ||
56550d94 | 917 | static int fimd_remove(struct platform_device *pdev) |
1c248b7d | 918 | { |
cb91f6a0 | 919 | struct device *dev = &pdev->dev; |
bb7704d6 SP |
920 | struct exynos_drm_manager *mgr = platform_get_drvdata(pdev); |
921 | struct fimd_context *ctx = mgr->ctx; | |
1c248b7d | 922 | |
080be03d | 923 | exynos_drm_manager_unregister(&fimd_manager); |
1c248b7d | 924 | |
cb91f6a0 JS |
925 | if (ctx->suspended) |
926 | goto out; | |
927 | ||
cb91f6a0 JS |
928 | pm_runtime_set_suspended(dev); |
929 | pm_runtime_put_sync(dev); | |
930 | ||
931 | out: | |
932 | pm_runtime_disable(dev); | |
933 | ||
1c248b7d ID |
934 | return 0; |
935 | } | |
936 | ||
e30d4bcf ID |
937 | #ifdef CONFIG_PM_SLEEP |
938 | static int fimd_suspend(struct device *dev) | |
939 | { | |
bb7704d6 | 940 | struct exynos_drm_manager *mgr = get_fimd_manager(dev); |
e30d4bcf | 941 | |
373af0c0 ID |
942 | /* |
943 | * do not use pm_runtime_suspend(). if pm_runtime_suspend() is | |
944 | * called here, an error would be returned by that interface | |
945 | * because the usage_count of pm runtime is more than 1. | |
946 | */ | |
5d55393a | 947 | if (!pm_runtime_suspended(dev)) |
bb7704d6 | 948 | return fimd_activate(mgr, false); |
5d55393a ID |
949 | |
950 | return 0; | |
e30d4bcf ID |
951 | } |
952 | ||
953 | static int fimd_resume(struct device *dev) | |
954 | { | |
bb7704d6 | 955 | struct exynos_drm_manager *mgr = get_fimd_manager(dev); |
e30d4bcf | 956 | |
373af0c0 ID |
957 | /* |
958 | * if entered to sleep when lcd panel was on, the usage_count | |
959 | * of pm runtime would still be 1 so in this case, fimd driver | |
960 | * should be on directly not drawing on pm runtime interface. | |
961 | */ | |
87244fa6 SP |
962 | if (pm_runtime_suspended(dev)) |
963 | return 0; | |
5d55393a | 964 | |
87244fa6 | 965 | return fimd_activate(mgr, true); |
e30d4bcf ID |
966 | } |
967 | #endif | |
968 | ||
cb91f6a0 JS |
969 | #ifdef CONFIG_PM_RUNTIME |
970 | static int fimd_runtime_suspend(struct device *dev) | |
971 | { | |
bb7704d6 | 972 | struct exynos_drm_manager *mgr = get_fimd_manager(dev); |
cb91f6a0 | 973 | |
bb7704d6 | 974 | return fimd_activate(mgr, false); |
cb91f6a0 JS |
975 | } |
976 | ||
977 | static int fimd_runtime_resume(struct device *dev) | |
978 | { | |
bb7704d6 | 979 | struct exynos_drm_manager *mgr = get_fimd_manager(dev); |
cb91f6a0 | 980 | |
bb7704d6 | 981 | return fimd_activate(mgr, true); |
cb91f6a0 JS |
982 | } |
983 | #endif | |
984 | ||
985 | static const struct dev_pm_ops fimd_pm_ops = { | |
e30d4bcf | 986 | SET_SYSTEM_SLEEP_PM_OPS(fimd_suspend, fimd_resume) |
cb91f6a0 JS |
987 | SET_RUNTIME_PM_OPS(fimd_runtime_suspend, fimd_runtime_resume, NULL) |
988 | }; | |
989 | ||
132a5b91 | 990 | struct platform_driver fimd_driver = { |
1c248b7d | 991 | .probe = fimd_probe, |
56550d94 | 992 | .remove = fimd_remove, |
1c248b7d ID |
993 | .driver = { |
994 | .name = "exynos4-fb", | |
995 | .owner = THIS_MODULE, | |
cb91f6a0 | 996 | .pm = &fimd_pm_ops, |
2d3f173c | 997 | .of_match_table = fimd_driver_dt_match, |
1c248b7d ID |
998 | }, |
999 | }; |