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Commit | Line | Data |
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1c248b7d ID |
1 | /* exynos_drm_fimd.c |
2 | * | |
3 | * Copyright (C) 2011 Samsung Electronics Co.Ltd | |
4 | * Authors: | |
5 | * Joonyoung Shim <jy0922.shim@samsung.com> | |
6 | * Inki Dae <inki.dae@samsung.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | */ | |
760285e7 | 14 | #include <drm/drmP.h> |
1c248b7d ID |
15 | |
16 | #include <linux/kernel.h> | |
1c248b7d ID |
17 | #include <linux/platform_device.h> |
18 | #include <linux/clk.h> | |
3f1c781d | 19 | #include <linux/of.h> |
d636ead8 | 20 | #include <linux/of_device.h> |
cb91f6a0 | 21 | #include <linux/pm_runtime.h> |
1c248b7d | 22 | |
7f4596f4 | 23 | #include <video/of_display_timing.h> |
111e6055 | 24 | #include <video/of_videomode.h> |
5a213a55 | 25 | #include <video/samsung_fimd.h> |
1c248b7d | 26 | #include <drm/exynos_drm.h> |
1c248b7d ID |
27 | |
28 | #include "exynos_drm_drv.h" | |
29 | #include "exynos_drm_fbdev.h" | |
30 | #include "exynos_drm_crtc.h" | |
bcc5cd1c | 31 | #include "exynos_drm_iommu.h" |
1c248b7d ID |
32 | |
33 | /* | |
b8654b37 | 34 | * FIMD stands for Fully Interactive Mobile Display and |
1c248b7d ID |
35 | * as a display controller, it transfers contents drawn on memory |
36 | * to a LCD Panel through Display Interfaces such as RGB or | |
37 | * CPU Interface. | |
38 | */ | |
39 | ||
111e6055 AH |
40 | #define FIMD_DEFAULT_FRAMERATE 60 |
41 | ||
1c248b7d ID |
42 | /* position control register for hardware window 0, 2 ~ 4.*/ |
43 | #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16) | |
44 | #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16) | |
0f10cf14 LKA |
45 | /* |
46 | * size control register for hardware windows 0 and alpha control register | |
47 | * for hardware windows 1 ~ 4 | |
48 | */ | |
49 | #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16) | |
50 | /* size control register for hardware windows 1 ~ 2. */ | |
1c248b7d ID |
51 | #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16) |
52 | ||
53 | #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8) | |
54 | #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8) | |
55 | #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4) | |
56 | ||
57 | /* color key control register for hardware window 1 ~ 4. */ | |
0f10cf14 | 58 | #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8)) |
1c248b7d | 59 | /* color key value register for hardware window 1 ~ 4. */ |
0f10cf14 | 60 | #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8)) |
1c248b7d ID |
61 | |
62 | /* FIMD has totally five hardware windows. */ | |
63 | #define WINDOWS_NR 5 | |
64 | ||
65 | #define get_fimd_context(dev) platform_get_drvdata(to_platform_device(dev)) | |
66 | ||
e2e13389 LKA |
67 | struct fimd_driver_data { |
68 | unsigned int timing_base; | |
de7af100 TF |
69 | |
70 | unsigned int has_shadowcon:1; | |
411d9ed4 | 71 | unsigned int has_clksel:1; |
5cc4621a | 72 | unsigned int has_limited_fmt:1; |
e2e13389 LKA |
73 | }; |
74 | ||
725ddead TF |
75 | static struct fimd_driver_data s3c64xx_fimd_driver_data = { |
76 | .timing_base = 0x0, | |
77 | .has_clksel = 1, | |
5cc4621a | 78 | .has_limited_fmt = 1, |
725ddead TF |
79 | }; |
80 | ||
6ecf18f9 | 81 | static struct fimd_driver_data exynos4_fimd_driver_data = { |
e2e13389 | 82 | .timing_base = 0x0, |
de7af100 | 83 | .has_shadowcon = 1, |
e2e13389 LKA |
84 | }; |
85 | ||
6ecf18f9 | 86 | static struct fimd_driver_data exynos5_fimd_driver_data = { |
e2e13389 | 87 | .timing_base = 0x20000, |
de7af100 | 88 | .has_shadowcon = 1, |
e2e13389 LKA |
89 | }; |
90 | ||
1c248b7d ID |
91 | struct fimd_win_data { |
92 | unsigned int offset_x; | |
93 | unsigned int offset_y; | |
19c8b834 ID |
94 | unsigned int ovl_width; |
95 | unsigned int ovl_height; | |
96 | unsigned int fb_width; | |
97 | unsigned int fb_height; | |
1c248b7d | 98 | unsigned int bpp; |
a4f38a80 | 99 | unsigned int pixel_format; |
2c871127 | 100 | dma_addr_t dma_addr; |
1c248b7d ID |
101 | unsigned int buf_offsize; |
102 | unsigned int line_size; /* bytes */ | |
ec05da95 | 103 | bool enabled; |
db7e55ae | 104 | bool resume; |
1c248b7d ID |
105 | }; |
106 | ||
107 | struct fimd_context { | |
108 | struct exynos_drm_subdrv subdrv; | |
109 | int irq; | |
110 | struct drm_crtc *crtc; | |
111 | struct clk *bus_clk; | |
112 | struct clk *lcd_clk; | |
1c248b7d ID |
113 | void __iomem *regs; |
114 | struct fimd_win_data win_data[WINDOWS_NR]; | |
115 | unsigned int clkdiv; | |
116 | unsigned int default_win; | |
117 | unsigned long irq_flags; | |
118 | u32 vidcon0; | |
119 | u32 vidcon1; | |
cb91f6a0 | 120 | bool suspended; |
c32b06ef | 121 | struct mutex lock; |
01ce113c P |
122 | wait_queue_head_t wait_vsync_queue; |
123 | atomic_t wait_vsync_event; | |
1c248b7d | 124 | |
562ad9f4 | 125 | struct exynos_drm_panel_info panel; |
18873465 | 126 | struct fimd_driver_data *driver_data; |
1c248b7d ID |
127 | }; |
128 | ||
d636ead8 | 129 | static const struct of_device_id fimd_driver_dt_match[] = { |
725ddead TF |
130 | { .compatible = "samsung,s3c6400-fimd", |
131 | .data = &s3c64xx_fimd_driver_data }, | |
5830daf8 | 132 | { .compatible = "samsung,exynos4210-fimd", |
d636ead8 | 133 | .data = &exynos4_fimd_driver_data }, |
5830daf8 | 134 | { .compatible = "samsung,exynos5250-fimd", |
d636ead8 JS |
135 | .data = &exynos5_fimd_driver_data }, |
136 | {}, | |
137 | }; | |
d636ead8 | 138 | |
e2e13389 LKA |
139 | static inline struct fimd_driver_data *drm_fimd_get_driver_data( |
140 | struct platform_device *pdev) | |
141 | { | |
d636ead8 JS |
142 | const struct of_device_id *of_id = |
143 | of_match_device(fimd_driver_dt_match, &pdev->dev); | |
144 | ||
2d3f173c | 145 | return (struct fimd_driver_data *)of_id->data; |
e2e13389 LKA |
146 | } |
147 | ||
1c248b7d ID |
148 | static bool fimd_display_is_connected(struct device *dev) |
149 | { | |
1c248b7d ID |
150 | /* TODO. */ |
151 | ||
152 | return true; | |
153 | } | |
154 | ||
607c50d4 | 155 | static void *fimd_get_panel(struct device *dev) |
1c248b7d ID |
156 | { |
157 | struct fimd_context *ctx = get_fimd_context(dev); | |
158 | ||
562ad9f4 | 159 | return &ctx->panel; |
1c248b7d ID |
160 | } |
161 | ||
16844fb1 | 162 | static int fimd_check_mode(struct device *dev, struct drm_display_mode *mode) |
1c248b7d | 163 | { |
1c248b7d ID |
164 | /* TODO. */ |
165 | ||
166 | return 0; | |
167 | } | |
168 | ||
169 | static int fimd_display_power_on(struct device *dev, int mode) | |
170 | { | |
ec05da95 | 171 | /* TODO */ |
1c248b7d ID |
172 | |
173 | return 0; | |
174 | } | |
175 | ||
74ccc539 | 176 | static struct exynos_drm_display_ops fimd_display_ops = { |
1c248b7d ID |
177 | .type = EXYNOS_DISPLAY_TYPE_LCD, |
178 | .is_connected = fimd_display_is_connected, | |
607c50d4 | 179 | .get_panel = fimd_get_panel, |
16844fb1 | 180 | .check_mode = fimd_check_mode, |
1c248b7d ID |
181 | .power_on = fimd_display_power_on, |
182 | }; | |
183 | ||
ec05da95 ID |
184 | static void fimd_dpms(struct device *subdrv_dev, int mode) |
185 | { | |
c32b06ef ID |
186 | struct fimd_context *ctx = get_fimd_context(subdrv_dev); |
187 | ||
bca34c9a | 188 | DRM_DEBUG_KMS("%d\n", mode); |
ec05da95 | 189 | |
c32b06ef ID |
190 | mutex_lock(&ctx->lock); |
191 | ||
cb91f6a0 JS |
192 | switch (mode) { |
193 | case DRM_MODE_DPMS_ON: | |
c32b06ef ID |
194 | /* |
195 | * enable fimd hardware only if suspended status. | |
196 | * | |
197 | * P.S. fimd_dpms function would be called at booting time so | |
198 | * clk_enable could be called double time. | |
199 | */ | |
200 | if (ctx->suspended) | |
201 | pm_runtime_get_sync(subdrv_dev); | |
cb91f6a0 JS |
202 | break; |
203 | case DRM_MODE_DPMS_STANDBY: | |
204 | case DRM_MODE_DPMS_SUSPEND: | |
205 | case DRM_MODE_DPMS_OFF: | |
373af0c0 ID |
206 | if (!ctx->suspended) |
207 | pm_runtime_put_sync(subdrv_dev); | |
cb91f6a0 JS |
208 | break; |
209 | default: | |
210 | DRM_DEBUG_KMS("unspecified mode %d\n", mode); | |
211 | break; | |
212 | } | |
c32b06ef ID |
213 | |
214 | mutex_unlock(&ctx->lock); | |
ec05da95 ID |
215 | } |
216 | ||
217 | static void fimd_apply(struct device *subdrv_dev) | |
218 | { | |
219 | struct fimd_context *ctx = get_fimd_context(subdrv_dev); | |
677e84c1 | 220 | struct exynos_drm_manager *mgr = ctx->subdrv.manager; |
ec05da95 ID |
221 | struct exynos_drm_manager_ops *mgr_ops = mgr->ops; |
222 | struct exynos_drm_overlay_ops *ovl_ops = mgr->overlay_ops; | |
223 | struct fimd_win_data *win_data; | |
864ee9e6 | 224 | int i; |
ec05da95 | 225 | |
864ee9e6 JS |
226 | for (i = 0; i < WINDOWS_NR; i++) { |
227 | win_data = &ctx->win_data[i]; | |
228 | if (win_data->enabled && (ovl_ops && ovl_ops->commit)) | |
229 | ovl_ops->commit(subdrv_dev, i); | |
230 | } | |
ec05da95 ID |
231 | |
232 | if (mgr_ops && mgr_ops->commit) | |
233 | mgr_ops->commit(subdrv_dev); | |
234 | } | |
235 | ||
1c248b7d ID |
236 | static void fimd_commit(struct device *dev) |
237 | { | |
238 | struct fimd_context *ctx = get_fimd_context(dev); | |
562ad9f4 | 239 | struct exynos_drm_panel_info *panel = &ctx->panel; |
111e6055 | 240 | struct videomode *vm = &panel->vm; |
e2e13389 | 241 | struct fimd_driver_data *driver_data; |
1c248b7d ID |
242 | u32 val; |
243 | ||
18873465 | 244 | driver_data = ctx->driver_data; |
e30d4bcf ID |
245 | if (ctx->suspended) |
246 | return; | |
247 | ||
1c248b7d | 248 | /* setup polarity values from machine code. */ |
e2e13389 | 249 | writel(ctx->vidcon1, ctx->regs + driver_data->timing_base + VIDCON1); |
1c248b7d ID |
250 | |
251 | /* setup vertical timing values. */ | |
111e6055 AH |
252 | val = VIDTCON0_VBPD(vm->vback_porch - 1) | |
253 | VIDTCON0_VFPD(vm->vfront_porch - 1) | | |
254 | VIDTCON0_VSPW(vm->vsync_len - 1); | |
e2e13389 | 255 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON0); |
1c248b7d ID |
256 | |
257 | /* setup horizontal timing values. */ | |
111e6055 AH |
258 | val = VIDTCON1_HBPD(vm->hback_porch - 1) | |
259 | VIDTCON1_HFPD(vm->hfront_porch - 1) | | |
260 | VIDTCON1_HSPW(vm->hsync_len - 1); | |
e2e13389 | 261 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON1); |
1c248b7d ID |
262 | |
263 | /* setup horizontal and vertical display size. */ | |
111e6055 AH |
264 | val = VIDTCON2_LINEVAL(vm->vactive - 1) | |
265 | VIDTCON2_HOZVAL(vm->hactive - 1) | | |
266 | VIDTCON2_LINEVAL_E(vm->vactive - 1) | | |
267 | VIDTCON2_HOZVAL_E(vm->hactive - 1); | |
e2e13389 | 268 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON2); |
1c248b7d ID |
269 | |
270 | /* setup clock source, clock divider, enable dma. */ | |
271 | val = ctx->vidcon0; | |
272 | val &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR); | |
273 | ||
411d9ed4 TF |
274 | if (ctx->driver_data->has_clksel) { |
275 | val &= ~VIDCON0_CLKSEL_MASK; | |
276 | val |= VIDCON0_CLKSEL_LCD; | |
277 | } | |
278 | ||
1c248b7d ID |
279 | if (ctx->clkdiv > 1) |
280 | val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR; | |
281 | else | |
282 | val &= ~VIDCON0_CLKDIR; /* 1:1 clock */ | |
283 | ||
284 | /* | |
285 | * fields of register with prefix '_F' would be updated | |
286 | * at vsync(same as dma start) | |
287 | */ | |
288 | val |= VIDCON0_ENVID | VIDCON0_ENVID_F; | |
289 | writel(val, ctx->regs + VIDCON0); | |
290 | } | |
291 | ||
292 | static int fimd_enable_vblank(struct device *dev) | |
293 | { | |
294 | struct fimd_context *ctx = get_fimd_context(dev); | |
295 | u32 val; | |
296 | ||
cb91f6a0 JS |
297 | if (ctx->suspended) |
298 | return -EPERM; | |
299 | ||
1c248b7d ID |
300 | if (!test_and_set_bit(0, &ctx->irq_flags)) { |
301 | val = readl(ctx->regs + VIDINTCON0); | |
302 | ||
303 | val |= VIDINTCON0_INT_ENABLE; | |
304 | val |= VIDINTCON0_INT_FRAME; | |
305 | ||
306 | val &= ~VIDINTCON0_FRAMESEL0_MASK; | |
307 | val |= VIDINTCON0_FRAMESEL0_VSYNC; | |
308 | val &= ~VIDINTCON0_FRAMESEL1_MASK; | |
309 | val |= VIDINTCON0_FRAMESEL1_NONE; | |
310 | ||
311 | writel(val, ctx->regs + VIDINTCON0); | |
312 | } | |
313 | ||
314 | return 0; | |
315 | } | |
316 | ||
317 | static void fimd_disable_vblank(struct device *dev) | |
318 | { | |
319 | struct fimd_context *ctx = get_fimd_context(dev); | |
320 | u32 val; | |
321 | ||
cb91f6a0 JS |
322 | if (ctx->suspended) |
323 | return; | |
324 | ||
1c248b7d ID |
325 | if (test_and_clear_bit(0, &ctx->irq_flags)) { |
326 | val = readl(ctx->regs + VIDINTCON0); | |
327 | ||
328 | val &= ~VIDINTCON0_INT_FRAME; | |
329 | val &= ~VIDINTCON0_INT_ENABLE; | |
330 | ||
331 | writel(val, ctx->regs + VIDINTCON0); | |
332 | } | |
333 | } | |
334 | ||
07033970 P |
335 | static void fimd_wait_for_vblank(struct device *dev) |
336 | { | |
337 | struct fimd_context *ctx = get_fimd_context(dev); | |
07033970 | 338 | |
01ce113c P |
339 | if (ctx->suspended) |
340 | return; | |
341 | ||
342 | atomic_set(&ctx->wait_vsync_event, 1); | |
343 | ||
344 | /* | |
345 | * wait for FIMD to signal VSYNC interrupt or return after | |
346 | * timeout which is set to 50ms (refresh rate of 20). | |
347 | */ | |
348 | if (!wait_event_timeout(ctx->wait_vsync_queue, | |
349 | !atomic_read(&ctx->wait_vsync_event), | |
8dd9ad5d | 350 | HZ/20)) |
07033970 P |
351 | DRM_DEBUG_KMS("vblank wait timed out.\n"); |
352 | } | |
353 | ||
1c248b7d | 354 | static struct exynos_drm_manager_ops fimd_manager_ops = { |
ec05da95 ID |
355 | .dpms = fimd_dpms, |
356 | .apply = fimd_apply, | |
1c248b7d ID |
357 | .commit = fimd_commit, |
358 | .enable_vblank = fimd_enable_vblank, | |
359 | .disable_vblank = fimd_disable_vblank, | |
07033970 | 360 | .wait_for_vblank = fimd_wait_for_vblank, |
1c248b7d ID |
361 | }; |
362 | ||
363 | static void fimd_win_mode_set(struct device *dev, | |
364 | struct exynos_drm_overlay *overlay) | |
365 | { | |
366 | struct fimd_context *ctx = get_fimd_context(dev); | |
367 | struct fimd_win_data *win_data; | |
864ee9e6 | 368 | int win; |
19c8b834 | 369 | unsigned long offset; |
1c248b7d | 370 | |
1c248b7d ID |
371 | if (!overlay) { |
372 | dev_err(dev, "overlay is NULL\n"); | |
373 | return; | |
374 | } | |
375 | ||
864ee9e6 JS |
376 | win = overlay->zpos; |
377 | if (win == DEFAULT_ZPOS) | |
378 | win = ctx->default_win; | |
379 | ||
37b006e8 | 380 | if (win < 0 || win >= WINDOWS_NR) |
864ee9e6 JS |
381 | return; |
382 | ||
19c8b834 ID |
383 | offset = overlay->fb_x * (overlay->bpp >> 3); |
384 | offset += overlay->fb_y * overlay->pitch; | |
385 | ||
386 | DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch); | |
387 | ||
864ee9e6 | 388 | win_data = &ctx->win_data[win]; |
1c248b7d | 389 | |
19c8b834 ID |
390 | win_data->offset_x = overlay->crtc_x; |
391 | win_data->offset_y = overlay->crtc_y; | |
392 | win_data->ovl_width = overlay->crtc_width; | |
393 | win_data->ovl_height = overlay->crtc_height; | |
394 | win_data->fb_width = overlay->fb_width; | |
395 | win_data->fb_height = overlay->fb_height; | |
229d3534 | 396 | win_data->dma_addr = overlay->dma_addr[0] + offset; |
1c248b7d | 397 | win_data->bpp = overlay->bpp; |
a4f38a80 | 398 | win_data->pixel_format = overlay->pixel_format; |
19c8b834 ID |
399 | win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) * |
400 | (overlay->bpp >> 3); | |
401 | win_data->line_size = overlay->crtc_width * (overlay->bpp >> 3); | |
402 | ||
403 | DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n", | |
404 | win_data->offset_x, win_data->offset_y); | |
405 | DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", | |
406 | win_data->ovl_width, win_data->ovl_height); | |
ddd8e959 | 407 | DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data->dma_addr); |
19c8b834 ID |
408 | DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n", |
409 | overlay->fb_width, overlay->crtc_width); | |
1c248b7d ID |
410 | } |
411 | ||
412 | static void fimd_win_set_pixfmt(struct device *dev, unsigned int win) | |
413 | { | |
414 | struct fimd_context *ctx = get_fimd_context(dev); | |
415 | struct fimd_win_data *win_data = &ctx->win_data[win]; | |
416 | unsigned long val; | |
417 | ||
1c248b7d ID |
418 | val = WINCONx_ENWIN; |
419 | ||
5cc4621a ID |
420 | /* |
421 | * In case of s3c64xx, window 0 doesn't support alpha channel. | |
422 | * So the request format is ARGB8888 then change it to XRGB8888. | |
423 | */ | |
424 | if (ctx->driver_data->has_limited_fmt && !win) { | |
425 | if (win_data->pixel_format == DRM_FORMAT_ARGB8888) | |
426 | win_data->pixel_format = DRM_FORMAT_XRGB8888; | |
427 | } | |
428 | ||
a4f38a80 ID |
429 | switch (win_data->pixel_format) { |
430 | case DRM_FORMAT_C8: | |
1c248b7d ID |
431 | val |= WINCON0_BPPMODE_8BPP_PALETTE; |
432 | val |= WINCONx_BURSTLEN_8WORD; | |
433 | val |= WINCONx_BYTSWP; | |
434 | break; | |
a4f38a80 ID |
435 | case DRM_FORMAT_XRGB1555: |
436 | val |= WINCON0_BPPMODE_16BPP_1555; | |
437 | val |= WINCONx_HAWSWP; | |
438 | val |= WINCONx_BURSTLEN_16WORD; | |
439 | break; | |
440 | case DRM_FORMAT_RGB565: | |
1c248b7d ID |
441 | val |= WINCON0_BPPMODE_16BPP_565; |
442 | val |= WINCONx_HAWSWP; | |
443 | val |= WINCONx_BURSTLEN_16WORD; | |
444 | break; | |
a4f38a80 | 445 | case DRM_FORMAT_XRGB8888: |
1c248b7d ID |
446 | val |= WINCON0_BPPMODE_24BPP_888; |
447 | val |= WINCONx_WSWP; | |
448 | val |= WINCONx_BURSTLEN_16WORD; | |
449 | break; | |
a4f38a80 ID |
450 | case DRM_FORMAT_ARGB8888: |
451 | val |= WINCON1_BPPMODE_25BPP_A1888 | |
1c248b7d ID |
452 | | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL; |
453 | val |= WINCONx_WSWP; | |
454 | val |= WINCONx_BURSTLEN_16WORD; | |
455 | break; | |
456 | default: | |
457 | DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n"); | |
458 | ||
459 | val |= WINCON0_BPPMODE_24BPP_888; | |
460 | val |= WINCONx_WSWP; | |
461 | val |= WINCONx_BURSTLEN_16WORD; | |
462 | break; | |
463 | } | |
464 | ||
465 | DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp); | |
466 | ||
467 | writel(val, ctx->regs + WINCON(win)); | |
468 | } | |
469 | ||
470 | static void fimd_win_set_colkey(struct device *dev, unsigned int win) | |
471 | { | |
472 | struct fimd_context *ctx = get_fimd_context(dev); | |
473 | unsigned int keycon0 = 0, keycon1 = 0; | |
474 | ||
1c248b7d ID |
475 | keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F | |
476 | WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); | |
477 | ||
478 | keycon1 = WxKEYCON1_COLVAL(0xffffffff); | |
479 | ||
480 | writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); | |
481 | writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); | |
482 | } | |
483 | ||
de7af100 TF |
484 | /** |
485 | * shadow_protect_win() - disable updating values from shadow registers at vsync | |
486 | * | |
487 | * @win: window to protect registers for | |
488 | * @protect: 1 to protect (disable updates) | |
489 | */ | |
490 | static void fimd_shadow_protect_win(struct fimd_context *ctx, | |
491 | int win, bool protect) | |
492 | { | |
493 | u32 reg, bits, val; | |
494 | ||
495 | if (ctx->driver_data->has_shadowcon) { | |
496 | reg = SHADOWCON; | |
497 | bits = SHADOWCON_WINx_PROTECT(win); | |
498 | } else { | |
499 | reg = PRTCON; | |
500 | bits = PRTCON_PROTECT; | |
501 | } | |
502 | ||
503 | val = readl(ctx->regs + reg); | |
504 | if (protect) | |
505 | val |= bits; | |
506 | else | |
507 | val &= ~bits; | |
508 | writel(val, ctx->regs + reg); | |
509 | } | |
510 | ||
864ee9e6 | 511 | static void fimd_win_commit(struct device *dev, int zpos) |
1c248b7d ID |
512 | { |
513 | struct fimd_context *ctx = get_fimd_context(dev); | |
514 | struct fimd_win_data *win_data; | |
864ee9e6 | 515 | int win = zpos; |
1c248b7d | 516 | unsigned long val, alpha, size; |
f56aad3a JS |
517 | unsigned int last_x; |
518 | unsigned int last_y; | |
1c248b7d | 519 | |
e30d4bcf ID |
520 | if (ctx->suspended) |
521 | return; | |
522 | ||
864ee9e6 JS |
523 | if (win == DEFAULT_ZPOS) |
524 | win = ctx->default_win; | |
525 | ||
37b006e8 | 526 | if (win < 0 || win >= WINDOWS_NR) |
1c248b7d ID |
527 | return; |
528 | ||
529 | win_data = &ctx->win_data[win]; | |
530 | ||
531 | /* | |
de7af100 | 532 | * SHADOWCON/PRTCON register is used for enabling timing. |
1c248b7d ID |
533 | * |
534 | * for example, once only width value of a register is set, | |
535 | * if the dma is started then fimd hardware could malfunction so | |
536 | * with protect window setting, the register fields with prefix '_F' | |
537 | * wouldn't be updated at vsync also but updated once unprotect window | |
538 | * is set. | |
539 | */ | |
540 | ||
541 | /* protect windows */ | |
de7af100 | 542 | fimd_shadow_protect_win(ctx, win, true); |
1c248b7d ID |
543 | |
544 | /* buffer start address */ | |
2c871127 | 545 | val = (unsigned long)win_data->dma_addr; |
1c248b7d ID |
546 | writel(val, ctx->regs + VIDWx_BUF_START(win, 0)); |
547 | ||
548 | /* buffer end address */ | |
19c8b834 | 549 | size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3); |
2c871127 | 550 | val = (unsigned long)(win_data->dma_addr + size); |
1c248b7d ID |
551 | writel(val, ctx->regs + VIDWx_BUF_END(win, 0)); |
552 | ||
553 | DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n", | |
2c871127 | 554 | (unsigned long)win_data->dma_addr, val, size); |
19c8b834 ID |
555 | DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", |
556 | win_data->ovl_width, win_data->ovl_height); | |
1c248b7d ID |
557 | |
558 | /* buffer size */ | |
559 | val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) | | |
ca555e5a JS |
560 | VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size) | |
561 | VIDW_BUF_SIZE_OFFSET_E(win_data->buf_offsize) | | |
562 | VIDW_BUF_SIZE_PAGEWIDTH_E(win_data->line_size); | |
1c248b7d ID |
563 | writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0)); |
564 | ||
565 | /* OSD position */ | |
566 | val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) | | |
ca555e5a JS |
567 | VIDOSDxA_TOPLEFT_Y(win_data->offset_y) | |
568 | VIDOSDxA_TOPLEFT_X_E(win_data->offset_x) | | |
569 | VIDOSDxA_TOPLEFT_Y_E(win_data->offset_y); | |
1c248b7d ID |
570 | writel(val, ctx->regs + VIDOSD_A(win)); |
571 | ||
f56aad3a JS |
572 | last_x = win_data->offset_x + win_data->ovl_width; |
573 | if (last_x) | |
574 | last_x--; | |
575 | last_y = win_data->offset_y + win_data->ovl_height; | |
576 | if (last_y) | |
577 | last_y--; | |
578 | ||
ca555e5a JS |
579 | val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) | |
580 | VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y); | |
581 | ||
1c248b7d ID |
582 | writel(val, ctx->regs + VIDOSD_B(win)); |
583 | ||
19c8b834 | 584 | DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", |
f56aad3a | 585 | win_data->offset_x, win_data->offset_y, last_x, last_y); |
1c248b7d ID |
586 | |
587 | /* hardware window 0 doesn't support alpha channel. */ | |
588 | if (win != 0) { | |
589 | /* OSD alpha */ | |
590 | alpha = VIDISD14C_ALPHA1_R(0xf) | | |
591 | VIDISD14C_ALPHA1_G(0xf) | | |
592 | VIDISD14C_ALPHA1_B(0xf); | |
593 | ||
594 | writel(alpha, ctx->regs + VIDOSD_C(win)); | |
595 | } | |
596 | ||
597 | /* OSD size */ | |
598 | if (win != 3 && win != 4) { | |
599 | u32 offset = VIDOSD_D(win); | |
600 | if (win == 0) | |
0f10cf14 | 601 | offset = VIDOSD_C(win); |
19c8b834 | 602 | val = win_data->ovl_width * win_data->ovl_height; |
1c248b7d ID |
603 | writel(val, ctx->regs + offset); |
604 | ||
605 | DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val); | |
606 | } | |
607 | ||
608 | fimd_win_set_pixfmt(dev, win); | |
609 | ||
610 | /* hardware window 0 doesn't support color key. */ | |
611 | if (win != 0) | |
612 | fimd_win_set_colkey(dev, win); | |
613 | ||
ec05da95 ID |
614 | /* wincon */ |
615 | val = readl(ctx->regs + WINCON(win)); | |
616 | val |= WINCONx_ENWIN; | |
617 | writel(val, ctx->regs + WINCON(win)); | |
618 | ||
1c248b7d | 619 | /* Enable DMA channel and unprotect windows */ |
de7af100 TF |
620 | fimd_shadow_protect_win(ctx, win, false); |
621 | ||
622 | if (ctx->driver_data->has_shadowcon) { | |
623 | val = readl(ctx->regs + SHADOWCON); | |
624 | val |= SHADOWCON_CHx_ENABLE(win); | |
625 | writel(val, ctx->regs + SHADOWCON); | |
626 | } | |
ec05da95 ID |
627 | |
628 | win_data->enabled = true; | |
1c248b7d ID |
629 | } |
630 | ||
864ee9e6 | 631 | static void fimd_win_disable(struct device *dev, int zpos) |
1c248b7d ID |
632 | { |
633 | struct fimd_context *ctx = get_fimd_context(dev); | |
ec05da95 | 634 | struct fimd_win_data *win_data; |
864ee9e6 | 635 | int win = zpos; |
1c248b7d ID |
636 | u32 val; |
637 | ||
864ee9e6 JS |
638 | if (win == DEFAULT_ZPOS) |
639 | win = ctx->default_win; | |
640 | ||
37b006e8 | 641 | if (win < 0 || win >= WINDOWS_NR) |
1c248b7d ID |
642 | return; |
643 | ||
ec05da95 ID |
644 | win_data = &ctx->win_data[win]; |
645 | ||
db7e55ae P |
646 | if (ctx->suspended) { |
647 | /* do not resume this window*/ | |
648 | win_data->resume = false; | |
649 | return; | |
650 | } | |
651 | ||
1c248b7d | 652 | /* protect windows */ |
de7af100 | 653 | fimd_shadow_protect_win(ctx, win, true); |
1c248b7d ID |
654 | |
655 | /* wincon */ | |
656 | val = readl(ctx->regs + WINCON(win)); | |
657 | val &= ~WINCONx_ENWIN; | |
658 | writel(val, ctx->regs + WINCON(win)); | |
659 | ||
660 | /* unprotect windows */ | |
de7af100 TF |
661 | if (ctx->driver_data->has_shadowcon) { |
662 | val = readl(ctx->regs + SHADOWCON); | |
663 | val &= ~SHADOWCON_CHx_ENABLE(win); | |
664 | writel(val, ctx->regs + SHADOWCON); | |
665 | } | |
666 | ||
667 | fimd_shadow_protect_win(ctx, win, false); | |
ec05da95 ID |
668 | |
669 | win_data->enabled = false; | |
1c248b7d ID |
670 | } |
671 | ||
672 | static struct exynos_drm_overlay_ops fimd_overlay_ops = { | |
673 | .mode_set = fimd_win_mode_set, | |
674 | .commit = fimd_win_commit, | |
675 | .disable = fimd_win_disable, | |
676 | }; | |
677 | ||
677e84c1 JS |
678 | static struct exynos_drm_manager fimd_manager = { |
679 | .pipe = -1, | |
680 | .ops = &fimd_manager_ops, | |
681 | .overlay_ops = &fimd_overlay_ops, | |
682 | .display_ops = &fimd_display_ops, | |
683 | }; | |
684 | ||
1c248b7d ID |
685 | static irqreturn_t fimd_irq_handler(int irq, void *dev_id) |
686 | { | |
687 | struct fimd_context *ctx = (struct fimd_context *)dev_id; | |
688 | struct exynos_drm_subdrv *subdrv = &ctx->subdrv; | |
689 | struct drm_device *drm_dev = subdrv->drm_dev; | |
677e84c1 | 690 | struct exynos_drm_manager *manager = subdrv->manager; |
1c248b7d ID |
691 | u32 val; |
692 | ||
693 | val = readl(ctx->regs + VIDINTCON1); | |
694 | ||
695 | if (val & VIDINTCON1_INT_FRAME) | |
696 | /* VSYNC interrupt */ | |
697 | writel(VIDINTCON1_INT_FRAME, ctx->regs + VIDINTCON1); | |
698 | ||
ec05da95 ID |
699 | /* check the crtc is detached already from encoder */ |
700 | if (manager->pipe < 0) | |
701 | goto out; | |
483b88f8 | 702 | |
1c248b7d | 703 | drm_handle_vblank(drm_dev, manager->pipe); |
663d8766 | 704 | exynos_drm_crtc_finish_pageflip(drm_dev, manager->pipe); |
1c248b7d | 705 | |
01ce113c P |
706 | /* set wait vsync event to zero and wake up queue. */ |
707 | if (atomic_read(&ctx->wait_vsync_event)) { | |
708 | atomic_set(&ctx->wait_vsync_event, 0); | |
8dd9ad5d | 709 | wake_up(&ctx->wait_vsync_queue); |
01ce113c | 710 | } |
ec05da95 | 711 | out: |
1c248b7d ID |
712 | return IRQ_HANDLED; |
713 | } | |
714 | ||
41c24346 | 715 | static int fimd_subdrv_probe(struct drm_device *drm_dev, struct device *dev) |
1c248b7d | 716 | { |
1c248b7d ID |
717 | /* |
718 | * enable drm irq mode. | |
4423843c | 719 | * - with irq_enabled = true, we can use the vblank feature. |
1c248b7d ID |
720 | * |
721 | * P.S. note that we wouldn't use drm irq handler but | |
722 | * just specific driver own one instead because | |
723 | * drm framework supports only one irq handler. | |
724 | */ | |
4423843c | 725 | drm_dev->irq_enabled = true; |
1c248b7d | 726 | |
ec05da95 | 727 | /* |
ba0bf120 | 728 | * with vblank_disable_allowed = true, vblank interrupt will be disabled |
ec05da95 ID |
729 | * by drm timer once a current process gives up ownership of |
730 | * vblank event.(after drm_vblank_put function is called) | |
731 | */ | |
ba0bf120 | 732 | drm_dev->vblank_disable_allowed = true; |
ec05da95 | 733 | |
bcc5cd1c ID |
734 | /* attach this sub driver to iommu mapping if supported. */ |
735 | if (is_drm_iommu_supported(drm_dev)) | |
736 | drm_iommu_attach_device(drm_dev, dev); | |
737 | ||
1c248b7d ID |
738 | return 0; |
739 | } | |
740 | ||
29cb6025 | 741 | static void fimd_subdrv_remove(struct drm_device *drm_dev, struct device *dev) |
1c248b7d | 742 | { |
bcc5cd1c ID |
743 | /* detach this sub driver from iommu mapping if supported. */ |
744 | if (is_drm_iommu_supported(drm_dev)) | |
745 | drm_iommu_detach_device(drm_dev, dev); | |
1c248b7d ID |
746 | } |
747 | ||
111e6055 | 748 | static int fimd_configure_clocks(struct fimd_context *ctx, struct device *dev) |
1c248b7d | 749 | { |
562ad9f4 | 750 | struct videomode *vm = &ctx->panel.vm; |
111e6055 AH |
751 | unsigned long clk; |
752 | ||
753 | ctx->bus_clk = devm_clk_get(dev, "fimd"); | |
754 | if (IS_ERR(ctx->bus_clk)) { | |
755 | dev_err(dev, "failed to get bus clock\n"); | |
756 | return PTR_ERR(ctx->bus_clk); | |
757 | } | |
758 | ||
759 | ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd"); | |
760 | if (IS_ERR(ctx->lcd_clk)) { | |
761 | dev_err(dev, "failed to get lcd clock\n"); | |
762 | return PTR_ERR(ctx->lcd_clk); | |
763 | } | |
764 | ||
765 | clk = clk_get_rate(ctx->lcd_clk); | |
766 | if (clk == 0) { | |
767 | dev_err(dev, "error getting sclk_fimd clock rate\n"); | |
768 | return -EINVAL; | |
769 | } | |
770 | ||
771 | if (vm->pixelclock == 0) { | |
772 | unsigned long c; | |
773 | c = vm->hactive + vm->hback_porch + vm->hfront_porch + | |
774 | vm->hsync_len; | |
775 | c *= vm->vactive + vm->vback_porch + vm->vfront_porch + | |
776 | vm->vsync_len; | |
777 | vm->pixelclock = c * FIMD_DEFAULT_FRAMERATE; | |
778 | if (vm->pixelclock == 0) { | |
779 | dev_err(dev, "incorrect display timings\n"); | |
780 | return -EINVAL; | |
1c248b7d | 781 | } |
111e6055 AH |
782 | dev_warn(dev, "pixel clock recalculated to %luHz (%dHz frame rate)\n", |
783 | vm->pixelclock, FIMD_DEFAULT_FRAMERATE); | |
784 | } | |
785 | ctx->clkdiv = DIV_ROUND_UP(clk, vm->pixelclock); | |
786 | if (ctx->clkdiv > 256) { | |
787 | dev_warn(dev, "calculated pixel clock divider too high (%u), lowered to 256\n", | |
788 | ctx->clkdiv); | |
789 | ctx->clkdiv = 256; | |
1c248b7d | 790 | } |
111e6055 AH |
791 | vm->pixelclock = clk / ctx->clkdiv; |
792 | DRM_DEBUG_KMS("pixel clock = %lu, clkdiv = %d\n", vm->pixelclock, | |
793 | ctx->clkdiv); | |
1c248b7d | 794 | |
111e6055 | 795 | return 0; |
1c248b7d ID |
796 | } |
797 | ||
798 | static void fimd_clear_win(struct fimd_context *ctx, int win) | |
799 | { | |
1c248b7d ID |
800 | writel(0, ctx->regs + WINCON(win)); |
801 | writel(0, ctx->regs + VIDOSD_A(win)); | |
802 | writel(0, ctx->regs + VIDOSD_B(win)); | |
803 | writel(0, ctx->regs + VIDOSD_C(win)); | |
804 | ||
805 | if (win == 1 || win == 2) | |
806 | writel(0, ctx->regs + VIDOSD_D(win)); | |
807 | ||
de7af100 | 808 | fimd_shadow_protect_win(ctx, win, false); |
1c248b7d ID |
809 | } |
810 | ||
5d55393a | 811 | static int fimd_clock(struct fimd_context *ctx, bool enable) |
373af0c0 | 812 | { |
373af0c0 ID |
813 | if (enable) { |
814 | int ret; | |
815 | ||
11963a63 | 816 | ret = clk_prepare_enable(ctx->bus_clk); |
373af0c0 ID |
817 | if (ret < 0) |
818 | return ret; | |
819 | ||
11963a63 | 820 | ret = clk_prepare_enable(ctx->lcd_clk); |
373af0c0 | 821 | if (ret < 0) { |
11963a63 | 822 | clk_disable_unprepare(ctx->bus_clk); |
373af0c0 ID |
823 | return ret; |
824 | } | |
5d55393a | 825 | } else { |
11963a63 VS |
826 | clk_disable_unprepare(ctx->lcd_clk); |
827 | clk_disable_unprepare(ctx->bus_clk); | |
5d55393a ID |
828 | } |
829 | ||
830 | return 0; | |
831 | } | |
832 | ||
db7e55ae P |
833 | static void fimd_window_suspend(struct device *dev) |
834 | { | |
835 | struct fimd_context *ctx = get_fimd_context(dev); | |
836 | struct fimd_win_data *win_data; | |
837 | int i; | |
838 | ||
839 | for (i = 0; i < WINDOWS_NR; i++) { | |
840 | win_data = &ctx->win_data[i]; | |
841 | win_data->resume = win_data->enabled; | |
842 | fimd_win_disable(dev, i); | |
843 | } | |
844 | fimd_wait_for_vblank(dev); | |
845 | } | |
846 | ||
847 | static void fimd_window_resume(struct device *dev) | |
848 | { | |
849 | struct fimd_context *ctx = get_fimd_context(dev); | |
850 | struct fimd_win_data *win_data; | |
851 | int i; | |
852 | ||
853 | for (i = 0; i < WINDOWS_NR; i++) { | |
854 | win_data = &ctx->win_data[i]; | |
855 | win_data->enabled = win_data->resume; | |
856 | win_data->resume = false; | |
857 | } | |
858 | } | |
859 | ||
5d55393a ID |
860 | static int fimd_activate(struct fimd_context *ctx, bool enable) |
861 | { | |
db7e55ae | 862 | struct device *dev = ctx->subdrv.dev; |
5d55393a ID |
863 | if (enable) { |
864 | int ret; | |
5d55393a ID |
865 | |
866 | ret = fimd_clock(ctx, true); | |
867 | if (ret < 0) | |
868 | return ret; | |
373af0c0 ID |
869 | |
870 | ctx->suspended = false; | |
871 | ||
872 | /* if vblank was enabled status, enable it again. */ | |
873 | if (test_and_clear_bit(0, &ctx->irq_flags)) | |
874 | fimd_enable_vblank(dev); | |
db7e55ae P |
875 | |
876 | fimd_window_resume(dev); | |
373af0c0 | 877 | } else { |
db7e55ae P |
878 | fimd_window_suspend(dev); |
879 | ||
5d55393a | 880 | fimd_clock(ctx, false); |
373af0c0 ID |
881 | ctx->suspended = true; |
882 | } | |
883 | ||
884 | return 0; | |
885 | } | |
886 | ||
562ad9f4 | 887 | static int fimd_get_platform_data(struct fimd_context *ctx, struct device *dev) |
1c248b7d | 888 | { |
2d3f173c SK |
889 | struct videomode *vm; |
890 | int ret; | |
7f4596f4 | 891 | |
2d3f173c SK |
892 | vm = &ctx->panel.vm; |
893 | ret = of_get_videomode(dev->of_node, vm, OF_USE_NATIVE_MODE); | |
894 | if (ret) { | |
895 | DRM_ERROR("failed: of_get_videomode() : %d\n", ret); | |
896 | return ret; | |
1c248b7d ID |
897 | } |
898 | ||
2d3f173c SK |
899 | if (vm->flags & DISPLAY_FLAGS_VSYNC_LOW) |
900 | ctx->vidcon1 |= VIDCON1_INV_VSYNC; | |
901 | if (vm->flags & DISPLAY_FLAGS_HSYNC_LOW) | |
902 | ctx->vidcon1 |= VIDCON1_INV_HSYNC; | |
903 | if (vm->flags & DISPLAY_FLAGS_DE_LOW) | |
904 | ctx->vidcon1 |= VIDCON1_INV_VDEN; | |
905 | if (vm->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) | |
906 | ctx->vidcon1 |= VIDCON1_INV_VCLK; | |
907 | ||
562ad9f4 AH |
908 | return 0; |
909 | } | |
910 | ||
911 | static int fimd_probe(struct platform_device *pdev) | |
912 | { | |
913 | struct device *dev = &pdev->dev; | |
914 | struct fimd_context *ctx; | |
915 | struct exynos_drm_subdrv *subdrv; | |
916 | struct resource *res; | |
917 | int win; | |
918 | int ret = -EINVAL; | |
1c248b7d | 919 | |
2d3f173c SK |
920 | if (!dev->of_node) |
921 | return -ENODEV; | |
922 | ||
d873ab99 | 923 | ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); |
1c248b7d ID |
924 | if (!ctx) |
925 | return -ENOMEM; | |
926 | ||
562ad9f4 AH |
927 | ret = fimd_get_platform_data(ctx, dev); |
928 | if (ret) | |
929 | return ret; | |
930 | ||
111e6055 AH |
931 | ret = fimd_configure_clocks(ctx, dev); |
932 | if (ret) | |
933 | return ret; | |
1c248b7d | 934 | |
1c248b7d | 935 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1c248b7d | 936 | |
d873ab99 | 937 | ctx->regs = devm_ioremap_resource(dev, res); |
d4ed6025 TR |
938 | if (IS_ERR(ctx->regs)) |
939 | return PTR_ERR(ctx->regs); | |
1c248b7d | 940 | |
1977e6d8 | 941 | res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "vsync"); |
1c248b7d ID |
942 | if (!res) { |
943 | dev_err(dev, "irq request failed.\n"); | |
a4d8de5f | 944 | return -ENXIO; |
1c248b7d ID |
945 | } |
946 | ||
947 | ctx->irq = res->start; | |
948 | ||
d873ab99 | 949 | ret = devm_request_irq(dev, ctx->irq, fimd_irq_handler, |
edc57266 SK |
950 | 0, "drm_fimd", ctx); |
951 | if (ret) { | |
1c248b7d | 952 | dev_err(dev, "irq request failed.\n"); |
a4d8de5f | 953 | return ret; |
1c248b7d ID |
954 | } |
955 | ||
18873465 | 956 | ctx->driver_data = drm_fimd_get_driver_data(pdev); |
57ed0f7b | 957 | init_waitqueue_head(&ctx->wait_vsync_queue); |
01ce113c | 958 | atomic_set(&ctx->wait_vsync_event, 0); |
1c248b7d | 959 | |
1c248b7d ID |
960 | subdrv = &ctx->subdrv; |
961 | ||
677e84c1 JS |
962 | subdrv->dev = dev; |
963 | subdrv->manager = &fimd_manager; | |
1c248b7d ID |
964 | subdrv->probe = fimd_subdrv_probe; |
965 | subdrv->remove = fimd_subdrv_remove; | |
1c248b7d | 966 | |
c32b06ef ID |
967 | mutex_init(&ctx->lock); |
968 | ||
1c248b7d | 969 | platform_set_drvdata(pdev, ctx); |
c32b06ef | 970 | |
c32b06ef ID |
971 | pm_runtime_enable(dev); |
972 | pm_runtime_get_sync(dev); | |
973 | ||
974 | for (win = 0; win < WINDOWS_NR; win++) | |
975 | fimd_clear_win(ctx, win); | |
976 | ||
1c248b7d ID |
977 | exynos_drm_subdrv_register(subdrv); |
978 | ||
979 | return 0; | |
1c248b7d ID |
980 | } |
981 | ||
56550d94 | 982 | static int fimd_remove(struct platform_device *pdev) |
1c248b7d | 983 | { |
cb91f6a0 | 984 | struct device *dev = &pdev->dev; |
1c248b7d ID |
985 | struct fimd_context *ctx = platform_get_drvdata(pdev); |
986 | ||
1c248b7d ID |
987 | exynos_drm_subdrv_unregister(&ctx->subdrv); |
988 | ||
cb91f6a0 JS |
989 | if (ctx->suspended) |
990 | goto out; | |
991 | ||
cb91f6a0 JS |
992 | pm_runtime_set_suspended(dev); |
993 | pm_runtime_put_sync(dev); | |
994 | ||
995 | out: | |
996 | pm_runtime_disable(dev); | |
997 | ||
1c248b7d ID |
998 | return 0; |
999 | } | |
1000 | ||
e30d4bcf ID |
1001 | #ifdef CONFIG_PM_SLEEP |
1002 | static int fimd_suspend(struct device *dev) | |
1003 | { | |
373af0c0 | 1004 | struct fimd_context *ctx = get_fimd_context(dev); |
e30d4bcf | 1005 | |
373af0c0 ID |
1006 | /* |
1007 | * do not use pm_runtime_suspend(). if pm_runtime_suspend() is | |
1008 | * called here, an error would be returned by that interface | |
1009 | * because the usage_count of pm runtime is more than 1. | |
1010 | */ | |
5d55393a ID |
1011 | if (!pm_runtime_suspended(dev)) |
1012 | return fimd_activate(ctx, false); | |
1013 | ||
1014 | return 0; | |
e30d4bcf ID |
1015 | } |
1016 | ||
1017 | static int fimd_resume(struct device *dev) | |
1018 | { | |
373af0c0 | 1019 | struct fimd_context *ctx = get_fimd_context(dev); |
e30d4bcf | 1020 | |
373af0c0 ID |
1021 | /* |
1022 | * if entered to sleep when lcd panel was on, the usage_count | |
1023 | * of pm runtime would still be 1 so in this case, fimd driver | |
1024 | * should be on directly not drawing on pm runtime interface. | |
1025 | */ | |
28998afa | 1026 | if (!pm_runtime_suspended(dev)) { |
5d55393a ID |
1027 | int ret; |
1028 | ||
1029 | ret = fimd_activate(ctx, true); | |
1030 | if (ret < 0) | |
1031 | return ret; | |
1032 | ||
1033 | /* | |
1034 | * in case of dpms on(standby), fimd_apply function will | |
1035 | * be called by encoder's dpms callback to update fimd's | |
1036 | * registers but in case of sleep wakeup, it's not. | |
1037 | * so fimd_apply function should be called at here. | |
1038 | */ | |
1039 | fimd_apply(dev); | |
1040 | } | |
e30d4bcf | 1041 | |
e30d4bcf ID |
1042 | return 0; |
1043 | } | |
1044 | #endif | |
1045 | ||
cb91f6a0 JS |
1046 | #ifdef CONFIG_PM_RUNTIME |
1047 | static int fimd_runtime_suspend(struct device *dev) | |
1048 | { | |
1049 | struct fimd_context *ctx = get_fimd_context(dev); | |
1050 | ||
5d55393a | 1051 | return fimd_activate(ctx, false); |
cb91f6a0 JS |
1052 | } |
1053 | ||
1054 | static int fimd_runtime_resume(struct device *dev) | |
1055 | { | |
1056 | struct fimd_context *ctx = get_fimd_context(dev); | |
cb91f6a0 | 1057 | |
5d55393a | 1058 | return fimd_activate(ctx, true); |
cb91f6a0 JS |
1059 | } |
1060 | #endif | |
1061 | ||
1062 | static const struct dev_pm_ops fimd_pm_ops = { | |
e30d4bcf | 1063 | SET_SYSTEM_SLEEP_PM_OPS(fimd_suspend, fimd_resume) |
cb91f6a0 JS |
1064 | SET_RUNTIME_PM_OPS(fimd_runtime_suspend, fimd_runtime_resume, NULL) |
1065 | }; | |
1066 | ||
132a5b91 | 1067 | struct platform_driver fimd_driver = { |
1c248b7d | 1068 | .probe = fimd_probe, |
56550d94 | 1069 | .remove = fimd_remove, |
1c248b7d ID |
1070 | .driver = { |
1071 | .name = "exynos4-fb", | |
1072 | .owner = THIS_MODULE, | |
cb91f6a0 | 1073 | .pm = &fimd_pm_ops, |
2d3f173c | 1074 | .of_match_table = fimd_driver_dt_match, |
1c248b7d ID |
1075 | }, |
1076 | }; |