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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
1c248b7d ID |
2 | /* exynos_drm_fimd.c |
3 | * | |
4 | * Copyright (C) 2011 Samsung Electronics Co.Ltd | |
5 | * Authors: | |
6 | * Joonyoung Shim <jy0922.shim@samsung.com> | |
7 | * Inki Dae <inki.dae@samsung.com> | |
1c248b7d | 8 | */ |
1c248b7d | 9 | |
1c248b7d | 10 | #include <linux/clk.h> |
2bda34d7 SR |
11 | #include <linux/component.h> |
12 | #include <linux/kernel.h> | |
13 | #include <linux/mfd/syscon.h> | |
3f1c781d | 14 | #include <linux/of.h> |
d636ead8 | 15 | #include <linux/of_device.h> |
2bda34d7 | 16 | #include <linux/platform_device.h> |
cb91f6a0 | 17 | #include <linux/pm_runtime.h> |
3854fab2 | 18 | #include <linux/regmap.h> |
1c248b7d | 19 | |
7f4596f4 | 20 | #include <video/of_display_timing.h> |
111e6055 | 21 | #include <video/of_videomode.h> |
5a213a55 | 22 | #include <video/samsung_fimd.h> |
2bda34d7 SR |
23 | |
24 | #include <drm/drm_fourcc.h> | |
25 | #include <drm/drm_vblank.h> | |
1c248b7d | 26 | #include <drm/exynos_drm.h> |
1c248b7d | 27 | |
2bda34d7 | 28 | #include "exynos_drm_crtc.h" |
1c248b7d | 29 | #include "exynos_drm_drv.h" |
0488f50e | 30 | #include "exynos_drm_fb.h" |
7ee14cdc | 31 | #include "exynos_drm_plane.h" |
1c248b7d ID |
32 | |
33 | /* | |
b8654b37 | 34 | * FIMD stands for Fully Interactive Mobile Display and |
1c248b7d ID |
35 | * as a display controller, it transfers contents drawn on memory |
36 | * to a LCD Panel through Display Interfaces such as RGB or | |
37 | * CPU Interface. | |
38 | */ | |
39 | ||
66367461 | 40 | #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 |
111e6055 | 41 | |
1c248b7d ID |
42 | /* position control register for hardware window 0, 2 ~ 4.*/ |
43 | #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16) | |
44 | #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16) | |
0f10cf14 LKA |
45 | /* |
46 | * size control register for hardware windows 0 and alpha control register | |
47 | * for hardware windows 1 ~ 4 | |
48 | */ | |
49 | #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16) | |
50 | /* size control register for hardware windows 1 ~ 2. */ | |
1c248b7d ID |
51 | #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16) |
52 | ||
453b44a3 GP |
53 | #define VIDWnALPHA0(win) (VIDW_ALPHA + 0x00 + (win) * 8) |
54 | #define VIDWnALPHA1(win) (VIDW_ALPHA + 0x04 + (win) * 8) | |
55 | ||
1c248b7d | 56 | #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8) |
cb11b3f1 | 57 | #define VIDWx_BUF_START_S(win, buf) (VIDW_BUF_START_S(buf) + (win) * 8) |
1c248b7d ID |
58 | #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8) |
59 | #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4) | |
60 | ||
61 | /* color key control register for hardware window 1 ~ 4. */ | |
0f10cf14 | 62 | #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8)) |
1c248b7d | 63 | /* color key value register for hardware window 1 ~ 4. */ |
0f10cf14 | 64 | #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8)) |
1c248b7d | 65 | |
b5bf0f1e | 66 | /* I80 trigger control register */ |
3854fab2 | 67 | #define TRIGCON 0x1A4 |
b5bf0f1e ID |
68 | #define TRGMODE_ENABLE (1 << 0) |
69 | #define SWTRGCMD_ENABLE (1 << 1) | |
6bdc92ee | 70 | /* Exynos3250, 3472, 5260 5410, 5420 and 5422 only supported. */ |
b5bf0f1e ID |
71 | #define HWTRGEN_ENABLE (1 << 3) |
72 | #define HWTRGMASK_ENABLE (1 << 4) | |
6bdc92ee | 73 | /* Exynos3250, 3472, 5260, 5420 and 5422 only supported. */ |
b5bf0f1e | 74 | #define HWTRIGEN_PER_ENABLE (1 << 31) |
3854fab2 YC |
75 | |
76 | /* display mode change control register except exynos4 */ | |
77 | #define VIDOUT_CON 0x000 | |
78 | #define VIDOUT_CON_F_I80_LDI0 (0x2 << 8) | |
79 | ||
80 | /* I80 interface control for main LDI register */ | |
81 | #define I80IFCONFAx(x) (0x1B0 + (x) * 4) | |
82 | #define I80IFCONFBx(x) (0x1B8 + (x) * 4) | |
83 | #define LCD_CS_SETUP(x) ((x) << 16) | |
84 | #define LCD_WR_SETUP(x) ((x) << 12) | |
85 | #define LCD_WR_ACTIVE(x) ((x) << 8) | |
86 | #define LCD_WR_HOLD(x) ((x) << 4) | |
87 | #define I80IFEN_ENABLE (1 << 0) | |
88 | ||
1c248b7d ID |
89 | /* FIMD has totally five hardware windows. */ |
90 | #define WINDOWS_NR 5 | |
91 | ||
a6f75aa1 ID |
92 | /* HW trigger flag on i80 panel. */ |
93 | #define I80_HW_TRG (1 << 1) | |
94 | ||
e2e13389 LKA |
95 | struct fimd_driver_data { |
96 | unsigned int timing_base; | |
3854fab2 YC |
97 | unsigned int lcdblk_offset; |
98 | unsigned int lcdblk_vt_shift; | |
99 | unsigned int lcdblk_bypass_shift; | |
1feafd3a | 100 | unsigned int lcdblk_mic_bypass_shift; |
a6f75aa1 | 101 | unsigned int trg_type; |
de7af100 TF |
102 | |
103 | unsigned int has_shadowcon:1; | |
411d9ed4 | 104 | unsigned int has_clksel:1; |
5cc4621a | 105 | unsigned int has_limited_fmt:1; |
3854fab2 | 106 | unsigned int has_vidoutcon:1; |
3c3c9c1d | 107 | unsigned int has_vtsel:1; |
1feafd3a | 108 | unsigned int has_mic_bypass:1; |
196e059a | 109 | unsigned int has_dp_clk:1; |
a6f75aa1 ID |
110 | unsigned int has_hw_trigger:1; |
111 | unsigned int has_trigger_per_te:1; | |
e2e13389 LKA |
112 | }; |
113 | ||
725ddead TF |
114 | static struct fimd_driver_data s3c64xx_fimd_driver_data = { |
115 | .timing_base = 0x0, | |
116 | .has_clksel = 1, | |
5cc4621a | 117 | .has_limited_fmt = 1, |
725ddead TF |
118 | }; |
119 | ||
fa50b7b4 TF |
120 | static struct fimd_driver_data s5pv210_fimd_driver_data = { |
121 | .timing_base = 0x0, | |
122 | .has_shadowcon = 1, | |
123 | .has_clksel = 1, | |
124 | }; | |
125 | ||
d6ce7b58 ID |
126 | static struct fimd_driver_data exynos3_fimd_driver_data = { |
127 | .timing_base = 0x20000, | |
128 | .lcdblk_offset = 0x210, | |
129 | .lcdblk_bypass_shift = 1, | |
130 | .has_shadowcon = 1, | |
131 | .has_vidoutcon = 1, | |
132 | }; | |
133 | ||
6ecf18f9 | 134 | static struct fimd_driver_data exynos4_fimd_driver_data = { |
e2e13389 | 135 | .timing_base = 0x0, |
3854fab2 YC |
136 | .lcdblk_offset = 0x210, |
137 | .lcdblk_vt_shift = 10, | |
138 | .lcdblk_bypass_shift = 1, | |
de7af100 | 139 | .has_shadowcon = 1, |
3c3c9c1d | 140 | .has_vtsel = 1, |
e2e13389 LKA |
141 | }; |
142 | ||
6ecf18f9 | 143 | static struct fimd_driver_data exynos5_fimd_driver_data = { |
e2e13389 | 144 | .timing_base = 0x20000, |
3854fab2 YC |
145 | .lcdblk_offset = 0x214, |
146 | .lcdblk_vt_shift = 24, | |
147 | .lcdblk_bypass_shift = 15, | |
de7af100 | 148 | .has_shadowcon = 1, |
3854fab2 | 149 | .has_vidoutcon = 1, |
3c3c9c1d | 150 | .has_vtsel = 1, |
196e059a | 151 | .has_dp_clk = 1, |
e2e13389 LKA |
152 | }; |
153 | ||
1feafd3a CP |
154 | static struct fimd_driver_data exynos5420_fimd_driver_data = { |
155 | .timing_base = 0x20000, | |
156 | .lcdblk_offset = 0x214, | |
157 | .lcdblk_vt_shift = 24, | |
158 | .lcdblk_bypass_shift = 15, | |
159 | .lcdblk_mic_bypass_shift = 11, | |
160 | .has_shadowcon = 1, | |
161 | .has_vidoutcon = 1, | |
162 | .has_vtsel = 1, | |
163 | .has_mic_bypass = 1, | |
196e059a | 164 | .has_dp_clk = 1, |
1feafd3a CP |
165 | }; |
166 | ||
1c248b7d | 167 | struct fimd_context { |
bb7704d6 | 168 | struct device *dev; |
40c8ab4b | 169 | struct drm_device *drm_dev; |
07dc3678 | 170 | void *dma_priv; |
93bca243 | 171 | struct exynos_drm_crtc *crtc; |
7ee14cdc | 172 | struct exynos_drm_plane planes[WINDOWS_NR]; |
fd2d2fc2 | 173 | struct exynos_drm_plane_config configs[WINDOWS_NR]; |
1c248b7d ID |
174 | struct clk *bus_clk; |
175 | struct clk *lcd_clk; | |
1c248b7d | 176 | void __iomem *regs; |
3854fab2 | 177 | struct regmap *sysreg; |
1c248b7d | 178 | unsigned long irq_flags; |
3854fab2 | 179 | u32 vidcon0; |
1c248b7d | 180 | u32 vidcon1; |
3854fab2 YC |
181 | u32 vidout_con; |
182 | u32 i80ifcon; | |
183 | bool i80_if; | |
cb91f6a0 | 184 | bool suspended; |
01ce113c P |
185 | wait_queue_head_t wait_vsync_queue; |
186 | atomic_t wait_vsync_event; | |
3854fab2 YC |
187 | atomic_t win_updated; |
188 | atomic_t triggering; | |
c96fdfde | 189 | u32 clkdiv; |
1c248b7d | 190 | |
e1a7b9b4 | 191 | const struct fimd_driver_data *driver_data; |
2b8376c8 | 192 | struct drm_encoder *encoder; |
196e059a | 193 | struct exynos_drm_clk dp_clk; |
1c248b7d ID |
194 | }; |
195 | ||
d636ead8 | 196 | static const struct of_device_id fimd_driver_dt_match[] = { |
725ddead TF |
197 | { .compatible = "samsung,s3c6400-fimd", |
198 | .data = &s3c64xx_fimd_driver_data }, | |
fa50b7b4 TF |
199 | { .compatible = "samsung,s5pv210-fimd", |
200 | .data = &s5pv210_fimd_driver_data }, | |
d6ce7b58 ID |
201 | { .compatible = "samsung,exynos3250-fimd", |
202 | .data = &exynos3_fimd_driver_data }, | |
5830daf8 | 203 | { .compatible = "samsung,exynos4210-fimd", |
d636ead8 | 204 | .data = &exynos4_fimd_driver_data }, |
5830daf8 | 205 | { .compatible = "samsung,exynos5250-fimd", |
d636ead8 | 206 | .data = &exynos5_fimd_driver_data }, |
1feafd3a CP |
207 | { .compatible = "samsung,exynos5420-fimd", |
208 | .data = &exynos5420_fimd_driver_data }, | |
d636ead8 JS |
209 | {}, |
210 | }; | |
0262ceeb | 211 | MODULE_DEVICE_TABLE(of, fimd_driver_dt_match); |
d636ead8 | 212 | |
fd2d2fc2 MS |
213 | static const enum drm_plane_type fimd_win_types[WINDOWS_NR] = { |
214 | DRM_PLANE_TYPE_PRIMARY, | |
215 | DRM_PLANE_TYPE_OVERLAY, | |
216 | DRM_PLANE_TYPE_OVERLAY, | |
217 | DRM_PLANE_TYPE_OVERLAY, | |
218 | DRM_PLANE_TYPE_CURSOR, | |
219 | }; | |
220 | ||
fbbb1e1a MS |
221 | static const uint32_t fimd_formats[] = { |
222 | DRM_FORMAT_C8, | |
223 | DRM_FORMAT_XRGB1555, | |
224 | DRM_FORMAT_RGB565, | |
225 | DRM_FORMAT_XRGB8888, | |
226 | DRM_FORMAT_ARGB8888, | |
227 | }; | |
228 | ||
6f8ee5c2 CM |
229 | static const unsigned int capabilities[WINDOWS_NR] = { |
230 | 0, | |
3b5129b3 CM |
231 | EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, |
232 | EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, | |
233 | EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, | |
234 | EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, | |
6f8ee5c2 CM |
235 | }; |
236 | ||
237 | static inline void fimd_set_bits(struct fimd_context *ctx, u32 reg, u32 mask, | |
238 | u32 val) | |
239 | { | |
240 | val = (val & mask) | (readl(ctx->regs + reg) & ~mask); | |
241 | writel(val, ctx->regs + reg); | |
242 | } | |
243 | ||
fb88e214 MS |
244 | static int fimd_enable_vblank(struct exynos_drm_crtc *crtc) |
245 | { | |
246 | struct fimd_context *ctx = crtc->ctx; | |
247 | u32 val; | |
248 | ||
249 | if (ctx->suspended) | |
250 | return -EPERM; | |
251 | ||
252 | if (!test_and_set_bit(0, &ctx->irq_flags)) { | |
253 | val = readl(ctx->regs + VIDINTCON0); | |
254 | ||
255 | val |= VIDINTCON0_INT_ENABLE; | |
256 | ||
257 | if (ctx->i80_if) { | |
258 | val |= VIDINTCON0_INT_I80IFDONE; | |
259 | val |= VIDINTCON0_INT_SYSMAINCON; | |
260 | val &= ~VIDINTCON0_INT_SYSSUBCON; | |
261 | } else { | |
262 | val |= VIDINTCON0_INT_FRAME; | |
263 | ||
264 | val &= ~VIDINTCON0_FRAMESEL0_MASK; | |
82a01783 | 265 | val |= VIDINTCON0_FRAMESEL0_FRONTPORCH; |
fb88e214 MS |
266 | val &= ~VIDINTCON0_FRAMESEL1_MASK; |
267 | val |= VIDINTCON0_FRAMESEL1_NONE; | |
268 | } | |
269 | ||
270 | writel(val, ctx->regs + VIDINTCON0); | |
271 | } | |
272 | ||
273 | return 0; | |
274 | } | |
275 | ||
276 | static void fimd_disable_vblank(struct exynos_drm_crtc *crtc) | |
277 | { | |
278 | struct fimd_context *ctx = crtc->ctx; | |
279 | u32 val; | |
280 | ||
281 | if (ctx->suspended) | |
282 | return; | |
283 | ||
284 | if (test_and_clear_bit(0, &ctx->irq_flags)) { | |
285 | val = readl(ctx->regs + VIDINTCON0); | |
286 | ||
287 | val &= ~VIDINTCON0_INT_ENABLE; | |
288 | ||
289 | if (ctx->i80_if) { | |
290 | val &= ~VIDINTCON0_INT_I80IFDONE; | |
291 | val &= ~VIDINTCON0_INT_SYSMAINCON; | |
292 | val &= ~VIDINTCON0_INT_SYSSUBCON; | |
293 | } else | |
294 | val &= ~VIDINTCON0_INT_FRAME; | |
295 | ||
296 | writel(val, ctx->regs + VIDINTCON0); | |
297 | } | |
298 | } | |
299 | ||
93bca243 | 300 | static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc) |
f13bdbd1 | 301 | { |
93bca243 | 302 | struct fimd_context *ctx = crtc->ctx; |
f13bdbd1 AA |
303 | |
304 | if (ctx->suspended) | |
305 | return; | |
306 | ||
307 | atomic_set(&ctx->wait_vsync_event, 1); | |
308 | ||
309 | /* | |
310 | * wait for FIMD to signal VSYNC interrupt or return after | |
311 | * timeout which is set to 50ms (refresh rate of 20). | |
312 | */ | |
313 | if (!wait_event_timeout(ctx->wait_vsync_queue, | |
314 | !atomic_read(&ctx->wait_vsync_event), | |
315 | HZ/20)) | |
6be90056 | 316 | DRM_DEV_DEBUG_KMS(ctx->dev, "vblank wait timed out.\n"); |
f13bdbd1 AA |
317 | } |
318 | ||
5b1d5bc6 | 319 | static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win, |
f181a543 YC |
320 | bool enable) |
321 | { | |
322 | u32 val = readl(ctx->regs + WINCON(win)); | |
323 | ||
324 | if (enable) | |
325 | val |= WINCONx_ENWIN; | |
326 | else | |
327 | val &= ~WINCONx_ENWIN; | |
328 | ||
329 | writel(val, ctx->regs + WINCON(win)); | |
330 | } | |
331 | ||
5b1d5bc6 TJ |
332 | static void fimd_enable_shadow_channel_path(struct fimd_context *ctx, |
333 | unsigned int win, | |
999d8b31 YC |
334 | bool enable) |
335 | { | |
336 | u32 val = readl(ctx->regs + SHADOWCON); | |
337 | ||
338 | if (enable) | |
339 | val |= SHADOWCON_CHx_ENABLE(win); | |
340 | else | |
341 | val &= ~SHADOWCON_CHx_ENABLE(win); | |
342 | ||
343 | writel(val, ctx->regs + SHADOWCON); | |
344 | } | |
345 | ||
fc2e013f | 346 | static void fimd_clear_channels(struct exynos_drm_crtc *crtc) |
f13bdbd1 | 347 | { |
fc2e013f | 348 | struct fimd_context *ctx = crtc->ctx; |
5b1d5bc6 | 349 | unsigned int win, ch_enabled = 0; |
f13bdbd1 | 350 | |
fb88e214 MS |
351 | /* Hardware is in unknown state, so ensure it gets enabled properly */ |
352 | pm_runtime_get_sync(ctx->dev); | |
353 | ||
354 | clk_prepare_enable(ctx->bus_clk); | |
355 | clk_prepare_enable(ctx->lcd_clk); | |
356 | ||
f13bdbd1 AA |
357 | /* Check if any channel is enabled. */ |
358 | for (win = 0; win < WINDOWS_NR; win++) { | |
eb8a3bf7 MS |
359 | u32 val = readl(ctx->regs + WINCON(win)); |
360 | ||
361 | if (val & WINCONx_ENWIN) { | |
f181a543 | 362 | fimd_enable_video_output(ctx, win, false); |
eb8a3bf7 | 363 | |
999d8b31 YC |
364 | if (ctx->driver_data->has_shadowcon) |
365 | fimd_enable_shadow_channel_path(ctx, win, | |
366 | false); | |
367 | ||
f13bdbd1 AA |
368 | ch_enabled = 1; |
369 | } | |
370 | } | |
371 | ||
372 | /* Wait for vsync, as disable channel takes effect at next vsync */ | |
eb8a3bf7 | 373 | if (ch_enabled) { |
fb88e214 | 374 | ctx->suspended = false; |
eb8a3bf7 | 375 | |
fb88e214 | 376 | fimd_enable_vblank(ctx->crtc); |
92dc7a04 | 377 | fimd_wait_for_vblank(ctx->crtc); |
fb88e214 MS |
378 | fimd_disable_vblank(ctx->crtc); |
379 | ||
380 | ctx->suspended = true; | |
eb8a3bf7 | 381 | } |
fb88e214 MS |
382 | |
383 | clk_disable_unprepare(ctx->lcd_clk); | |
384 | clk_disable_unprepare(ctx->bus_clk); | |
385 | ||
386 | pm_runtime_put(ctx->dev); | |
f13bdbd1 AA |
387 | } |
388 | ||
c96fdfde AH |
389 | |
390 | static int fimd_atomic_check(struct exynos_drm_crtc *crtc, | |
391 | struct drm_crtc_state *state) | |
a968e727 | 392 | { |
c96fdfde AH |
393 | struct drm_display_mode *mode = &state->adjusted_mode; |
394 | struct fimd_context *ctx = crtc->ctx; | |
395 | unsigned long ideal_clk, lcd_rate; | |
a968e727 SP |
396 | u32 clkdiv; |
397 | ||
fa9971d6 | 398 | if (mode->clock == 0) { |
6f83d208 | 399 | DRM_DEV_ERROR(ctx->dev, "Mode has zero clock value.\n"); |
c96fdfde | 400 | return -EINVAL; |
fa9971d6 TJ |
401 | } |
402 | ||
403 | ideal_clk = mode->clock * 1000; | |
404 | ||
3854fab2 YC |
405 | if (ctx->i80_if) { |
406 | /* | |
407 | * The frame done interrupt should be occurred prior to the | |
408 | * next TE signal. | |
409 | */ | |
410 | ideal_clk *= 2; | |
411 | } | |
412 | ||
c96fdfde AH |
413 | lcd_rate = clk_get_rate(ctx->lcd_clk); |
414 | if (2 * lcd_rate < ideal_clk) { | |
6f83d208 ID |
415 | DRM_DEV_ERROR(ctx->dev, |
416 | "sclk_fimd clock too low(%lu) for requested pixel clock(%lu)\n", | |
417 | lcd_rate, ideal_clk); | |
c96fdfde AH |
418 | return -EINVAL; |
419 | } | |
420 | ||
a968e727 | 421 | /* Find the clock divider value that gets us closest to ideal_clk */ |
c96fdfde AH |
422 | clkdiv = DIV_ROUND_CLOSEST(lcd_rate, ideal_clk); |
423 | if (clkdiv >= 0x200) { | |
6f83d208 ID |
424 | DRM_DEV_ERROR(ctx->dev, "requested pixel clock(%lu) too low\n", |
425 | ideal_clk); | |
c96fdfde AH |
426 | return -EINVAL; |
427 | } | |
428 | ||
429 | ctx->clkdiv = (clkdiv < 0x100) ? clkdiv : 0xff; | |
a968e727 | 430 | |
c96fdfde | 431 | return 0; |
a968e727 SP |
432 | } |
433 | ||
a6f75aa1 ID |
434 | static void fimd_setup_trigger(struct fimd_context *ctx) |
435 | { | |
436 | void __iomem *timing_base = ctx->regs + ctx->driver_data->timing_base; | |
437 | u32 trg_type = ctx->driver_data->trg_type; | |
438 | u32 val = readl(timing_base + TRIGCON); | |
439 | ||
b5bf0f1e | 440 | val &= ~(TRGMODE_ENABLE); |
a6f75aa1 ID |
441 | |
442 | if (trg_type == I80_HW_TRG) { | |
443 | if (ctx->driver_data->has_hw_trigger) | |
b5bf0f1e | 444 | val |= HWTRGEN_ENABLE | HWTRGMASK_ENABLE; |
a6f75aa1 | 445 | if (ctx->driver_data->has_trigger_per_te) |
b5bf0f1e | 446 | val |= HWTRIGEN_PER_ENABLE; |
a6f75aa1 | 447 | } else { |
b5bf0f1e | 448 | val |= TRGMODE_ENABLE; |
a6f75aa1 ID |
449 | } |
450 | ||
451 | writel(val, timing_base + TRIGCON); | |
452 | } | |
453 | ||
93bca243 | 454 | static void fimd_commit(struct exynos_drm_crtc *crtc) |
1c248b7d | 455 | { |
93bca243 | 456 | struct fimd_context *ctx = crtc->ctx; |
020e79de | 457 | struct drm_display_mode *mode = &crtc->base.state->adjusted_mode; |
e1a7b9b4 | 458 | const struct fimd_driver_data *driver_data = ctx->driver_data; |
3854fab2 | 459 | void *timing_base = ctx->regs + driver_data->timing_base; |
c96fdfde | 460 | u32 val; |
1c248b7d | 461 | |
e30d4bcf ID |
462 | if (ctx->suspended) |
463 | return; | |
464 | ||
a968e727 SP |
465 | /* nothing to do if we haven't set the mode yet */ |
466 | if (mode->htotal == 0 || mode->vtotal == 0) | |
467 | return; | |
468 | ||
3854fab2 YC |
469 | if (ctx->i80_if) { |
470 | val = ctx->i80ifcon | I80IFEN_ENABLE; | |
471 | writel(val, timing_base + I80IFCONFAx(0)); | |
472 | ||
473 | /* disable auto frame rate */ | |
474 | writel(0, timing_base + I80IFCONFBx(0)); | |
475 | ||
476 | /* set video type selection to I80 interface */ | |
3c3c9c1d JS |
477 | if (driver_data->has_vtsel && ctx->sysreg && |
478 | regmap_update_bits(ctx->sysreg, | |
3854fab2 YC |
479 | driver_data->lcdblk_offset, |
480 | 0x3 << driver_data->lcdblk_vt_shift, | |
481 | 0x1 << driver_data->lcdblk_vt_shift)) { | |
6f83d208 ID |
482 | DRM_DEV_ERROR(ctx->dev, |
483 | "Failed to update sysreg for I80 i/f.\n"); | |
3854fab2 YC |
484 | return; |
485 | } | |
486 | } else { | |
487 | int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd; | |
488 | u32 vidcon1; | |
489 | ||
490 | /* setup polarity values */ | |
491 | vidcon1 = ctx->vidcon1; | |
492 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
493 | vidcon1 |= VIDCON1_INV_VSYNC; | |
494 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
495 | vidcon1 |= VIDCON1_INV_HSYNC; | |
496 | writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1); | |
497 | ||
498 | /* setup vertical timing values. */ | |
499 | vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; | |
500 | vbpd = mode->crtc_vtotal - mode->crtc_vsync_end; | |
501 | vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay; | |
502 | ||
503 | val = VIDTCON0_VBPD(vbpd - 1) | | |
504 | VIDTCON0_VFPD(vfpd - 1) | | |
505 | VIDTCON0_VSPW(vsync_len - 1); | |
506 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON0); | |
507 | ||
508 | /* setup horizontal timing values. */ | |
509 | hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; | |
510 | hbpd = mode->crtc_htotal - mode->crtc_hsync_end; | |
511 | hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay; | |
512 | ||
513 | val = VIDTCON1_HBPD(hbpd - 1) | | |
514 | VIDTCON1_HFPD(hfpd - 1) | | |
515 | VIDTCON1_HSPW(hsync_len - 1); | |
516 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON1); | |
517 | } | |
518 | ||
519 | if (driver_data->has_vidoutcon) | |
520 | writel(ctx->vidout_con, timing_base + VIDOUT_CON); | |
521 | ||
522 | /* set bypass selection */ | |
523 | if (ctx->sysreg && regmap_update_bits(ctx->sysreg, | |
524 | driver_data->lcdblk_offset, | |
525 | 0x1 << driver_data->lcdblk_bypass_shift, | |
526 | 0x1 << driver_data->lcdblk_bypass_shift)) { | |
6f83d208 ID |
527 | DRM_DEV_ERROR(ctx->dev, |
528 | "Failed to update sysreg for bypass setting.\n"); | |
3854fab2 YC |
529 | return; |
530 | } | |
1c248b7d | 531 | |
1feafd3a CP |
532 | /* TODO: When MIC is enabled for display path, the lcdblk_mic_bypass |
533 | * bit should be cleared. | |
534 | */ | |
535 | if (driver_data->has_mic_bypass && ctx->sysreg && | |
536 | regmap_update_bits(ctx->sysreg, | |
537 | driver_data->lcdblk_offset, | |
538 | 0x1 << driver_data->lcdblk_mic_bypass_shift, | |
539 | 0x1 << driver_data->lcdblk_mic_bypass_shift)) { | |
6f83d208 ID |
540 | DRM_DEV_ERROR(ctx->dev, |
541 | "Failed to update sysreg for bypass mic.\n"); | |
1feafd3a CP |
542 | return; |
543 | } | |
544 | ||
1c248b7d | 545 | /* setup horizontal and vertical display size. */ |
a968e727 SP |
546 | val = VIDTCON2_LINEVAL(mode->vdisplay - 1) | |
547 | VIDTCON2_HOZVAL(mode->hdisplay - 1) | | |
548 | VIDTCON2_LINEVAL_E(mode->vdisplay - 1) | | |
549 | VIDTCON2_HOZVAL_E(mode->hdisplay - 1); | |
e2e13389 | 550 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON2); |
1c248b7d | 551 | |
a6f75aa1 ID |
552 | fimd_setup_trigger(ctx); |
553 | ||
1d531062 AH |
554 | /* |
555 | * fields of register with prefix '_F' would be updated | |
556 | * at vsync(same as dma start) | |
557 | */ | |
3854fab2 YC |
558 | val = ctx->vidcon0; |
559 | val |= VIDCON0_ENVID | VIDCON0_ENVID_F; | |
1c248b7d | 560 | |
1d531062 | 561 | if (ctx->driver_data->has_clksel) |
411d9ed4 | 562 | val |= VIDCON0_CLKSEL_LCD; |
411d9ed4 | 563 | |
c96fdfde AH |
564 | if (ctx->clkdiv > 1) |
565 | val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR; | |
1c248b7d | 566 | |
1c248b7d ID |
567 | writel(val, ctx->regs + VIDCON0); |
568 | } | |
569 | ||
3b5129b3 CM |
570 | static void fimd_win_set_bldeq(struct fimd_context *ctx, unsigned int win, |
571 | unsigned int alpha, unsigned int pixel_alpha) | |
572 | { | |
573 | u32 mask = BLENDEQ_A_FUNC_F(0xf) | BLENDEQ_B_FUNC_F(0xf); | |
574 | u32 val = 0; | |
575 | ||
576 | switch (pixel_alpha) { | |
577 | case DRM_MODE_BLEND_PIXEL_NONE: | |
578 | case DRM_MODE_BLEND_COVERAGE: | |
579 | val |= BLENDEQ_A_FUNC_F(BLENDEQ_ALPHA_A); | |
580 | val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A); | |
581 | break; | |
582 | case DRM_MODE_BLEND_PREMULTI: | |
583 | default: | |
584 | if (alpha != DRM_BLEND_ALPHA_OPAQUE) { | |
585 | val |= BLENDEQ_A_FUNC_F(BLENDEQ_ALPHA0); | |
586 | val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A); | |
587 | } else { | |
588 | val |= BLENDEQ_A_FUNC_F(BLENDEQ_ONE); | |
589 | val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A); | |
590 | } | |
591 | break; | |
592 | } | |
593 | fimd_set_bits(ctx, BLENDEQx(win), mask, val); | |
594 | } | |
595 | ||
6f8ee5c2 | 596 | static void fimd_win_set_bldmod(struct fimd_context *ctx, unsigned int win, |
3b5129b3 | 597 | unsigned int alpha, unsigned int pixel_alpha) |
6f8ee5c2 CM |
598 | { |
599 | u32 win_alpha_l = (alpha >> 8) & 0xf; | |
600 | u32 win_alpha_h = alpha >> 12; | |
601 | u32 val = 0; | |
602 | ||
3b5129b3 CM |
603 | switch (pixel_alpha) { |
604 | case DRM_MODE_BLEND_PIXEL_NONE: | |
605 | break; | |
606 | case DRM_MODE_BLEND_COVERAGE: | |
607 | case DRM_MODE_BLEND_PREMULTI: | |
608 | default: | |
609 | val |= WINCON1_ALPHA_SEL; | |
610 | val |= WINCON1_BLD_PIX; | |
611 | val |= WINCON1_ALPHA_MUL; | |
612 | break; | |
613 | } | |
614 | fimd_set_bits(ctx, WINCON(win), WINCONx_BLEND_MODE_MASK, val); | |
615 | ||
6f8ee5c2 CM |
616 | /* OSD alpha */ |
617 | val = VIDISD14C_ALPHA0_R(win_alpha_h) | | |
618 | VIDISD14C_ALPHA0_G(win_alpha_h) | | |
619 | VIDISD14C_ALPHA0_B(win_alpha_h) | | |
620 | VIDISD14C_ALPHA1_R(0x0) | | |
621 | VIDISD14C_ALPHA1_G(0x0) | | |
622 | VIDISD14C_ALPHA1_B(0x0); | |
623 | writel(val, ctx->regs + VIDOSD_C(win)); | |
624 | ||
625 | val = VIDW_ALPHA_R(win_alpha_l) | VIDW_ALPHA_G(win_alpha_l) | | |
626 | VIDW_ALPHA_B(win_alpha_l); | |
627 | writel(val, ctx->regs + VIDWnALPHA0(win)); | |
628 | ||
629 | val = VIDW_ALPHA_R(0x0) | VIDW_ALPHA_G(0x0) | | |
630 | VIDW_ALPHA_B(0x0); | |
631 | writel(val, ctx->regs + VIDWnALPHA1(win)); | |
632 | ||
633 | fimd_set_bits(ctx, BLENDCON, BLENDCON_NEW_MASK, | |
634 | BLENDCON_NEW_8BIT_ALPHA_VALUE); | |
635 | } | |
1c248b7d | 636 | |
2eeb2e5e | 637 | static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win, |
6f8ee5c2 | 638 | struct drm_framebuffer *fb, int width) |
1c248b7d | 639 | { |
6f8ee5c2 CM |
640 | struct exynos_drm_plane plane = ctx->planes[win]; |
641 | struct exynos_drm_plane_state *state = | |
642 | to_exynos_plane_state(plane.base.state); | |
643 | uint32_t pixel_format = fb->format->format; | |
644 | unsigned int alpha = state->base.alpha; | |
645 | u32 val = WINCONx_ENWIN; | |
3b5129b3 CM |
646 | unsigned int pixel_alpha; |
647 | ||
648 | if (fb->format->has_alpha) | |
649 | pixel_alpha = state->base.pixel_blend_mode; | |
650 | else | |
651 | pixel_alpha = DRM_MODE_BLEND_PIXEL_NONE; | |
1c248b7d | 652 | |
5cc4621a ID |
653 | /* |
654 | * In case of s3c64xx, window 0 doesn't support alpha channel. | |
655 | * So the request format is ARGB8888 then change it to XRGB8888. | |
656 | */ | |
657 | if (ctx->driver_data->has_limited_fmt && !win) { | |
8b704d8a MS |
658 | if (pixel_format == DRM_FORMAT_ARGB8888) |
659 | pixel_format = DRM_FORMAT_XRGB8888; | |
5cc4621a ID |
660 | } |
661 | ||
8b704d8a | 662 | switch (pixel_format) { |
a4f38a80 | 663 | case DRM_FORMAT_C8: |
1c248b7d ID |
664 | val |= WINCON0_BPPMODE_8BPP_PALETTE; |
665 | val |= WINCONx_BURSTLEN_8WORD; | |
666 | val |= WINCONx_BYTSWP; | |
667 | break; | |
a4f38a80 ID |
668 | case DRM_FORMAT_XRGB1555: |
669 | val |= WINCON0_BPPMODE_16BPP_1555; | |
670 | val |= WINCONx_HAWSWP; | |
671 | val |= WINCONx_BURSTLEN_16WORD; | |
672 | break; | |
673 | case DRM_FORMAT_RGB565: | |
1c248b7d ID |
674 | val |= WINCON0_BPPMODE_16BPP_565; |
675 | val |= WINCONx_HAWSWP; | |
676 | val |= WINCONx_BURSTLEN_16WORD; | |
677 | break; | |
a4f38a80 | 678 | case DRM_FORMAT_XRGB8888: |
1c248b7d ID |
679 | val |= WINCON0_BPPMODE_24BPP_888; |
680 | val |= WINCONx_WSWP; | |
681 | val |= WINCONx_BURSTLEN_16WORD; | |
682 | break; | |
a4f38a80 | 683 | case DRM_FORMAT_ARGB8888: |
5b7b1b7f | 684 | default: |
3b5129b3 | 685 | val |= WINCON1_BPPMODE_25BPP_A1888; |
1c248b7d ID |
686 | val |= WINCONx_WSWP; |
687 | val |= WINCONx_BURSTLEN_16WORD; | |
688 | break; | |
1c248b7d ID |
689 | } |
690 | ||
66367461 | 691 | /* |
8b704d8a MS |
692 | * Setting dma-burst to 16Word causes permanent tearing for very small |
693 | * buffers, e.g. cursor buffer. Burst Mode switching which based on | |
694 | * plane size is not recommended as plane size varies alot towards the | |
695 | * end of the screen and rapid movement causes unstable DMA, but it is | |
696 | * still better to change dma-burst than displaying garbage. | |
66367461 RS |
697 | */ |
698 | ||
8b704d8a | 699 | if (width < MIN_FB_WIDTH_FOR_16WORD_BURST) { |
66367461 RS |
700 | val &= ~WINCONx_BURSTLEN_MASK; |
701 | val |= WINCONx_BURSTLEN_4WORD; | |
702 | } | |
3b5129b3 | 703 | fimd_set_bits(ctx, WINCON(win), ~WINCONx_BLEND_MODE_MASK, val); |
453b44a3 GP |
704 | |
705 | /* hardware window 0 doesn't support alpha channel. */ | |
3b5129b3 CM |
706 | if (win != 0) { |
707 | fimd_win_set_bldmod(ctx, win, alpha, pixel_alpha); | |
708 | fimd_win_set_bldeq(ctx, win, alpha, pixel_alpha); | |
709 | } | |
1c248b7d ID |
710 | } |
711 | ||
bb7704d6 | 712 | static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win) |
1c248b7d | 713 | { |
1c248b7d ID |
714 | unsigned int keycon0 = 0, keycon1 = 0; |
715 | ||
1c248b7d ID |
716 | keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F | |
717 | WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); | |
718 | ||
719 | keycon1 = WxKEYCON1_COLVAL(0xffffffff); | |
720 | ||
721 | writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); | |
722 | writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); | |
723 | } | |
724 | ||
de7af100 TF |
725 | /** |
726 | * shadow_protect_win() - disable updating values from shadow registers at vsync | |
727 | * | |
728 | * @win: window to protect registers for | |
729 | * @protect: 1 to protect (disable updates) | |
730 | */ | |
731 | static void fimd_shadow_protect_win(struct fimd_context *ctx, | |
6e2a3b66 | 732 | unsigned int win, bool protect) |
de7af100 TF |
733 | { |
734 | u32 reg, bits, val; | |
735 | ||
ce3ff36b GP |
736 | /* |
737 | * SHADOWCON/PRTCON register is used for enabling timing. | |
738 | * | |
739 | * for example, once only width value of a register is set, | |
740 | * if the dma is started then fimd hardware could malfunction so | |
741 | * with protect window setting, the register fields with prefix '_F' | |
742 | * wouldn't be updated at vsync also but updated once unprotect window | |
743 | * is set. | |
744 | */ | |
745 | ||
de7af100 TF |
746 | if (ctx->driver_data->has_shadowcon) { |
747 | reg = SHADOWCON; | |
748 | bits = SHADOWCON_WINx_PROTECT(win); | |
749 | } else { | |
750 | reg = PRTCON; | |
751 | bits = PRTCON_PROTECT; | |
752 | } | |
753 | ||
754 | val = readl(ctx->regs + reg); | |
755 | if (protect) | |
756 | val |= bits; | |
757 | else | |
758 | val &= ~bits; | |
759 | writel(val, ctx->regs + reg); | |
760 | } | |
761 | ||
d29c2c14 | 762 | static void fimd_atomic_begin(struct exynos_drm_crtc *crtc) |
ce3ff36b GP |
763 | { |
764 | struct fimd_context *ctx = crtc->ctx; | |
d29c2c14 | 765 | int i; |
ce3ff36b GP |
766 | |
767 | if (ctx->suspended) | |
768 | return; | |
769 | ||
d29c2c14 MS |
770 | for (i = 0; i < WINDOWS_NR; i++) |
771 | fimd_shadow_protect_win(ctx, i, true); | |
ce3ff36b GP |
772 | } |
773 | ||
d29c2c14 | 774 | static void fimd_atomic_flush(struct exynos_drm_crtc *crtc) |
ce3ff36b GP |
775 | { |
776 | struct fimd_context *ctx = crtc->ctx; | |
d29c2c14 | 777 | int i; |
ce3ff36b GP |
778 | |
779 | if (ctx->suspended) | |
780 | return; | |
781 | ||
d29c2c14 MS |
782 | for (i = 0; i < WINDOWS_NR; i++) |
783 | fimd_shadow_protect_win(ctx, i, false); | |
a392276d AH |
784 | |
785 | exynos_crtc_handle_event(crtc); | |
ce3ff36b GP |
786 | } |
787 | ||
1e1d1393 GP |
788 | static void fimd_update_plane(struct exynos_drm_crtc *crtc, |
789 | struct exynos_drm_plane *plane) | |
1c248b7d | 790 | { |
0114f404 MS |
791 | struct exynos_drm_plane_state *state = |
792 | to_exynos_plane_state(plane->base.state); | |
93bca243 | 793 | struct fimd_context *ctx = crtc->ctx; |
0114f404 | 794 | struct drm_framebuffer *fb = state->base.fb; |
7ee14cdc GP |
795 | dma_addr_t dma_addr; |
796 | unsigned long val, size, offset; | |
797 | unsigned int last_x, last_y, buf_offsize, line_size; | |
40bdfb0a | 798 | unsigned int win = plane->index; |
ac60944c | 799 | unsigned int cpp = fb->format->cpp[0]; |
0488f50e | 800 | unsigned int pitch = fb->pitches[0]; |
1c248b7d | 801 | |
e30d4bcf ID |
802 | if (ctx->suspended) |
803 | return; | |
804 | ||
ac60944c | 805 | offset = state->src.x * cpp; |
0114f404 | 806 | offset += state->src.y * pitch; |
7ee14cdc | 807 | |
1c248b7d | 808 | /* buffer start address */ |
0488f50e | 809 | dma_addr = exynos_drm_fb_dma_addr(fb, 0) + offset; |
7ee14cdc | 810 | val = (unsigned long)dma_addr; |
1c248b7d ID |
811 | writel(val, ctx->regs + VIDWx_BUF_START(win, 0)); |
812 | ||
813 | /* buffer end address */ | |
0114f404 | 814 | size = pitch * state->crtc.h; |
7ee14cdc | 815 | val = (unsigned long)(dma_addr + size); |
1c248b7d ID |
816 | writel(val, ctx->regs + VIDWx_BUF_END(win, 0)); |
817 | ||
6be90056 ID |
818 | DRM_DEV_DEBUG_KMS(ctx->dev, |
819 | "start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n", | |
820 | (unsigned long)dma_addr, val, size); | |
821 | DRM_DEV_DEBUG_KMS(ctx->dev, "ovl_width = %d, ovl_height = %d\n", | |
822 | state->crtc.w, state->crtc.h); | |
1c248b7d ID |
823 | |
824 | /* buffer size */ | |
ac60944c TJ |
825 | buf_offsize = pitch - (state->crtc.w * cpp); |
826 | line_size = state->crtc.w * cpp; | |
7ee14cdc GP |
827 | val = VIDW_BUF_SIZE_OFFSET(buf_offsize) | |
828 | VIDW_BUF_SIZE_PAGEWIDTH(line_size) | | |
829 | VIDW_BUF_SIZE_OFFSET_E(buf_offsize) | | |
830 | VIDW_BUF_SIZE_PAGEWIDTH_E(line_size); | |
1c248b7d ID |
831 | writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0)); |
832 | ||
833 | /* OSD position */ | |
0114f404 MS |
834 | val = VIDOSDxA_TOPLEFT_X(state->crtc.x) | |
835 | VIDOSDxA_TOPLEFT_Y(state->crtc.y) | | |
836 | VIDOSDxA_TOPLEFT_X_E(state->crtc.x) | | |
837 | VIDOSDxA_TOPLEFT_Y_E(state->crtc.y); | |
1c248b7d ID |
838 | writel(val, ctx->regs + VIDOSD_A(win)); |
839 | ||
0114f404 | 840 | last_x = state->crtc.x + state->crtc.w; |
f56aad3a JS |
841 | if (last_x) |
842 | last_x--; | |
0114f404 | 843 | last_y = state->crtc.y + state->crtc.h; |
f56aad3a JS |
844 | if (last_y) |
845 | last_y--; | |
846 | ||
ca555e5a JS |
847 | val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) | |
848 | VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y); | |
849 | ||
1c248b7d ID |
850 | writel(val, ctx->regs + VIDOSD_B(win)); |
851 | ||
6be90056 ID |
852 | DRM_DEV_DEBUG_KMS(ctx->dev, |
853 | "osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", | |
854 | state->crtc.x, state->crtc.y, last_x, last_y); | |
1c248b7d | 855 | |
1c248b7d ID |
856 | /* OSD size */ |
857 | if (win != 3 && win != 4) { | |
858 | u32 offset = VIDOSD_D(win); | |
859 | if (win == 0) | |
0f10cf14 | 860 | offset = VIDOSD_C(win); |
0114f404 | 861 | val = state->crtc.w * state->crtc.h; |
1c248b7d ID |
862 | writel(val, ctx->regs + offset); |
863 | ||
6be90056 ID |
864 | DRM_DEV_DEBUG_KMS(ctx->dev, "osd size = 0x%x\n", |
865 | (unsigned int)val); | |
1c248b7d ID |
866 | } |
867 | ||
6f8ee5c2 | 868 | fimd_win_set_pixfmt(ctx, win, fb, state->src.w); |
1c248b7d ID |
869 | |
870 | /* hardware window 0 doesn't support color key. */ | |
871 | if (win != 0) | |
bb7704d6 | 872 | fimd_win_set_colkey(ctx, win); |
1c248b7d | 873 | |
f181a543 | 874 | fimd_enable_video_output(ctx, win, true); |
ec05da95 | 875 | |
999d8b31 YC |
876 | if (ctx->driver_data->has_shadowcon) |
877 | fimd_enable_shadow_channel_path(ctx, win, true); | |
ec05da95 | 878 | |
3854fab2 YC |
879 | if (ctx->i80_if) |
880 | atomic_set(&ctx->win_updated, 1); | |
1c248b7d ID |
881 | } |
882 | ||
1e1d1393 GP |
883 | static void fimd_disable_plane(struct exynos_drm_crtc *crtc, |
884 | struct exynos_drm_plane *plane) | |
1c248b7d | 885 | { |
93bca243 | 886 | struct fimd_context *ctx = crtc->ctx; |
40bdfb0a | 887 | unsigned int win = plane->index; |
ec05da95 | 888 | |
c329f667 | 889 | if (ctx->suspended) |
db7e55ae | 890 | return; |
db7e55ae | 891 | |
f181a543 | 892 | fimd_enable_video_output(ctx, win, false); |
1c248b7d | 893 | |
999d8b31 YC |
894 | if (ctx->driver_data->has_shadowcon) |
895 | fimd_enable_shadow_channel_path(ctx, win, false); | |
a43b933b SP |
896 | } |
897 | ||
11f95489 | 898 | static void fimd_atomic_enable(struct exynos_drm_crtc *crtc) |
a43b933b | 899 | { |
3cecda03 | 900 | struct fimd_context *ctx = crtc->ctx; |
a43b933b SP |
901 | |
902 | if (!ctx->suspended) | |
3cecda03 | 903 | return; |
a43b933b SP |
904 | |
905 | ctx->suspended = false; | |
906 | ||
af65c804 SP |
907 | pm_runtime_get_sync(ctx->dev); |
908 | ||
a43b933b | 909 | /* if vblank was enabled status, enable it again. */ |
3cecda03 GP |
910 | if (test_and_clear_bit(0, &ctx->irq_flags)) |
911 | fimd_enable_vblank(ctx->crtc); | |
a43b933b | 912 | |
c329f667 | 913 | fimd_commit(ctx->crtc); |
a43b933b SP |
914 | } |
915 | ||
11f95489 | 916 | static void fimd_atomic_disable(struct exynos_drm_crtc *crtc) |
a43b933b | 917 | { |
3cecda03 | 918 | struct fimd_context *ctx = crtc->ctx; |
c329f667 | 919 | int i; |
3cecda03 | 920 | |
a43b933b | 921 | if (ctx->suspended) |
3cecda03 | 922 | return; |
a43b933b SP |
923 | |
924 | /* | |
925 | * We need to make sure that all windows are disabled before we | |
926 | * suspend that connector. Otherwise we might try to scan from | |
927 | * a destroyed buffer later. | |
928 | */ | |
c329f667 | 929 | for (i = 0; i < WINDOWS_NR; i++) |
1e1d1393 | 930 | fimd_disable_plane(crtc, &ctx->planes[i]); |
a43b933b | 931 | |
94ab95a9 ID |
932 | fimd_enable_vblank(crtc); |
933 | fimd_wait_for_vblank(crtc); | |
934 | fimd_disable_vblank(crtc); | |
935 | ||
b74f14fd JS |
936 | writel(0, ctx->regs + VIDCON0); |
937 | ||
af65c804 | 938 | pm_runtime_put_sync(ctx->dev); |
a43b933b | 939 | ctx->suspended = true; |
080be03d SP |
940 | } |
941 | ||
3854fab2 YC |
942 | static void fimd_trigger(struct device *dev) |
943 | { | |
e152dbd7 | 944 | struct fimd_context *ctx = dev_get_drvdata(dev); |
e1a7b9b4 | 945 | const struct fimd_driver_data *driver_data = ctx->driver_data; |
3854fab2 YC |
946 | void *timing_base = ctx->regs + driver_data->timing_base; |
947 | u32 reg; | |
948 | ||
9b67eb73 | 949 | /* |
1c905d95 YC |
950 | * Skips triggering if in triggering state, because multiple triggering |
951 | * requests can cause panel reset. | |
952 | */ | |
9b67eb73 JS |
953 | if (atomic_read(&ctx->triggering)) |
954 | return; | |
955 | ||
1c905d95 | 956 | /* Enters triggering mode */ |
3854fab2 YC |
957 | atomic_set(&ctx->triggering, 1); |
958 | ||
3854fab2 | 959 | reg = readl(timing_base + TRIGCON); |
b5bf0f1e | 960 | reg |= (TRGMODE_ENABLE | SWTRGCMD_ENABLE); |
3854fab2 | 961 | writel(reg, timing_base + TRIGCON); |
87ab85b3 YC |
962 | |
963 | /* | |
964 | * Exits triggering mode if vblank is not enabled yet, because when the | |
965 | * VIDINTCON0 register is not set, it can not exit from triggering mode. | |
966 | */ | |
967 | if (!test_bit(0, &ctx->irq_flags)) | |
968 | atomic_set(&ctx->triggering, 0); | |
3854fab2 YC |
969 | } |
970 | ||
93bca243 | 971 | static void fimd_te_handler(struct exynos_drm_crtc *crtc) |
3854fab2 | 972 | { |
93bca243 | 973 | struct fimd_context *ctx = crtc->ctx; |
a6f75aa1 | 974 | u32 trg_type = ctx->driver_data->trg_type; |
3854fab2 YC |
975 | |
976 | /* Checks the crtc is detached already from encoder */ | |
2949390e | 977 | if (!ctx->drm_dev) |
3854fab2 YC |
978 | return; |
979 | ||
a6f75aa1 ID |
980 | if (trg_type == I80_HW_TRG) |
981 | goto out; | |
982 | ||
3854fab2 YC |
983 | /* |
984 | * If there is a page flip request, triggers and handles the page flip | |
985 | * event so that current fb can be updated into panel GRAM. | |
986 | */ | |
987 | if (atomic_add_unless(&ctx->win_updated, -1, 0)) | |
988 | fimd_trigger(ctx->dev); | |
989 | ||
a6f75aa1 | 990 | out: |
3854fab2 YC |
991 | /* Wakes up vsync event queue */ |
992 | if (atomic_read(&ctx->wait_vsync_event)) { | |
993 | atomic_set(&ctx->wait_vsync_event, 0); | |
994 | wake_up(&ctx->wait_vsync_queue); | |
3854fab2 | 995 | } |
b301ae24 | 996 | |
adf67abf | 997 | if (test_bit(0, &ctx->irq_flags)) |
eafd540a | 998 | drm_crtc_handle_vblank(&ctx->crtc->base); |
3854fab2 YC |
999 | } |
1000 | ||
196e059a | 1001 | static void fimd_dp_clock_enable(struct exynos_drm_clk *clk, bool enable) |
48107d7b | 1002 | { |
196e059a AH |
1003 | struct fimd_context *ctx = container_of(clk, struct fimd_context, |
1004 | dp_clk); | |
1005 | u32 val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE; | |
3c79fb8c | 1006 | writel(val, ctx->regs + DP_MIE_CLKCON); |
48107d7b KK |
1007 | } |
1008 | ||
f3aaf762 | 1009 | static const struct exynos_drm_crtc_ops fimd_crtc_ops = { |
11f95489 ID |
1010 | .atomic_enable = fimd_atomic_enable, |
1011 | .atomic_disable = fimd_atomic_disable, | |
1c6244c3 SP |
1012 | .enable_vblank = fimd_enable_vblank, |
1013 | .disable_vblank = fimd_disable_vblank, | |
ce3ff36b | 1014 | .atomic_begin = fimd_atomic_begin, |
9cc7610a GP |
1015 | .update_plane = fimd_update_plane, |
1016 | .disable_plane = fimd_disable_plane, | |
ce3ff36b | 1017 | .atomic_flush = fimd_atomic_flush, |
c96fdfde | 1018 | .atomic_check = fimd_atomic_check, |
3854fab2 | 1019 | .te_handler = fimd_te_handler, |
1c248b7d ID |
1020 | }; |
1021 | ||
1c248b7d ID |
1022 | static irqreturn_t fimd_irq_handler(int irq, void *dev_id) |
1023 | { | |
1024 | struct fimd_context *ctx = (struct fimd_context *)dev_id; | |
9276dff7 | 1025 | u32 val, clear_bit; |
1c248b7d ID |
1026 | |
1027 | val = readl(ctx->regs + VIDINTCON1); | |
1028 | ||
3854fab2 YC |
1029 | clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME; |
1030 | if (val & clear_bit) | |
1031 | writel(clear_bit, ctx->regs + VIDINTCON1); | |
1c248b7d | 1032 | |
ec05da95 | 1033 | /* check the crtc is detached already from encoder */ |
2949390e | 1034 | if (!ctx->drm_dev) |
ec05da95 | 1035 | goto out; |
483b88f8 | 1036 | |
fc75f710 GP |
1037 | if (!ctx->i80_if) |
1038 | drm_crtc_handle_vblank(&ctx->crtc->base); | |
1039 | ||
fc75f710 | 1040 | if (ctx->i80_if) { |
1c905d95 | 1041 | /* Exits triggering mode */ |
3854fab2 | 1042 | atomic_set(&ctx->triggering, 0); |
3854fab2 | 1043 | } else { |
3854fab2 YC |
1044 | /* set wait vsync event to zero and wake up queue. */ |
1045 | if (atomic_read(&ctx->wait_vsync_event)) { | |
1046 | atomic_set(&ctx->wait_vsync_event, 0); | |
1047 | wake_up(&ctx->wait_vsync_queue); | |
1048 | } | |
01ce113c | 1049 | } |
3854fab2 | 1050 | |
ec05da95 | 1051 | out: |
1c248b7d ID |
1052 | return IRQ_HANDLED; |
1053 | } | |
1054 | ||
f37cd5e8 | 1055 | static int fimd_bind(struct device *dev, struct device *master, void *data) |
562ad9f4 | 1056 | { |
e152dbd7 | 1057 | struct fimd_context *ctx = dev_get_drvdata(dev); |
f37cd5e8 | 1058 | struct drm_device *drm_dev = data; |
7ee14cdc | 1059 | struct exynos_drm_plane *exynos_plane; |
fd2d2fc2 | 1060 | unsigned int i; |
6e2a3b66 | 1061 | int ret; |
000cc920 | 1062 | |
cdbfca89 | 1063 | ctx->drm_dev = drm_dev; |
efa75bcd | 1064 | |
fd2d2fc2 MS |
1065 | for (i = 0; i < WINDOWS_NR; i++) { |
1066 | ctx->configs[i].pixel_formats = fimd_formats; | |
1067 | ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats); | |
1068 | ctx->configs[i].zpos = i; | |
1069 | ctx->configs[i].type = fimd_win_types[i]; | |
6f8ee5c2 | 1070 | ctx->configs[i].capabilities = capabilities[i]; |
40bdfb0a | 1071 | ret = exynos_plane_init(drm_dev, &ctx->planes[i], i, |
2c82607b | 1072 | &ctx->configs[i]); |
7ee14cdc GP |
1073 | if (ret) |
1074 | return ret; | |
1075 | } | |
1076 | ||
5d3d0995 | 1077 | exynos_plane = &ctx->planes[DEFAULT_WIN]; |
7ee14cdc | 1078 | ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, |
d644951c | 1079 | EXYNOS_DISPLAY_TYPE_LCD, &fimd_crtc_ops, ctx); |
d1222842 HH |
1080 | if (IS_ERR(ctx->crtc)) |
1081 | return PTR_ERR(ctx->crtc); | |
93bca243 | 1082 | |
196e059a AH |
1083 | if (ctx->driver_data->has_dp_clk) { |
1084 | ctx->dp_clk.enable = fimd_dp_clock_enable; | |
1085 | ctx->crtc->pipe_clk = &ctx->dp_clk; | |
1086 | } | |
1087 | ||
cf67cc9a | 1088 | if (ctx->encoder) |
a2986e80 | 1089 | exynos_dpi_bind(drm_dev, ctx->encoder); |
000cc920 | 1090 | |
43a3b866 JS |
1091 | if (is_drm_iommu_supported(drm_dev)) |
1092 | fimd_clear_channels(ctx->crtc); | |
eb7a3fc7 | 1093 | |
07dc3678 | 1094 | return exynos_drm_register_dma(drm_dev, dev, &ctx->dma_priv); |
000cc920 AH |
1095 | } |
1096 | ||
1097 | static void fimd_unbind(struct device *dev, struct device *master, | |
1098 | void *data) | |
1099 | { | |
e152dbd7 | 1100 | struct fimd_context *ctx = dev_get_drvdata(dev); |
000cc920 | 1101 | |
11f95489 | 1102 | fimd_atomic_disable(ctx->crtc); |
000cc920 | 1103 | |
07dc3678 | 1104 | exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev, &ctx->dma_priv); |
cdbfca89 | 1105 | |
cf67cc9a GP |
1106 | if (ctx->encoder) |
1107 | exynos_dpi_remove(ctx->encoder); | |
000cc920 AH |
1108 | } |
1109 | ||
1110 | static const struct component_ops fimd_component_ops = { | |
1111 | .bind = fimd_bind, | |
1112 | .unbind = fimd_unbind, | |
1113 | }; | |
1114 | ||
1115 | static int fimd_probe(struct platform_device *pdev) | |
1116 | { | |
1117 | struct device *dev = &pdev->dev; | |
562ad9f4 | 1118 | struct fimd_context *ctx; |
3854fab2 | 1119 | struct device_node *i80_if_timings; |
562ad9f4 | 1120 | struct resource *res; |
fe42cfb4 | 1121 | int ret; |
1c248b7d | 1122 | |
e152dbd7 AH |
1123 | if (!dev->of_node) |
1124 | return -ENODEV; | |
2d3f173c | 1125 | |
d873ab99 | 1126 | ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); |
e152dbd7 AH |
1127 | if (!ctx) |
1128 | return -ENOMEM; | |
1129 | ||
bb7704d6 | 1130 | ctx->dev = dev; |
a43b933b | 1131 | ctx->suspended = true; |
e1a7b9b4 | 1132 | ctx->driver_data = of_device_get_match_data(dev); |
bb7704d6 | 1133 | |
1417f109 SP |
1134 | if (of_property_read_bool(dev->of_node, "samsung,invert-vden")) |
1135 | ctx->vidcon1 |= VIDCON1_INV_VDEN; | |
1136 | if (of_property_read_bool(dev->of_node, "samsung,invert-vclk")) | |
1137 | ctx->vidcon1 |= VIDCON1_INV_VCLK; | |
562ad9f4 | 1138 | |
3854fab2 YC |
1139 | i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings"); |
1140 | if (i80_if_timings) { | |
1141 | u32 val; | |
1142 | ||
1143 | ctx->i80_if = true; | |
1144 | ||
1145 | if (ctx->driver_data->has_vidoutcon) | |
1146 | ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0; | |
1147 | else | |
1148 | ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0; | |
1149 | /* | |
1150 | * The user manual describes that this "DSI_EN" bit is required | |
1151 | * to enable I80 24-bit data interface. | |
1152 | */ | |
1153 | ctx->vidcon0 |= VIDCON0_DSI_EN; | |
1154 | ||
1155 | if (of_property_read_u32(i80_if_timings, "cs-setup", &val)) | |
1156 | val = 0; | |
1157 | ctx->i80ifcon = LCD_CS_SETUP(val); | |
1158 | if (of_property_read_u32(i80_if_timings, "wr-setup", &val)) | |
1159 | val = 0; | |
1160 | ctx->i80ifcon |= LCD_WR_SETUP(val); | |
1161 | if (of_property_read_u32(i80_if_timings, "wr-active", &val)) | |
1162 | val = 1; | |
1163 | ctx->i80ifcon |= LCD_WR_ACTIVE(val); | |
1164 | if (of_property_read_u32(i80_if_timings, "wr-hold", &val)) | |
1165 | val = 0; | |
1166 | ctx->i80ifcon |= LCD_WR_HOLD(val); | |
1167 | } | |
1168 | of_node_put(i80_if_timings); | |
1169 | ||
1170 | ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node, | |
1171 | "samsung,sysreg"); | |
1172 | if (IS_ERR(ctx->sysreg)) { | |
1173 | dev_warn(dev, "failed to get system register.\n"); | |
1174 | ctx->sysreg = NULL; | |
1175 | } | |
1176 | ||
a968e727 SP |
1177 | ctx->bus_clk = devm_clk_get(dev, "fimd"); |
1178 | if (IS_ERR(ctx->bus_clk)) { | |
1179 | dev_err(dev, "failed to get bus clock\n"); | |
86650408 | 1180 | return PTR_ERR(ctx->bus_clk); |
a968e727 SP |
1181 | } |
1182 | ||
1183 | ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd"); | |
1184 | if (IS_ERR(ctx->lcd_clk)) { | |
1185 | dev_err(dev, "failed to get lcd clock\n"); | |
86650408 | 1186 | return PTR_ERR(ctx->lcd_clk); |
a968e727 | 1187 | } |
1c248b7d | 1188 | |
1c248b7d | 1189 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1c248b7d | 1190 | |
d873ab99 | 1191 | ctx->regs = devm_ioremap_resource(dev, res); |
86650408 AH |
1192 | if (IS_ERR(ctx->regs)) |
1193 | return PTR_ERR(ctx->regs); | |
1c248b7d | 1194 | |
3854fab2 YC |
1195 | res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, |
1196 | ctx->i80_if ? "lcd_sys" : "vsync"); | |
1c248b7d ID |
1197 | if (!res) { |
1198 | dev_err(dev, "irq request failed.\n"); | |
86650408 | 1199 | return -ENXIO; |
1c248b7d ID |
1200 | } |
1201 | ||
055e0c06 | 1202 | ret = devm_request_irq(dev, res->start, fimd_irq_handler, |
edc57266 SK |
1203 | 0, "drm_fimd", ctx); |
1204 | if (ret) { | |
1c248b7d | 1205 | dev_err(dev, "irq request failed.\n"); |
86650408 | 1206 | return ret; |
1c248b7d ID |
1207 | } |
1208 | ||
57ed0f7b | 1209 | init_waitqueue_head(&ctx->wait_vsync_queue); |
01ce113c | 1210 | atomic_set(&ctx->wait_vsync_event, 0); |
1c248b7d | 1211 | |
e152dbd7 | 1212 | platform_set_drvdata(pdev, ctx); |
14b6873a | 1213 | |
cf67cc9a GP |
1214 | ctx->encoder = exynos_dpi_probe(dev); |
1215 | if (IS_ERR(ctx->encoder)) | |
1216 | return PTR_ERR(ctx->encoder); | |
f37cd5e8 | 1217 | |
e152dbd7 | 1218 | pm_runtime_enable(dev); |
f37cd5e8 | 1219 | |
e152dbd7 | 1220 | ret = component_add(dev, &fimd_component_ops); |
df5225bc ID |
1221 | if (ret) |
1222 | goto err_disable_pm_runtime; | |
1223 | ||
1224 | return ret; | |
1225 | ||
1226 | err_disable_pm_runtime: | |
e152dbd7 | 1227 | pm_runtime_disable(dev); |
df5225bc | 1228 | |
df5225bc | 1229 | return ret; |
f37cd5e8 | 1230 | } |
cb91f6a0 | 1231 | |
f37cd5e8 ID |
1232 | static int fimd_remove(struct platform_device *pdev) |
1233 | { | |
af65c804 | 1234 | pm_runtime_disable(&pdev->dev); |
5d55393a | 1235 | |
df5225bc | 1236 | component_del(&pdev->dev, &fimd_component_ops); |
df5225bc | 1237 | |
5d55393a | 1238 | return 0; |
e30d4bcf ID |
1239 | } |
1240 | ||
41571976 GP |
1241 | #ifdef CONFIG_PM |
1242 | static int exynos_fimd_suspend(struct device *dev) | |
1243 | { | |
1244 | struct fimd_context *ctx = dev_get_drvdata(dev); | |
1245 | ||
1246 | clk_disable_unprepare(ctx->lcd_clk); | |
1247 | clk_disable_unprepare(ctx->bus_clk); | |
1248 | ||
1249 | return 0; | |
1250 | } | |
1251 | ||
1252 | static int exynos_fimd_resume(struct device *dev) | |
1253 | { | |
1254 | struct fimd_context *ctx = dev_get_drvdata(dev); | |
1255 | int ret; | |
1256 | ||
1257 | ret = clk_prepare_enable(ctx->bus_clk); | |
1258 | if (ret < 0) { | |
6f83d208 ID |
1259 | DRM_DEV_ERROR(dev, |
1260 | "Failed to prepare_enable the bus clk [%d]\n", | |
1261 | ret); | |
41571976 GP |
1262 | return ret; |
1263 | } | |
1264 | ||
1265 | ret = clk_prepare_enable(ctx->lcd_clk); | |
1266 | if (ret < 0) { | |
6f83d208 ID |
1267 | DRM_DEV_ERROR(dev, |
1268 | "Failed to prepare_enable the lcd clk [%d]\n", | |
1269 | ret); | |
41571976 GP |
1270 | return ret; |
1271 | } | |
1272 | ||
1273 | return 0; | |
1274 | } | |
1275 | #endif | |
1276 | ||
1277 | static const struct dev_pm_ops exynos_fimd_pm_ops = { | |
1278 | SET_RUNTIME_PM_OPS(exynos_fimd_suspend, exynos_fimd_resume, NULL) | |
7e915746 MS |
1279 | SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, |
1280 | pm_runtime_force_resume) | |
41571976 GP |
1281 | }; |
1282 | ||
132a5b91 | 1283 | struct platform_driver fimd_driver = { |
1c248b7d | 1284 | .probe = fimd_probe, |
56550d94 | 1285 | .remove = fimd_remove, |
1c248b7d ID |
1286 | .driver = { |
1287 | .name = "exynos4-fb", | |
1288 | .owner = THIS_MODULE, | |
41571976 | 1289 | .pm = &exynos_fimd_pm_ops, |
2d3f173c | 1290 | .of_match_table = fimd_driver_dt_match, |
1c248b7d ID |
1291 | }, |
1292 | }; |