]>
Commit | Line | Data |
---|---|---|
1c248b7d ID |
1 | /* exynos_drm_fimd.c |
2 | * | |
3 | * Copyright (C) 2011 Samsung Electronics Co.Ltd | |
4 | * Authors: | |
5 | * Joonyoung Shim <jy0922.shim@samsung.com> | |
6 | * Inki Dae <inki.dae@samsung.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | */ | |
760285e7 | 14 | #include <drm/drmP.h> |
1c248b7d ID |
15 | |
16 | #include <linux/kernel.h> | |
1c248b7d ID |
17 | #include <linux/platform_device.h> |
18 | #include <linux/clk.h> | |
3f1c781d | 19 | #include <linux/of.h> |
d636ead8 | 20 | #include <linux/of_device.h> |
cb91f6a0 | 21 | #include <linux/pm_runtime.h> |
1c248b7d | 22 | |
7f4596f4 | 23 | #include <video/of_display_timing.h> |
111e6055 | 24 | #include <video/of_videomode.h> |
5a213a55 | 25 | #include <video/samsung_fimd.h> |
1c248b7d | 26 | #include <drm/exynos_drm.h> |
1c248b7d ID |
27 | |
28 | #include "exynos_drm_drv.h" | |
29 | #include "exynos_drm_fbdev.h" | |
30 | #include "exynos_drm_crtc.h" | |
bcc5cd1c | 31 | #include "exynos_drm_iommu.h" |
1c248b7d ID |
32 | |
33 | /* | |
b8654b37 | 34 | * FIMD stands for Fully Interactive Mobile Display and |
1c248b7d ID |
35 | * as a display controller, it transfers contents drawn on memory |
36 | * to a LCD Panel through Display Interfaces such as RGB or | |
37 | * CPU Interface. | |
38 | */ | |
39 | ||
111e6055 AH |
40 | #define FIMD_DEFAULT_FRAMERATE 60 |
41 | ||
1c248b7d ID |
42 | /* position control register for hardware window 0, 2 ~ 4.*/ |
43 | #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16) | |
44 | #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16) | |
0f10cf14 LKA |
45 | /* |
46 | * size control register for hardware windows 0 and alpha control register | |
47 | * for hardware windows 1 ~ 4 | |
48 | */ | |
49 | #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16) | |
50 | /* size control register for hardware windows 1 ~ 2. */ | |
1c248b7d ID |
51 | #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16) |
52 | ||
53 | #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8) | |
54 | #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8) | |
55 | #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4) | |
56 | ||
57 | /* color key control register for hardware window 1 ~ 4. */ | |
0f10cf14 | 58 | #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8)) |
1c248b7d | 59 | /* color key value register for hardware window 1 ~ 4. */ |
0f10cf14 | 60 | #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8)) |
1c248b7d ID |
61 | |
62 | /* FIMD has totally five hardware windows. */ | |
63 | #define WINDOWS_NR 5 | |
64 | ||
bb7704d6 | 65 | #define get_fimd_manager(mgr) platform_get_drvdata(to_platform_device(dev)) |
1c248b7d | 66 | |
e2e13389 LKA |
67 | struct fimd_driver_data { |
68 | unsigned int timing_base; | |
de7af100 TF |
69 | |
70 | unsigned int has_shadowcon:1; | |
411d9ed4 | 71 | unsigned int has_clksel:1; |
5cc4621a | 72 | unsigned int has_limited_fmt:1; |
e2e13389 LKA |
73 | }; |
74 | ||
725ddead TF |
75 | static struct fimd_driver_data s3c64xx_fimd_driver_data = { |
76 | .timing_base = 0x0, | |
77 | .has_clksel = 1, | |
5cc4621a | 78 | .has_limited_fmt = 1, |
725ddead TF |
79 | }; |
80 | ||
6ecf18f9 | 81 | static struct fimd_driver_data exynos4_fimd_driver_data = { |
e2e13389 | 82 | .timing_base = 0x0, |
de7af100 | 83 | .has_shadowcon = 1, |
e2e13389 LKA |
84 | }; |
85 | ||
6ecf18f9 | 86 | static struct fimd_driver_data exynos5_fimd_driver_data = { |
e2e13389 | 87 | .timing_base = 0x20000, |
de7af100 | 88 | .has_shadowcon = 1, |
e2e13389 LKA |
89 | }; |
90 | ||
1c248b7d ID |
91 | struct fimd_win_data { |
92 | unsigned int offset_x; | |
93 | unsigned int offset_y; | |
19c8b834 ID |
94 | unsigned int ovl_width; |
95 | unsigned int ovl_height; | |
96 | unsigned int fb_width; | |
97 | unsigned int fb_height; | |
1c248b7d | 98 | unsigned int bpp; |
a4f38a80 | 99 | unsigned int pixel_format; |
2c871127 | 100 | dma_addr_t dma_addr; |
1c248b7d ID |
101 | unsigned int buf_offsize; |
102 | unsigned int line_size; /* bytes */ | |
ec05da95 | 103 | bool enabled; |
db7e55ae | 104 | bool resume; |
1c248b7d ID |
105 | }; |
106 | ||
107 | struct fimd_context { | |
108 | struct exynos_drm_subdrv subdrv; | |
bb7704d6 | 109 | struct device *dev; |
40c8ab4b | 110 | struct drm_device *drm_dev; |
1c248b7d ID |
111 | int irq; |
112 | struct drm_crtc *crtc; | |
113 | struct clk *bus_clk; | |
114 | struct clk *lcd_clk; | |
1c248b7d ID |
115 | void __iomem *regs; |
116 | struct fimd_win_data win_data[WINDOWS_NR]; | |
117 | unsigned int clkdiv; | |
118 | unsigned int default_win; | |
119 | unsigned long irq_flags; | |
120 | u32 vidcon0; | |
121 | u32 vidcon1; | |
cb91f6a0 | 122 | bool suspended; |
c32b06ef | 123 | struct mutex lock; |
01ce113c P |
124 | wait_queue_head_t wait_vsync_queue; |
125 | atomic_t wait_vsync_event; | |
1c248b7d | 126 | |
562ad9f4 | 127 | struct exynos_drm_panel_info panel; |
18873465 | 128 | struct fimd_driver_data *driver_data; |
1c248b7d ID |
129 | }; |
130 | ||
d636ead8 | 131 | static const struct of_device_id fimd_driver_dt_match[] = { |
725ddead TF |
132 | { .compatible = "samsung,s3c6400-fimd", |
133 | .data = &s3c64xx_fimd_driver_data }, | |
5830daf8 | 134 | { .compatible = "samsung,exynos4210-fimd", |
d636ead8 | 135 | .data = &exynos4_fimd_driver_data }, |
5830daf8 | 136 | { .compatible = "samsung,exynos5250-fimd", |
d636ead8 JS |
137 | .data = &exynos5_fimd_driver_data }, |
138 | {}, | |
139 | }; | |
d636ead8 | 140 | |
e2e13389 LKA |
141 | static inline struct fimd_driver_data *drm_fimd_get_driver_data( |
142 | struct platform_device *pdev) | |
143 | { | |
d636ead8 JS |
144 | const struct of_device_id *of_id = |
145 | of_match_device(fimd_driver_dt_match, &pdev->dev); | |
146 | ||
2d3f173c | 147 | return (struct fimd_driver_data *)of_id->data; |
e2e13389 LKA |
148 | } |
149 | ||
1c248b7d ID |
150 | static bool fimd_display_is_connected(struct device *dev) |
151 | { | |
1c248b7d ID |
152 | /* TODO. */ |
153 | ||
154 | return true; | |
155 | } | |
156 | ||
607c50d4 | 157 | static void *fimd_get_panel(struct device *dev) |
1c248b7d | 158 | { |
bb7704d6 SP |
159 | struct exynos_drm_manager *mgr = get_fimd_manager(dev); |
160 | struct fimd_context *ctx = mgr->ctx; | |
1c248b7d | 161 | |
562ad9f4 | 162 | return &ctx->panel; |
1c248b7d ID |
163 | } |
164 | ||
16844fb1 | 165 | static int fimd_check_mode(struct device *dev, struct drm_display_mode *mode) |
1c248b7d | 166 | { |
1c248b7d ID |
167 | /* TODO. */ |
168 | ||
169 | return 0; | |
170 | } | |
171 | ||
74ccc539 | 172 | static struct exynos_drm_display_ops fimd_display_ops = { |
1c248b7d ID |
173 | .type = EXYNOS_DISPLAY_TYPE_LCD, |
174 | .is_connected = fimd_display_is_connected, | |
607c50d4 | 175 | .get_panel = fimd_get_panel, |
16844fb1 | 176 | .check_mode = fimd_check_mode, |
1c248b7d ID |
177 | }; |
178 | ||
bb7704d6 SP |
179 | static int fimd_mgr_initialize(struct exynos_drm_manager *mgr, |
180 | struct drm_device *drm_dev) | |
40c8ab4b | 181 | { |
bb7704d6 | 182 | struct fimd_context *ctx = mgr->ctx; |
40c8ab4b SP |
183 | |
184 | ctx->drm_dev = drm_dev; | |
185 | ||
186 | return 0; | |
187 | } | |
188 | ||
bb7704d6 | 189 | static void fimd_dpms(struct exynos_drm_manager *mgr, int mode) |
ec05da95 | 190 | { |
bb7704d6 | 191 | struct fimd_context *ctx = mgr->ctx; |
c32b06ef | 192 | |
bca34c9a | 193 | DRM_DEBUG_KMS("%d\n", mode); |
ec05da95 | 194 | |
c32b06ef ID |
195 | mutex_lock(&ctx->lock); |
196 | ||
cb91f6a0 JS |
197 | switch (mode) { |
198 | case DRM_MODE_DPMS_ON: | |
c32b06ef ID |
199 | /* |
200 | * enable fimd hardware only if suspended status. | |
201 | * | |
202 | * P.S. fimd_dpms function would be called at booting time so | |
203 | * clk_enable could be called double time. | |
204 | */ | |
205 | if (ctx->suspended) | |
bb7704d6 | 206 | pm_runtime_get_sync(ctx->dev); |
cb91f6a0 JS |
207 | break; |
208 | case DRM_MODE_DPMS_STANDBY: | |
209 | case DRM_MODE_DPMS_SUSPEND: | |
210 | case DRM_MODE_DPMS_OFF: | |
373af0c0 | 211 | if (!ctx->suspended) |
bb7704d6 | 212 | pm_runtime_put_sync(ctx->dev); |
cb91f6a0 JS |
213 | break; |
214 | default: | |
215 | DRM_DEBUG_KMS("unspecified mode %d\n", mode); | |
216 | break; | |
217 | } | |
c32b06ef ID |
218 | |
219 | mutex_unlock(&ctx->lock); | |
ec05da95 ID |
220 | } |
221 | ||
bb7704d6 | 222 | static void fimd_apply(struct exynos_drm_manager *mgr) |
ec05da95 | 223 | { |
bb7704d6 | 224 | struct fimd_context *ctx = mgr->ctx; |
ec05da95 | 225 | struct exynos_drm_manager_ops *mgr_ops = mgr->ops; |
ec05da95 | 226 | struct fimd_win_data *win_data; |
864ee9e6 | 227 | int i; |
ec05da95 | 228 | |
864ee9e6 JS |
229 | for (i = 0; i < WINDOWS_NR; i++) { |
230 | win_data = &ctx->win_data[i]; | |
1c6244c3 | 231 | if (win_data->enabled && (mgr_ops && mgr_ops->win_commit)) |
bb7704d6 | 232 | mgr_ops->win_commit(mgr, i); |
864ee9e6 | 233 | } |
ec05da95 ID |
234 | |
235 | if (mgr_ops && mgr_ops->commit) | |
bb7704d6 | 236 | mgr_ops->commit(mgr); |
ec05da95 ID |
237 | } |
238 | ||
bb7704d6 | 239 | static void fimd_commit(struct exynos_drm_manager *mgr) |
1c248b7d | 240 | { |
bb7704d6 | 241 | struct fimd_context *ctx = mgr->ctx; |
562ad9f4 | 242 | struct exynos_drm_panel_info *panel = &ctx->panel; |
111e6055 | 243 | struct videomode *vm = &panel->vm; |
e2e13389 | 244 | struct fimd_driver_data *driver_data; |
1c248b7d ID |
245 | u32 val; |
246 | ||
18873465 | 247 | driver_data = ctx->driver_data; |
e30d4bcf ID |
248 | if (ctx->suspended) |
249 | return; | |
250 | ||
1c248b7d | 251 | /* setup polarity values from machine code. */ |
e2e13389 | 252 | writel(ctx->vidcon1, ctx->regs + driver_data->timing_base + VIDCON1); |
1c248b7d ID |
253 | |
254 | /* setup vertical timing values. */ | |
111e6055 AH |
255 | val = VIDTCON0_VBPD(vm->vback_porch - 1) | |
256 | VIDTCON0_VFPD(vm->vfront_porch - 1) | | |
257 | VIDTCON0_VSPW(vm->vsync_len - 1); | |
e2e13389 | 258 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON0); |
1c248b7d ID |
259 | |
260 | /* setup horizontal timing values. */ | |
111e6055 AH |
261 | val = VIDTCON1_HBPD(vm->hback_porch - 1) | |
262 | VIDTCON1_HFPD(vm->hfront_porch - 1) | | |
263 | VIDTCON1_HSPW(vm->hsync_len - 1); | |
e2e13389 | 264 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON1); |
1c248b7d ID |
265 | |
266 | /* setup horizontal and vertical display size. */ | |
111e6055 AH |
267 | val = VIDTCON2_LINEVAL(vm->vactive - 1) | |
268 | VIDTCON2_HOZVAL(vm->hactive - 1) | | |
269 | VIDTCON2_LINEVAL_E(vm->vactive - 1) | | |
270 | VIDTCON2_HOZVAL_E(vm->hactive - 1); | |
e2e13389 | 271 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON2); |
1c248b7d ID |
272 | |
273 | /* setup clock source, clock divider, enable dma. */ | |
274 | val = ctx->vidcon0; | |
275 | val &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR); | |
276 | ||
411d9ed4 TF |
277 | if (ctx->driver_data->has_clksel) { |
278 | val &= ~VIDCON0_CLKSEL_MASK; | |
279 | val |= VIDCON0_CLKSEL_LCD; | |
280 | } | |
281 | ||
1c248b7d ID |
282 | if (ctx->clkdiv > 1) |
283 | val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR; | |
284 | else | |
285 | val &= ~VIDCON0_CLKDIR; /* 1:1 clock */ | |
286 | ||
287 | /* | |
288 | * fields of register with prefix '_F' would be updated | |
289 | * at vsync(same as dma start) | |
290 | */ | |
291 | val |= VIDCON0_ENVID | VIDCON0_ENVID_F; | |
292 | writel(val, ctx->regs + VIDCON0); | |
293 | } | |
294 | ||
bb7704d6 | 295 | static int fimd_enable_vblank(struct exynos_drm_manager *mgr) |
1c248b7d | 296 | { |
bb7704d6 | 297 | struct fimd_context *ctx = mgr->ctx; |
1c248b7d ID |
298 | u32 val; |
299 | ||
cb91f6a0 JS |
300 | if (ctx->suspended) |
301 | return -EPERM; | |
302 | ||
1c248b7d ID |
303 | if (!test_and_set_bit(0, &ctx->irq_flags)) { |
304 | val = readl(ctx->regs + VIDINTCON0); | |
305 | ||
306 | val |= VIDINTCON0_INT_ENABLE; | |
307 | val |= VIDINTCON0_INT_FRAME; | |
308 | ||
309 | val &= ~VIDINTCON0_FRAMESEL0_MASK; | |
310 | val |= VIDINTCON0_FRAMESEL0_VSYNC; | |
311 | val &= ~VIDINTCON0_FRAMESEL1_MASK; | |
312 | val |= VIDINTCON0_FRAMESEL1_NONE; | |
313 | ||
314 | writel(val, ctx->regs + VIDINTCON0); | |
315 | } | |
316 | ||
317 | return 0; | |
318 | } | |
319 | ||
bb7704d6 | 320 | static void fimd_disable_vblank(struct exynos_drm_manager *mgr) |
1c248b7d | 321 | { |
bb7704d6 | 322 | struct fimd_context *ctx = mgr->ctx; |
1c248b7d ID |
323 | u32 val; |
324 | ||
cb91f6a0 JS |
325 | if (ctx->suspended) |
326 | return; | |
327 | ||
1c248b7d ID |
328 | if (test_and_clear_bit(0, &ctx->irq_flags)) { |
329 | val = readl(ctx->regs + VIDINTCON0); | |
330 | ||
331 | val &= ~VIDINTCON0_INT_FRAME; | |
332 | val &= ~VIDINTCON0_INT_ENABLE; | |
333 | ||
334 | writel(val, ctx->regs + VIDINTCON0); | |
335 | } | |
336 | } | |
337 | ||
bb7704d6 | 338 | static void fimd_wait_for_vblank(struct exynos_drm_manager *mgr) |
07033970 | 339 | { |
bb7704d6 | 340 | struct fimd_context *ctx = mgr->ctx; |
07033970 | 341 | |
01ce113c P |
342 | if (ctx->suspended) |
343 | return; | |
344 | ||
345 | atomic_set(&ctx->wait_vsync_event, 1); | |
346 | ||
347 | /* | |
348 | * wait for FIMD to signal VSYNC interrupt or return after | |
349 | * timeout which is set to 50ms (refresh rate of 20). | |
350 | */ | |
351 | if (!wait_event_timeout(ctx->wait_vsync_queue, | |
352 | !atomic_read(&ctx->wait_vsync_event), | |
8dd9ad5d | 353 | HZ/20)) |
07033970 P |
354 | DRM_DEBUG_KMS("vblank wait timed out.\n"); |
355 | } | |
356 | ||
bb7704d6 SP |
357 | static void fimd_win_mode_set(struct exynos_drm_manager *mgr, |
358 | struct exynos_drm_overlay *overlay) | |
1c248b7d | 359 | { |
bb7704d6 | 360 | struct fimd_context *ctx = mgr->ctx; |
1c248b7d | 361 | struct fimd_win_data *win_data; |
864ee9e6 | 362 | int win; |
19c8b834 | 363 | unsigned long offset; |
1c248b7d | 364 | |
1c248b7d | 365 | if (!overlay) { |
bb7704d6 | 366 | DRM_ERROR("overlay is NULL\n"); |
1c248b7d ID |
367 | return; |
368 | } | |
369 | ||
864ee9e6 JS |
370 | win = overlay->zpos; |
371 | if (win == DEFAULT_ZPOS) | |
372 | win = ctx->default_win; | |
373 | ||
37b006e8 | 374 | if (win < 0 || win >= WINDOWS_NR) |
864ee9e6 JS |
375 | return; |
376 | ||
19c8b834 ID |
377 | offset = overlay->fb_x * (overlay->bpp >> 3); |
378 | offset += overlay->fb_y * overlay->pitch; | |
379 | ||
380 | DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch); | |
381 | ||
864ee9e6 | 382 | win_data = &ctx->win_data[win]; |
1c248b7d | 383 | |
19c8b834 ID |
384 | win_data->offset_x = overlay->crtc_x; |
385 | win_data->offset_y = overlay->crtc_y; | |
386 | win_data->ovl_width = overlay->crtc_width; | |
387 | win_data->ovl_height = overlay->crtc_height; | |
388 | win_data->fb_width = overlay->fb_width; | |
389 | win_data->fb_height = overlay->fb_height; | |
229d3534 | 390 | win_data->dma_addr = overlay->dma_addr[0] + offset; |
1c248b7d | 391 | win_data->bpp = overlay->bpp; |
a4f38a80 | 392 | win_data->pixel_format = overlay->pixel_format; |
19c8b834 ID |
393 | win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) * |
394 | (overlay->bpp >> 3); | |
395 | win_data->line_size = overlay->crtc_width * (overlay->bpp >> 3); | |
396 | ||
397 | DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n", | |
398 | win_data->offset_x, win_data->offset_y); | |
399 | DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", | |
400 | win_data->ovl_width, win_data->ovl_height); | |
ddd8e959 | 401 | DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data->dma_addr); |
19c8b834 ID |
402 | DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n", |
403 | overlay->fb_width, overlay->crtc_width); | |
1c248b7d ID |
404 | } |
405 | ||
bb7704d6 | 406 | static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win) |
1c248b7d | 407 | { |
1c248b7d ID |
408 | struct fimd_win_data *win_data = &ctx->win_data[win]; |
409 | unsigned long val; | |
410 | ||
1c248b7d ID |
411 | val = WINCONx_ENWIN; |
412 | ||
5cc4621a ID |
413 | /* |
414 | * In case of s3c64xx, window 0 doesn't support alpha channel. | |
415 | * So the request format is ARGB8888 then change it to XRGB8888. | |
416 | */ | |
417 | if (ctx->driver_data->has_limited_fmt && !win) { | |
418 | if (win_data->pixel_format == DRM_FORMAT_ARGB8888) | |
419 | win_data->pixel_format = DRM_FORMAT_XRGB8888; | |
420 | } | |
421 | ||
a4f38a80 ID |
422 | switch (win_data->pixel_format) { |
423 | case DRM_FORMAT_C8: | |
1c248b7d ID |
424 | val |= WINCON0_BPPMODE_8BPP_PALETTE; |
425 | val |= WINCONx_BURSTLEN_8WORD; | |
426 | val |= WINCONx_BYTSWP; | |
427 | break; | |
a4f38a80 ID |
428 | case DRM_FORMAT_XRGB1555: |
429 | val |= WINCON0_BPPMODE_16BPP_1555; | |
430 | val |= WINCONx_HAWSWP; | |
431 | val |= WINCONx_BURSTLEN_16WORD; | |
432 | break; | |
433 | case DRM_FORMAT_RGB565: | |
1c248b7d ID |
434 | val |= WINCON0_BPPMODE_16BPP_565; |
435 | val |= WINCONx_HAWSWP; | |
436 | val |= WINCONx_BURSTLEN_16WORD; | |
437 | break; | |
a4f38a80 | 438 | case DRM_FORMAT_XRGB8888: |
1c248b7d ID |
439 | val |= WINCON0_BPPMODE_24BPP_888; |
440 | val |= WINCONx_WSWP; | |
441 | val |= WINCONx_BURSTLEN_16WORD; | |
442 | break; | |
a4f38a80 ID |
443 | case DRM_FORMAT_ARGB8888: |
444 | val |= WINCON1_BPPMODE_25BPP_A1888 | |
1c248b7d ID |
445 | | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL; |
446 | val |= WINCONx_WSWP; | |
447 | val |= WINCONx_BURSTLEN_16WORD; | |
448 | break; | |
449 | default: | |
450 | DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n"); | |
451 | ||
452 | val |= WINCON0_BPPMODE_24BPP_888; | |
453 | val |= WINCONx_WSWP; | |
454 | val |= WINCONx_BURSTLEN_16WORD; | |
455 | break; | |
456 | } | |
457 | ||
458 | DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp); | |
459 | ||
460 | writel(val, ctx->regs + WINCON(win)); | |
461 | } | |
462 | ||
bb7704d6 | 463 | static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win) |
1c248b7d | 464 | { |
1c248b7d ID |
465 | unsigned int keycon0 = 0, keycon1 = 0; |
466 | ||
1c248b7d ID |
467 | keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F | |
468 | WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); | |
469 | ||
470 | keycon1 = WxKEYCON1_COLVAL(0xffffffff); | |
471 | ||
472 | writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); | |
473 | writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); | |
474 | } | |
475 | ||
de7af100 TF |
476 | /** |
477 | * shadow_protect_win() - disable updating values from shadow registers at vsync | |
478 | * | |
479 | * @win: window to protect registers for | |
480 | * @protect: 1 to protect (disable updates) | |
481 | */ | |
482 | static void fimd_shadow_protect_win(struct fimd_context *ctx, | |
483 | int win, bool protect) | |
484 | { | |
485 | u32 reg, bits, val; | |
486 | ||
487 | if (ctx->driver_data->has_shadowcon) { | |
488 | reg = SHADOWCON; | |
489 | bits = SHADOWCON_WINx_PROTECT(win); | |
490 | } else { | |
491 | reg = PRTCON; | |
492 | bits = PRTCON_PROTECT; | |
493 | } | |
494 | ||
495 | val = readl(ctx->regs + reg); | |
496 | if (protect) | |
497 | val |= bits; | |
498 | else | |
499 | val &= ~bits; | |
500 | writel(val, ctx->regs + reg); | |
501 | } | |
502 | ||
bb7704d6 | 503 | static void fimd_win_commit(struct exynos_drm_manager *mgr, int zpos) |
1c248b7d | 504 | { |
bb7704d6 | 505 | struct fimd_context *ctx = mgr->ctx; |
1c248b7d | 506 | struct fimd_win_data *win_data; |
864ee9e6 | 507 | int win = zpos; |
1c248b7d | 508 | unsigned long val, alpha, size; |
f56aad3a JS |
509 | unsigned int last_x; |
510 | unsigned int last_y; | |
1c248b7d | 511 | |
e30d4bcf ID |
512 | if (ctx->suspended) |
513 | return; | |
514 | ||
864ee9e6 JS |
515 | if (win == DEFAULT_ZPOS) |
516 | win = ctx->default_win; | |
517 | ||
37b006e8 | 518 | if (win < 0 || win >= WINDOWS_NR) |
1c248b7d ID |
519 | return; |
520 | ||
521 | win_data = &ctx->win_data[win]; | |
522 | ||
523 | /* | |
de7af100 | 524 | * SHADOWCON/PRTCON register is used for enabling timing. |
1c248b7d ID |
525 | * |
526 | * for example, once only width value of a register is set, | |
527 | * if the dma is started then fimd hardware could malfunction so | |
528 | * with protect window setting, the register fields with prefix '_F' | |
529 | * wouldn't be updated at vsync also but updated once unprotect window | |
530 | * is set. | |
531 | */ | |
532 | ||
533 | /* protect windows */ | |
de7af100 | 534 | fimd_shadow_protect_win(ctx, win, true); |
1c248b7d ID |
535 | |
536 | /* buffer start address */ | |
2c871127 | 537 | val = (unsigned long)win_data->dma_addr; |
1c248b7d ID |
538 | writel(val, ctx->regs + VIDWx_BUF_START(win, 0)); |
539 | ||
540 | /* buffer end address */ | |
19c8b834 | 541 | size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3); |
2c871127 | 542 | val = (unsigned long)(win_data->dma_addr + size); |
1c248b7d ID |
543 | writel(val, ctx->regs + VIDWx_BUF_END(win, 0)); |
544 | ||
545 | DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n", | |
2c871127 | 546 | (unsigned long)win_data->dma_addr, val, size); |
19c8b834 ID |
547 | DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", |
548 | win_data->ovl_width, win_data->ovl_height); | |
1c248b7d ID |
549 | |
550 | /* buffer size */ | |
551 | val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) | | |
ca555e5a JS |
552 | VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size) | |
553 | VIDW_BUF_SIZE_OFFSET_E(win_data->buf_offsize) | | |
554 | VIDW_BUF_SIZE_PAGEWIDTH_E(win_data->line_size); | |
1c248b7d ID |
555 | writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0)); |
556 | ||
557 | /* OSD position */ | |
558 | val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) | | |
ca555e5a JS |
559 | VIDOSDxA_TOPLEFT_Y(win_data->offset_y) | |
560 | VIDOSDxA_TOPLEFT_X_E(win_data->offset_x) | | |
561 | VIDOSDxA_TOPLEFT_Y_E(win_data->offset_y); | |
1c248b7d ID |
562 | writel(val, ctx->regs + VIDOSD_A(win)); |
563 | ||
f56aad3a JS |
564 | last_x = win_data->offset_x + win_data->ovl_width; |
565 | if (last_x) | |
566 | last_x--; | |
567 | last_y = win_data->offset_y + win_data->ovl_height; | |
568 | if (last_y) | |
569 | last_y--; | |
570 | ||
ca555e5a JS |
571 | val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) | |
572 | VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y); | |
573 | ||
1c248b7d ID |
574 | writel(val, ctx->regs + VIDOSD_B(win)); |
575 | ||
19c8b834 | 576 | DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", |
f56aad3a | 577 | win_data->offset_x, win_data->offset_y, last_x, last_y); |
1c248b7d ID |
578 | |
579 | /* hardware window 0 doesn't support alpha channel. */ | |
580 | if (win != 0) { | |
581 | /* OSD alpha */ | |
582 | alpha = VIDISD14C_ALPHA1_R(0xf) | | |
583 | VIDISD14C_ALPHA1_G(0xf) | | |
584 | VIDISD14C_ALPHA1_B(0xf); | |
585 | ||
586 | writel(alpha, ctx->regs + VIDOSD_C(win)); | |
587 | } | |
588 | ||
589 | /* OSD size */ | |
590 | if (win != 3 && win != 4) { | |
591 | u32 offset = VIDOSD_D(win); | |
592 | if (win == 0) | |
0f10cf14 | 593 | offset = VIDOSD_C(win); |
19c8b834 | 594 | val = win_data->ovl_width * win_data->ovl_height; |
1c248b7d ID |
595 | writel(val, ctx->regs + offset); |
596 | ||
597 | DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val); | |
598 | } | |
599 | ||
bb7704d6 | 600 | fimd_win_set_pixfmt(ctx, win); |
1c248b7d ID |
601 | |
602 | /* hardware window 0 doesn't support color key. */ | |
603 | if (win != 0) | |
bb7704d6 | 604 | fimd_win_set_colkey(ctx, win); |
1c248b7d | 605 | |
ec05da95 ID |
606 | /* wincon */ |
607 | val = readl(ctx->regs + WINCON(win)); | |
608 | val |= WINCONx_ENWIN; | |
609 | writel(val, ctx->regs + WINCON(win)); | |
610 | ||
1c248b7d | 611 | /* Enable DMA channel and unprotect windows */ |
de7af100 TF |
612 | fimd_shadow_protect_win(ctx, win, false); |
613 | ||
614 | if (ctx->driver_data->has_shadowcon) { | |
615 | val = readl(ctx->regs + SHADOWCON); | |
616 | val |= SHADOWCON_CHx_ENABLE(win); | |
617 | writel(val, ctx->regs + SHADOWCON); | |
618 | } | |
ec05da95 ID |
619 | |
620 | win_data->enabled = true; | |
1c248b7d ID |
621 | } |
622 | ||
bb7704d6 | 623 | static void fimd_win_disable(struct exynos_drm_manager *mgr, int zpos) |
1c248b7d | 624 | { |
bb7704d6 | 625 | struct fimd_context *ctx = mgr->ctx; |
ec05da95 | 626 | struct fimd_win_data *win_data; |
864ee9e6 | 627 | int win = zpos; |
1c248b7d ID |
628 | u32 val; |
629 | ||
864ee9e6 JS |
630 | if (win == DEFAULT_ZPOS) |
631 | win = ctx->default_win; | |
632 | ||
37b006e8 | 633 | if (win < 0 || win >= WINDOWS_NR) |
1c248b7d ID |
634 | return; |
635 | ||
ec05da95 ID |
636 | win_data = &ctx->win_data[win]; |
637 | ||
db7e55ae P |
638 | if (ctx->suspended) { |
639 | /* do not resume this window*/ | |
640 | win_data->resume = false; | |
641 | return; | |
642 | } | |
643 | ||
1c248b7d | 644 | /* protect windows */ |
de7af100 | 645 | fimd_shadow_protect_win(ctx, win, true); |
1c248b7d ID |
646 | |
647 | /* wincon */ | |
648 | val = readl(ctx->regs + WINCON(win)); | |
649 | val &= ~WINCONx_ENWIN; | |
650 | writel(val, ctx->regs + WINCON(win)); | |
651 | ||
652 | /* unprotect windows */ | |
de7af100 TF |
653 | if (ctx->driver_data->has_shadowcon) { |
654 | val = readl(ctx->regs + SHADOWCON); | |
655 | val &= ~SHADOWCON_CHx_ENABLE(win); | |
656 | writel(val, ctx->regs + SHADOWCON); | |
657 | } | |
658 | ||
659 | fimd_shadow_protect_win(ctx, win, false); | |
ec05da95 ID |
660 | |
661 | win_data->enabled = false; | |
1c248b7d ID |
662 | } |
663 | ||
1c6244c3 | 664 | static struct exynos_drm_manager_ops fimd_manager_ops = { |
40c8ab4b | 665 | .initialize = fimd_mgr_initialize, |
1c6244c3 | 666 | .dpms = fimd_dpms, |
1c6244c3 SP |
667 | .commit = fimd_commit, |
668 | .enable_vblank = fimd_enable_vblank, | |
669 | .disable_vblank = fimd_disable_vblank, | |
670 | .wait_for_vblank = fimd_wait_for_vblank, | |
671 | .win_mode_set = fimd_win_mode_set, | |
672 | .win_commit = fimd_win_commit, | |
673 | .win_disable = fimd_win_disable, | |
1c248b7d ID |
674 | }; |
675 | ||
677e84c1 JS |
676 | static struct exynos_drm_manager fimd_manager = { |
677 | .pipe = -1, | |
678 | .ops = &fimd_manager_ops, | |
677e84c1 JS |
679 | .display_ops = &fimd_display_ops, |
680 | }; | |
681 | ||
1c248b7d ID |
682 | static irqreturn_t fimd_irq_handler(int irq, void *dev_id) |
683 | { | |
684 | struct fimd_context *ctx = (struct fimd_context *)dev_id; | |
685 | struct exynos_drm_subdrv *subdrv = &ctx->subdrv; | |
677e84c1 | 686 | struct exynos_drm_manager *manager = subdrv->manager; |
1c248b7d ID |
687 | u32 val; |
688 | ||
689 | val = readl(ctx->regs + VIDINTCON1); | |
690 | ||
691 | if (val & VIDINTCON1_INT_FRAME) | |
692 | /* VSYNC interrupt */ | |
693 | writel(VIDINTCON1_INT_FRAME, ctx->regs + VIDINTCON1); | |
694 | ||
ec05da95 | 695 | /* check the crtc is detached already from encoder */ |
40c8ab4b | 696 | if (manager->pipe < 0 || !ctx->drm_dev) |
ec05da95 | 697 | goto out; |
483b88f8 | 698 | |
40c8ab4b SP |
699 | drm_handle_vblank(ctx->drm_dev, manager->pipe); |
700 | exynos_drm_crtc_finish_pageflip(ctx->drm_dev, manager->pipe); | |
1c248b7d | 701 | |
01ce113c P |
702 | /* set wait vsync event to zero and wake up queue. */ |
703 | if (atomic_read(&ctx->wait_vsync_event)) { | |
704 | atomic_set(&ctx->wait_vsync_event, 0); | |
8dd9ad5d | 705 | wake_up(&ctx->wait_vsync_queue); |
01ce113c | 706 | } |
ec05da95 | 707 | out: |
1c248b7d ID |
708 | return IRQ_HANDLED; |
709 | } | |
710 | ||
41c24346 | 711 | static int fimd_subdrv_probe(struct drm_device *drm_dev, struct device *dev) |
1c248b7d | 712 | { |
1c248b7d ID |
713 | /* |
714 | * enable drm irq mode. | |
4423843c | 715 | * - with irq_enabled = true, we can use the vblank feature. |
1c248b7d ID |
716 | * |
717 | * P.S. note that we wouldn't use drm irq handler but | |
718 | * just specific driver own one instead because | |
719 | * drm framework supports only one irq handler. | |
720 | */ | |
4423843c | 721 | drm_dev->irq_enabled = true; |
1c248b7d | 722 | |
ec05da95 | 723 | /* |
ba0bf120 | 724 | * with vblank_disable_allowed = true, vblank interrupt will be disabled |
ec05da95 ID |
725 | * by drm timer once a current process gives up ownership of |
726 | * vblank event.(after drm_vblank_put function is called) | |
727 | */ | |
ba0bf120 | 728 | drm_dev->vblank_disable_allowed = true; |
ec05da95 | 729 | |
bcc5cd1c ID |
730 | /* attach this sub driver to iommu mapping if supported. */ |
731 | if (is_drm_iommu_supported(drm_dev)) | |
732 | drm_iommu_attach_device(drm_dev, dev); | |
733 | ||
1c248b7d ID |
734 | return 0; |
735 | } | |
736 | ||
29cb6025 | 737 | static void fimd_subdrv_remove(struct drm_device *drm_dev, struct device *dev) |
1c248b7d | 738 | { |
bcc5cd1c ID |
739 | /* detach this sub driver from iommu mapping if supported. */ |
740 | if (is_drm_iommu_supported(drm_dev)) | |
741 | drm_iommu_detach_device(drm_dev, dev); | |
1c248b7d ID |
742 | } |
743 | ||
111e6055 | 744 | static int fimd_configure_clocks(struct fimd_context *ctx, struct device *dev) |
1c248b7d | 745 | { |
562ad9f4 | 746 | struct videomode *vm = &ctx->panel.vm; |
111e6055 AH |
747 | unsigned long clk; |
748 | ||
749 | ctx->bus_clk = devm_clk_get(dev, "fimd"); | |
750 | if (IS_ERR(ctx->bus_clk)) { | |
751 | dev_err(dev, "failed to get bus clock\n"); | |
752 | return PTR_ERR(ctx->bus_clk); | |
753 | } | |
754 | ||
755 | ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd"); | |
756 | if (IS_ERR(ctx->lcd_clk)) { | |
757 | dev_err(dev, "failed to get lcd clock\n"); | |
758 | return PTR_ERR(ctx->lcd_clk); | |
759 | } | |
760 | ||
761 | clk = clk_get_rate(ctx->lcd_clk); | |
762 | if (clk == 0) { | |
763 | dev_err(dev, "error getting sclk_fimd clock rate\n"); | |
764 | return -EINVAL; | |
765 | } | |
766 | ||
767 | if (vm->pixelclock == 0) { | |
768 | unsigned long c; | |
769 | c = vm->hactive + vm->hback_porch + vm->hfront_porch + | |
770 | vm->hsync_len; | |
771 | c *= vm->vactive + vm->vback_porch + vm->vfront_porch + | |
772 | vm->vsync_len; | |
773 | vm->pixelclock = c * FIMD_DEFAULT_FRAMERATE; | |
774 | if (vm->pixelclock == 0) { | |
775 | dev_err(dev, "incorrect display timings\n"); | |
776 | return -EINVAL; | |
1c248b7d | 777 | } |
111e6055 AH |
778 | dev_warn(dev, "pixel clock recalculated to %luHz (%dHz frame rate)\n", |
779 | vm->pixelclock, FIMD_DEFAULT_FRAMERATE); | |
780 | } | |
781 | ctx->clkdiv = DIV_ROUND_UP(clk, vm->pixelclock); | |
782 | if (ctx->clkdiv > 256) { | |
783 | dev_warn(dev, "calculated pixel clock divider too high (%u), lowered to 256\n", | |
784 | ctx->clkdiv); | |
785 | ctx->clkdiv = 256; | |
1c248b7d | 786 | } |
111e6055 AH |
787 | vm->pixelclock = clk / ctx->clkdiv; |
788 | DRM_DEBUG_KMS("pixel clock = %lu, clkdiv = %d\n", vm->pixelclock, | |
789 | ctx->clkdiv); | |
1c248b7d | 790 | |
111e6055 | 791 | return 0; |
1c248b7d ID |
792 | } |
793 | ||
794 | static void fimd_clear_win(struct fimd_context *ctx, int win) | |
795 | { | |
1c248b7d ID |
796 | writel(0, ctx->regs + WINCON(win)); |
797 | writel(0, ctx->regs + VIDOSD_A(win)); | |
798 | writel(0, ctx->regs + VIDOSD_B(win)); | |
799 | writel(0, ctx->regs + VIDOSD_C(win)); | |
800 | ||
801 | if (win == 1 || win == 2) | |
802 | writel(0, ctx->regs + VIDOSD_D(win)); | |
803 | ||
de7af100 | 804 | fimd_shadow_protect_win(ctx, win, false); |
1c248b7d ID |
805 | } |
806 | ||
5d55393a | 807 | static int fimd_clock(struct fimd_context *ctx, bool enable) |
373af0c0 | 808 | { |
373af0c0 ID |
809 | if (enable) { |
810 | int ret; | |
811 | ||
11963a63 | 812 | ret = clk_prepare_enable(ctx->bus_clk); |
373af0c0 ID |
813 | if (ret < 0) |
814 | return ret; | |
815 | ||
11963a63 | 816 | ret = clk_prepare_enable(ctx->lcd_clk); |
373af0c0 | 817 | if (ret < 0) { |
11963a63 | 818 | clk_disable_unprepare(ctx->bus_clk); |
373af0c0 ID |
819 | return ret; |
820 | } | |
5d55393a | 821 | } else { |
11963a63 VS |
822 | clk_disable_unprepare(ctx->lcd_clk); |
823 | clk_disable_unprepare(ctx->bus_clk); | |
5d55393a ID |
824 | } |
825 | ||
826 | return 0; | |
827 | } | |
828 | ||
db7e55ae P |
829 | static void fimd_window_suspend(struct device *dev) |
830 | { | |
bb7704d6 SP |
831 | struct exynos_drm_manager *mgr = get_fimd_manager(dev); |
832 | struct fimd_context *ctx = mgr->ctx; | |
db7e55ae P |
833 | struct fimd_win_data *win_data; |
834 | int i; | |
835 | ||
836 | for (i = 0; i < WINDOWS_NR; i++) { | |
837 | win_data = &ctx->win_data[i]; | |
838 | win_data->resume = win_data->enabled; | |
bb7704d6 | 839 | fimd_win_disable(mgr, i); |
db7e55ae | 840 | } |
bb7704d6 | 841 | fimd_wait_for_vblank(mgr); |
db7e55ae P |
842 | } |
843 | ||
844 | static void fimd_window_resume(struct device *dev) | |
845 | { | |
bb7704d6 SP |
846 | struct exynos_drm_manager *mgr = get_fimd_manager(dev); |
847 | struct fimd_context *ctx = mgr->ctx; | |
db7e55ae P |
848 | struct fimd_win_data *win_data; |
849 | int i; | |
850 | ||
851 | for (i = 0; i < WINDOWS_NR; i++) { | |
852 | win_data = &ctx->win_data[i]; | |
853 | win_data->enabled = win_data->resume; | |
854 | win_data->resume = false; | |
855 | } | |
856 | } | |
857 | ||
bb7704d6 | 858 | static int fimd_activate(struct exynos_drm_manager *mgr, bool enable) |
5d55393a | 859 | { |
bb7704d6 | 860 | struct fimd_context *ctx = mgr->ctx; |
db7e55ae | 861 | struct device *dev = ctx->subdrv.dev; |
bb7704d6 | 862 | |
5d55393a ID |
863 | if (enable) { |
864 | int ret; | |
5d55393a ID |
865 | |
866 | ret = fimd_clock(ctx, true); | |
867 | if (ret < 0) | |
868 | return ret; | |
373af0c0 ID |
869 | |
870 | ctx->suspended = false; | |
871 | ||
872 | /* if vblank was enabled status, enable it again. */ | |
873 | if (test_and_clear_bit(0, &ctx->irq_flags)) | |
bb7704d6 | 874 | fimd_enable_vblank(mgr); |
db7e55ae P |
875 | |
876 | fimd_window_resume(dev); | |
87244fa6 SP |
877 | |
878 | fimd_apply(mgr); | |
373af0c0 | 879 | } else { |
db7e55ae P |
880 | fimd_window_suspend(dev); |
881 | ||
5d55393a | 882 | fimd_clock(ctx, false); |
373af0c0 ID |
883 | ctx->suspended = true; |
884 | } | |
885 | ||
886 | return 0; | |
887 | } | |
888 | ||
562ad9f4 | 889 | static int fimd_get_platform_data(struct fimd_context *ctx, struct device *dev) |
1c248b7d | 890 | { |
2d3f173c SK |
891 | struct videomode *vm; |
892 | int ret; | |
7f4596f4 | 893 | |
2d3f173c SK |
894 | vm = &ctx->panel.vm; |
895 | ret = of_get_videomode(dev->of_node, vm, OF_USE_NATIVE_MODE); | |
896 | if (ret) { | |
897 | DRM_ERROR("failed: of_get_videomode() : %d\n", ret); | |
898 | return ret; | |
1c248b7d ID |
899 | } |
900 | ||
2d3f173c SK |
901 | if (vm->flags & DISPLAY_FLAGS_VSYNC_LOW) |
902 | ctx->vidcon1 |= VIDCON1_INV_VSYNC; | |
903 | if (vm->flags & DISPLAY_FLAGS_HSYNC_LOW) | |
904 | ctx->vidcon1 |= VIDCON1_INV_HSYNC; | |
905 | if (vm->flags & DISPLAY_FLAGS_DE_LOW) | |
906 | ctx->vidcon1 |= VIDCON1_INV_VDEN; | |
907 | if (vm->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) | |
908 | ctx->vidcon1 |= VIDCON1_INV_VCLK; | |
909 | ||
562ad9f4 AH |
910 | return 0; |
911 | } | |
912 | ||
913 | static int fimd_probe(struct platform_device *pdev) | |
914 | { | |
915 | struct device *dev = &pdev->dev; | |
916 | struct fimd_context *ctx; | |
917 | struct exynos_drm_subdrv *subdrv; | |
918 | struct resource *res; | |
919 | int win; | |
920 | int ret = -EINVAL; | |
1c248b7d | 921 | |
2d3f173c SK |
922 | if (!dev->of_node) |
923 | return -ENODEV; | |
924 | ||
d873ab99 | 925 | ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); |
1c248b7d ID |
926 | if (!ctx) |
927 | return -ENOMEM; | |
928 | ||
bb7704d6 SP |
929 | ctx->dev = dev; |
930 | ||
562ad9f4 AH |
931 | ret = fimd_get_platform_data(ctx, dev); |
932 | if (ret) | |
933 | return ret; | |
934 | ||
111e6055 AH |
935 | ret = fimd_configure_clocks(ctx, dev); |
936 | if (ret) | |
937 | return ret; | |
1c248b7d | 938 | |
1c248b7d | 939 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1c248b7d | 940 | |
d873ab99 | 941 | ctx->regs = devm_ioremap_resource(dev, res); |
d4ed6025 TR |
942 | if (IS_ERR(ctx->regs)) |
943 | return PTR_ERR(ctx->regs); | |
1c248b7d | 944 | |
1977e6d8 | 945 | res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "vsync"); |
1c248b7d ID |
946 | if (!res) { |
947 | dev_err(dev, "irq request failed.\n"); | |
a4d8de5f | 948 | return -ENXIO; |
1c248b7d ID |
949 | } |
950 | ||
951 | ctx->irq = res->start; | |
952 | ||
d873ab99 | 953 | ret = devm_request_irq(dev, ctx->irq, fimd_irq_handler, |
edc57266 SK |
954 | 0, "drm_fimd", ctx); |
955 | if (ret) { | |
1c248b7d | 956 | dev_err(dev, "irq request failed.\n"); |
a4d8de5f | 957 | return ret; |
1c248b7d ID |
958 | } |
959 | ||
18873465 | 960 | ctx->driver_data = drm_fimd_get_driver_data(pdev); |
57ed0f7b | 961 | init_waitqueue_head(&ctx->wait_vsync_queue); |
01ce113c | 962 | atomic_set(&ctx->wait_vsync_event, 0); |
1c248b7d | 963 | |
bb7704d6 SP |
964 | fimd_manager.ctx = ctx; |
965 | ||
1c248b7d ID |
966 | subdrv = &ctx->subdrv; |
967 | ||
677e84c1 JS |
968 | subdrv->dev = dev; |
969 | subdrv->manager = &fimd_manager; | |
1c248b7d ID |
970 | subdrv->probe = fimd_subdrv_probe; |
971 | subdrv->remove = fimd_subdrv_remove; | |
1c248b7d | 972 | |
c32b06ef ID |
973 | mutex_init(&ctx->lock); |
974 | ||
bb7704d6 | 975 | platform_set_drvdata(pdev, &fimd_manager); |
c32b06ef | 976 | |
c32b06ef ID |
977 | pm_runtime_enable(dev); |
978 | pm_runtime_get_sync(dev); | |
979 | ||
980 | for (win = 0; win < WINDOWS_NR; win++) | |
981 | fimd_clear_win(ctx, win); | |
982 | ||
1c248b7d ID |
983 | exynos_drm_subdrv_register(subdrv); |
984 | ||
985 | return 0; | |
1c248b7d ID |
986 | } |
987 | ||
56550d94 | 988 | static int fimd_remove(struct platform_device *pdev) |
1c248b7d | 989 | { |
cb91f6a0 | 990 | struct device *dev = &pdev->dev; |
bb7704d6 SP |
991 | struct exynos_drm_manager *mgr = platform_get_drvdata(pdev); |
992 | struct fimd_context *ctx = mgr->ctx; | |
1c248b7d | 993 | |
1c248b7d ID |
994 | exynos_drm_subdrv_unregister(&ctx->subdrv); |
995 | ||
cb91f6a0 JS |
996 | if (ctx->suspended) |
997 | goto out; | |
998 | ||
cb91f6a0 JS |
999 | pm_runtime_set_suspended(dev); |
1000 | pm_runtime_put_sync(dev); | |
1001 | ||
1002 | out: | |
1003 | pm_runtime_disable(dev); | |
1004 | ||
1c248b7d ID |
1005 | return 0; |
1006 | } | |
1007 | ||
e30d4bcf ID |
1008 | #ifdef CONFIG_PM_SLEEP |
1009 | static int fimd_suspend(struct device *dev) | |
1010 | { | |
bb7704d6 | 1011 | struct exynos_drm_manager *mgr = get_fimd_manager(dev); |
e30d4bcf | 1012 | |
373af0c0 ID |
1013 | /* |
1014 | * do not use pm_runtime_suspend(). if pm_runtime_suspend() is | |
1015 | * called here, an error would be returned by that interface | |
1016 | * because the usage_count of pm runtime is more than 1. | |
1017 | */ | |
5d55393a | 1018 | if (!pm_runtime_suspended(dev)) |
bb7704d6 | 1019 | return fimd_activate(mgr, false); |
5d55393a ID |
1020 | |
1021 | return 0; | |
e30d4bcf ID |
1022 | } |
1023 | ||
1024 | static int fimd_resume(struct device *dev) | |
1025 | { | |
bb7704d6 | 1026 | struct exynos_drm_manager *mgr = get_fimd_manager(dev); |
e30d4bcf | 1027 | |
373af0c0 ID |
1028 | /* |
1029 | * if entered to sleep when lcd panel was on, the usage_count | |
1030 | * of pm runtime would still be 1 so in this case, fimd driver | |
1031 | * should be on directly not drawing on pm runtime interface. | |
1032 | */ | |
87244fa6 SP |
1033 | if (pm_runtime_suspended(dev)) |
1034 | return 0; | |
5d55393a | 1035 | |
87244fa6 | 1036 | return fimd_activate(mgr, true); |
e30d4bcf ID |
1037 | } |
1038 | #endif | |
1039 | ||
cb91f6a0 JS |
1040 | #ifdef CONFIG_PM_RUNTIME |
1041 | static int fimd_runtime_suspend(struct device *dev) | |
1042 | { | |
bb7704d6 | 1043 | struct exynos_drm_manager *mgr = get_fimd_manager(dev); |
cb91f6a0 | 1044 | |
bb7704d6 | 1045 | return fimd_activate(mgr, false); |
cb91f6a0 JS |
1046 | } |
1047 | ||
1048 | static int fimd_runtime_resume(struct device *dev) | |
1049 | { | |
bb7704d6 | 1050 | struct exynos_drm_manager *mgr = get_fimd_manager(dev); |
cb91f6a0 | 1051 | |
bb7704d6 | 1052 | return fimd_activate(mgr, true); |
cb91f6a0 JS |
1053 | } |
1054 | #endif | |
1055 | ||
1056 | static const struct dev_pm_ops fimd_pm_ops = { | |
e30d4bcf | 1057 | SET_SYSTEM_SLEEP_PM_OPS(fimd_suspend, fimd_resume) |
cb91f6a0 JS |
1058 | SET_RUNTIME_PM_OPS(fimd_runtime_suspend, fimd_runtime_resume, NULL) |
1059 | }; | |
1060 | ||
132a5b91 | 1061 | struct platform_driver fimd_driver = { |
1c248b7d | 1062 | .probe = fimd_probe, |
56550d94 | 1063 | .remove = fimd_remove, |
1c248b7d ID |
1064 | .driver = { |
1065 | .name = "exynos4-fb", | |
1066 | .owner = THIS_MODULE, | |
cb91f6a0 | 1067 | .pm = &fimd_pm_ops, |
2d3f173c | 1068 | .of_match_table = fimd_driver_dt_match, |
1c248b7d ID |
1069 | }, |
1070 | }; |