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1c248b7d ID |
1 | /* exynos_drm_fimd.c |
2 | * | |
3 | * Copyright (C) 2011 Samsung Electronics Co.Ltd | |
4 | * Authors: | |
5 | * Joonyoung Shim <jy0922.shim@samsung.com> | |
6 | * Inki Dae <inki.dae@samsung.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | */ | |
760285e7 | 14 | #include <drm/drmP.h> |
1c248b7d ID |
15 | |
16 | #include <linux/kernel.h> | |
1c248b7d ID |
17 | #include <linux/platform_device.h> |
18 | #include <linux/clk.h> | |
3f1c781d | 19 | #include <linux/of.h> |
d636ead8 | 20 | #include <linux/of_device.h> |
cb91f6a0 | 21 | #include <linux/pm_runtime.h> |
f37cd5e8 | 22 | #include <linux/component.h> |
3854fab2 YC |
23 | #include <linux/mfd/syscon.h> |
24 | #include <linux/regmap.h> | |
1c248b7d | 25 | |
7f4596f4 | 26 | #include <video/of_display_timing.h> |
111e6055 | 27 | #include <video/of_videomode.h> |
5a213a55 | 28 | #include <video/samsung_fimd.h> |
1c248b7d | 29 | #include <drm/exynos_drm.h> |
1c248b7d ID |
30 | |
31 | #include "exynos_drm_drv.h" | |
32 | #include "exynos_drm_fbdev.h" | |
33 | #include "exynos_drm_crtc.h" | |
7ee14cdc | 34 | #include "exynos_drm_plane.h" |
bcc5cd1c | 35 | #include "exynos_drm_iommu.h" |
1c248b7d ID |
36 | |
37 | /* | |
b8654b37 | 38 | * FIMD stands for Fully Interactive Mobile Display and |
1c248b7d ID |
39 | * as a display controller, it transfers contents drawn on memory |
40 | * to a LCD Panel through Display Interfaces such as RGB or | |
41 | * CPU Interface. | |
42 | */ | |
43 | ||
111e6055 | 44 | #define FIMD_DEFAULT_FRAMERATE 60 |
66367461 | 45 | #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 |
111e6055 | 46 | |
1c248b7d ID |
47 | /* position control register for hardware window 0, 2 ~ 4.*/ |
48 | #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16) | |
49 | #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16) | |
0f10cf14 LKA |
50 | /* |
51 | * size control register for hardware windows 0 and alpha control register | |
52 | * for hardware windows 1 ~ 4 | |
53 | */ | |
54 | #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16) | |
55 | /* size control register for hardware windows 1 ~ 2. */ | |
1c248b7d ID |
56 | #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16) |
57 | ||
453b44a3 GP |
58 | #define VIDWnALPHA0(win) (VIDW_ALPHA + 0x00 + (win) * 8) |
59 | #define VIDWnALPHA1(win) (VIDW_ALPHA + 0x04 + (win) * 8) | |
60 | ||
1c248b7d ID |
61 | #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8) |
62 | #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8) | |
63 | #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4) | |
64 | ||
65 | /* color key control register for hardware window 1 ~ 4. */ | |
0f10cf14 | 66 | #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8)) |
1c248b7d | 67 | /* color key value register for hardware window 1 ~ 4. */ |
0f10cf14 | 68 | #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8)) |
1c248b7d | 69 | |
3854fab2 YC |
70 | /* I80 / RGB trigger control register */ |
71 | #define TRIGCON 0x1A4 | |
72 | #define TRGMODE_I80_RGB_ENABLE_I80 (1 << 0) | |
73 | #define SWTRGCMD_I80_RGB_ENABLE (1 << 1) | |
74 | ||
75 | /* display mode change control register except exynos4 */ | |
76 | #define VIDOUT_CON 0x000 | |
77 | #define VIDOUT_CON_F_I80_LDI0 (0x2 << 8) | |
78 | ||
79 | /* I80 interface control for main LDI register */ | |
80 | #define I80IFCONFAx(x) (0x1B0 + (x) * 4) | |
81 | #define I80IFCONFBx(x) (0x1B8 + (x) * 4) | |
82 | #define LCD_CS_SETUP(x) ((x) << 16) | |
83 | #define LCD_WR_SETUP(x) ((x) << 12) | |
84 | #define LCD_WR_ACTIVE(x) ((x) << 8) | |
85 | #define LCD_WR_HOLD(x) ((x) << 4) | |
86 | #define I80IFEN_ENABLE (1 << 0) | |
87 | ||
1c248b7d ID |
88 | /* FIMD has totally five hardware windows. */ |
89 | #define WINDOWS_NR 5 | |
90 | ||
e2e13389 LKA |
91 | struct fimd_driver_data { |
92 | unsigned int timing_base; | |
3854fab2 YC |
93 | unsigned int lcdblk_offset; |
94 | unsigned int lcdblk_vt_shift; | |
95 | unsigned int lcdblk_bypass_shift; | |
de7af100 TF |
96 | |
97 | unsigned int has_shadowcon:1; | |
411d9ed4 | 98 | unsigned int has_clksel:1; |
5cc4621a | 99 | unsigned int has_limited_fmt:1; |
3854fab2 | 100 | unsigned int has_vidoutcon:1; |
3c3c9c1d | 101 | unsigned int has_vtsel:1; |
e2e13389 LKA |
102 | }; |
103 | ||
725ddead TF |
104 | static struct fimd_driver_data s3c64xx_fimd_driver_data = { |
105 | .timing_base = 0x0, | |
106 | .has_clksel = 1, | |
5cc4621a | 107 | .has_limited_fmt = 1, |
725ddead TF |
108 | }; |
109 | ||
d6ce7b58 ID |
110 | static struct fimd_driver_data exynos3_fimd_driver_data = { |
111 | .timing_base = 0x20000, | |
112 | .lcdblk_offset = 0x210, | |
113 | .lcdblk_bypass_shift = 1, | |
114 | .has_shadowcon = 1, | |
115 | .has_vidoutcon = 1, | |
116 | }; | |
117 | ||
6ecf18f9 | 118 | static struct fimd_driver_data exynos4_fimd_driver_data = { |
e2e13389 | 119 | .timing_base = 0x0, |
3854fab2 YC |
120 | .lcdblk_offset = 0x210, |
121 | .lcdblk_vt_shift = 10, | |
122 | .lcdblk_bypass_shift = 1, | |
de7af100 | 123 | .has_shadowcon = 1, |
3c3c9c1d | 124 | .has_vtsel = 1, |
e2e13389 LKA |
125 | }; |
126 | ||
dcb622aa YC |
127 | static struct fimd_driver_data exynos4415_fimd_driver_data = { |
128 | .timing_base = 0x20000, | |
129 | .lcdblk_offset = 0x210, | |
130 | .lcdblk_vt_shift = 10, | |
131 | .lcdblk_bypass_shift = 1, | |
132 | .has_shadowcon = 1, | |
133 | .has_vidoutcon = 1, | |
3c3c9c1d | 134 | .has_vtsel = 1, |
dcb622aa YC |
135 | }; |
136 | ||
6ecf18f9 | 137 | static struct fimd_driver_data exynos5_fimd_driver_data = { |
e2e13389 | 138 | .timing_base = 0x20000, |
3854fab2 YC |
139 | .lcdblk_offset = 0x214, |
140 | .lcdblk_vt_shift = 24, | |
141 | .lcdblk_bypass_shift = 15, | |
de7af100 | 142 | .has_shadowcon = 1, |
3854fab2 | 143 | .has_vidoutcon = 1, |
3c3c9c1d | 144 | .has_vtsel = 1, |
e2e13389 LKA |
145 | }; |
146 | ||
1c248b7d | 147 | struct fimd_context { |
bb7704d6 | 148 | struct device *dev; |
40c8ab4b | 149 | struct drm_device *drm_dev; |
93bca243 | 150 | struct exynos_drm_crtc *crtc; |
7ee14cdc | 151 | struct exynos_drm_plane planes[WINDOWS_NR]; |
1c248b7d ID |
152 | struct clk *bus_clk; |
153 | struct clk *lcd_clk; | |
1c248b7d | 154 | void __iomem *regs; |
3854fab2 | 155 | struct regmap *sysreg; |
1c248b7d ID |
156 | unsigned int default_win; |
157 | unsigned long irq_flags; | |
3854fab2 | 158 | u32 vidcon0; |
1c248b7d | 159 | u32 vidcon1; |
3854fab2 YC |
160 | u32 vidout_con; |
161 | u32 i80ifcon; | |
162 | bool i80_if; | |
cb91f6a0 | 163 | bool suspended; |
080be03d | 164 | int pipe; |
01ce113c P |
165 | wait_queue_head_t wait_vsync_queue; |
166 | atomic_t wait_vsync_event; | |
3854fab2 YC |
167 | atomic_t win_updated; |
168 | atomic_t triggering; | |
1c248b7d | 169 | |
562ad9f4 | 170 | struct exynos_drm_panel_info panel; |
18873465 | 171 | struct fimd_driver_data *driver_data; |
cf67cc9a | 172 | struct exynos_drm_encoder *encoder; |
1c248b7d ID |
173 | }; |
174 | ||
d636ead8 | 175 | static const struct of_device_id fimd_driver_dt_match[] = { |
725ddead TF |
176 | { .compatible = "samsung,s3c6400-fimd", |
177 | .data = &s3c64xx_fimd_driver_data }, | |
d6ce7b58 ID |
178 | { .compatible = "samsung,exynos3250-fimd", |
179 | .data = &exynos3_fimd_driver_data }, | |
5830daf8 | 180 | { .compatible = "samsung,exynos4210-fimd", |
d636ead8 | 181 | .data = &exynos4_fimd_driver_data }, |
dcb622aa YC |
182 | { .compatible = "samsung,exynos4415-fimd", |
183 | .data = &exynos4415_fimd_driver_data }, | |
5830daf8 | 184 | { .compatible = "samsung,exynos5250-fimd", |
d636ead8 JS |
185 | .data = &exynos5_fimd_driver_data }, |
186 | {}, | |
187 | }; | |
0262ceeb | 188 | MODULE_DEVICE_TABLE(of, fimd_driver_dt_match); |
d636ead8 | 189 | |
e2e13389 LKA |
190 | static inline struct fimd_driver_data *drm_fimd_get_driver_data( |
191 | struct platform_device *pdev) | |
192 | { | |
d636ead8 JS |
193 | const struct of_device_id *of_id = |
194 | of_match_device(fimd_driver_dt_match, &pdev->dev); | |
195 | ||
2d3f173c | 196 | return (struct fimd_driver_data *)of_id->data; |
e2e13389 LKA |
197 | } |
198 | ||
fb88e214 MS |
199 | static int fimd_enable_vblank(struct exynos_drm_crtc *crtc) |
200 | { | |
201 | struct fimd_context *ctx = crtc->ctx; | |
202 | u32 val; | |
203 | ||
204 | if (ctx->suspended) | |
205 | return -EPERM; | |
206 | ||
207 | if (!test_and_set_bit(0, &ctx->irq_flags)) { | |
208 | val = readl(ctx->regs + VIDINTCON0); | |
209 | ||
210 | val |= VIDINTCON0_INT_ENABLE; | |
211 | ||
212 | if (ctx->i80_if) { | |
213 | val |= VIDINTCON0_INT_I80IFDONE; | |
214 | val |= VIDINTCON0_INT_SYSMAINCON; | |
215 | val &= ~VIDINTCON0_INT_SYSSUBCON; | |
216 | } else { | |
217 | val |= VIDINTCON0_INT_FRAME; | |
218 | ||
219 | val &= ~VIDINTCON0_FRAMESEL0_MASK; | |
220 | val |= VIDINTCON0_FRAMESEL0_VSYNC; | |
221 | val &= ~VIDINTCON0_FRAMESEL1_MASK; | |
222 | val |= VIDINTCON0_FRAMESEL1_NONE; | |
223 | } | |
224 | ||
225 | writel(val, ctx->regs + VIDINTCON0); | |
226 | } | |
227 | ||
228 | return 0; | |
229 | } | |
230 | ||
231 | static void fimd_disable_vblank(struct exynos_drm_crtc *crtc) | |
232 | { | |
233 | struct fimd_context *ctx = crtc->ctx; | |
234 | u32 val; | |
235 | ||
236 | if (ctx->suspended) | |
237 | return; | |
238 | ||
239 | if (test_and_clear_bit(0, &ctx->irq_flags)) { | |
240 | val = readl(ctx->regs + VIDINTCON0); | |
241 | ||
242 | val &= ~VIDINTCON0_INT_ENABLE; | |
243 | ||
244 | if (ctx->i80_if) { | |
245 | val &= ~VIDINTCON0_INT_I80IFDONE; | |
246 | val &= ~VIDINTCON0_INT_SYSMAINCON; | |
247 | val &= ~VIDINTCON0_INT_SYSSUBCON; | |
248 | } else | |
249 | val &= ~VIDINTCON0_INT_FRAME; | |
250 | ||
251 | writel(val, ctx->regs + VIDINTCON0); | |
252 | } | |
253 | } | |
254 | ||
93bca243 | 255 | static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc) |
f13bdbd1 | 256 | { |
93bca243 | 257 | struct fimd_context *ctx = crtc->ctx; |
f13bdbd1 AA |
258 | |
259 | if (ctx->suspended) | |
260 | return; | |
261 | ||
262 | atomic_set(&ctx->wait_vsync_event, 1); | |
263 | ||
264 | /* | |
265 | * wait for FIMD to signal VSYNC interrupt or return after | |
266 | * timeout which is set to 50ms (refresh rate of 20). | |
267 | */ | |
268 | if (!wait_event_timeout(ctx->wait_vsync_queue, | |
269 | !atomic_read(&ctx->wait_vsync_event), | |
270 | HZ/20)) | |
271 | DRM_DEBUG_KMS("vblank wait timed out.\n"); | |
272 | } | |
273 | ||
5b1d5bc6 | 274 | static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win, |
f181a543 YC |
275 | bool enable) |
276 | { | |
277 | u32 val = readl(ctx->regs + WINCON(win)); | |
278 | ||
279 | if (enable) | |
280 | val |= WINCONx_ENWIN; | |
281 | else | |
282 | val &= ~WINCONx_ENWIN; | |
283 | ||
284 | writel(val, ctx->regs + WINCON(win)); | |
285 | } | |
286 | ||
5b1d5bc6 TJ |
287 | static void fimd_enable_shadow_channel_path(struct fimd_context *ctx, |
288 | unsigned int win, | |
999d8b31 YC |
289 | bool enable) |
290 | { | |
291 | u32 val = readl(ctx->regs + SHADOWCON); | |
292 | ||
293 | if (enable) | |
294 | val |= SHADOWCON_CHx_ENABLE(win); | |
295 | else | |
296 | val &= ~SHADOWCON_CHx_ENABLE(win); | |
297 | ||
298 | writel(val, ctx->regs + SHADOWCON); | |
299 | } | |
300 | ||
fc2e013f | 301 | static void fimd_clear_channels(struct exynos_drm_crtc *crtc) |
f13bdbd1 | 302 | { |
fc2e013f | 303 | struct fimd_context *ctx = crtc->ctx; |
5b1d5bc6 | 304 | unsigned int win, ch_enabled = 0; |
f13bdbd1 AA |
305 | |
306 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
307 | ||
fb88e214 MS |
308 | /* Hardware is in unknown state, so ensure it gets enabled properly */ |
309 | pm_runtime_get_sync(ctx->dev); | |
310 | ||
311 | clk_prepare_enable(ctx->bus_clk); | |
312 | clk_prepare_enable(ctx->lcd_clk); | |
313 | ||
f13bdbd1 AA |
314 | /* Check if any channel is enabled. */ |
315 | for (win = 0; win < WINDOWS_NR; win++) { | |
eb8a3bf7 MS |
316 | u32 val = readl(ctx->regs + WINCON(win)); |
317 | ||
318 | if (val & WINCONx_ENWIN) { | |
f181a543 | 319 | fimd_enable_video_output(ctx, win, false); |
eb8a3bf7 | 320 | |
999d8b31 YC |
321 | if (ctx->driver_data->has_shadowcon) |
322 | fimd_enable_shadow_channel_path(ctx, win, | |
323 | false); | |
324 | ||
f13bdbd1 AA |
325 | ch_enabled = 1; |
326 | } | |
327 | } | |
328 | ||
329 | /* Wait for vsync, as disable channel takes effect at next vsync */ | |
eb8a3bf7 | 330 | if (ch_enabled) { |
fb88e214 MS |
331 | int pipe = ctx->pipe; |
332 | ||
333 | /* ensure that vblank interrupt won't be reported to core */ | |
334 | ctx->suspended = false; | |
335 | ctx->pipe = -1; | |
eb8a3bf7 | 336 | |
fb88e214 | 337 | fimd_enable_vblank(ctx->crtc); |
92dc7a04 | 338 | fimd_wait_for_vblank(ctx->crtc); |
fb88e214 MS |
339 | fimd_disable_vblank(ctx->crtc); |
340 | ||
341 | ctx->suspended = true; | |
342 | ctx->pipe = pipe; | |
eb8a3bf7 | 343 | } |
fb88e214 MS |
344 | |
345 | clk_disable_unprepare(ctx->lcd_clk); | |
346 | clk_disable_unprepare(ctx->bus_clk); | |
347 | ||
348 | pm_runtime_put(ctx->dev); | |
f13bdbd1 AA |
349 | } |
350 | ||
a968e727 SP |
351 | static u32 fimd_calc_clkdiv(struct fimd_context *ctx, |
352 | const struct drm_display_mode *mode) | |
353 | { | |
354 | unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh; | |
355 | u32 clkdiv; | |
356 | ||
3854fab2 YC |
357 | if (ctx->i80_if) { |
358 | /* | |
359 | * The frame done interrupt should be occurred prior to the | |
360 | * next TE signal. | |
361 | */ | |
362 | ideal_clk *= 2; | |
363 | } | |
364 | ||
a968e727 SP |
365 | /* Find the clock divider value that gets us closest to ideal_clk */ |
366 | clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk); | |
367 | ||
368 | return (clkdiv < 0x100) ? clkdiv : 0xff; | |
369 | } | |
370 | ||
93bca243 | 371 | static bool fimd_mode_fixup(struct exynos_drm_crtc *crtc, |
a968e727 SP |
372 | const struct drm_display_mode *mode, |
373 | struct drm_display_mode *adjusted_mode) | |
374 | { | |
375 | if (adjusted_mode->vrefresh == 0) | |
376 | adjusted_mode->vrefresh = FIMD_DEFAULT_FRAMERATE; | |
377 | ||
378 | return true; | |
379 | } | |
380 | ||
93bca243 | 381 | static void fimd_commit(struct exynos_drm_crtc *crtc) |
1c248b7d | 382 | { |
93bca243 | 383 | struct fimd_context *ctx = crtc->ctx; |
020e79de | 384 | struct drm_display_mode *mode = &crtc->base.state->adjusted_mode; |
3854fab2 YC |
385 | struct fimd_driver_data *driver_data = ctx->driver_data; |
386 | void *timing_base = ctx->regs + driver_data->timing_base; | |
387 | u32 val, clkdiv; | |
1c248b7d | 388 | |
e30d4bcf ID |
389 | if (ctx->suspended) |
390 | return; | |
391 | ||
a968e727 SP |
392 | /* nothing to do if we haven't set the mode yet */ |
393 | if (mode->htotal == 0 || mode->vtotal == 0) | |
394 | return; | |
395 | ||
3854fab2 YC |
396 | if (ctx->i80_if) { |
397 | val = ctx->i80ifcon | I80IFEN_ENABLE; | |
398 | writel(val, timing_base + I80IFCONFAx(0)); | |
399 | ||
400 | /* disable auto frame rate */ | |
401 | writel(0, timing_base + I80IFCONFBx(0)); | |
402 | ||
403 | /* set video type selection to I80 interface */ | |
3c3c9c1d JS |
404 | if (driver_data->has_vtsel && ctx->sysreg && |
405 | regmap_update_bits(ctx->sysreg, | |
3854fab2 YC |
406 | driver_data->lcdblk_offset, |
407 | 0x3 << driver_data->lcdblk_vt_shift, | |
408 | 0x1 << driver_data->lcdblk_vt_shift)) { | |
409 | DRM_ERROR("Failed to update sysreg for I80 i/f.\n"); | |
410 | return; | |
411 | } | |
412 | } else { | |
413 | int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd; | |
414 | u32 vidcon1; | |
415 | ||
416 | /* setup polarity values */ | |
417 | vidcon1 = ctx->vidcon1; | |
418 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
419 | vidcon1 |= VIDCON1_INV_VSYNC; | |
420 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
421 | vidcon1 |= VIDCON1_INV_HSYNC; | |
422 | writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1); | |
423 | ||
424 | /* setup vertical timing values. */ | |
425 | vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; | |
426 | vbpd = mode->crtc_vtotal - mode->crtc_vsync_end; | |
427 | vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay; | |
428 | ||
429 | val = VIDTCON0_VBPD(vbpd - 1) | | |
430 | VIDTCON0_VFPD(vfpd - 1) | | |
431 | VIDTCON0_VSPW(vsync_len - 1); | |
432 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON0); | |
433 | ||
434 | /* setup horizontal timing values. */ | |
435 | hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; | |
436 | hbpd = mode->crtc_htotal - mode->crtc_hsync_end; | |
437 | hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay; | |
438 | ||
439 | val = VIDTCON1_HBPD(hbpd - 1) | | |
440 | VIDTCON1_HFPD(hfpd - 1) | | |
441 | VIDTCON1_HSPW(hsync_len - 1); | |
442 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON1); | |
443 | } | |
444 | ||
445 | if (driver_data->has_vidoutcon) | |
446 | writel(ctx->vidout_con, timing_base + VIDOUT_CON); | |
447 | ||
448 | /* set bypass selection */ | |
449 | if (ctx->sysreg && regmap_update_bits(ctx->sysreg, | |
450 | driver_data->lcdblk_offset, | |
451 | 0x1 << driver_data->lcdblk_bypass_shift, | |
452 | 0x1 << driver_data->lcdblk_bypass_shift)) { | |
453 | DRM_ERROR("Failed to update sysreg for bypass setting.\n"); | |
454 | return; | |
455 | } | |
1c248b7d ID |
456 | |
457 | /* setup horizontal and vertical display size. */ | |
a968e727 SP |
458 | val = VIDTCON2_LINEVAL(mode->vdisplay - 1) | |
459 | VIDTCON2_HOZVAL(mode->hdisplay - 1) | | |
460 | VIDTCON2_LINEVAL_E(mode->vdisplay - 1) | | |
461 | VIDTCON2_HOZVAL_E(mode->hdisplay - 1); | |
e2e13389 | 462 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON2); |
1c248b7d | 463 | |
1d531062 AH |
464 | /* |
465 | * fields of register with prefix '_F' would be updated | |
466 | * at vsync(same as dma start) | |
467 | */ | |
3854fab2 YC |
468 | val = ctx->vidcon0; |
469 | val |= VIDCON0_ENVID | VIDCON0_ENVID_F; | |
1c248b7d | 470 | |
1d531062 | 471 | if (ctx->driver_data->has_clksel) |
411d9ed4 | 472 | val |= VIDCON0_CLKSEL_LCD; |
411d9ed4 | 473 | |
a968e727 SP |
474 | clkdiv = fimd_calc_clkdiv(ctx, mode); |
475 | if (clkdiv > 1) | |
476 | val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR; | |
1c248b7d | 477 | |
1c248b7d ID |
478 | writel(val, ctx->regs + VIDCON0); |
479 | } | |
480 | ||
1c248b7d | 481 | |
2eeb2e5e GP |
482 | static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win, |
483 | struct drm_framebuffer *fb) | |
1c248b7d | 484 | { |
1c248b7d ID |
485 | unsigned long val; |
486 | ||
1c248b7d ID |
487 | val = WINCONx_ENWIN; |
488 | ||
5cc4621a ID |
489 | /* |
490 | * In case of s3c64xx, window 0 doesn't support alpha channel. | |
491 | * So the request format is ARGB8888 then change it to XRGB8888. | |
492 | */ | |
493 | if (ctx->driver_data->has_limited_fmt && !win) { | |
2eeb2e5e GP |
494 | if (fb->pixel_format == DRM_FORMAT_ARGB8888) |
495 | fb->pixel_format = DRM_FORMAT_XRGB8888; | |
5cc4621a ID |
496 | } |
497 | ||
2eeb2e5e | 498 | switch (fb->pixel_format) { |
a4f38a80 | 499 | case DRM_FORMAT_C8: |
1c248b7d ID |
500 | val |= WINCON0_BPPMODE_8BPP_PALETTE; |
501 | val |= WINCONx_BURSTLEN_8WORD; | |
502 | val |= WINCONx_BYTSWP; | |
503 | break; | |
a4f38a80 ID |
504 | case DRM_FORMAT_XRGB1555: |
505 | val |= WINCON0_BPPMODE_16BPP_1555; | |
506 | val |= WINCONx_HAWSWP; | |
507 | val |= WINCONx_BURSTLEN_16WORD; | |
508 | break; | |
509 | case DRM_FORMAT_RGB565: | |
1c248b7d ID |
510 | val |= WINCON0_BPPMODE_16BPP_565; |
511 | val |= WINCONx_HAWSWP; | |
512 | val |= WINCONx_BURSTLEN_16WORD; | |
513 | break; | |
a4f38a80 | 514 | case DRM_FORMAT_XRGB8888: |
1c248b7d ID |
515 | val |= WINCON0_BPPMODE_24BPP_888; |
516 | val |= WINCONx_WSWP; | |
517 | val |= WINCONx_BURSTLEN_16WORD; | |
518 | break; | |
a4f38a80 ID |
519 | case DRM_FORMAT_ARGB8888: |
520 | val |= WINCON1_BPPMODE_25BPP_A1888 | |
1c248b7d ID |
521 | | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL; |
522 | val |= WINCONx_WSWP; | |
523 | val |= WINCONx_BURSTLEN_16WORD; | |
524 | break; | |
525 | default: | |
526 | DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n"); | |
527 | ||
528 | val |= WINCON0_BPPMODE_24BPP_888; | |
529 | val |= WINCONx_WSWP; | |
530 | val |= WINCONx_BURSTLEN_16WORD; | |
531 | break; | |
532 | } | |
533 | ||
2eeb2e5e | 534 | DRM_DEBUG_KMS("bpp = %d\n", fb->bits_per_pixel); |
1c248b7d | 535 | |
66367461 RS |
536 | /* |
537 | * In case of exynos, setting dma-burst to 16Word causes permanent | |
538 | * tearing for very small buffers, e.g. cursor buffer. Burst Mode | |
8837deea GP |
539 | * switching which is based on plane size is not recommended as |
540 | * plane size varies alot towards the end of the screen and rapid | |
66367461 RS |
541 | * movement causes unstable DMA which results into iommu crash/tear. |
542 | */ | |
543 | ||
2eeb2e5e | 544 | if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) { |
66367461 RS |
545 | val &= ~WINCONx_BURSTLEN_MASK; |
546 | val |= WINCONx_BURSTLEN_4WORD; | |
547 | } | |
548 | ||
1c248b7d | 549 | writel(val, ctx->regs + WINCON(win)); |
453b44a3 GP |
550 | |
551 | /* hardware window 0 doesn't support alpha channel. */ | |
552 | if (win != 0) { | |
553 | /* OSD alpha */ | |
554 | val = VIDISD14C_ALPHA0_R(0xf) | | |
555 | VIDISD14C_ALPHA0_G(0xf) | | |
556 | VIDISD14C_ALPHA0_B(0xf) | | |
557 | VIDISD14C_ALPHA1_R(0xf) | | |
558 | VIDISD14C_ALPHA1_G(0xf) | | |
559 | VIDISD14C_ALPHA1_B(0xf); | |
560 | ||
561 | writel(val, ctx->regs + VIDOSD_C(win)); | |
562 | ||
563 | val = VIDW_ALPHA_R(0xf) | VIDW_ALPHA_G(0xf) | | |
564 | VIDW_ALPHA_G(0xf); | |
565 | writel(val, ctx->regs + VIDWnALPHA0(win)); | |
566 | writel(val, ctx->regs + VIDWnALPHA1(win)); | |
567 | } | |
1c248b7d ID |
568 | } |
569 | ||
bb7704d6 | 570 | static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win) |
1c248b7d | 571 | { |
1c248b7d ID |
572 | unsigned int keycon0 = 0, keycon1 = 0; |
573 | ||
1c248b7d ID |
574 | keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F | |
575 | WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); | |
576 | ||
577 | keycon1 = WxKEYCON1_COLVAL(0xffffffff); | |
578 | ||
579 | writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); | |
580 | writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); | |
581 | } | |
582 | ||
de7af100 TF |
583 | /** |
584 | * shadow_protect_win() - disable updating values from shadow registers at vsync | |
585 | * | |
586 | * @win: window to protect registers for | |
587 | * @protect: 1 to protect (disable updates) | |
588 | */ | |
589 | static void fimd_shadow_protect_win(struct fimd_context *ctx, | |
6e2a3b66 | 590 | unsigned int win, bool protect) |
de7af100 TF |
591 | { |
592 | u32 reg, bits, val; | |
593 | ||
594 | if (ctx->driver_data->has_shadowcon) { | |
595 | reg = SHADOWCON; | |
596 | bits = SHADOWCON_WINx_PROTECT(win); | |
597 | } else { | |
598 | reg = PRTCON; | |
599 | bits = PRTCON_PROTECT; | |
600 | } | |
601 | ||
602 | val = readl(ctx->regs + reg); | |
603 | if (protect) | |
604 | val |= bits; | |
605 | else | |
606 | val &= ~bits; | |
607 | writel(val, ctx->regs + reg); | |
608 | } | |
609 | ||
1e1d1393 GP |
610 | static void fimd_update_plane(struct exynos_drm_crtc *crtc, |
611 | struct exynos_drm_plane *plane) | |
1c248b7d | 612 | { |
93bca243 | 613 | struct fimd_context *ctx = crtc->ctx; |
2eeb2e5e | 614 | struct drm_plane_state *state = plane->base.state; |
7ee14cdc GP |
615 | dma_addr_t dma_addr; |
616 | unsigned long val, size, offset; | |
617 | unsigned int last_x, last_y, buf_offsize, line_size; | |
1e1d1393 | 618 | unsigned int win = plane->zpos; |
2eeb2e5e GP |
619 | unsigned int bpp = state->fb->bits_per_pixel >> 3; |
620 | unsigned int pitch = state->fb->pitches[0]; | |
1c248b7d | 621 | |
e30d4bcf ID |
622 | if (ctx->suspended) |
623 | return; | |
624 | ||
1c248b7d | 625 | /* |
de7af100 | 626 | * SHADOWCON/PRTCON register is used for enabling timing. |
1c248b7d ID |
627 | * |
628 | * for example, once only width value of a register is set, | |
629 | * if the dma is started then fimd hardware could malfunction so | |
630 | * with protect window setting, the register fields with prefix '_F' | |
631 | * wouldn't be updated at vsync also but updated once unprotect window | |
632 | * is set. | |
633 | */ | |
634 | ||
635 | /* protect windows */ | |
de7af100 | 636 | fimd_shadow_protect_win(ctx, win, true); |
1c248b7d | 637 | |
7ee14cdc | 638 | |
2eeb2e5e GP |
639 | offset = plane->src_x * bpp; |
640 | offset += plane->src_y * pitch; | |
7ee14cdc | 641 | |
1c248b7d | 642 | /* buffer start address */ |
7ee14cdc GP |
643 | dma_addr = plane->dma_addr[0] + offset; |
644 | val = (unsigned long)dma_addr; | |
1c248b7d ID |
645 | writel(val, ctx->regs + VIDWx_BUF_START(win, 0)); |
646 | ||
647 | /* buffer end address */ | |
d88d2463 | 648 | size = pitch * plane->crtc_h; |
7ee14cdc | 649 | val = (unsigned long)(dma_addr + size); |
1c248b7d ID |
650 | writel(val, ctx->regs + VIDWx_BUF_END(win, 0)); |
651 | ||
652 | DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n", | |
7ee14cdc | 653 | (unsigned long)dma_addr, val, size); |
19c8b834 | 654 | DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", |
d88d2463 | 655 | plane->crtc_w, plane->crtc_h); |
1c248b7d ID |
656 | |
657 | /* buffer size */ | |
d88d2463 GP |
658 | buf_offsize = pitch - (plane->crtc_w * bpp); |
659 | line_size = plane->crtc_w * bpp; | |
7ee14cdc GP |
660 | val = VIDW_BUF_SIZE_OFFSET(buf_offsize) | |
661 | VIDW_BUF_SIZE_PAGEWIDTH(line_size) | | |
662 | VIDW_BUF_SIZE_OFFSET_E(buf_offsize) | | |
663 | VIDW_BUF_SIZE_PAGEWIDTH_E(line_size); | |
1c248b7d ID |
664 | writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0)); |
665 | ||
666 | /* OSD position */ | |
7ee14cdc GP |
667 | val = VIDOSDxA_TOPLEFT_X(plane->crtc_x) | |
668 | VIDOSDxA_TOPLEFT_Y(plane->crtc_y) | | |
669 | VIDOSDxA_TOPLEFT_X_E(plane->crtc_x) | | |
670 | VIDOSDxA_TOPLEFT_Y_E(plane->crtc_y); | |
1c248b7d ID |
671 | writel(val, ctx->regs + VIDOSD_A(win)); |
672 | ||
d88d2463 | 673 | last_x = plane->crtc_x + plane->crtc_w; |
f56aad3a JS |
674 | if (last_x) |
675 | last_x--; | |
d88d2463 | 676 | last_y = plane->crtc_y + plane->crtc_h; |
f56aad3a JS |
677 | if (last_y) |
678 | last_y--; | |
679 | ||
ca555e5a JS |
680 | val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) | |
681 | VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y); | |
682 | ||
1c248b7d ID |
683 | writel(val, ctx->regs + VIDOSD_B(win)); |
684 | ||
19c8b834 | 685 | DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", |
7ee14cdc | 686 | plane->crtc_x, plane->crtc_y, last_x, last_y); |
1c248b7d | 687 | |
1c248b7d ID |
688 | /* OSD size */ |
689 | if (win != 3 && win != 4) { | |
690 | u32 offset = VIDOSD_D(win); | |
691 | if (win == 0) | |
0f10cf14 | 692 | offset = VIDOSD_C(win); |
d88d2463 | 693 | val = plane->crtc_w * plane->crtc_h; |
1c248b7d ID |
694 | writel(val, ctx->regs + offset); |
695 | ||
696 | DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val); | |
697 | } | |
698 | ||
2eeb2e5e | 699 | fimd_win_set_pixfmt(ctx, win, state->fb); |
1c248b7d ID |
700 | |
701 | /* hardware window 0 doesn't support color key. */ | |
702 | if (win != 0) | |
bb7704d6 | 703 | fimd_win_set_colkey(ctx, win); |
1c248b7d | 704 | |
f181a543 | 705 | fimd_enable_video_output(ctx, win, true); |
ec05da95 | 706 | |
999d8b31 YC |
707 | if (ctx->driver_data->has_shadowcon) |
708 | fimd_enable_shadow_channel_path(ctx, win, true); | |
ec05da95 | 709 | |
74944a58 YC |
710 | /* Enable DMA channel and unprotect windows */ |
711 | fimd_shadow_protect_win(ctx, win, false); | |
712 | ||
3854fab2 YC |
713 | if (ctx->i80_if) |
714 | atomic_set(&ctx->win_updated, 1); | |
1c248b7d ID |
715 | } |
716 | ||
1e1d1393 GP |
717 | static void fimd_disable_plane(struct exynos_drm_crtc *crtc, |
718 | struct exynos_drm_plane *plane) | |
1c248b7d | 719 | { |
93bca243 | 720 | struct fimd_context *ctx = crtc->ctx; |
1e1d1393 | 721 | unsigned int win = plane->zpos; |
ec05da95 | 722 | |
c329f667 | 723 | if (ctx->suspended) |
db7e55ae | 724 | return; |
db7e55ae | 725 | |
1c248b7d | 726 | /* protect windows */ |
de7af100 | 727 | fimd_shadow_protect_win(ctx, win, true); |
1c248b7d | 728 | |
f181a543 | 729 | fimd_enable_video_output(ctx, win, false); |
1c248b7d | 730 | |
999d8b31 YC |
731 | if (ctx->driver_data->has_shadowcon) |
732 | fimd_enable_shadow_channel_path(ctx, win, false); | |
de7af100 | 733 | |
999d8b31 | 734 | /* unprotect windows */ |
de7af100 | 735 | fimd_shadow_protect_win(ctx, win, false); |
a43b933b SP |
736 | } |
737 | ||
3cecda03 | 738 | static void fimd_enable(struct exynos_drm_crtc *crtc) |
a43b933b | 739 | { |
3cecda03 | 740 | struct fimd_context *ctx = crtc->ctx; |
38000dbb | 741 | int ret; |
a43b933b SP |
742 | |
743 | if (!ctx->suspended) | |
3cecda03 | 744 | return; |
a43b933b SP |
745 | |
746 | ctx->suspended = false; | |
747 | ||
af65c804 SP |
748 | pm_runtime_get_sync(ctx->dev); |
749 | ||
38000dbb GP |
750 | ret = clk_prepare_enable(ctx->bus_clk); |
751 | if (ret < 0) { | |
752 | DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret); | |
753 | return; | |
754 | } | |
755 | ||
756 | ret = clk_prepare_enable(ctx->lcd_clk); | |
757 | if (ret < 0) { | |
758 | DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret); | |
759 | return; | |
760 | } | |
a43b933b SP |
761 | |
762 | /* if vblank was enabled status, enable it again. */ | |
3cecda03 GP |
763 | if (test_and_clear_bit(0, &ctx->irq_flags)) |
764 | fimd_enable_vblank(ctx->crtc); | |
a43b933b | 765 | |
c329f667 | 766 | fimd_commit(ctx->crtc); |
a43b933b SP |
767 | } |
768 | ||
3cecda03 | 769 | static void fimd_disable(struct exynos_drm_crtc *crtc) |
a43b933b | 770 | { |
3cecda03 | 771 | struct fimd_context *ctx = crtc->ctx; |
c329f667 | 772 | int i; |
3cecda03 | 773 | |
a43b933b | 774 | if (ctx->suspended) |
3cecda03 | 775 | return; |
a43b933b SP |
776 | |
777 | /* | |
778 | * We need to make sure that all windows are disabled before we | |
779 | * suspend that connector. Otherwise we might try to scan from | |
780 | * a destroyed buffer later. | |
781 | */ | |
c329f667 | 782 | for (i = 0; i < WINDOWS_NR; i++) |
1e1d1393 | 783 | fimd_disable_plane(crtc, &ctx->planes[i]); |
a43b933b | 784 | |
94ab95a9 ID |
785 | fimd_enable_vblank(crtc); |
786 | fimd_wait_for_vblank(crtc); | |
787 | fimd_disable_vblank(crtc); | |
788 | ||
b74f14fd JS |
789 | writel(0, ctx->regs + VIDCON0); |
790 | ||
a43b933b SP |
791 | clk_disable_unprepare(ctx->lcd_clk); |
792 | clk_disable_unprepare(ctx->bus_clk); | |
793 | ||
af65c804 SP |
794 | pm_runtime_put_sync(ctx->dev); |
795 | ||
a43b933b | 796 | ctx->suspended = true; |
080be03d SP |
797 | } |
798 | ||
3854fab2 YC |
799 | static void fimd_trigger(struct device *dev) |
800 | { | |
e152dbd7 | 801 | struct fimd_context *ctx = dev_get_drvdata(dev); |
3854fab2 YC |
802 | struct fimd_driver_data *driver_data = ctx->driver_data; |
803 | void *timing_base = ctx->regs + driver_data->timing_base; | |
804 | u32 reg; | |
805 | ||
9b67eb73 | 806 | /* |
1c905d95 YC |
807 | * Skips triggering if in triggering state, because multiple triggering |
808 | * requests can cause panel reset. | |
809 | */ | |
9b67eb73 JS |
810 | if (atomic_read(&ctx->triggering)) |
811 | return; | |
812 | ||
1c905d95 | 813 | /* Enters triggering mode */ |
3854fab2 YC |
814 | atomic_set(&ctx->triggering, 1); |
815 | ||
3854fab2 YC |
816 | reg = readl(timing_base + TRIGCON); |
817 | reg |= (TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE); | |
818 | writel(reg, timing_base + TRIGCON); | |
87ab85b3 YC |
819 | |
820 | /* | |
821 | * Exits triggering mode if vblank is not enabled yet, because when the | |
822 | * VIDINTCON0 register is not set, it can not exit from triggering mode. | |
823 | */ | |
824 | if (!test_bit(0, &ctx->irq_flags)) | |
825 | atomic_set(&ctx->triggering, 0); | |
3854fab2 YC |
826 | } |
827 | ||
93bca243 | 828 | static void fimd_te_handler(struct exynos_drm_crtc *crtc) |
3854fab2 | 829 | { |
93bca243 | 830 | struct fimd_context *ctx = crtc->ctx; |
3854fab2 YC |
831 | |
832 | /* Checks the crtc is detached already from encoder */ | |
833 | if (ctx->pipe < 0 || !ctx->drm_dev) | |
834 | return; | |
835 | ||
3854fab2 YC |
836 | /* |
837 | * If there is a page flip request, triggers and handles the page flip | |
838 | * event so that current fb can be updated into panel GRAM. | |
839 | */ | |
840 | if (atomic_add_unless(&ctx->win_updated, -1, 0)) | |
841 | fimd_trigger(ctx->dev); | |
842 | ||
843 | /* Wakes up vsync event queue */ | |
844 | if (atomic_read(&ctx->wait_vsync_event)) { | |
845 | atomic_set(&ctx->wait_vsync_event, 0); | |
846 | wake_up(&ctx->wait_vsync_queue); | |
3854fab2 | 847 | } |
b301ae24 | 848 | |
adf67abf | 849 | if (test_bit(0, &ctx->irq_flags)) |
eafd540a | 850 | drm_crtc_handle_vblank(&ctx->crtc->base); |
3854fab2 YC |
851 | } |
852 | ||
48107d7b KK |
853 | static void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable) |
854 | { | |
855 | struct fimd_context *ctx = crtc->ctx; | |
856 | u32 val; | |
857 | ||
858 | /* | |
859 | * Only Exynos 5250, 5260, 5410 and 542x requires enabling DP/MIE | |
860 | * clock. On these SoCs the bootloader may enable it but any | |
861 | * power domain off/on will reset it to disable state. | |
862 | */ | |
863 | if (ctx->driver_data != &exynos5_fimd_driver_data) | |
864 | return; | |
865 | ||
866 | val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE; | |
867 | writel(DP_MIE_CLK_DP_ENABLE, ctx->regs + DP_MIE_CLKCON); | |
868 | } | |
869 | ||
f3aaf762 | 870 | static const struct exynos_drm_crtc_ops fimd_crtc_ops = { |
3cecda03 GP |
871 | .enable = fimd_enable, |
872 | .disable = fimd_disable, | |
a968e727 | 873 | .mode_fixup = fimd_mode_fixup, |
1c6244c3 SP |
874 | .commit = fimd_commit, |
875 | .enable_vblank = fimd_enable_vblank, | |
876 | .disable_vblank = fimd_disable_vblank, | |
877 | .wait_for_vblank = fimd_wait_for_vblank, | |
9cc7610a GP |
878 | .update_plane = fimd_update_plane, |
879 | .disable_plane = fimd_disable_plane, | |
3854fab2 | 880 | .te_handler = fimd_te_handler, |
48107d7b | 881 | .clock_enable = fimd_dp_clock_enable, |
1c248b7d ID |
882 | }; |
883 | ||
1c248b7d ID |
884 | static irqreturn_t fimd_irq_handler(int irq, void *dev_id) |
885 | { | |
886 | struct fimd_context *ctx = (struct fimd_context *)dev_id; | |
3854fab2 | 887 | u32 val, clear_bit; |
1c248b7d ID |
888 | |
889 | val = readl(ctx->regs + VIDINTCON1); | |
890 | ||
3854fab2 YC |
891 | clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME; |
892 | if (val & clear_bit) | |
893 | writel(clear_bit, ctx->regs + VIDINTCON1); | |
1c248b7d | 894 | |
ec05da95 | 895 | /* check the crtc is detached already from encoder */ |
080be03d | 896 | if (ctx->pipe < 0 || !ctx->drm_dev) |
ec05da95 | 897 | goto out; |
483b88f8 | 898 | |
1c905d95 | 899 | if (ctx->i80_if) { |
eafd540a | 900 | exynos_drm_crtc_finish_pageflip(ctx->crtc); |
adf67abf | 901 | |
1c905d95 | 902 | /* Exits triggering mode */ |
3854fab2 | 903 | atomic_set(&ctx->triggering, 0); |
3854fab2 | 904 | } else { |
eafd540a GP |
905 | drm_crtc_handle_vblank(&ctx->crtc->base); |
906 | exynos_drm_crtc_finish_pageflip(ctx->crtc); | |
adf67abf | 907 | |
3854fab2 YC |
908 | /* set wait vsync event to zero and wake up queue. */ |
909 | if (atomic_read(&ctx->wait_vsync_event)) { | |
910 | atomic_set(&ctx->wait_vsync_event, 0); | |
911 | wake_up(&ctx->wait_vsync_queue); | |
912 | } | |
01ce113c | 913 | } |
3854fab2 | 914 | |
ec05da95 | 915 | out: |
1c248b7d ID |
916 | return IRQ_HANDLED; |
917 | } | |
918 | ||
f37cd5e8 | 919 | static int fimd_bind(struct device *dev, struct device *master, void *data) |
562ad9f4 | 920 | { |
e152dbd7 | 921 | struct fimd_context *ctx = dev_get_drvdata(dev); |
f37cd5e8 | 922 | struct drm_device *drm_dev = data; |
cdbfca89 | 923 | struct exynos_drm_private *priv = drm_dev->dev_private; |
7ee14cdc GP |
924 | struct exynos_drm_plane *exynos_plane; |
925 | enum drm_plane_type type; | |
6e2a3b66 GP |
926 | unsigned int zpos; |
927 | int ret; | |
000cc920 | 928 | |
cdbfca89 HH |
929 | ctx->drm_dev = drm_dev; |
930 | ctx->pipe = priv->pipe++; | |
efa75bcd | 931 | |
7ee14cdc GP |
932 | for (zpos = 0; zpos < WINDOWS_NR; zpos++) { |
933 | type = (zpos == ctx->default_win) ? DRM_PLANE_TYPE_PRIMARY : | |
934 | DRM_PLANE_TYPE_OVERLAY; | |
935 | ret = exynos_plane_init(drm_dev, &ctx->planes[zpos], | |
6e2a3b66 | 936 | 1 << ctx->pipe, type, zpos); |
7ee14cdc GP |
937 | if (ret) |
938 | return ret; | |
939 | } | |
940 | ||
941 | exynos_plane = &ctx->planes[ctx->default_win]; | |
942 | ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, | |
943 | ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD, | |
0f04cf8d | 944 | &fimd_crtc_ops, ctx); |
d1222842 HH |
945 | if (IS_ERR(ctx->crtc)) |
946 | return PTR_ERR(ctx->crtc); | |
93bca243 | 947 | |
cf67cc9a | 948 | if (ctx->encoder) |
a2986e80 | 949 | exynos_dpi_bind(drm_dev, ctx->encoder); |
000cc920 | 950 | |
43a3b866 JS |
951 | if (is_drm_iommu_supported(drm_dev)) |
952 | fimd_clear_channels(ctx->crtc); | |
eb7a3fc7 JS |
953 | |
954 | ret = drm_iommu_attach_device(drm_dev, dev); | |
fc2e013f HH |
955 | if (ret) |
956 | priv->pipe--; | |
957 | ||
958 | return ret; | |
000cc920 AH |
959 | } |
960 | ||
961 | static void fimd_unbind(struct device *dev, struct device *master, | |
962 | void *data) | |
963 | { | |
e152dbd7 | 964 | struct fimd_context *ctx = dev_get_drvdata(dev); |
000cc920 | 965 | |
3cecda03 | 966 | fimd_disable(ctx->crtc); |
000cc920 | 967 | |
bf56608a | 968 | drm_iommu_detach_device(ctx->drm_dev, ctx->dev); |
cdbfca89 | 969 | |
cf67cc9a GP |
970 | if (ctx->encoder) |
971 | exynos_dpi_remove(ctx->encoder); | |
000cc920 AH |
972 | } |
973 | ||
974 | static const struct component_ops fimd_component_ops = { | |
975 | .bind = fimd_bind, | |
976 | .unbind = fimd_unbind, | |
977 | }; | |
978 | ||
979 | static int fimd_probe(struct platform_device *pdev) | |
980 | { | |
981 | struct device *dev = &pdev->dev; | |
562ad9f4 | 982 | struct fimd_context *ctx; |
3854fab2 | 983 | struct device_node *i80_if_timings; |
562ad9f4 | 984 | struct resource *res; |
fe42cfb4 | 985 | int ret; |
1c248b7d | 986 | |
e152dbd7 AH |
987 | if (!dev->of_node) |
988 | return -ENODEV; | |
2d3f173c | 989 | |
d873ab99 | 990 | ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); |
e152dbd7 AH |
991 | if (!ctx) |
992 | return -ENOMEM; | |
993 | ||
bb7704d6 | 994 | ctx->dev = dev; |
a43b933b | 995 | ctx->suspended = true; |
3854fab2 | 996 | ctx->driver_data = drm_fimd_get_driver_data(pdev); |
bb7704d6 | 997 | |
1417f109 SP |
998 | if (of_property_read_bool(dev->of_node, "samsung,invert-vden")) |
999 | ctx->vidcon1 |= VIDCON1_INV_VDEN; | |
1000 | if (of_property_read_bool(dev->of_node, "samsung,invert-vclk")) | |
1001 | ctx->vidcon1 |= VIDCON1_INV_VCLK; | |
562ad9f4 | 1002 | |
3854fab2 YC |
1003 | i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings"); |
1004 | if (i80_if_timings) { | |
1005 | u32 val; | |
1006 | ||
1007 | ctx->i80_if = true; | |
1008 | ||
1009 | if (ctx->driver_data->has_vidoutcon) | |
1010 | ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0; | |
1011 | else | |
1012 | ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0; | |
1013 | /* | |
1014 | * The user manual describes that this "DSI_EN" bit is required | |
1015 | * to enable I80 24-bit data interface. | |
1016 | */ | |
1017 | ctx->vidcon0 |= VIDCON0_DSI_EN; | |
1018 | ||
1019 | if (of_property_read_u32(i80_if_timings, "cs-setup", &val)) | |
1020 | val = 0; | |
1021 | ctx->i80ifcon = LCD_CS_SETUP(val); | |
1022 | if (of_property_read_u32(i80_if_timings, "wr-setup", &val)) | |
1023 | val = 0; | |
1024 | ctx->i80ifcon |= LCD_WR_SETUP(val); | |
1025 | if (of_property_read_u32(i80_if_timings, "wr-active", &val)) | |
1026 | val = 1; | |
1027 | ctx->i80ifcon |= LCD_WR_ACTIVE(val); | |
1028 | if (of_property_read_u32(i80_if_timings, "wr-hold", &val)) | |
1029 | val = 0; | |
1030 | ctx->i80ifcon |= LCD_WR_HOLD(val); | |
1031 | } | |
1032 | of_node_put(i80_if_timings); | |
1033 | ||
1034 | ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node, | |
1035 | "samsung,sysreg"); | |
1036 | if (IS_ERR(ctx->sysreg)) { | |
1037 | dev_warn(dev, "failed to get system register.\n"); | |
1038 | ctx->sysreg = NULL; | |
1039 | } | |
1040 | ||
a968e727 SP |
1041 | ctx->bus_clk = devm_clk_get(dev, "fimd"); |
1042 | if (IS_ERR(ctx->bus_clk)) { | |
1043 | dev_err(dev, "failed to get bus clock\n"); | |
86650408 | 1044 | return PTR_ERR(ctx->bus_clk); |
a968e727 SP |
1045 | } |
1046 | ||
1047 | ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd"); | |
1048 | if (IS_ERR(ctx->lcd_clk)) { | |
1049 | dev_err(dev, "failed to get lcd clock\n"); | |
86650408 | 1050 | return PTR_ERR(ctx->lcd_clk); |
a968e727 | 1051 | } |
1c248b7d | 1052 | |
1c248b7d | 1053 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1c248b7d | 1054 | |
d873ab99 | 1055 | ctx->regs = devm_ioremap_resource(dev, res); |
86650408 AH |
1056 | if (IS_ERR(ctx->regs)) |
1057 | return PTR_ERR(ctx->regs); | |
1c248b7d | 1058 | |
3854fab2 YC |
1059 | res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, |
1060 | ctx->i80_if ? "lcd_sys" : "vsync"); | |
1c248b7d ID |
1061 | if (!res) { |
1062 | dev_err(dev, "irq request failed.\n"); | |
86650408 | 1063 | return -ENXIO; |
1c248b7d ID |
1064 | } |
1065 | ||
055e0c06 | 1066 | ret = devm_request_irq(dev, res->start, fimd_irq_handler, |
edc57266 SK |
1067 | 0, "drm_fimd", ctx); |
1068 | if (ret) { | |
1c248b7d | 1069 | dev_err(dev, "irq request failed.\n"); |
86650408 | 1070 | return ret; |
1c248b7d ID |
1071 | } |
1072 | ||
57ed0f7b | 1073 | init_waitqueue_head(&ctx->wait_vsync_queue); |
01ce113c | 1074 | atomic_set(&ctx->wait_vsync_event, 0); |
1c248b7d | 1075 | |
e152dbd7 | 1076 | platform_set_drvdata(pdev, ctx); |
14b6873a | 1077 | |
cf67cc9a GP |
1078 | ctx->encoder = exynos_dpi_probe(dev); |
1079 | if (IS_ERR(ctx->encoder)) | |
1080 | return PTR_ERR(ctx->encoder); | |
f37cd5e8 | 1081 | |
e152dbd7 | 1082 | pm_runtime_enable(dev); |
f37cd5e8 | 1083 | |
e152dbd7 | 1084 | ret = component_add(dev, &fimd_component_ops); |
df5225bc ID |
1085 | if (ret) |
1086 | goto err_disable_pm_runtime; | |
1087 | ||
1088 | return ret; | |
1089 | ||
1090 | err_disable_pm_runtime: | |
e152dbd7 | 1091 | pm_runtime_disable(dev); |
df5225bc | 1092 | |
df5225bc | 1093 | return ret; |
f37cd5e8 | 1094 | } |
cb91f6a0 | 1095 | |
f37cd5e8 ID |
1096 | static int fimd_remove(struct platform_device *pdev) |
1097 | { | |
af65c804 | 1098 | pm_runtime_disable(&pdev->dev); |
5d55393a | 1099 | |
df5225bc | 1100 | component_del(&pdev->dev, &fimd_component_ops); |
df5225bc | 1101 | |
5d55393a | 1102 | return 0; |
e30d4bcf ID |
1103 | } |
1104 | ||
132a5b91 | 1105 | struct platform_driver fimd_driver = { |
1c248b7d | 1106 | .probe = fimd_probe, |
56550d94 | 1107 | .remove = fimd_remove, |
1c248b7d ID |
1108 | .driver = { |
1109 | .name = "exynos4-fb", | |
1110 | .owner = THIS_MODULE, | |
2d3f173c | 1111 | .of_match_table = fimd_driver_dt_match, |
1c248b7d ID |
1112 | }, |
1113 | }; |