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Commit | Line | Data |
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1c248b7d ID |
1 | /* exynos_drm_fimd.c |
2 | * | |
3 | * Copyright (C) 2011 Samsung Electronics Co.Ltd | |
4 | * Authors: | |
5 | * Joonyoung Shim <jy0922.shim@samsung.com> | |
6 | * Inki Dae <inki.dae@samsung.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | */ | |
760285e7 | 14 | #include <drm/drmP.h> |
1c248b7d ID |
15 | |
16 | #include <linux/kernel.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/clk.h> | |
d636ead8 | 20 | #include <linux/of_device.h> |
cb91f6a0 | 21 | #include <linux/pm_runtime.h> |
1c248b7d | 22 | |
5a213a55 | 23 | #include <video/samsung_fimd.h> |
1c248b7d | 24 | #include <drm/exynos_drm.h> |
1c248b7d ID |
25 | |
26 | #include "exynos_drm_drv.h" | |
27 | #include "exynos_drm_fbdev.h" | |
28 | #include "exynos_drm_crtc.h" | |
bcc5cd1c | 29 | #include "exynos_drm_iommu.h" |
1c248b7d ID |
30 | |
31 | /* | |
32 | * FIMD is stand for Fully Interactive Mobile Display and | |
33 | * as a display controller, it transfers contents drawn on memory | |
34 | * to a LCD Panel through Display Interfaces such as RGB or | |
35 | * CPU Interface. | |
36 | */ | |
37 | ||
38 | /* position control register for hardware window 0, 2 ~ 4.*/ | |
39 | #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16) | |
40 | #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16) | |
0f10cf14 LKA |
41 | /* |
42 | * size control register for hardware windows 0 and alpha control register | |
43 | * for hardware windows 1 ~ 4 | |
44 | */ | |
45 | #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16) | |
46 | /* size control register for hardware windows 1 ~ 2. */ | |
1c248b7d ID |
47 | #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16) |
48 | ||
49 | #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8) | |
50 | #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8) | |
51 | #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4) | |
52 | ||
53 | /* color key control register for hardware window 1 ~ 4. */ | |
0f10cf14 | 54 | #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8)) |
1c248b7d | 55 | /* color key value register for hardware window 1 ~ 4. */ |
0f10cf14 | 56 | #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8)) |
1c248b7d ID |
57 | |
58 | /* FIMD has totally five hardware windows. */ | |
59 | #define WINDOWS_NR 5 | |
60 | ||
61 | #define get_fimd_context(dev) platform_get_drvdata(to_platform_device(dev)) | |
62 | ||
e2e13389 LKA |
63 | struct fimd_driver_data { |
64 | unsigned int timing_base; | |
65 | }; | |
66 | ||
6ecf18f9 | 67 | static struct fimd_driver_data exynos4_fimd_driver_data = { |
e2e13389 LKA |
68 | .timing_base = 0x0, |
69 | }; | |
70 | ||
6ecf18f9 | 71 | static struct fimd_driver_data exynos5_fimd_driver_data = { |
e2e13389 LKA |
72 | .timing_base = 0x20000, |
73 | }; | |
74 | ||
1c248b7d ID |
75 | struct fimd_win_data { |
76 | unsigned int offset_x; | |
77 | unsigned int offset_y; | |
19c8b834 ID |
78 | unsigned int ovl_width; |
79 | unsigned int ovl_height; | |
80 | unsigned int fb_width; | |
81 | unsigned int fb_height; | |
1c248b7d | 82 | unsigned int bpp; |
2c871127 | 83 | dma_addr_t dma_addr; |
1c248b7d ID |
84 | unsigned int buf_offsize; |
85 | unsigned int line_size; /* bytes */ | |
ec05da95 | 86 | bool enabled; |
db7e55ae | 87 | bool resume; |
1c248b7d ID |
88 | }; |
89 | ||
90 | struct fimd_context { | |
91 | struct exynos_drm_subdrv subdrv; | |
92 | int irq; | |
93 | struct drm_crtc *crtc; | |
94 | struct clk *bus_clk; | |
95 | struct clk *lcd_clk; | |
1c248b7d ID |
96 | void __iomem *regs; |
97 | struct fimd_win_data win_data[WINDOWS_NR]; | |
98 | unsigned int clkdiv; | |
99 | unsigned int default_win; | |
100 | unsigned long irq_flags; | |
101 | u32 vidcon0; | |
102 | u32 vidcon1; | |
cb91f6a0 | 103 | bool suspended; |
c32b06ef | 104 | struct mutex lock; |
01ce113c P |
105 | wait_queue_head_t wait_vsync_queue; |
106 | atomic_t wait_vsync_event; | |
1c248b7d | 107 | |
607c50d4 | 108 | struct exynos_drm_panel_info *panel; |
1c248b7d ID |
109 | }; |
110 | ||
d636ead8 JS |
111 | #ifdef CONFIG_OF |
112 | static const struct of_device_id fimd_driver_dt_match[] = { | |
5830daf8 | 113 | { .compatible = "samsung,exynos4210-fimd", |
d636ead8 | 114 | .data = &exynos4_fimd_driver_data }, |
5830daf8 | 115 | { .compatible = "samsung,exynos5250-fimd", |
d636ead8 JS |
116 | .data = &exynos5_fimd_driver_data }, |
117 | {}, | |
118 | }; | |
119 | MODULE_DEVICE_TABLE(of, fimd_driver_dt_match); | |
120 | #endif | |
121 | ||
e2e13389 LKA |
122 | static inline struct fimd_driver_data *drm_fimd_get_driver_data( |
123 | struct platform_device *pdev) | |
124 | { | |
d636ead8 JS |
125 | #ifdef CONFIG_OF |
126 | const struct of_device_id *of_id = | |
127 | of_match_device(fimd_driver_dt_match, &pdev->dev); | |
128 | ||
129 | if (of_id) | |
130 | return (struct fimd_driver_data *)of_id->data; | |
131 | #endif | |
132 | ||
e2e13389 LKA |
133 | return (struct fimd_driver_data *) |
134 | platform_get_device_id(pdev)->driver_data; | |
135 | } | |
136 | ||
1c248b7d ID |
137 | static bool fimd_display_is_connected(struct device *dev) |
138 | { | |
1c248b7d ID |
139 | DRM_DEBUG_KMS("%s\n", __FILE__); |
140 | ||
141 | /* TODO. */ | |
142 | ||
143 | return true; | |
144 | } | |
145 | ||
607c50d4 | 146 | static void *fimd_get_panel(struct device *dev) |
1c248b7d ID |
147 | { |
148 | struct fimd_context *ctx = get_fimd_context(dev); | |
149 | ||
150 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
151 | ||
607c50d4 | 152 | return ctx->panel; |
1c248b7d ID |
153 | } |
154 | ||
155 | static int fimd_check_timing(struct device *dev, void *timing) | |
156 | { | |
1c248b7d ID |
157 | DRM_DEBUG_KMS("%s\n", __FILE__); |
158 | ||
159 | /* TODO. */ | |
160 | ||
161 | return 0; | |
162 | } | |
163 | ||
164 | static int fimd_display_power_on(struct device *dev, int mode) | |
165 | { | |
1c248b7d ID |
166 | DRM_DEBUG_KMS("%s\n", __FILE__); |
167 | ||
ec05da95 | 168 | /* TODO */ |
1c248b7d ID |
169 | |
170 | return 0; | |
171 | } | |
172 | ||
74ccc539 | 173 | static struct exynos_drm_display_ops fimd_display_ops = { |
1c248b7d ID |
174 | .type = EXYNOS_DISPLAY_TYPE_LCD, |
175 | .is_connected = fimd_display_is_connected, | |
607c50d4 | 176 | .get_panel = fimd_get_panel, |
1c248b7d ID |
177 | .check_timing = fimd_check_timing, |
178 | .power_on = fimd_display_power_on, | |
179 | }; | |
180 | ||
ec05da95 ID |
181 | static void fimd_dpms(struct device *subdrv_dev, int mode) |
182 | { | |
c32b06ef ID |
183 | struct fimd_context *ctx = get_fimd_context(subdrv_dev); |
184 | ||
ec05da95 ID |
185 | DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode); |
186 | ||
c32b06ef ID |
187 | mutex_lock(&ctx->lock); |
188 | ||
cb91f6a0 JS |
189 | switch (mode) { |
190 | case DRM_MODE_DPMS_ON: | |
c32b06ef ID |
191 | /* |
192 | * enable fimd hardware only if suspended status. | |
193 | * | |
194 | * P.S. fimd_dpms function would be called at booting time so | |
195 | * clk_enable could be called double time. | |
196 | */ | |
197 | if (ctx->suspended) | |
198 | pm_runtime_get_sync(subdrv_dev); | |
cb91f6a0 JS |
199 | break; |
200 | case DRM_MODE_DPMS_STANDBY: | |
201 | case DRM_MODE_DPMS_SUSPEND: | |
202 | case DRM_MODE_DPMS_OFF: | |
373af0c0 ID |
203 | if (!ctx->suspended) |
204 | pm_runtime_put_sync(subdrv_dev); | |
cb91f6a0 JS |
205 | break; |
206 | default: | |
207 | DRM_DEBUG_KMS("unspecified mode %d\n", mode); | |
208 | break; | |
209 | } | |
c32b06ef ID |
210 | |
211 | mutex_unlock(&ctx->lock); | |
ec05da95 ID |
212 | } |
213 | ||
214 | static void fimd_apply(struct device *subdrv_dev) | |
215 | { | |
216 | struct fimd_context *ctx = get_fimd_context(subdrv_dev); | |
677e84c1 | 217 | struct exynos_drm_manager *mgr = ctx->subdrv.manager; |
ec05da95 ID |
218 | struct exynos_drm_manager_ops *mgr_ops = mgr->ops; |
219 | struct exynos_drm_overlay_ops *ovl_ops = mgr->overlay_ops; | |
220 | struct fimd_win_data *win_data; | |
864ee9e6 | 221 | int i; |
ec05da95 ID |
222 | |
223 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
224 | ||
864ee9e6 JS |
225 | for (i = 0; i < WINDOWS_NR; i++) { |
226 | win_data = &ctx->win_data[i]; | |
227 | if (win_data->enabled && (ovl_ops && ovl_ops->commit)) | |
228 | ovl_ops->commit(subdrv_dev, i); | |
229 | } | |
ec05da95 ID |
230 | |
231 | if (mgr_ops && mgr_ops->commit) | |
232 | mgr_ops->commit(subdrv_dev); | |
233 | } | |
234 | ||
1c248b7d ID |
235 | static void fimd_commit(struct device *dev) |
236 | { | |
237 | struct fimd_context *ctx = get_fimd_context(dev); | |
607c50d4 ECK |
238 | struct exynos_drm_panel_info *panel = ctx->panel; |
239 | struct fb_videomode *timing = &panel->timing; | |
e2e13389 LKA |
240 | struct fimd_driver_data *driver_data; |
241 | struct platform_device *pdev = to_platform_device(dev); | |
1c248b7d ID |
242 | u32 val; |
243 | ||
e2e13389 | 244 | driver_data = drm_fimd_get_driver_data(pdev); |
e30d4bcf ID |
245 | if (ctx->suspended) |
246 | return; | |
247 | ||
1c248b7d ID |
248 | DRM_DEBUG_KMS("%s\n", __FILE__); |
249 | ||
250 | /* setup polarity values from machine code. */ | |
e2e13389 | 251 | writel(ctx->vidcon1, ctx->regs + driver_data->timing_base + VIDCON1); |
1c248b7d ID |
252 | |
253 | /* setup vertical timing values. */ | |
254 | val = VIDTCON0_VBPD(timing->upper_margin - 1) | | |
255 | VIDTCON0_VFPD(timing->lower_margin - 1) | | |
256 | VIDTCON0_VSPW(timing->vsync_len - 1); | |
e2e13389 | 257 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON0); |
1c248b7d ID |
258 | |
259 | /* setup horizontal timing values. */ | |
260 | val = VIDTCON1_HBPD(timing->left_margin - 1) | | |
261 | VIDTCON1_HFPD(timing->right_margin - 1) | | |
262 | VIDTCON1_HSPW(timing->hsync_len - 1); | |
e2e13389 | 263 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON1); |
1c248b7d ID |
264 | |
265 | /* setup horizontal and vertical display size. */ | |
266 | val = VIDTCON2_LINEVAL(timing->yres - 1) | | |
ca555e5a JS |
267 | VIDTCON2_HOZVAL(timing->xres - 1) | |
268 | VIDTCON2_LINEVAL_E(timing->yres - 1) | | |
269 | VIDTCON2_HOZVAL_E(timing->xres - 1); | |
e2e13389 | 270 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON2); |
1c248b7d ID |
271 | |
272 | /* setup clock source, clock divider, enable dma. */ | |
273 | val = ctx->vidcon0; | |
274 | val &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR); | |
275 | ||
276 | if (ctx->clkdiv > 1) | |
277 | val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR; | |
278 | else | |
279 | val &= ~VIDCON0_CLKDIR; /* 1:1 clock */ | |
280 | ||
281 | /* | |
282 | * fields of register with prefix '_F' would be updated | |
283 | * at vsync(same as dma start) | |
284 | */ | |
285 | val |= VIDCON0_ENVID | VIDCON0_ENVID_F; | |
286 | writel(val, ctx->regs + VIDCON0); | |
287 | } | |
288 | ||
289 | static int fimd_enable_vblank(struct device *dev) | |
290 | { | |
291 | struct fimd_context *ctx = get_fimd_context(dev); | |
292 | u32 val; | |
293 | ||
294 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
295 | ||
cb91f6a0 JS |
296 | if (ctx->suspended) |
297 | return -EPERM; | |
298 | ||
1c248b7d ID |
299 | if (!test_and_set_bit(0, &ctx->irq_flags)) { |
300 | val = readl(ctx->regs + VIDINTCON0); | |
301 | ||
302 | val |= VIDINTCON0_INT_ENABLE; | |
303 | val |= VIDINTCON0_INT_FRAME; | |
304 | ||
305 | val &= ~VIDINTCON0_FRAMESEL0_MASK; | |
306 | val |= VIDINTCON0_FRAMESEL0_VSYNC; | |
307 | val &= ~VIDINTCON0_FRAMESEL1_MASK; | |
308 | val |= VIDINTCON0_FRAMESEL1_NONE; | |
309 | ||
310 | writel(val, ctx->regs + VIDINTCON0); | |
311 | } | |
312 | ||
313 | return 0; | |
314 | } | |
315 | ||
316 | static void fimd_disable_vblank(struct device *dev) | |
317 | { | |
318 | struct fimd_context *ctx = get_fimd_context(dev); | |
319 | u32 val; | |
320 | ||
321 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
322 | ||
cb91f6a0 JS |
323 | if (ctx->suspended) |
324 | return; | |
325 | ||
1c248b7d ID |
326 | if (test_and_clear_bit(0, &ctx->irq_flags)) { |
327 | val = readl(ctx->regs + VIDINTCON0); | |
328 | ||
329 | val &= ~VIDINTCON0_INT_FRAME; | |
330 | val &= ~VIDINTCON0_INT_ENABLE; | |
331 | ||
332 | writel(val, ctx->regs + VIDINTCON0); | |
333 | } | |
334 | } | |
335 | ||
07033970 P |
336 | static void fimd_wait_for_vblank(struct device *dev) |
337 | { | |
338 | struct fimd_context *ctx = get_fimd_context(dev); | |
07033970 | 339 | |
01ce113c P |
340 | if (ctx->suspended) |
341 | return; | |
342 | ||
343 | atomic_set(&ctx->wait_vsync_event, 1); | |
344 | ||
345 | /* | |
346 | * wait for FIMD to signal VSYNC interrupt or return after | |
347 | * timeout which is set to 50ms (refresh rate of 20). | |
348 | */ | |
349 | if (!wait_event_timeout(ctx->wait_vsync_queue, | |
350 | !atomic_read(&ctx->wait_vsync_event), | |
351 | DRM_HZ/20)) | |
07033970 P |
352 | DRM_DEBUG_KMS("vblank wait timed out.\n"); |
353 | } | |
354 | ||
1c248b7d | 355 | static struct exynos_drm_manager_ops fimd_manager_ops = { |
ec05da95 ID |
356 | .dpms = fimd_dpms, |
357 | .apply = fimd_apply, | |
1c248b7d ID |
358 | .commit = fimd_commit, |
359 | .enable_vblank = fimd_enable_vblank, | |
360 | .disable_vblank = fimd_disable_vblank, | |
07033970 | 361 | .wait_for_vblank = fimd_wait_for_vblank, |
1c248b7d ID |
362 | }; |
363 | ||
364 | static void fimd_win_mode_set(struct device *dev, | |
365 | struct exynos_drm_overlay *overlay) | |
366 | { | |
367 | struct fimd_context *ctx = get_fimd_context(dev); | |
368 | struct fimd_win_data *win_data; | |
864ee9e6 | 369 | int win; |
19c8b834 | 370 | unsigned long offset; |
1c248b7d ID |
371 | |
372 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
373 | ||
374 | if (!overlay) { | |
375 | dev_err(dev, "overlay is NULL\n"); | |
376 | return; | |
377 | } | |
378 | ||
864ee9e6 JS |
379 | win = overlay->zpos; |
380 | if (win == DEFAULT_ZPOS) | |
381 | win = ctx->default_win; | |
382 | ||
383 | if (win < 0 || win > WINDOWS_NR) | |
384 | return; | |
385 | ||
19c8b834 ID |
386 | offset = overlay->fb_x * (overlay->bpp >> 3); |
387 | offset += overlay->fb_y * overlay->pitch; | |
388 | ||
389 | DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch); | |
390 | ||
864ee9e6 | 391 | win_data = &ctx->win_data[win]; |
1c248b7d | 392 | |
19c8b834 ID |
393 | win_data->offset_x = overlay->crtc_x; |
394 | win_data->offset_y = overlay->crtc_y; | |
395 | win_data->ovl_width = overlay->crtc_width; | |
396 | win_data->ovl_height = overlay->crtc_height; | |
397 | win_data->fb_width = overlay->fb_width; | |
398 | win_data->fb_height = overlay->fb_height; | |
229d3534 | 399 | win_data->dma_addr = overlay->dma_addr[0] + offset; |
1c248b7d | 400 | win_data->bpp = overlay->bpp; |
19c8b834 ID |
401 | win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) * |
402 | (overlay->bpp >> 3); | |
403 | win_data->line_size = overlay->crtc_width * (overlay->bpp >> 3); | |
404 | ||
405 | DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n", | |
406 | win_data->offset_x, win_data->offset_y); | |
407 | DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", | |
408 | win_data->ovl_width, win_data->ovl_height); | |
ddd8e959 | 409 | DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data->dma_addr); |
19c8b834 ID |
410 | DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n", |
411 | overlay->fb_width, overlay->crtc_width); | |
1c248b7d ID |
412 | } |
413 | ||
414 | static void fimd_win_set_pixfmt(struct device *dev, unsigned int win) | |
415 | { | |
416 | struct fimd_context *ctx = get_fimd_context(dev); | |
417 | struct fimd_win_data *win_data = &ctx->win_data[win]; | |
418 | unsigned long val; | |
419 | ||
420 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
421 | ||
422 | val = WINCONx_ENWIN; | |
423 | ||
424 | switch (win_data->bpp) { | |
425 | case 1: | |
426 | val |= WINCON0_BPPMODE_1BPP; | |
427 | val |= WINCONx_BITSWP; | |
428 | val |= WINCONx_BURSTLEN_4WORD; | |
429 | break; | |
430 | case 2: | |
431 | val |= WINCON0_BPPMODE_2BPP; | |
432 | val |= WINCONx_BITSWP; | |
433 | val |= WINCONx_BURSTLEN_8WORD; | |
434 | break; | |
435 | case 4: | |
436 | val |= WINCON0_BPPMODE_4BPP; | |
437 | val |= WINCONx_BITSWP; | |
438 | val |= WINCONx_BURSTLEN_8WORD; | |
439 | break; | |
440 | case 8: | |
441 | val |= WINCON0_BPPMODE_8BPP_PALETTE; | |
442 | val |= WINCONx_BURSTLEN_8WORD; | |
443 | val |= WINCONx_BYTSWP; | |
444 | break; | |
445 | case 16: | |
446 | val |= WINCON0_BPPMODE_16BPP_565; | |
447 | val |= WINCONx_HAWSWP; | |
448 | val |= WINCONx_BURSTLEN_16WORD; | |
449 | break; | |
450 | case 24: | |
451 | val |= WINCON0_BPPMODE_24BPP_888; | |
452 | val |= WINCONx_WSWP; | |
453 | val |= WINCONx_BURSTLEN_16WORD; | |
454 | break; | |
455 | case 32: | |
456 | val |= WINCON1_BPPMODE_28BPP_A4888 | |
457 | | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL; | |
458 | val |= WINCONx_WSWP; | |
459 | val |= WINCONx_BURSTLEN_16WORD; | |
460 | break; | |
461 | default: | |
462 | DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n"); | |
463 | ||
464 | val |= WINCON0_BPPMODE_24BPP_888; | |
465 | val |= WINCONx_WSWP; | |
466 | val |= WINCONx_BURSTLEN_16WORD; | |
467 | break; | |
468 | } | |
469 | ||
470 | DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp); | |
471 | ||
472 | writel(val, ctx->regs + WINCON(win)); | |
473 | } | |
474 | ||
475 | static void fimd_win_set_colkey(struct device *dev, unsigned int win) | |
476 | { | |
477 | struct fimd_context *ctx = get_fimd_context(dev); | |
478 | unsigned int keycon0 = 0, keycon1 = 0; | |
479 | ||
480 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
481 | ||
482 | keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F | | |
483 | WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); | |
484 | ||
485 | keycon1 = WxKEYCON1_COLVAL(0xffffffff); | |
486 | ||
487 | writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); | |
488 | writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); | |
489 | } | |
490 | ||
864ee9e6 | 491 | static void fimd_win_commit(struct device *dev, int zpos) |
1c248b7d ID |
492 | { |
493 | struct fimd_context *ctx = get_fimd_context(dev); | |
494 | struct fimd_win_data *win_data; | |
864ee9e6 | 495 | int win = zpos; |
1c248b7d | 496 | unsigned long val, alpha, size; |
f56aad3a JS |
497 | unsigned int last_x; |
498 | unsigned int last_y; | |
1c248b7d ID |
499 | |
500 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
501 | ||
e30d4bcf ID |
502 | if (ctx->suspended) |
503 | return; | |
504 | ||
864ee9e6 JS |
505 | if (win == DEFAULT_ZPOS) |
506 | win = ctx->default_win; | |
507 | ||
1c248b7d ID |
508 | if (win < 0 || win > WINDOWS_NR) |
509 | return; | |
510 | ||
511 | win_data = &ctx->win_data[win]; | |
512 | ||
513 | /* | |
514 | * SHADOWCON register is used for enabling timing. | |
515 | * | |
516 | * for example, once only width value of a register is set, | |
517 | * if the dma is started then fimd hardware could malfunction so | |
518 | * with protect window setting, the register fields with prefix '_F' | |
519 | * wouldn't be updated at vsync also but updated once unprotect window | |
520 | * is set. | |
521 | */ | |
522 | ||
523 | /* protect windows */ | |
524 | val = readl(ctx->regs + SHADOWCON); | |
525 | val |= SHADOWCON_WINx_PROTECT(win); | |
526 | writel(val, ctx->regs + SHADOWCON); | |
527 | ||
528 | /* buffer start address */ | |
2c871127 | 529 | val = (unsigned long)win_data->dma_addr; |
1c248b7d ID |
530 | writel(val, ctx->regs + VIDWx_BUF_START(win, 0)); |
531 | ||
532 | /* buffer end address */ | |
19c8b834 | 533 | size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3); |
2c871127 | 534 | val = (unsigned long)(win_data->dma_addr + size); |
1c248b7d ID |
535 | writel(val, ctx->regs + VIDWx_BUF_END(win, 0)); |
536 | ||
537 | DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n", | |
2c871127 | 538 | (unsigned long)win_data->dma_addr, val, size); |
19c8b834 ID |
539 | DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", |
540 | win_data->ovl_width, win_data->ovl_height); | |
1c248b7d ID |
541 | |
542 | /* buffer size */ | |
543 | val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) | | |
ca555e5a JS |
544 | VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size) | |
545 | VIDW_BUF_SIZE_OFFSET_E(win_data->buf_offsize) | | |
546 | VIDW_BUF_SIZE_PAGEWIDTH_E(win_data->line_size); | |
1c248b7d ID |
547 | writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0)); |
548 | ||
549 | /* OSD position */ | |
550 | val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) | | |
ca555e5a JS |
551 | VIDOSDxA_TOPLEFT_Y(win_data->offset_y) | |
552 | VIDOSDxA_TOPLEFT_X_E(win_data->offset_x) | | |
553 | VIDOSDxA_TOPLEFT_Y_E(win_data->offset_y); | |
1c248b7d ID |
554 | writel(val, ctx->regs + VIDOSD_A(win)); |
555 | ||
f56aad3a JS |
556 | last_x = win_data->offset_x + win_data->ovl_width; |
557 | if (last_x) | |
558 | last_x--; | |
559 | last_y = win_data->offset_y + win_data->ovl_height; | |
560 | if (last_y) | |
561 | last_y--; | |
562 | ||
ca555e5a JS |
563 | val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) | |
564 | VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y); | |
565 | ||
1c248b7d ID |
566 | writel(val, ctx->regs + VIDOSD_B(win)); |
567 | ||
19c8b834 | 568 | DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", |
f56aad3a | 569 | win_data->offset_x, win_data->offset_y, last_x, last_y); |
1c248b7d ID |
570 | |
571 | /* hardware window 0 doesn't support alpha channel. */ | |
572 | if (win != 0) { | |
573 | /* OSD alpha */ | |
574 | alpha = VIDISD14C_ALPHA1_R(0xf) | | |
575 | VIDISD14C_ALPHA1_G(0xf) | | |
576 | VIDISD14C_ALPHA1_B(0xf); | |
577 | ||
578 | writel(alpha, ctx->regs + VIDOSD_C(win)); | |
579 | } | |
580 | ||
581 | /* OSD size */ | |
582 | if (win != 3 && win != 4) { | |
583 | u32 offset = VIDOSD_D(win); | |
584 | if (win == 0) | |
0f10cf14 | 585 | offset = VIDOSD_C(win); |
19c8b834 | 586 | val = win_data->ovl_width * win_data->ovl_height; |
1c248b7d ID |
587 | writel(val, ctx->regs + offset); |
588 | ||
589 | DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val); | |
590 | } | |
591 | ||
592 | fimd_win_set_pixfmt(dev, win); | |
593 | ||
594 | /* hardware window 0 doesn't support color key. */ | |
595 | if (win != 0) | |
596 | fimd_win_set_colkey(dev, win); | |
597 | ||
ec05da95 ID |
598 | /* wincon */ |
599 | val = readl(ctx->regs + WINCON(win)); | |
600 | val |= WINCONx_ENWIN; | |
601 | writel(val, ctx->regs + WINCON(win)); | |
602 | ||
1c248b7d ID |
603 | /* Enable DMA channel and unprotect windows */ |
604 | val = readl(ctx->regs + SHADOWCON); | |
605 | val |= SHADOWCON_CHx_ENABLE(win); | |
606 | val &= ~SHADOWCON_WINx_PROTECT(win); | |
607 | writel(val, ctx->regs + SHADOWCON); | |
ec05da95 ID |
608 | |
609 | win_data->enabled = true; | |
1c248b7d ID |
610 | } |
611 | ||
864ee9e6 | 612 | static void fimd_win_disable(struct device *dev, int zpos) |
1c248b7d ID |
613 | { |
614 | struct fimd_context *ctx = get_fimd_context(dev); | |
ec05da95 | 615 | struct fimd_win_data *win_data; |
864ee9e6 | 616 | int win = zpos; |
1c248b7d ID |
617 | u32 val; |
618 | ||
619 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
620 | ||
864ee9e6 JS |
621 | if (win == DEFAULT_ZPOS) |
622 | win = ctx->default_win; | |
623 | ||
1c248b7d ID |
624 | if (win < 0 || win > WINDOWS_NR) |
625 | return; | |
626 | ||
ec05da95 ID |
627 | win_data = &ctx->win_data[win]; |
628 | ||
db7e55ae P |
629 | if (ctx->suspended) { |
630 | /* do not resume this window*/ | |
631 | win_data->resume = false; | |
632 | return; | |
633 | } | |
634 | ||
1c248b7d ID |
635 | /* protect windows */ |
636 | val = readl(ctx->regs + SHADOWCON); | |
637 | val |= SHADOWCON_WINx_PROTECT(win); | |
638 | writel(val, ctx->regs + SHADOWCON); | |
639 | ||
640 | /* wincon */ | |
641 | val = readl(ctx->regs + WINCON(win)); | |
642 | val &= ~WINCONx_ENWIN; | |
643 | writel(val, ctx->regs + WINCON(win)); | |
644 | ||
645 | /* unprotect windows */ | |
646 | val = readl(ctx->regs + SHADOWCON); | |
647 | val &= ~SHADOWCON_CHx_ENABLE(win); | |
648 | val &= ~SHADOWCON_WINx_PROTECT(win); | |
649 | writel(val, ctx->regs + SHADOWCON); | |
ec05da95 ID |
650 | |
651 | win_data->enabled = false; | |
1c248b7d ID |
652 | } |
653 | ||
654 | static struct exynos_drm_overlay_ops fimd_overlay_ops = { | |
655 | .mode_set = fimd_win_mode_set, | |
656 | .commit = fimd_win_commit, | |
657 | .disable = fimd_win_disable, | |
658 | }; | |
659 | ||
677e84c1 JS |
660 | static struct exynos_drm_manager fimd_manager = { |
661 | .pipe = -1, | |
662 | .ops = &fimd_manager_ops, | |
663 | .overlay_ops = &fimd_overlay_ops, | |
664 | .display_ops = &fimd_display_ops, | |
665 | }; | |
666 | ||
1c248b7d ID |
667 | static irqreturn_t fimd_irq_handler(int irq, void *dev_id) |
668 | { | |
669 | struct fimd_context *ctx = (struct fimd_context *)dev_id; | |
670 | struct exynos_drm_subdrv *subdrv = &ctx->subdrv; | |
671 | struct drm_device *drm_dev = subdrv->drm_dev; | |
677e84c1 | 672 | struct exynos_drm_manager *manager = subdrv->manager; |
1c248b7d ID |
673 | u32 val; |
674 | ||
675 | val = readl(ctx->regs + VIDINTCON1); | |
676 | ||
677 | if (val & VIDINTCON1_INT_FRAME) | |
678 | /* VSYNC interrupt */ | |
679 | writel(VIDINTCON1_INT_FRAME, ctx->regs + VIDINTCON1); | |
680 | ||
ec05da95 ID |
681 | /* check the crtc is detached already from encoder */ |
682 | if (manager->pipe < 0) | |
683 | goto out; | |
483b88f8 | 684 | |
1c248b7d | 685 | drm_handle_vblank(drm_dev, manager->pipe); |
663d8766 | 686 | exynos_drm_crtc_finish_pageflip(drm_dev, manager->pipe); |
1c248b7d | 687 | |
01ce113c P |
688 | /* set wait vsync event to zero and wake up queue. */ |
689 | if (atomic_read(&ctx->wait_vsync_event)) { | |
690 | atomic_set(&ctx->wait_vsync_event, 0); | |
691 | DRM_WAKEUP(&ctx->wait_vsync_queue); | |
692 | } | |
ec05da95 | 693 | out: |
1c248b7d ID |
694 | return IRQ_HANDLED; |
695 | } | |
696 | ||
41c24346 | 697 | static int fimd_subdrv_probe(struct drm_device *drm_dev, struct device *dev) |
1c248b7d | 698 | { |
1c248b7d ID |
699 | DRM_DEBUG_KMS("%s\n", __FILE__); |
700 | ||
701 | /* | |
702 | * enable drm irq mode. | |
703 | * - with irq_enabled = 1, we can use the vblank feature. | |
704 | * | |
705 | * P.S. note that we wouldn't use drm irq handler but | |
706 | * just specific driver own one instead because | |
707 | * drm framework supports only one irq handler. | |
708 | */ | |
709 | drm_dev->irq_enabled = 1; | |
710 | ||
ec05da95 ID |
711 | /* |
712 | * with vblank_disable_allowed = 1, vblank interrupt will be disabled | |
713 | * by drm timer once a current process gives up ownership of | |
714 | * vblank event.(after drm_vblank_put function is called) | |
715 | */ | |
716 | drm_dev->vblank_disable_allowed = 1; | |
717 | ||
bcc5cd1c ID |
718 | /* attach this sub driver to iommu mapping if supported. */ |
719 | if (is_drm_iommu_supported(drm_dev)) | |
720 | drm_iommu_attach_device(drm_dev, dev); | |
721 | ||
1c248b7d ID |
722 | return 0; |
723 | } | |
724 | ||
29cb6025 | 725 | static void fimd_subdrv_remove(struct drm_device *drm_dev, struct device *dev) |
1c248b7d | 726 | { |
1c248b7d ID |
727 | DRM_DEBUG_KMS("%s\n", __FILE__); |
728 | ||
bcc5cd1c ID |
729 | /* detach this sub driver from iommu mapping if supported. */ |
730 | if (is_drm_iommu_supported(drm_dev)) | |
731 | drm_iommu_detach_device(drm_dev, dev); | |
1c248b7d ID |
732 | } |
733 | ||
734 | static int fimd_calc_clkdiv(struct fimd_context *ctx, | |
735 | struct fb_videomode *timing) | |
736 | { | |
737 | unsigned long clk = clk_get_rate(ctx->lcd_clk); | |
738 | u32 retrace; | |
739 | u32 clkdiv; | |
740 | u32 best_framerate = 0; | |
741 | u32 framerate; | |
742 | ||
743 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
744 | ||
745 | retrace = timing->left_margin + timing->hsync_len + | |
746 | timing->right_margin + timing->xres; | |
747 | retrace *= timing->upper_margin + timing->vsync_len + | |
748 | timing->lower_margin + timing->yres; | |
749 | ||
750 | /* default framerate is 60Hz */ | |
751 | if (!timing->refresh) | |
752 | timing->refresh = 60; | |
753 | ||
754 | clk /= retrace; | |
755 | ||
756 | for (clkdiv = 1; clkdiv < 0x100; clkdiv++) { | |
757 | int tmp; | |
758 | ||
759 | /* get best framerate */ | |
760 | framerate = clk / clkdiv; | |
761 | tmp = timing->refresh - framerate; | |
762 | if (tmp < 0) { | |
763 | best_framerate = framerate; | |
764 | continue; | |
765 | } else { | |
766 | if (!best_framerate) | |
767 | best_framerate = framerate; | |
768 | else if (tmp < (best_framerate - framerate)) | |
769 | best_framerate = framerate; | |
770 | break; | |
771 | } | |
772 | } | |
773 | ||
774 | return clkdiv; | |
775 | } | |
776 | ||
777 | static void fimd_clear_win(struct fimd_context *ctx, int win) | |
778 | { | |
779 | u32 val; | |
780 | ||
781 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
782 | ||
783 | writel(0, ctx->regs + WINCON(win)); | |
784 | writel(0, ctx->regs + VIDOSD_A(win)); | |
785 | writel(0, ctx->regs + VIDOSD_B(win)); | |
786 | writel(0, ctx->regs + VIDOSD_C(win)); | |
787 | ||
788 | if (win == 1 || win == 2) | |
789 | writel(0, ctx->regs + VIDOSD_D(win)); | |
790 | ||
791 | val = readl(ctx->regs + SHADOWCON); | |
792 | val &= ~SHADOWCON_WINx_PROTECT(win); | |
793 | writel(val, ctx->regs + SHADOWCON); | |
794 | } | |
795 | ||
5d55393a | 796 | static int fimd_clock(struct fimd_context *ctx, bool enable) |
373af0c0 | 797 | { |
373af0c0 ID |
798 | DRM_DEBUG_KMS("%s\n", __FILE__); |
799 | ||
373af0c0 ID |
800 | if (enable) { |
801 | int ret; | |
802 | ||
803 | ret = clk_enable(ctx->bus_clk); | |
804 | if (ret < 0) | |
805 | return ret; | |
806 | ||
807 | ret = clk_enable(ctx->lcd_clk); | |
808 | if (ret < 0) { | |
809 | clk_disable(ctx->bus_clk); | |
810 | return ret; | |
811 | } | |
5d55393a ID |
812 | } else { |
813 | clk_disable(ctx->lcd_clk); | |
814 | clk_disable(ctx->bus_clk); | |
815 | } | |
816 | ||
817 | return 0; | |
818 | } | |
819 | ||
db7e55ae P |
820 | static void fimd_window_suspend(struct device *dev) |
821 | { | |
822 | struct fimd_context *ctx = get_fimd_context(dev); | |
823 | struct fimd_win_data *win_data; | |
824 | int i; | |
825 | ||
826 | for (i = 0; i < WINDOWS_NR; i++) { | |
827 | win_data = &ctx->win_data[i]; | |
828 | win_data->resume = win_data->enabled; | |
829 | fimd_win_disable(dev, i); | |
830 | } | |
831 | fimd_wait_for_vblank(dev); | |
832 | } | |
833 | ||
834 | static void fimd_window_resume(struct device *dev) | |
835 | { | |
836 | struct fimd_context *ctx = get_fimd_context(dev); | |
837 | struct fimd_win_data *win_data; | |
838 | int i; | |
839 | ||
840 | for (i = 0; i < WINDOWS_NR; i++) { | |
841 | win_data = &ctx->win_data[i]; | |
842 | win_data->enabled = win_data->resume; | |
843 | win_data->resume = false; | |
844 | } | |
845 | } | |
846 | ||
5d55393a ID |
847 | static int fimd_activate(struct fimd_context *ctx, bool enable) |
848 | { | |
db7e55ae | 849 | struct device *dev = ctx->subdrv.dev; |
5d55393a ID |
850 | if (enable) { |
851 | int ret; | |
5d55393a ID |
852 | |
853 | ret = fimd_clock(ctx, true); | |
854 | if (ret < 0) | |
855 | return ret; | |
373af0c0 ID |
856 | |
857 | ctx->suspended = false; | |
858 | ||
859 | /* if vblank was enabled status, enable it again. */ | |
860 | if (test_and_clear_bit(0, &ctx->irq_flags)) | |
861 | fimd_enable_vblank(dev); | |
db7e55ae P |
862 | |
863 | fimd_window_resume(dev); | |
373af0c0 | 864 | } else { |
db7e55ae P |
865 | fimd_window_suspend(dev); |
866 | ||
5d55393a | 867 | fimd_clock(ctx, false); |
373af0c0 ID |
868 | ctx->suspended = true; |
869 | } | |
870 | ||
871 | return 0; | |
872 | } | |
873 | ||
56550d94 | 874 | static int fimd_probe(struct platform_device *pdev) |
1c248b7d ID |
875 | { |
876 | struct device *dev = &pdev->dev; | |
877 | struct fimd_context *ctx; | |
878 | struct exynos_drm_subdrv *subdrv; | |
879 | struct exynos_drm_fimd_pdata *pdata; | |
607c50d4 | 880 | struct exynos_drm_panel_info *panel; |
1c248b7d ID |
881 | struct resource *res; |
882 | int win; | |
883 | int ret = -EINVAL; | |
884 | ||
885 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
886 | ||
887 | pdata = pdev->dev.platform_data; | |
888 | if (!pdata) { | |
889 | dev_err(dev, "no platform data specified\n"); | |
890 | return -EINVAL; | |
891 | } | |
892 | ||
607c50d4 ECK |
893 | panel = &pdata->panel; |
894 | if (!panel) { | |
895 | dev_err(dev, "panel is null.\n"); | |
1c248b7d ID |
896 | return -EINVAL; |
897 | } | |
898 | ||
edc57266 | 899 | ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL); |
1c248b7d ID |
900 | if (!ctx) |
901 | return -ENOMEM; | |
902 | ||
a4d8de5f | 903 | ctx->bus_clk = devm_clk_get(dev, "fimd"); |
1c248b7d ID |
904 | if (IS_ERR(ctx->bus_clk)) { |
905 | dev_err(dev, "failed to get bus clock\n"); | |
a4d8de5f | 906 | return PTR_ERR(ctx->bus_clk); |
1c248b7d ID |
907 | } |
908 | ||
a4d8de5f | 909 | ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd"); |
1c248b7d ID |
910 | if (IS_ERR(ctx->lcd_clk)) { |
911 | dev_err(dev, "failed to get lcd clock\n"); | |
a4d8de5f | 912 | return PTR_ERR(ctx->lcd_clk); |
1c248b7d ID |
913 | } |
914 | ||
1c248b7d | 915 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1c248b7d | 916 | |
d4ed6025 TR |
917 | ctx->regs = devm_ioremap_resource(&pdev->dev, res); |
918 | if (IS_ERR(ctx->regs)) | |
919 | return PTR_ERR(ctx->regs); | |
1c248b7d ID |
920 | |
921 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
922 | if (!res) { | |
923 | dev_err(dev, "irq request failed.\n"); | |
a4d8de5f | 924 | return -ENXIO; |
1c248b7d ID |
925 | } |
926 | ||
927 | ctx->irq = res->start; | |
928 | ||
edc57266 SK |
929 | ret = devm_request_irq(&pdev->dev, ctx->irq, fimd_irq_handler, |
930 | 0, "drm_fimd", ctx); | |
931 | if (ret) { | |
1c248b7d | 932 | dev_err(dev, "irq request failed.\n"); |
a4d8de5f | 933 | return ret; |
1c248b7d ID |
934 | } |
935 | ||
1c248b7d ID |
936 | ctx->vidcon0 = pdata->vidcon0; |
937 | ctx->vidcon1 = pdata->vidcon1; | |
938 | ctx->default_win = pdata->default_win; | |
607c50d4 | 939 | ctx->panel = panel; |
01ce113c P |
940 | DRM_INIT_WAITQUEUE(&ctx->wait_vsync_queue); |
941 | atomic_set(&ctx->wait_vsync_event, 0); | |
1c248b7d | 942 | |
1c248b7d ID |
943 | subdrv = &ctx->subdrv; |
944 | ||
677e84c1 JS |
945 | subdrv->dev = dev; |
946 | subdrv->manager = &fimd_manager; | |
1c248b7d ID |
947 | subdrv->probe = fimd_subdrv_probe; |
948 | subdrv->remove = fimd_subdrv_remove; | |
1c248b7d | 949 | |
c32b06ef ID |
950 | mutex_init(&ctx->lock); |
951 | ||
1c248b7d | 952 | platform_set_drvdata(pdev, ctx); |
c32b06ef | 953 | |
c32b06ef ID |
954 | pm_runtime_enable(dev); |
955 | pm_runtime_get_sync(dev); | |
956 | ||
0d8ce3ae MS |
957 | ctx->clkdiv = fimd_calc_clkdiv(ctx, &panel->timing); |
958 | panel->timing.pixclock = clk_get_rate(ctx->lcd_clk) / ctx->clkdiv; | |
959 | ||
960 | DRM_DEBUG_KMS("pixel clock = %d, clkdiv = %d\n", | |
961 | panel->timing.pixclock, ctx->clkdiv); | |
962 | ||
c32b06ef ID |
963 | for (win = 0; win < WINDOWS_NR; win++) |
964 | fimd_clear_win(ctx, win); | |
965 | ||
1c248b7d ID |
966 | exynos_drm_subdrv_register(subdrv); |
967 | ||
968 | return 0; | |
1c248b7d ID |
969 | } |
970 | ||
56550d94 | 971 | static int fimd_remove(struct platform_device *pdev) |
1c248b7d | 972 | { |
cb91f6a0 | 973 | struct device *dev = &pdev->dev; |
1c248b7d ID |
974 | struct fimd_context *ctx = platform_get_drvdata(pdev); |
975 | ||
976 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
977 | ||
978 | exynos_drm_subdrv_unregister(&ctx->subdrv); | |
979 | ||
cb91f6a0 JS |
980 | if (ctx->suspended) |
981 | goto out; | |
982 | ||
1c248b7d ID |
983 | clk_disable(ctx->lcd_clk); |
984 | clk_disable(ctx->bus_clk); | |
cb91f6a0 JS |
985 | |
986 | pm_runtime_set_suspended(dev); | |
987 | pm_runtime_put_sync(dev); | |
988 | ||
989 | out: | |
990 | pm_runtime_disable(dev); | |
991 | ||
1c248b7d ID |
992 | return 0; |
993 | } | |
994 | ||
e30d4bcf ID |
995 | #ifdef CONFIG_PM_SLEEP |
996 | static int fimd_suspend(struct device *dev) | |
997 | { | |
373af0c0 | 998 | struct fimd_context *ctx = get_fimd_context(dev); |
e30d4bcf | 999 | |
373af0c0 ID |
1000 | /* |
1001 | * do not use pm_runtime_suspend(). if pm_runtime_suspend() is | |
1002 | * called here, an error would be returned by that interface | |
1003 | * because the usage_count of pm runtime is more than 1. | |
1004 | */ | |
5d55393a ID |
1005 | if (!pm_runtime_suspended(dev)) |
1006 | return fimd_activate(ctx, false); | |
1007 | ||
1008 | return 0; | |
e30d4bcf ID |
1009 | } |
1010 | ||
1011 | static int fimd_resume(struct device *dev) | |
1012 | { | |
373af0c0 | 1013 | struct fimd_context *ctx = get_fimd_context(dev); |
e30d4bcf | 1014 | |
373af0c0 ID |
1015 | /* |
1016 | * if entered to sleep when lcd panel was on, the usage_count | |
1017 | * of pm runtime would still be 1 so in this case, fimd driver | |
1018 | * should be on directly not drawing on pm runtime interface. | |
1019 | */ | |
28998afa | 1020 | if (!pm_runtime_suspended(dev)) { |
5d55393a ID |
1021 | int ret; |
1022 | ||
1023 | ret = fimd_activate(ctx, true); | |
1024 | if (ret < 0) | |
1025 | return ret; | |
1026 | ||
1027 | /* | |
1028 | * in case of dpms on(standby), fimd_apply function will | |
1029 | * be called by encoder's dpms callback to update fimd's | |
1030 | * registers but in case of sleep wakeup, it's not. | |
1031 | * so fimd_apply function should be called at here. | |
1032 | */ | |
1033 | fimd_apply(dev); | |
1034 | } | |
e30d4bcf | 1035 | |
e30d4bcf ID |
1036 | return 0; |
1037 | } | |
1038 | #endif | |
1039 | ||
cb91f6a0 JS |
1040 | #ifdef CONFIG_PM_RUNTIME |
1041 | static int fimd_runtime_suspend(struct device *dev) | |
1042 | { | |
1043 | struct fimd_context *ctx = get_fimd_context(dev); | |
1044 | ||
1045 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
1046 | ||
5d55393a | 1047 | return fimd_activate(ctx, false); |
cb91f6a0 JS |
1048 | } |
1049 | ||
1050 | static int fimd_runtime_resume(struct device *dev) | |
1051 | { | |
1052 | struct fimd_context *ctx = get_fimd_context(dev); | |
cb91f6a0 JS |
1053 | |
1054 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
1055 | ||
5d55393a | 1056 | return fimd_activate(ctx, true); |
cb91f6a0 JS |
1057 | } |
1058 | #endif | |
1059 | ||
e2e13389 LKA |
1060 | static struct platform_device_id fimd_driver_ids[] = { |
1061 | { | |
1062 | .name = "exynos4-fb", | |
1063 | .driver_data = (unsigned long)&exynos4_fimd_driver_data, | |
1064 | }, { | |
1065 | .name = "exynos5-fb", | |
1066 | .driver_data = (unsigned long)&exynos5_fimd_driver_data, | |
1067 | }, | |
1068 | {}, | |
1069 | }; | |
1070 | MODULE_DEVICE_TABLE(platform, fimd_driver_ids); | |
1071 | ||
cb91f6a0 | 1072 | static const struct dev_pm_ops fimd_pm_ops = { |
e30d4bcf | 1073 | SET_SYSTEM_SLEEP_PM_OPS(fimd_suspend, fimd_resume) |
cb91f6a0 JS |
1074 | SET_RUNTIME_PM_OPS(fimd_runtime_suspend, fimd_runtime_resume, NULL) |
1075 | }; | |
1076 | ||
132a5b91 | 1077 | struct platform_driver fimd_driver = { |
1c248b7d | 1078 | .probe = fimd_probe, |
56550d94 | 1079 | .remove = fimd_remove, |
e2e13389 | 1080 | .id_table = fimd_driver_ids, |
1c248b7d ID |
1081 | .driver = { |
1082 | .name = "exynos4-fb", | |
1083 | .owner = THIS_MODULE, | |
cb91f6a0 | 1084 | .pm = &fimd_pm_ops, |
d636ead8 | 1085 | .of_match_table = of_match_ptr(fimd_driver_dt_match), |
1c248b7d ID |
1086 | }, |
1087 | }; |