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1c248b7d ID |
1 | /* exynos_drm_fimd.c |
2 | * | |
3 | * Copyright (C) 2011 Samsung Electronics Co.Ltd | |
4 | * Authors: | |
5 | * Joonyoung Shim <jy0922.shim@samsung.com> | |
6 | * Inki Dae <inki.dae@samsung.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | */ | |
760285e7 | 14 | #include <drm/drmP.h> |
1c248b7d ID |
15 | |
16 | #include <linux/kernel.h> | |
1c248b7d ID |
17 | #include <linux/platform_device.h> |
18 | #include <linux/clk.h> | |
3f1c781d | 19 | #include <linux/of.h> |
d636ead8 | 20 | #include <linux/of_device.h> |
cb91f6a0 | 21 | #include <linux/pm_runtime.h> |
1c248b7d | 22 | |
7f4596f4 | 23 | #include <video/of_display_timing.h> |
111e6055 | 24 | #include <video/of_videomode.h> |
5a213a55 | 25 | #include <video/samsung_fimd.h> |
1c248b7d | 26 | #include <drm/exynos_drm.h> |
1c248b7d ID |
27 | |
28 | #include "exynos_drm_drv.h" | |
29 | #include "exynos_drm_fbdev.h" | |
30 | #include "exynos_drm_crtc.h" | |
bcc5cd1c | 31 | #include "exynos_drm_iommu.h" |
1c248b7d ID |
32 | |
33 | /* | |
34 | * FIMD is stand for Fully Interactive Mobile Display and | |
35 | * as a display controller, it transfers contents drawn on memory | |
36 | * to a LCD Panel through Display Interfaces such as RGB or | |
37 | * CPU Interface. | |
38 | */ | |
39 | ||
111e6055 AH |
40 | #define FIMD_DEFAULT_FRAMERATE 60 |
41 | ||
1c248b7d ID |
42 | /* position control register for hardware window 0, 2 ~ 4.*/ |
43 | #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16) | |
44 | #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16) | |
0f10cf14 LKA |
45 | /* |
46 | * size control register for hardware windows 0 and alpha control register | |
47 | * for hardware windows 1 ~ 4 | |
48 | */ | |
49 | #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16) | |
50 | /* size control register for hardware windows 1 ~ 2. */ | |
1c248b7d ID |
51 | #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16) |
52 | ||
53 | #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8) | |
54 | #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8) | |
55 | #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4) | |
56 | ||
57 | /* color key control register for hardware window 1 ~ 4. */ | |
0f10cf14 | 58 | #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8)) |
1c248b7d | 59 | /* color key value register for hardware window 1 ~ 4. */ |
0f10cf14 | 60 | #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8)) |
1c248b7d ID |
61 | |
62 | /* FIMD has totally five hardware windows. */ | |
63 | #define WINDOWS_NR 5 | |
64 | ||
65 | #define get_fimd_context(dev) platform_get_drvdata(to_platform_device(dev)) | |
66 | ||
e2e13389 LKA |
67 | struct fimd_driver_data { |
68 | unsigned int timing_base; | |
de7af100 TF |
69 | |
70 | unsigned int has_shadowcon:1; | |
411d9ed4 | 71 | unsigned int has_clksel:1; |
5cc4621a | 72 | unsigned int has_limited_fmt:1; |
e2e13389 LKA |
73 | }; |
74 | ||
725ddead TF |
75 | static struct fimd_driver_data s3c64xx_fimd_driver_data = { |
76 | .timing_base = 0x0, | |
77 | .has_clksel = 1, | |
5cc4621a | 78 | .has_limited_fmt = 1, |
725ddead TF |
79 | }; |
80 | ||
6ecf18f9 | 81 | static struct fimd_driver_data exynos4_fimd_driver_data = { |
e2e13389 | 82 | .timing_base = 0x0, |
de7af100 | 83 | .has_shadowcon = 1, |
e2e13389 LKA |
84 | }; |
85 | ||
6ecf18f9 | 86 | static struct fimd_driver_data exynos5_fimd_driver_data = { |
e2e13389 | 87 | .timing_base = 0x20000, |
de7af100 | 88 | .has_shadowcon = 1, |
e2e13389 LKA |
89 | }; |
90 | ||
1c248b7d ID |
91 | struct fimd_win_data { |
92 | unsigned int offset_x; | |
93 | unsigned int offset_y; | |
19c8b834 ID |
94 | unsigned int ovl_width; |
95 | unsigned int ovl_height; | |
96 | unsigned int fb_width; | |
97 | unsigned int fb_height; | |
1c248b7d | 98 | unsigned int bpp; |
a4f38a80 | 99 | unsigned int pixel_format; |
2c871127 | 100 | dma_addr_t dma_addr; |
1c248b7d ID |
101 | unsigned int buf_offsize; |
102 | unsigned int line_size; /* bytes */ | |
ec05da95 | 103 | bool enabled; |
db7e55ae | 104 | bool resume; |
1c248b7d ID |
105 | }; |
106 | ||
107 | struct fimd_context { | |
108 | struct exynos_drm_subdrv subdrv; | |
109 | int irq; | |
110 | struct drm_crtc *crtc; | |
111 | struct clk *bus_clk; | |
112 | struct clk *lcd_clk; | |
1c248b7d ID |
113 | void __iomem *regs; |
114 | struct fimd_win_data win_data[WINDOWS_NR]; | |
115 | unsigned int clkdiv; | |
116 | unsigned int default_win; | |
117 | unsigned long irq_flags; | |
118 | u32 vidcon0; | |
119 | u32 vidcon1; | |
cb91f6a0 | 120 | bool suspended; |
c32b06ef | 121 | struct mutex lock; |
01ce113c P |
122 | wait_queue_head_t wait_vsync_queue; |
123 | atomic_t wait_vsync_event; | |
1c248b7d | 124 | |
562ad9f4 | 125 | struct exynos_drm_panel_info panel; |
18873465 | 126 | struct fimd_driver_data *driver_data; |
1c248b7d ID |
127 | }; |
128 | ||
d636ead8 JS |
129 | #ifdef CONFIG_OF |
130 | static const struct of_device_id fimd_driver_dt_match[] = { | |
725ddead TF |
131 | { .compatible = "samsung,s3c6400-fimd", |
132 | .data = &s3c64xx_fimd_driver_data }, | |
5830daf8 | 133 | { .compatible = "samsung,exynos4210-fimd", |
d636ead8 | 134 | .data = &exynos4_fimd_driver_data }, |
5830daf8 | 135 | { .compatible = "samsung,exynos5250-fimd", |
d636ead8 JS |
136 | .data = &exynos5_fimd_driver_data }, |
137 | {}, | |
138 | }; | |
d636ead8 JS |
139 | #endif |
140 | ||
e2e13389 LKA |
141 | static inline struct fimd_driver_data *drm_fimd_get_driver_data( |
142 | struct platform_device *pdev) | |
143 | { | |
d636ead8 JS |
144 | #ifdef CONFIG_OF |
145 | const struct of_device_id *of_id = | |
146 | of_match_device(fimd_driver_dt_match, &pdev->dev); | |
147 | ||
148 | if (of_id) | |
149 | return (struct fimd_driver_data *)of_id->data; | |
150 | #endif | |
151 | ||
e2e13389 LKA |
152 | return (struct fimd_driver_data *) |
153 | platform_get_device_id(pdev)->driver_data; | |
154 | } | |
155 | ||
1c248b7d ID |
156 | static bool fimd_display_is_connected(struct device *dev) |
157 | { | |
1c248b7d ID |
158 | /* TODO. */ |
159 | ||
160 | return true; | |
161 | } | |
162 | ||
607c50d4 | 163 | static void *fimd_get_panel(struct device *dev) |
1c248b7d ID |
164 | { |
165 | struct fimd_context *ctx = get_fimd_context(dev); | |
166 | ||
562ad9f4 | 167 | return &ctx->panel; |
1c248b7d ID |
168 | } |
169 | ||
16844fb1 | 170 | static int fimd_check_mode(struct device *dev, struct drm_display_mode *mode) |
1c248b7d | 171 | { |
1c248b7d ID |
172 | /* TODO. */ |
173 | ||
174 | return 0; | |
175 | } | |
176 | ||
177 | static int fimd_display_power_on(struct device *dev, int mode) | |
178 | { | |
ec05da95 | 179 | /* TODO */ |
1c248b7d ID |
180 | |
181 | return 0; | |
182 | } | |
183 | ||
74ccc539 | 184 | static struct exynos_drm_display_ops fimd_display_ops = { |
1c248b7d ID |
185 | .type = EXYNOS_DISPLAY_TYPE_LCD, |
186 | .is_connected = fimd_display_is_connected, | |
607c50d4 | 187 | .get_panel = fimd_get_panel, |
16844fb1 | 188 | .check_mode = fimd_check_mode, |
1c248b7d ID |
189 | .power_on = fimd_display_power_on, |
190 | }; | |
191 | ||
ec05da95 ID |
192 | static void fimd_dpms(struct device *subdrv_dev, int mode) |
193 | { | |
c32b06ef ID |
194 | struct fimd_context *ctx = get_fimd_context(subdrv_dev); |
195 | ||
bca34c9a | 196 | DRM_DEBUG_KMS("%d\n", mode); |
ec05da95 | 197 | |
c32b06ef ID |
198 | mutex_lock(&ctx->lock); |
199 | ||
cb91f6a0 JS |
200 | switch (mode) { |
201 | case DRM_MODE_DPMS_ON: | |
c32b06ef ID |
202 | /* |
203 | * enable fimd hardware only if suspended status. | |
204 | * | |
205 | * P.S. fimd_dpms function would be called at booting time so | |
206 | * clk_enable could be called double time. | |
207 | */ | |
208 | if (ctx->suspended) | |
209 | pm_runtime_get_sync(subdrv_dev); | |
cb91f6a0 JS |
210 | break; |
211 | case DRM_MODE_DPMS_STANDBY: | |
212 | case DRM_MODE_DPMS_SUSPEND: | |
213 | case DRM_MODE_DPMS_OFF: | |
373af0c0 ID |
214 | if (!ctx->suspended) |
215 | pm_runtime_put_sync(subdrv_dev); | |
cb91f6a0 JS |
216 | break; |
217 | default: | |
218 | DRM_DEBUG_KMS("unspecified mode %d\n", mode); | |
219 | break; | |
220 | } | |
c32b06ef ID |
221 | |
222 | mutex_unlock(&ctx->lock); | |
ec05da95 ID |
223 | } |
224 | ||
225 | static void fimd_apply(struct device *subdrv_dev) | |
226 | { | |
227 | struct fimd_context *ctx = get_fimd_context(subdrv_dev); | |
677e84c1 | 228 | struct exynos_drm_manager *mgr = ctx->subdrv.manager; |
ec05da95 ID |
229 | struct exynos_drm_manager_ops *mgr_ops = mgr->ops; |
230 | struct exynos_drm_overlay_ops *ovl_ops = mgr->overlay_ops; | |
231 | struct fimd_win_data *win_data; | |
864ee9e6 | 232 | int i; |
ec05da95 | 233 | |
864ee9e6 JS |
234 | for (i = 0; i < WINDOWS_NR; i++) { |
235 | win_data = &ctx->win_data[i]; | |
236 | if (win_data->enabled && (ovl_ops && ovl_ops->commit)) | |
237 | ovl_ops->commit(subdrv_dev, i); | |
238 | } | |
ec05da95 ID |
239 | |
240 | if (mgr_ops && mgr_ops->commit) | |
241 | mgr_ops->commit(subdrv_dev); | |
242 | } | |
243 | ||
1c248b7d ID |
244 | static void fimd_commit(struct device *dev) |
245 | { | |
246 | struct fimd_context *ctx = get_fimd_context(dev); | |
562ad9f4 | 247 | struct exynos_drm_panel_info *panel = &ctx->panel; |
111e6055 | 248 | struct videomode *vm = &panel->vm; |
e2e13389 | 249 | struct fimd_driver_data *driver_data; |
1c248b7d ID |
250 | u32 val; |
251 | ||
18873465 | 252 | driver_data = ctx->driver_data; |
e30d4bcf ID |
253 | if (ctx->suspended) |
254 | return; | |
255 | ||
1c248b7d | 256 | /* setup polarity values from machine code. */ |
e2e13389 | 257 | writel(ctx->vidcon1, ctx->regs + driver_data->timing_base + VIDCON1); |
1c248b7d ID |
258 | |
259 | /* setup vertical timing values. */ | |
111e6055 AH |
260 | val = VIDTCON0_VBPD(vm->vback_porch - 1) | |
261 | VIDTCON0_VFPD(vm->vfront_porch - 1) | | |
262 | VIDTCON0_VSPW(vm->vsync_len - 1); | |
e2e13389 | 263 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON0); |
1c248b7d ID |
264 | |
265 | /* setup horizontal timing values. */ | |
111e6055 AH |
266 | val = VIDTCON1_HBPD(vm->hback_porch - 1) | |
267 | VIDTCON1_HFPD(vm->hfront_porch - 1) | | |
268 | VIDTCON1_HSPW(vm->hsync_len - 1); | |
e2e13389 | 269 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON1); |
1c248b7d ID |
270 | |
271 | /* setup horizontal and vertical display size. */ | |
111e6055 AH |
272 | val = VIDTCON2_LINEVAL(vm->vactive - 1) | |
273 | VIDTCON2_HOZVAL(vm->hactive - 1) | | |
274 | VIDTCON2_LINEVAL_E(vm->vactive - 1) | | |
275 | VIDTCON2_HOZVAL_E(vm->hactive - 1); | |
e2e13389 | 276 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON2); |
1c248b7d ID |
277 | |
278 | /* setup clock source, clock divider, enable dma. */ | |
279 | val = ctx->vidcon0; | |
280 | val &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR); | |
281 | ||
411d9ed4 TF |
282 | if (ctx->driver_data->has_clksel) { |
283 | val &= ~VIDCON0_CLKSEL_MASK; | |
284 | val |= VIDCON0_CLKSEL_LCD; | |
285 | } | |
286 | ||
1c248b7d ID |
287 | if (ctx->clkdiv > 1) |
288 | val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR; | |
289 | else | |
290 | val &= ~VIDCON0_CLKDIR; /* 1:1 clock */ | |
291 | ||
292 | /* | |
293 | * fields of register with prefix '_F' would be updated | |
294 | * at vsync(same as dma start) | |
295 | */ | |
296 | val |= VIDCON0_ENVID | VIDCON0_ENVID_F; | |
297 | writel(val, ctx->regs + VIDCON0); | |
298 | } | |
299 | ||
300 | static int fimd_enable_vblank(struct device *dev) | |
301 | { | |
302 | struct fimd_context *ctx = get_fimd_context(dev); | |
303 | u32 val; | |
304 | ||
cb91f6a0 JS |
305 | if (ctx->suspended) |
306 | return -EPERM; | |
307 | ||
1c248b7d ID |
308 | if (!test_and_set_bit(0, &ctx->irq_flags)) { |
309 | val = readl(ctx->regs + VIDINTCON0); | |
310 | ||
311 | val |= VIDINTCON0_INT_ENABLE; | |
312 | val |= VIDINTCON0_INT_FRAME; | |
313 | ||
314 | val &= ~VIDINTCON0_FRAMESEL0_MASK; | |
315 | val |= VIDINTCON0_FRAMESEL0_VSYNC; | |
316 | val &= ~VIDINTCON0_FRAMESEL1_MASK; | |
317 | val |= VIDINTCON0_FRAMESEL1_NONE; | |
318 | ||
319 | writel(val, ctx->regs + VIDINTCON0); | |
320 | } | |
321 | ||
322 | return 0; | |
323 | } | |
324 | ||
325 | static void fimd_disable_vblank(struct device *dev) | |
326 | { | |
327 | struct fimd_context *ctx = get_fimd_context(dev); | |
328 | u32 val; | |
329 | ||
cb91f6a0 JS |
330 | if (ctx->suspended) |
331 | return; | |
332 | ||
1c248b7d ID |
333 | if (test_and_clear_bit(0, &ctx->irq_flags)) { |
334 | val = readl(ctx->regs + VIDINTCON0); | |
335 | ||
336 | val &= ~VIDINTCON0_INT_FRAME; | |
337 | val &= ~VIDINTCON0_INT_ENABLE; | |
338 | ||
339 | writel(val, ctx->regs + VIDINTCON0); | |
340 | } | |
341 | } | |
342 | ||
07033970 P |
343 | static void fimd_wait_for_vblank(struct device *dev) |
344 | { | |
345 | struct fimd_context *ctx = get_fimd_context(dev); | |
07033970 | 346 | |
01ce113c P |
347 | if (ctx->suspended) |
348 | return; | |
349 | ||
350 | atomic_set(&ctx->wait_vsync_event, 1); | |
351 | ||
352 | /* | |
353 | * wait for FIMD to signal VSYNC interrupt or return after | |
354 | * timeout which is set to 50ms (refresh rate of 20). | |
355 | */ | |
356 | if (!wait_event_timeout(ctx->wait_vsync_queue, | |
357 | !atomic_read(&ctx->wait_vsync_event), | |
358 | DRM_HZ/20)) | |
07033970 P |
359 | DRM_DEBUG_KMS("vblank wait timed out.\n"); |
360 | } | |
361 | ||
1c248b7d | 362 | static struct exynos_drm_manager_ops fimd_manager_ops = { |
ec05da95 ID |
363 | .dpms = fimd_dpms, |
364 | .apply = fimd_apply, | |
1c248b7d ID |
365 | .commit = fimd_commit, |
366 | .enable_vblank = fimd_enable_vblank, | |
367 | .disable_vblank = fimd_disable_vblank, | |
07033970 | 368 | .wait_for_vblank = fimd_wait_for_vblank, |
1c248b7d ID |
369 | }; |
370 | ||
371 | static void fimd_win_mode_set(struct device *dev, | |
372 | struct exynos_drm_overlay *overlay) | |
373 | { | |
374 | struct fimd_context *ctx = get_fimd_context(dev); | |
375 | struct fimd_win_data *win_data; | |
864ee9e6 | 376 | int win; |
19c8b834 | 377 | unsigned long offset; |
1c248b7d | 378 | |
1c248b7d ID |
379 | if (!overlay) { |
380 | dev_err(dev, "overlay is NULL\n"); | |
381 | return; | |
382 | } | |
383 | ||
864ee9e6 JS |
384 | win = overlay->zpos; |
385 | if (win == DEFAULT_ZPOS) | |
386 | win = ctx->default_win; | |
387 | ||
37b006e8 | 388 | if (win < 0 || win >= WINDOWS_NR) |
864ee9e6 JS |
389 | return; |
390 | ||
19c8b834 ID |
391 | offset = overlay->fb_x * (overlay->bpp >> 3); |
392 | offset += overlay->fb_y * overlay->pitch; | |
393 | ||
394 | DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch); | |
395 | ||
864ee9e6 | 396 | win_data = &ctx->win_data[win]; |
1c248b7d | 397 | |
19c8b834 ID |
398 | win_data->offset_x = overlay->crtc_x; |
399 | win_data->offset_y = overlay->crtc_y; | |
400 | win_data->ovl_width = overlay->crtc_width; | |
401 | win_data->ovl_height = overlay->crtc_height; | |
402 | win_data->fb_width = overlay->fb_width; | |
403 | win_data->fb_height = overlay->fb_height; | |
229d3534 | 404 | win_data->dma_addr = overlay->dma_addr[0] + offset; |
1c248b7d | 405 | win_data->bpp = overlay->bpp; |
a4f38a80 | 406 | win_data->pixel_format = overlay->pixel_format; |
19c8b834 ID |
407 | win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) * |
408 | (overlay->bpp >> 3); | |
409 | win_data->line_size = overlay->crtc_width * (overlay->bpp >> 3); | |
410 | ||
411 | DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n", | |
412 | win_data->offset_x, win_data->offset_y); | |
413 | DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", | |
414 | win_data->ovl_width, win_data->ovl_height); | |
ddd8e959 | 415 | DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data->dma_addr); |
19c8b834 ID |
416 | DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n", |
417 | overlay->fb_width, overlay->crtc_width); | |
1c248b7d ID |
418 | } |
419 | ||
420 | static void fimd_win_set_pixfmt(struct device *dev, unsigned int win) | |
421 | { | |
422 | struct fimd_context *ctx = get_fimd_context(dev); | |
423 | struct fimd_win_data *win_data = &ctx->win_data[win]; | |
424 | unsigned long val; | |
425 | ||
1c248b7d ID |
426 | val = WINCONx_ENWIN; |
427 | ||
5cc4621a ID |
428 | /* |
429 | * In case of s3c64xx, window 0 doesn't support alpha channel. | |
430 | * So the request format is ARGB8888 then change it to XRGB8888. | |
431 | */ | |
432 | if (ctx->driver_data->has_limited_fmt && !win) { | |
433 | if (win_data->pixel_format == DRM_FORMAT_ARGB8888) | |
434 | win_data->pixel_format = DRM_FORMAT_XRGB8888; | |
435 | } | |
436 | ||
a4f38a80 ID |
437 | switch (win_data->pixel_format) { |
438 | case DRM_FORMAT_C8: | |
1c248b7d ID |
439 | val |= WINCON0_BPPMODE_8BPP_PALETTE; |
440 | val |= WINCONx_BURSTLEN_8WORD; | |
441 | val |= WINCONx_BYTSWP; | |
442 | break; | |
a4f38a80 ID |
443 | case DRM_FORMAT_XRGB1555: |
444 | val |= WINCON0_BPPMODE_16BPP_1555; | |
445 | val |= WINCONx_HAWSWP; | |
446 | val |= WINCONx_BURSTLEN_16WORD; | |
447 | break; | |
448 | case DRM_FORMAT_RGB565: | |
1c248b7d ID |
449 | val |= WINCON0_BPPMODE_16BPP_565; |
450 | val |= WINCONx_HAWSWP; | |
451 | val |= WINCONx_BURSTLEN_16WORD; | |
452 | break; | |
a4f38a80 | 453 | case DRM_FORMAT_XRGB8888: |
1c248b7d ID |
454 | val |= WINCON0_BPPMODE_24BPP_888; |
455 | val |= WINCONx_WSWP; | |
456 | val |= WINCONx_BURSTLEN_16WORD; | |
457 | break; | |
a4f38a80 ID |
458 | case DRM_FORMAT_ARGB8888: |
459 | val |= WINCON1_BPPMODE_25BPP_A1888 | |
1c248b7d ID |
460 | | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL; |
461 | val |= WINCONx_WSWP; | |
462 | val |= WINCONx_BURSTLEN_16WORD; | |
463 | break; | |
464 | default: | |
465 | DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n"); | |
466 | ||
467 | val |= WINCON0_BPPMODE_24BPP_888; | |
468 | val |= WINCONx_WSWP; | |
469 | val |= WINCONx_BURSTLEN_16WORD; | |
470 | break; | |
471 | } | |
472 | ||
473 | DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp); | |
474 | ||
475 | writel(val, ctx->regs + WINCON(win)); | |
476 | } | |
477 | ||
478 | static void fimd_win_set_colkey(struct device *dev, unsigned int win) | |
479 | { | |
480 | struct fimd_context *ctx = get_fimd_context(dev); | |
481 | unsigned int keycon0 = 0, keycon1 = 0; | |
482 | ||
1c248b7d ID |
483 | keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F | |
484 | WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); | |
485 | ||
486 | keycon1 = WxKEYCON1_COLVAL(0xffffffff); | |
487 | ||
488 | writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); | |
489 | writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); | |
490 | } | |
491 | ||
de7af100 TF |
492 | /** |
493 | * shadow_protect_win() - disable updating values from shadow registers at vsync | |
494 | * | |
495 | * @win: window to protect registers for | |
496 | * @protect: 1 to protect (disable updates) | |
497 | */ | |
498 | static void fimd_shadow_protect_win(struct fimd_context *ctx, | |
499 | int win, bool protect) | |
500 | { | |
501 | u32 reg, bits, val; | |
502 | ||
503 | if (ctx->driver_data->has_shadowcon) { | |
504 | reg = SHADOWCON; | |
505 | bits = SHADOWCON_WINx_PROTECT(win); | |
506 | } else { | |
507 | reg = PRTCON; | |
508 | bits = PRTCON_PROTECT; | |
509 | } | |
510 | ||
511 | val = readl(ctx->regs + reg); | |
512 | if (protect) | |
513 | val |= bits; | |
514 | else | |
515 | val &= ~bits; | |
516 | writel(val, ctx->regs + reg); | |
517 | } | |
518 | ||
864ee9e6 | 519 | static void fimd_win_commit(struct device *dev, int zpos) |
1c248b7d ID |
520 | { |
521 | struct fimd_context *ctx = get_fimd_context(dev); | |
522 | struct fimd_win_data *win_data; | |
864ee9e6 | 523 | int win = zpos; |
1c248b7d | 524 | unsigned long val, alpha, size; |
f56aad3a JS |
525 | unsigned int last_x; |
526 | unsigned int last_y; | |
1c248b7d | 527 | |
e30d4bcf ID |
528 | if (ctx->suspended) |
529 | return; | |
530 | ||
864ee9e6 JS |
531 | if (win == DEFAULT_ZPOS) |
532 | win = ctx->default_win; | |
533 | ||
37b006e8 | 534 | if (win < 0 || win >= WINDOWS_NR) |
1c248b7d ID |
535 | return; |
536 | ||
537 | win_data = &ctx->win_data[win]; | |
538 | ||
539 | /* | |
de7af100 | 540 | * SHADOWCON/PRTCON register is used for enabling timing. |
1c248b7d ID |
541 | * |
542 | * for example, once only width value of a register is set, | |
543 | * if the dma is started then fimd hardware could malfunction so | |
544 | * with protect window setting, the register fields with prefix '_F' | |
545 | * wouldn't be updated at vsync also but updated once unprotect window | |
546 | * is set. | |
547 | */ | |
548 | ||
549 | /* protect windows */ | |
de7af100 | 550 | fimd_shadow_protect_win(ctx, win, true); |
1c248b7d ID |
551 | |
552 | /* buffer start address */ | |
2c871127 | 553 | val = (unsigned long)win_data->dma_addr; |
1c248b7d ID |
554 | writel(val, ctx->regs + VIDWx_BUF_START(win, 0)); |
555 | ||
556 | /* buffer end address */ | |
19c8b834 | 557 | size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3); |
2c871127 | 558 | val = (unsigned long)(win_data->dma_addr + size); |
1c248b7d ID |
559 | writel(val, ctx->regs + VIDWx_BUF_END(win, 0)); |
560 | ||
561 | DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n", | |
2c871127 | 562 | (unsigned long)win_data->dma_addr, val, size); |
19c8b834 ID |
563 | DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", |
564 | win_data->ovl_width, win_data->ovl_height); | |
1c248b7d ID |
565 | |
566 | /* buffer size */ | |
567 | val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) | | |
ca555e5a JS |
568 | VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size) | |
569 | VIDW_BUF_SIZE_OFFSET_E(win_data->buf_offsize) | | |
570 | VIDW_BUF_SIZE_PAGEWIDTH_E(win_data->line_size); | |
1c248b7d ID |
571 | writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0)); |
572 | ||
573 | /* OSD position */ | |
574 | val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) | | |
ca555e5a JS |
575 | VIDOSDxA_TOPLEFT_Y(win_data->offset_y) | |
576 | VIDOSDxA_TOPLEFT_X_E(win_data->offset_x) | | |
577 | VIDOSDxA_TOPLEFT_Y_E(win_data->offset_y); | |
1c248b7d ID |
578 | writel(val, ctx->regs + VIDOSD_A(win)); |
579 | ||
f56aad3a JS |
580 | last_x = win_data->offset_x + win_data->ovl_width; |
581 | if (last_x) | |
582 | last_x--; | |
583 | last_y = win_data->offset_y + win_data->ovl_height; | |
584 | if (last_y) | |
585 | last_y--; | |
586 | ||
ca555e5a JS |
587 | val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) | |
588 | VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y); | |
589 | ||
1c248b7d ID |
590 | writel(val, ctx->regs + VIDOSD_B(win)); |
591 | ||
19c8b834 | 592 | DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", |
f56aad3a | 593 | win_data->offset_x, win_data->offset_y, last_x, last_y); |
1c248b7d ID |
594 | |
595 | /* hardware window 0 doesn't support alpha channel. */ | |
596 | if (win != 0) { | |
597 | /* OSD alpha */ | |
598 | alpha = VIDISD14C_ALPHA1_R(0xf) | | |
599 | VIDISD14C_ALPHA1_G(0xf) | | |
600 | VIDISD14C_ALPHA1_B(0xf); | |
601 | ||
602 | writel(alpha, ctx->regs + VIDOSD_C(win)); | |
603 | } | |
604 | ||
605 | /* OSD size */ | |
606 | if (win != 3 && win != 4) { | |
607 | u32 offset = VIDOSD_D(win); | |
608 | if (win == 0) | |
0f10cf14 | 609 | offset = VIDOSD_C(win); |
19c8b834 | 610 | val = win_data->ovl_width * win_data->ovl_height; |
1c248b7d ID |
611 | writel(val, ctx->regs + offset); |
612 | ||
613 | DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val); | |
614 | } | |
615 | ||
616 | fimd_win_set_pixfmt(dev, win); | |
617 | ||
618 | /* hardware window 0 doesn't support color key. */ | |
619 | if (win != 0) | |
620 | fimd_win_set_colkey(dev, win); | |
621 | ||
ec05da95 ID |
622 | /* wincon */ |
623 | val = readl(ctx->regs + WINCON(win)); | |
624 | val |= WINCONx_ENWIN; | |
625 | writel(val, ctx->regs + WINCON(win)); | |
626 | ||
1c248b7d | 627 | /* Enable DMA channel and unprotect windows */ |
de7af100 TF |
628 | fimd_shadow_protect_win(ctx, win, false); |
629 | ||
630 | if (ctx->driver_data->has_shadowcon) { | |
631 | val = readl(ctx->regs + SHADOWCON); | |
632 | val |= SHADOWCON_CHx_ENABLE(win); | |
633 | writel(val, ctx->regs + SHADOWCON); | |
634 | } | |
ec05da95 ID |
635 | |
636 | win_data->enabled = true; | |
1c248b7d ID |
637 | } |
638 | ||
864ee9e6 | 639 | static void fimd_win_disable(struct device *dev, int zpos) |
1c248b7d ID |
640 | { |
641 | struct fimd_context *ctx = get_fimd_context(dev); | |
ec05da95 | 642 | struct fimd_win_data *win_data; |
864ee9e6 | 643 | int win = zpos; |
1c248b7d ID |
644 | u32 val; |
645 | ||
864ee9e6 JS |
646 | if (win == DEFAULT_ZPOS) |
647 | win = ctx->default_win; | |
648 | ||
37b006e8 | 649 | if (win < 0 || win >= WINDOWS_NR) |
1c248b7d ID |
650 | return; |
651 | ||
ec05da95 ID |
652 | win_data = &ctx->win_data[win]; |
653 | ||
db7e55ae P |
654 | if (ctx->suspended) { |
655 | /* do not resume this window*/ | |
656 | win_data->resume = false; | |
657 | return; | |
658 | } | |
659 | ||
1c248b7d | 660 | /* protect windows */ |
de7af100 | 661 | fimd_shadow_protect_win(ctx, win, true); |
1c248b7d ID |
662 | |
663 | /* wincon */ | |
664 | val = readl(ctx->regs + WINCON(win)); | |
665 | val &= ~WINCONx_ENWIN; | |
666 | writel(val, ctx->regs + WINCON(win)); | |
667 | ||
668 | /* unprotect windows */ | |
de7af100 TF |
669 | if (ctx->driver_data->has_shadowcon) { |
670 | val = readl(ctx->regs + SHADOWCON); | |
671 | val &= ~SHADOWCON_CHx_ENABLE(win); | |
672 | writel(val, ctx->regs + SHADOWCON); | |
673 | } | |
674 | ||
675 | fimd_shadow_protect_win(ctx, win, false); | |
ec05da95 ID |
676 | |
677 | win_data->enabled = false; | |
1c248b7d ID |
678 | } |
679 | ||
680 | static struct exynos_drm_overlay_ops fimd_overlay_ops = { | |
681 | .mode_set = fimd_win_mode_set, | |
682 | .commit = fimd_win_commit, | |
683 | .disable = fimd_win_disable, | |
684 | }; | |
685 | ||
677e84c1 JS |
686 | static struct exynos_drm_manager fimd_manager = { |
687 | .pipe = -1, | |
688 | .ops = &fimd_manager_ops, | |
689 | .overlay_ops = &fimd_overlay_ops, | |
690 | .display_ops = &fimd_display_ops, | |
691 | }; | |
692 | ||
1c248b7d ID |
693 | static irqreturn_t fimd_irq_handler(int irq, void *dev_id) |
694 | { | |
695 | struct fimd_context *ctx = (struct fimd_context *)dev_id; | |
696 | struct exynos_drm_subdrv *subdrv = &ctx->subdrv; | |
697 | struct drm_device *drm_dev = subdrv->drm_dev; | |
677e84c1 | 698 | struct exynos_drm_manager *manager = subdrv->manager; |
1c248b7d ID |
699 | u32 val; |
700 | ||
701 | val = readl(ctx->regs + VIDINTCON1); | |
702 | ||
703 | if (val & VIDINTCON1_INT_FRAME) | |
704 | /* VSYNC interrupt */ | |
705 | writel(VIDINTCON1_INT_FRAME, ctx->regs + VIDINTCON1); | |
706 | ||
ec05da95 ID |
707 | /* check the crtc is detached already from encoder */ |
708 | if (manager->pipe < 0) | |
709 | goto out; | |
483b88f8 | 710 | |
1c248b7d | 711 | drm_handle_vblank(drm_dev, manager->pipe); |
663d8766 | 712 | exynos_drm_crtc_finish_pageflip(drm_dev, manager->pipe); |
1c248b7d | 713 | |
01ce113c P |
714 | /* set wait vsync event to zero and wake up queue. */ |
715 | if (atomic_read(&ctx->wait_vsync_event)) { | |
716 | atomic_set(&ctx->wait_vsync_event, 0); | |
717 | DRM_WAKEUP(&ctx->wait_vsync_queue); | |
718 | } | |
ec05da95 | 719 | out: |
1c248b7d ID |
720 | return IRQ_HANDLED; |
721 | } | |
722 | ||
41c24346 | 723 | static int fimd_subdrv_probe(struct drm_device *drm_dev, struct device *dev) |
1c248b7d | 724 | { |
1c248b7d ID |
725 | /* |
726 | * enable drm irq mode. | |
727 | * - with irq_enabled = 1, we can use the vblank feature. | |
728 | * | |
729 | * P.S. note that we wouldn't use drm irq handler but | |
730 | * just specific driver own one instead because | |
731 | * drm framework supports only one irq handler. | |
732 | */ | |
733 | drm_dev->irq_enabled = 1; | |
734 | ||
ec05da95 ID |
735 | /* |
736 | * with vblank_disable_allowed = 1, vblank interrupt will be disabled | |
737 | * by drm timer once a current process gives up ownership of | |
738 | * vblank event.(after drm_vblank_put function is called) | |
739 | */ | |
740 | drm_dev->vblank_disable_allowed = 1; | |
741 | ||
bcc5cd1c ID |
742 | /* attach this sub driver to iommu mapping if supported. */ |
743 | if (is_drm_iommu_supported(drm_dev)) | |
744 | drm_iommu_attach_device(drm_dev, dev); | |
745 | ||
1c248b7d ID |
746 | return 0; |
747 | } | |
748 | ||
29cb6025 | 749 | static void fimd_subdrv_remove(struct drm_device *drm_dev, struct device *dev) |
1c248b7d | 750 | { |
bcc5cd1c ID |
751 | /* detach this sub driver from iommu mapping if supported. */ |
752 | if (is_drm_iommu_supported(drm_dev)) | |
753 | drm_iommu_detach_device(drm_dev, dev); | |
1c248b7d ID |
754 | } |
755 | ||
111e6055 | 756 | static int fimd_configure_clocks(struct fimd_context *ctx, struct device *dev) |
1c248b7d | 757 | { |
562ad9f4 | 758 | struct videomode *vm = &ctx->panel.vm; |
111e6055 AH |
759 | unsigned long clk; |
760 | ||
761 | ctx->bus_clk = devm_clk_get(dev, "fimd"); | |
762 | if (IS_ERR(ctx->bus_clk)) { | |
763 | dev_err(dev, "failed to get bus clock\n"); | |
764 | return PTR_ERR(ctx->bus_clk); | |
765 | } | |
766 | ||
767 | ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd"); | |
768 | if (IS_ERR(ctx->lcd_clk)) { | |
769 | dev_err(dev, "failed to get lcd clock\n"); | |
770 | return PTR_ERR(ctx->lcd_clk); | |
771 | } | |
772 | ||
773 | clk = clk_get_rate(ctx->lcd_clk); | |
774 | if (clk == 0) { | |
775 | dev_err(dev, "error getting sclk_fimd clock rate\n"); | |
776 | return -EINVAL; | |
777 | } | |
778 | ||
779 | if (vm->pixelclock == 0) { | |
780 | unsigned long c; | |
781 | c = vm->hactive + vm->hback_porch + vm->hfront_porch + | |
782 | vm->hsync_len; | |
783 | c *= vm->vactive + vm->vback_porch + vm->vfront_porch + | |
784 | vm->vsync_len; | |
785 | vm->pixelclock = c * FIMD_DEFAULT_FRAMERATE; | |
786 | if (vm->pixelclock == 0) { | |
787 | dev_err(dev, "incorrect display timings\n"); | |
788 | return -EINVAL; | |
1c248b7d | 789 | } |
111e6055 AH |
790 | dev_warn(dev, "pixel clock recalculated to %luHz (%dHz frame rate)\n", |
791 | vm->pixelclock, FIMD_DEFAULT_FRAMERATE); | |
792 | } | |
793 | ctx->clkdiv = DIV_ROUND_UP(clk, vm->pixelclock); | |
794 | if (ctx->clkdiv > 256) { | |
795 | dev_warn(dev, "calculated pixel clock divider too high (%u), lowered to 256\n", | |
796 | ctx->clkdiv); | |
797 | ctx->clkdiv = 256; | |
1c248b7d | 798 | } |
111e6055 AH |
799 | vm->pixelclock = clk / ctx->clkdiv; |
800 | DRM_DEBUG_KMS("pixel clock = %lu, clkdiv = %d\n", vm->pixelclock, | |
801 | ctx->clkdiv); | |
1c248b7d | 802 | |
111e6055 | 803 | return 0; |
1c248b7d ID |
804 | } |
805 | ||
806 | static void fimd_clear_win(struct fimd_context *ctx, int win) | |
807 | { | |
1c248b7d ID |
808 | writel(0, ctx->regs + WINCON(win)); |
809 | writel(0, ctx->regs + VIDOSD_A(win)); | |
810 | writel(0, ctx->regs + VIDOSD_B(win)); | |
811 | writel(0, ctx->regs + VIDOSD_C(win)); | |
812 | ||
813 | if (win == 1 || win == 2) | |
814 | writel(0, ctx->regs + VIDOSD_D(win)); | |
815 | ||
de7af100 | 816 | fimd_shadow_protect_win(ctx, win, false); |
1c248b7d ID |
817 | } |
818 | ||
5d55393a | 819 | static int fimd_clock(struct fimd_context *ctx, bool enable) |
373af0c0 | 820 | { |
373af0c0 ID |
821 | if (enable) { |
822 | int ret; | |
823 | ||
11963a63 | 824 | ret = clk_prepare_enable(ctx->bus_clk); |
373af0c0 ID |
825 | if (ret < 0) |
826 | return ret; | |
827 | ||
11963a63 | 828 | ret = clk_prepare_enable(ctx->lcd_clk); |
373af0c0 | 829 | if (ret < 0) { |
11963a63 | 830 | clk_disable_unprepare(ctx->bus_clk); |
373af0c0 ID |
831 | return ret; |
832 | } | |
5d55393a | 833 | } else { |
11963a63 VS |
834 | clk_disable_unprepare(ctx->lcd_clk); |
835 | clk_disable_unprepare(ctx->bus_clk); | |
5d55393a ID |
836 | } |
837 | ||
838 | return 0; | |
839 | } | |
840 | ||
db7e55ae P |
841 | static void fimd_window_suspend(struct device *dev) |
842 | { | |
843 | struct fimd_context *ctx = get_fimd_context(dev); | |
844 | struct fimd_win_data *win_data; | |
845 | int i; | |
846 | ||
847 | for (i = 0; i < WINDOWS_NR; i++) { | |
848 | win_data = &ctx->win_data[i]; | |
849 | win_data->resume = win_data->enabled; | |
850 | fimd_win_disable(dev, i); | |
851 | } | |
852 | fimd_wait_for_vblank(dev); | |
853 | } | |
854 | ||
855 | static void fimd_window_resume(struct device *dev) | |
856 | { | |
857 | struct fimd_context *ctx = get_fimd_context(dev); | |
858 | struct fimd_win_data *win_data; | |
859 | int i; | |
860 | ||
861 | for (i = 0; i < WINDOWS_NR; i++) { | |
862 | win_data = &ctx->win_data[i]; | |
863 | win_data->enabled = win_data->resume; | |
864 | win_data->resume = false; | |
865 | } | |
866 | } | |
867 | ||
5d55393a ID |
868 | static int fimd_activate(struct fimd_context *ctx, bool enable) |
869 | { | |
db7e55ae | 870 | struct device *dev = ctx->subdrv.dev; |
5d55393a ID |
871 | if (enable) { |
872 | int ret; | |
5d55393a ID |
873 | |
874 | ret = fimd_clock(ctx, true); | |
875 | if (ret < 0) | |
876 | return ret; | |
373af0c0 ID |
877 | |
878 | ctx->suspended = false; | |
879 | ||
880 | /* if vblank was enabled status, enable it again. */ | |
881 | if (test_and_clear_bit(0, &ctx->irq_flags)) | |
882 | fimd_enable_vblank(dev); | |
db7e55ae P |
883 | |
884 | fimd_window_resume(dev); | |
373af0c0 | 885 | } else { |
db7e55ae P |
886 | fimd_window_suspend(dev); |
887 | ||
5d55393a | 888 | fimd_clock(ctx, false); |
373af0c0 ID |
889 | ctx->suspended = true; |
890 | } | |
891 | ||
892 | return 0; | |
893 | } | |
894 | ||
562ad9f4 | 895 | static int fimd_get_platform_data(struct fimd_context *ctx, struct device *dev) |
1c248b7d | 896 | { |
d873ab99 | 897 | if (dev->of_node) { |
111e6055 | 898 | struct videomode *vm; |
562ad9f4 | 899 | int ret; |
7f4596f4 | 900 | |
562ad9f4 | 901 | vm = &ctx->panel.vm; |
111e6055 | 902 | ret = of_get_videomode(dev->of_node, vm, OF_USE_NATIVE_MODE); |
7f4596f4 | 903 | if (ret) { |
111e6055 | 904 | DRM_ERROR("failed: of_get_videomode() : %d\n", ret); |
7f4596f4 VS |
905 | return ret; |
906 | } | |
b063f4af AH |
907 | |
908 | if (vm->flags & DISPLAY_FLAGS_VSYNC_LOW) | |
562ad9f4 | 909 | ctx->vidcon1 |= VIDCON1_INV_VSYNC; |
b063f4af | 910 | if (vm->flags & DISPLAY_FLAGS_HSYNC_LOW) |
562ad9f4 | 911 | ctx->vidcon1 |= VIDCON1_INV_HSYNC; |
b063f4af | 912 | if (vm->flags & DISPLAY_FLAGS_DE_LOW) |
562ad9f4 | 913 | ctx->vidcon1 |= VIDCON1_INV_VDEN; |
b063f4af | 914 | if (vm->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) |
562ad9f4 | 915 | ctx->vidcon1 |= VIDCON1_INV_VCLK; |
7f4596f4 | 916 | } else { |
562ad9f4 | 917 | struct exynos_drm_fimd_pdata *pdata = dev->platform_data; |
7f4596f4 VS |
918 | if (!pdata) { |
919 | DRM_ERROR("no platform data specified\n"); | |
920 | return -EINVAL; | |
921 | } | |
562ad9f4 AH |
922 | ctx->vidcon0 = pdata->vidcon0; |
923 | ctx->vidcon1 = pdata->vidcon1; | |
924 | ctx->default_win = pdata->default_win; | |
925 | ctx->panel = pdata->panel; | |
1c248b7d ID |
926 | } |
927 | ||
562ad9f4 AH |
928 | return 0; |
929 | } | |
930 | ||
931 | static int fimd_probe(struct platform_device *pdev) | |
932 | { | |
933 | struct device *dev = &pdev->dev; | |
934 | struct fimd_context *ctx; | |
935 | struct exynos_drm_subdrv *subdrv; | |
936 | struct resource *res; | |
937 | int win; | |
938 | int ret = -EINVAL; | |
1c248b7d | 939 | |
d873ab99 | 940 | ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); |
1c248b7d ID |
941 | if (!ctx) |
942 | return -ENOMEM; | |
943 | ||
562ad9f4 AH |
944 | ret = fimd_get_platform_data(ctx, dev); |
945 | if (ret) | |
946 | return ret; | |
947 | ||
111e6055 AH |
948 | ret = fimd_configure_clocks(ctx, dev); |
949 | if (ret) | |
950 | return ret; | |
1c248b7d | 951 | |
1c248b7d | 952 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1c248b7d | 953 | |
d873ab99 | 954 | ctx->regs = devm_ioremap_resource(dev, res); |
d4ed6025 TR |
955 | if (IS_ERR(ctx->regs)) |
956 | return PTR_ERR(ctx->regs); | |
1c248b7d | 957 | |
1977e6d8 | 958 | res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "vsync"); |
1c248b7d ID |
959 | if (!res) { |
960 | dev_err(dev, "irq request failed.\n"); | |
a4d8de5f | 961 | return -ENXIO; |
1c248b7d ID |
962 | } |
963 | ||
964 | ctx->irq = res->start; | |
965 | ||
d873ab99 | 966 | ret = devm_request_irq(dev, ctx->irq, fimd_irq_handler, |
edc57266 SK |
967 | 0, "drm_fimd", ctx); |
968 | if (ret) { | |
1c248b7d | 969 | dev_err(dev, "irq request failed.\n"); |
a4d8de5f | 970 | return ret; |
1c248b7d ID |
971 | } |
972 | ||
18873465 | 973 | ctx->driver_data = drm_fimd_get_driver_data(pdev); |
01ce113c P |
974 | DRM_INIT_WAITQUEUE(&ctx->wait_vsync_queue); |
975 | atomic_set(&ctx->wait_vsync_event, 0); | |
1c248b7d | 976 | |
1c248b7d ID |
977 | subdrv = &ctx->subdrv; |
978 | ||
677e84c1 JS |
979 | subdrv->dev = dev; |
980 | subdrv->manager = &fimd_manager; | |
1c248b7d ID |
981 | subdrv->probe = fimd_subdrv_probe; |
982 | subdrv->remove = fimd_subdrv_remove; | |
1c248b7d | 983 | |
c32b06ef ID |
984 | mutex_init(&ctx->lock); |
985 | ||
1c248b7d | 986 | platform_set_drvdata(pdev, ctx); |
c32b06ef | 987 | |
c32b06ef ID |
988 | pm_runtime_enable(dev); |
989 | pm_runtime_get_sync(dev); | |
990 | ||
991 | for (win = 0; win < WINDOWS_NR; win++) | |
992 | fimd_clear_win(ctx, win); | |
993 | ||
1c248b7d ID |
994 | exynos_drm_subdrv_register(subdrv); |
995 | ||
996 | return 0; | |
1c248b7d ID |
997 | } |
998 | ||
56550d94 | 999 | static int fimd_remove(struct platform_device *pdev) |
1c248b7d | 1000 | { |
cb91f6a0 | 1001 | struct device *dev = &pdev->dev; |
1c248b7d ID |
1002 | struct fimd_context *ctx = platform_get_drvdata(pdev); |
1003 | ||
1c248b7d ID |
1004 | exynos_drm_subdrv_unregister(&ctx->subdrv); |
1005 | ||
cb91f6a0 JS |
1006 | if (ctx->suspended) |
1007 | goto out; | |
1008 | ||
cb91f6a0 JS |
1009 | pm_runtime_set_suspended(dev); |
1010 | pm_runtime_put_sync(dev); | |
1011 | ||
1012 | out: | |
1013 | pm_runtime_disable(dev); | |
1014 | ||
1c248b7d ID |
1015 | return 0; |
1016 | } | |
1017 | ||
e30d4bcf ID |
1018 | #ifdef CONFIG_PM_SLEEP |
1019 | static int fimd_suspend(struct device *dev) | |
1020 | { | |
373af0c0 | 1021 | struct fimd_context *ctx = get_fimd_context(dev); |
e30d4bcf | 1022 | |
373af0c0 ID |
1023 | /* |
1024 | * do not use pm_runtime_suspend(). if pm_runtime_suspend() is | |
1025 | * called here, an error would be returned by that interface | |
1026 | * because the usage_count of pm runtime is more than 1. | |
1027 | */ | |
5d55393a ID |
1028 | if (!pm_runtime_suspended(dev)) |
1029 | return fimd_activate(ctx, false); | |
1030 | ||
1031 | return 0; | |
e30d4bcf ID |
1032 | } |
1033 | ||
1034 | static int fimd_resume(struct device *dev) | |
1035 | { | |
373af0c0 | 1036 | struct fimd_context *ctx = get_fimd_context(dev); |
e30d4bcf | 1037 | |
373af0c0 ID |
1038 | /* |
1039 | * if entered to sleep when lcd panel was on, the usage_count | |
1040 | * of pm runtime would still be 1 so in this case, fimd driver | |
1041 | * should be on directly not drawing on pm runtime interface. | |
1042 | */ | |
28998afa | 1043 | if (!pm_runtime_suspended(dev)) { |
5d55393a ID |
1044 | int ret; |
1045 | ||
1046 | ret = fimd_activate(ctx, true); | |
1047 | if (ret < 0) | |
1048 | return ret; | |
1049 | ||
1050 | /* | |
1051 | * in case of dpms on(standby), fimd_apply function will | |
1052 | * be called by encoder's dpms callback to update fimd's | |
1053 | * registers but in case of sleep wakeup, it's not. | |
1054 | * so fimd_apply function should be called at here. | |
1055 | */ | |
1056 | fimd_apply(dev); | |
1057 | } | |
e30d4bcf | 1058 | |
e30d4bcf ID |
1059 | return 0; |
1060 | } | |
1061 | #endif | |
1062 | ||
cb91f6a0 JS |
1063 | #ifdef CONFIG_PM_RUNTIME |
1064 | static int fimd_runtime_suspend(struct device *dev) | |
1065 | { | |
1066 | struct fimd_context *ctx = get_fimd_context(dev); | |
1067 | ||
5d55393a | 1068 | return fimd_activate(ctx, false); |
cb91f6a0 JS |
1069 | } |
1070 | ||
1071 | static int fimd_runtime_resume(struct device *dev) | |
1072 | { | |
1073 | struct fimd_context *ctx = get_fimd_context(dev); | |
cb91f6a0 | 1074 | |
5d55393a | 1075 | return fimd_activate(ctx, true); |
cb91f6a0 JS |
1076 | } |
1077 | #endif | |
1078 | ||
e2e13389 LKA |
1079 | static struct platform_device_id fimd_driver_ids[] = { |
1080 | { | |
725ddead TF |
1081 | .name = "s3c64xx-fb", |
1082 | .driver_data = (unsigned long)&s3c64xx_fimd_driver_data, | |
1083 | }, { | |
e2e13389 LKA |
1084 | .name = "exynos4-fb", |
1085 | .driver_data = (unsigned long)&exynos4_fimd_driver_data, | |
1086 | }, { | |
1087 | .name = "exynos5-fb", | |
1088 | .driver_data = (unsigned long)&exynos5_fimd_driver_data, | |
1089 | }, | |
1090 | {}, | |
1091 | }; | |
e2e13389 | 1092 | |
cb91f6a0 | 1093 | static const struct dev_pm_ops fimd_pm_ops = { |
e30d4bcf | 1094 | SET_SYSTEM_SLEEP_PM_OPS(fimd_suspend, fimd_resume) |
cb91f6a0 JS |
1095 | SET_RUNTIME_PM_OPS(fimd_runtime_suspend, fimd_runtime_resume, NULL) |
1096 | }; | |
1097 | ||
132a5b91 | 1098 | struct platform_driver fimd_driver = { |
1c248b7d | 1099 | .probe = fimd_probe, |
56550d94 | 1100 | .remove = fimd_remove, |
e2e13389 | 1101 | .id_table = fimd_driver_ids, |
1c248b7d ID |
1102 | .driver = { |
1103 | .name = "exynos4-fb", | |
1104 | .owner = THIS_MODULE, | |
cb91f6a0 | 1105 | .pm = &fimd_pm_ops, |
d636ead8 | 1106 | .of_match_table = of_match_ptr(fimd_driver_dt_match), |
1c248b7d ID |
1107 | }, |
1108 | }; |