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1c248b7d ID |
1 | /* exynos_drm_fimd.c |
2 | * | |
3 | * Copyright (C) 2011 Samsung Electronics Co.Ltd | |
4 | * Authors: | |
5 | * Joonyoung Shim <jy0922.shim@samsung.com> | |
6 | * Inki Dae <inki.dae@samsung.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | */ | |
760285e7 | 14 | #include <drm/drmP.h> |
1c248b7d ID |
15 | |
16 | #include <linux/kernel.h> | |
1c248b7d ID |
17 | #include <linux/platform_device.h> |
18 | #include <linux/clk.h> | |
3f1c781d | 19 | #include <linux/of.h> |
d636ead8 | 20 | #include <linux/of_device.h> |
cb91f6a0 | 21 | #include <linux/pm_runtime.h> |
f37cd5e8 | 22 | #include <linux/component.h> |
3854fab2 YC |
23 | #include <linux/mfd/syscon.h> |
24 | #include <linux/regmap.h> | |
1c248b7d | 25 | |
7f4596f4 | 26 | #include <video/of_display_timing.h> |
111e6055 | 27 | #include <video/of_videomode.h> |
5a213a55 | 28 | #include <video/samsung_fimd.h> |
1c248b7d | 29 | #include <drm/exynos_drm.h> |
1c248b7d ID |
30 | |
31 | #include "exynos_drm_drv.h" | |
32 | #include "exynos_drm_fbdev.h" | |
33 | #include "exynos_drm_crtc.h" | |
7ee14cdc | 34 | #include "exynos_drm_plane.h" |
bcc5cd1c | 35 | #include "exynos_drm_iommu.h" |
1c363c7c | 36 | #include "exynos_drm_fimd.h" |
1c248b7d ID |
37 | |
38 | /* | |
b8654b37 | 39 | * FIMD stands for Fully Interactive Mobile Display and |
1c248b7d ID |
40 | * as a display controller, it transfers contents drawn on memory |
41 | * to a LCD Panel through Display Interfaces such as RGB or | |
42 | * CPU Interface. | |
43 | */ | |
44 | ||
111e6055 | 45 | #define FIMD_DEFAULT_FRAMERATE 60 |
66367461 | 46 | #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 |
111e6055 | 47 | |
1c248b7d ID |
48 | /* position control register for hardware window 0, 2 ~ 4.*/ |
49 | #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16) | |
50 | #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16) | |
0f10cf14 LKA |
51 | /* |
52 | * size control register for hardware windows 0 and alpha control register | |
53 | * for hardware windows 1 ~ 4 | |
54 | */ | |
55 | #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16) | |
56 | /* size control register for hardware windows 1 ~ 2. */ | |
1c248b7d ID |
57 | #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16) |
58 | ||
453b44a3 GP |
59 | #define VIDWnALPHA0(win) (VIDW_ALPHA + 0x00 + (win) * 8) |
60 | #define VIDWnALPHA1(win) (VIDW_ALPHA + 0x04 + (win) * 8) | |
61 | ||
1c248b7d ID |
62 | #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8) |
63 | #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8) | |
64 | #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4) | |
65 | ||
66 | /* color key control register for hardware window 1 ~ 4. */ | |
0f10cf14 | 67 | #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8)) |
1c248b7d | 68 | /* color key value register for hardware window 1 ~ 4. */ |
0f10cf14 | 69 | #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8)) |
1c248b7d | 70 | |
3854fab2 YC |
71 | /* I80 / RGB trigger control register */ |
72 | #define TRIGCON 0x1A4 | |
73 | #define TRGMODE_I80_RGB_ENABLE_I80 (1 << 0) | |
74 | #define SWTRGCMD_I80_RGB_ENABLE (1 << 1) | |
75 | ||
76 | /* display mode change control register except exynos4 */ | |
77 | #define VIDOUT_CON 0x000 | |
78 | #define VIDOUT_CON_F_I80_LDI0 (0x2 << 8) | |
79 | ||
80 | /* I80 interface control for main LDI register */ | |
81 | #define I80IFCONFAx(x) (0x1B0 + (x) * 4) | |
82 | #define I80IFCONFBx(x) (0x1B8 + (x) * 4) | |
83 | #define LCD_CS_SETUP(x) ((x) << 16) | |
84 | #define LCD_WR_SETUP(x) ((x) << 12) | |
85 | #define LCD_WR_ACTIVE(x) ((x) << 8) | |
86 | #define LCD_WR_HOLD(x) ((x) << 4) | |
87 | #define I80IFEN_ENABLE (1 << 0) | |
88 | ||
1c248b7d ID |
89 | /* FIMD has totally five hardware windows. */ |
90 | #define WINDOWS_NR 5 | |
91 | ||
e2e13389 LKA |
92 | struct fimd_driver_data { |
93 | unsigned int timing_base; | |
3854fab2 YC |
94 | unsigned int lcdblk_offset; |
95 | unsigned int lcdblk_vt_shift; | |
96 | unsigned int lcdblk_bypass_shift; | |
de7af100 TF |
97 | |
98 | unsigned int has_shadowcon:1; | |
411d9ed4 | 99 | unsigned int has_clksel:1; |
5cc4621a | 100 | unsigned int has_limited_fmt:1; |
3854fab2 | 101 | unsigned int has_vidoutcon:1; |
3c3c9c1d | 102 | unsigned int has_vtsel:1; |
e2e13389 LKA |
103 | }; |
104 | ||
725ddead TF |
105 | static struct fimd_driver_data s3c64xx_fimd_driver_data = { |
106 | .timing_base = 0x0, | |
107 | .has_clksel = 1, | |
5cc4621a | 108 | .has_limited_fmt = 1, |
725ddead TF |
109 | }; |
110 | ||
d6ce7b58 ID |
111 | static struct fimd_driver_data exynos3_fimd_driver_data = { |
112 | .timing_base = 0x20000, | |
113 | .lcdblk_offset = 0x210, | |
114 | .lcdblk_bypass_shift = 1, | |
115 | .has_shadowcon = 1, | |
116 | .has_vidoutcon = 1, | |
117 | }; | |
118 | ||
6ecf18f9 | 119 | static struct fimd_driver_data exynos4_fimd_driver_data = { |
e2e13389 | 120 | .timing_base = 0x0, |
3854fab2 YC |
121 | .lcdblk_offset = 0x210, |
122 | .lcdblk_vt_shift = 10, | |
123 | .lcdblk_bypass_shift = 1, | |
de7af100 | 124 | .has_shadowcon = 1, |
3c3c9c1d | 125 | .has_vtsel = 1, |
e2e13389 LKA |
126 | }; |
127 | ||
dcb622aa YC |
128 | static struct fimd_driver_data exynos4415_fimd_driver_data = { |
129 | .timing_base = 0x20000, | |
130 | .lcdblk_offset = 0x210, | |
131 | .lcdblk_vt_shift = 10, | |
132 | .lcdblk_bypass_shift = 1, | |
133 | .has_shadowcon = 1, | |
134 | .has_vidoutcon = 1, | |
3c3c9c1d | 135 | .has_vtsel = 1, |
dcb622aa YC |
136 | }; |
137 | ||
6ecf18f9 | 138 | static struct fimd_driver_data exynos5_fimd_driver_data = { |
e2e13389 | 139 | .timing_base = 0x20000, |
3854fab2 YC |
140 | .lcdblk_offset = 0x214, |
141 | .lcdblk_vt_shift = 24, | |
142 | .lcdblk_bypass_shift = 15, | |
de7af100 | 143 | .has_shadowcon = 1, |
3854fab2 | 144 | .has_vidoutcon = 1, |
3c3c9c1d | 145 | .has_vtsel = 1, |
e2e13389 LKA |
146 | }; |
147 | ||
1c248b7d | 148 | struct fimd_context { |
bb7704d6 | 149 | struct device *dev; |
40c8ab4b | 150 | struct drm_device *drm_dev; |
93bca243 | 151 | struct exynos_drm_crtc *crtc; |
7ee14cdc | 152 | struct exynos_drm_plane planes[WINDOWS_NR]; |
1c248b7d ID |
153 | struct clk *bus_clk; |
154 | struct clk *lcd_clk; | |
1c248b7d | 155 | void __iomem *regs; |
3854fab2 | 156 | struct regmap *sysreg; |
1c248b7d ID |
157 | unsigned int default_win; |
158 | unsigned long irq_flags; | |
3854fab2 | 159 | u32 vidcon0; |
1c248b7d | 160 | u32 vidcon1; |
3854fab2 YC |
161 | u32 vidout_con; |
162 | u32 i80ifcon; | |
163 | bool i80_if; | |
cb91f6a0 | 164 | bool suspended; |
080be03d | 165 | int pipe; |
01ce113c P |
166 | wait_queue_head_t wait_vsync_queue; |
167 | atomic_t wait_vsync_event; | |
3854fab2 YC |
168 | atomic_t win_updated; |
169 | atomic_t triggering; | |
1c248b7d | 170 | |
562ad9f4 | 171 | struct exynos_drm_panel_info panel; |
18873465 | 172 | struct fimd_driver_data *driver_data; |
000cc920 | 173 | struct exynos_drm_display *display; |
1c248b7d ID |
174 | }; |
175 | ||
d636ead8 | 176 | static const struct of_device_id fimd_driver_dt_match[] = { |
725ddead TF |
177 | { .compatible = "samsung,s3c6400-fimd", |
178 | .data = &s3c64xx_fimd_driver_data }, | |
d6ce7b58 ID |
179 | { .compatible = "samsung,exynos3250-fimd", |
180 | .data = &exynos3_fimd_driver_data }, | |
5830daf8 | 181 | { .compatible = "samsung,exynos4210-fimd", |
d636ead8 | 182 | .data = &exynos4_fimd_driver_data }, |
dcb622aa YC |
183 | { .compatible = "samsung,exynos4415-fimd", |
184 | .data = &exynos4415_fimd_driver_data }, | |
5830daf8 | 185 | { .compatible = "samsung,exynos5250-fimd", |
d636ead8 JS |
186 | .data = &exynos5_fimd_driver_data }, |
187 | {}, | |
188 | }; | |
0262ceeb | 189 | MODULE_DEVICE_TABLE(of, fimd_driver_dt_match); |
d636ead8 | 190 | |
e2e13389 LKA |
191 | static inline struct fimd_driver_data *drm_fimd_get_driver_data( |
192 | struct platform_device *pdev) | |
193 | { | |
d636ead8 JS |
194 | const struct of_device_id *of_id = |
195 | of_match_device(fimd_driver_dt_match, &pdev->dev); | |
196 | ||
2d3f173c | 197 | return (struct fimd_driver_data *)of_id->data; |
e2e13389 LKA |
198 | } |
199 | ||
93bca243 | 200 | static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc) |
f13bdbd1 | 201 | { |
93bca243 | 202 | struct fimd_context *ctx = crtc->ctx; |
f13bdbd1 AA |
203 | |
204 | if (ctx->suspended) | |
205 | return; | |
206 | ||
207 | atomic_set(&ctx->wait_vsync_event, 1); | |
208 | ||
209 | /* | |
210 | * wait for FIMD to signal VSYNC interrupt or return after | |
211 | * timeout which is set to 50ms (refresh rate of 20). | |
212 | */ | |
213 | if (!wait_event_timeout(ctx->wait_vsync_queue, | |
214 | !atomic_read(&ctx->wait_vsync_event), | |
215 | HZ/20)) | |
216 | DRM_DEBUG_KMS("vblank wait timed out.\n"); | |
217 | } | |
218 | ||
f181a543 YC |
219 | static void fimd_enable_video_output(struct fimd_context *ctx, int win, |
220 | bool enable) | |
221 | { | |
222 | u32 val = readl(ctx->regs + WINCON(win)); | |
223 | ||
224 | if (enable) | |
225 | val |= WINCONx_ENWIN; | |
226 | else | |
227 | val &= ~WINCONx_ENWIN; | |
228 | ||
229 | writel(val, ctx->regs + WINCON(win)); | |
230 | } | |
231 | ||
999d8b31 YC |
232 | static void fimd_enable_shadow_channel_path(struct fimd_context *ctx, int win, |
233 | bool enable) | |
234 | { | |
235 | u32 val = readl(ctx->regs + SHADOWCON); | |
236 | ||
237 | if (enable) | |
238 | val |= SHADOWCON_CHx_ENABLE(win); | |
239 | else | |
240 | val &= ~SHADOWCON_CHx_ENABLE(win); | |
241 | ||
242 | writel(val, ctx->regs + SHADOWCON); | |
243 | } | |
244 | ||
92dc7a04 | 245 | static void fimd_clear_channel(struct fimd_context *ctx) |
f13bdbd1 | 246 | { |
f13bdbd1 AA |
247 | int win, ch_enabled = 0; |
248 | ||
249 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
250 | ||
251 | /* Check if any channel is enabled. */ | |
252 | for (win = 0; win < WINDOWS_NR; win++) { | |
eb8a3bf7 MS |
253 | u32 val = readl(ctx->regs + WINCON(win)); |
254 | ||
255 | if (val & WINCONx_ENWIN) { | |
f181a543 | 256 | fimd_enable_video_output(ctx, win, false); |
eb8a3bf7 | 257 | |
999d8b31 YC |
258 | if (ctx->driver_data->has_shadowcon) |
259 | fimd_enable_shadow_channel_path(ctx, win, | |
260 | false); | |
261 | ||
f13bdbd1 AA |
262 | ch_enabled = 1; |
263 | } | |
264 | } | |
265 | ||
266 | /* Wait for vsync, as disable channel takes effect at next vsync */ | |
eb8a3bf7 MS |
267 | if (ch_enabled) { |
268 | unsigned int state = ctx->suspended; | |
269 | ||
270 | ctx->suspended = 0; | |
92dc7a04 | 271 | fimd_wait_for_vblank(ctx->crtc); |
eb8a3bf7 MS |
272 | ctx->suspended = state; |
273 | } | |
f13bdbd1 AA |
274 | } |
275 | ||
cdbfca89 | 276 | static int fimd_iommu_attach_devices(struct fimd_context *ctx, |
f37cd5e8 | 277 | struct drm_device *drm_dev) |
40c8ab4b | 278 | { |
40c8ab4b | 279 | |
080be03d | 280 | /* attach this sub driver to iommu mapping if supported. */ |
f13bdbd1 | 281 | if (is_drm_iommu_supported(ctx->drm_dev)) { |
efa75bcd AK |
282 | int ret; |
283 | ||
f13bdbd1 AA |
284 | /* |
285 | * If any channel is already active, iommu will throw | |
286 | * a PAGE FAULT when enabled. So clear any channel if enabled. | |
287 | */ | |
92dc7a04 | 288 | fimd_clear_channel(ctx); |
efa75bcd AK |
289 | ret = drm_iommu_attach_device(ctx->drm_dev, ctx->dev); |
290 | if (ret) { | |
291 | DRM_ERROR("drm_iommu_attach failed.\n"); | |
292 | return ret; | |
293 | } | |
294 | ||
f13bdbd1 | 295 | } |
c32b06ef | 296 | |
080be03d | 297 | return 0; |
ec05da95 ID |
298 | } |
299 | ||
cdbfca89 | 300 | static void fimd_iommu_detach_devices(struct fimd_context *ctx) |
ec05da95 | 301 | { |
080be03d SP |
302 | /* detach this sub driver from iommu mapping if supported. */ |
303 | if (is_drm_iommu_supported(ctx->drm_dev)) | |
304 | drm_iommu_detach_device(ctx->drm_dev, ctx->dev); | |
ec05da95 ID |
305 | } |
306 | ||
a968e727 SP |
307 | static u32 fimd_calc_clkdiv(struct fimd_context *ctx, |
308 | const struct drm_display_mode *mode) | |
309 | { | |
310 | unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh; | |
311 | u32 clkdiv; | |
312 | ||
3854fab2 YC |
313 | if (ctx->i80_if) { |
314 | /* | |
315 | * The frame done interrupt should be occurred prior to the | |
316 | * next TE signal. | |
317 | */ | |
318 | ideal_clk *= 2; | |
319 | } | |
320 | ||
a968e727 SP |
321 | /* Find the clock divider value that gets us closest to ideal_clk */ |
322 | clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk); | |
323 | ||
324 | return (clkdiv < 0x100) ? clkdiv : 0xff; | |
325 | } | |
326 | ||
93bca243 | 327 | static bool fimd_mode_fixup(struct exynos_drm_crtc *crtc, |
a968e727 SP |
328 | const struct drm_display_mode *mode, |
329 | struct drm_display_mode *adjusted_mode) | |
330 | { | |
331 | if (adjusted_mode->vrefresh == 0) | |
332 | adjusted_mode->vrefresh = FIMD_DEFAULT_FRAMERATE; | |
333 | ||
334 | return true; | |
335 | } | |
336 | ||
93bca243 | 337 | static void fimd_commit(struct exynos_drm_crtc *crtc) |
1c248b7d | 338 | { |
93bca243 | 339 | struct fimd_context *ctx = crtc->ctx; |
a8dc5ed6 | 340 | struct drm_display_mode *mode = &crtc->base.mode; |
3854fab2 YC |
341 | struct fimd_driver_data *driver_data = ctx->driver_data; |
342 | void *timing_base = ctx->regs + driver_data->timing_base; | |
343 | u32 val, clkdiv; | |
1c248b7d | 344 | |
e30d4bcf ID |
345 | if (ctx->suspended) |
346 | return; | |
347 | ||
a968e727 SP |
348 | /* nothing to do if we haven't set the mode yet */ |
349 | if (mode->htotal == 0 || mode->vtotal == 0) | |
350 | return; | |
351 | ||
3854fab2 YC |
352 | if (ctx->i80_if) { |
353 | val = ctx->i80ifcon | I80IFEN_ENABLE; | |
354 | writel(val, timing_base + I80IFCONFAx(0)); | |
355 | ||
356 | /* disable auto frame rate */ | |
357 | writel(0, timing_base + I80IFCONFBx(0)); | |
358 | ||
359 | /* set video type selection to I80 interface */ | |
3c3c9c1d JS |
360 | if (driver_data->has_vtsel && ctx->sysreg && |
361 | regmap_update_bits(ctx->sysreg, | |
3854fab2 YC |
362 | driver_data->lcdblk_offset, |
363 | 0x3 << driver_data->lcdblk_vt_shift, | |
364 | 0x1 << driver_data->lcdblk_vt_shift)) { | |
365 | DRM_ERROR("Failed to update sysreg for I80 i/f.\n"); | |
366 | return; | |
367 | } | |
368 | } else { | |
369 | int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd; | |
370 | u32 vidcon1; | |
371 | ||
372 | /* setup polarity values */ | |
373 | vidcon1 = ctx->vidcon1; | |
374 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
375 | vidcon1 |= VIDCON1_INV_VSYNC; | |
376 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
377 | vidcon1 |= VIDCON1_INV_HSYNC; | |
378 | writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1); | |
379 | ||
380 | /* setup vertical timing values. */ | |
381 | vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; | |
382 | vbpd = mode->crtc_vtotal - mode->crtc_vsync_end; | |
383 | vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay; | |
384 | ||
385 | val = VIDTCON0_VBPD(vbpd - 1) | | |
386 | VIDTCON0_VFPD(vfpd - 1) | | |
387 | VIDTCON0_VSPW(vsync_len - 1); | |
388 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON0); | |
389 | ||
390 | /* setup horizontal timing values. */ | |
391 | hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; | |
392 | hbpd = mode->crtc_htotal - mode->crtc_hsync_end; | |
393 | hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay; | |
394 | ||
395 | val = VIDTCON1_HBPD(hbpd - 1) | | |
396 | VIDTCON1_HFPD(hfpd - 1) | | |
397 | VIDTCON1_HSPW(hsync_len - 1); | |
398 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON1); | |
399 | } | |
400 | ||
401 | if (driver_data->has_vidoutcon) | |
402 | writel(ctx->vidout_con, timing_base + VIDOUT_CON); | |
403 | ||
404 | /* set bypass selection */ | |
405 | if (ctx->sysreg && regmap_update_bits(ctx->sysreg, | |
406 | driver_data->lcdblk_offset, | |
407 | 0x1 << driver_data->lcdblk_bypass_shift, | |
408 | 0x1 << driver_data->lcdblk_bypass_shift)) { | |
409 | DRM_ERROR("Failed to update sysreg for bypass setting.\n"); | |
410 | return; | |
411 | } | |
1c248b7d ID |
412 | |
413 | /* setup horizontal and vertical display size. */ | |
a968e727 SP |
414 | val = VIDTCON2_LINEVAL(mode->vdisplay - 1) | |
415 | VIDTCON2_HOZVAL(mode->hdisplay - 1) | | |
416 | VIDTCON2_LINEVAL_E(mode->vdisplay - 1) | | |
417 | VIDTCON2_HOZVAL_E(mode->hdisplay - 1); | |
e2e13389 | 418 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON2); |
1c248b7d | 419 | |
1d531062 AH |
420 | /* |
421 | * fields of register with prefix '_F' would be updated | |
422 | * at vsync(same as dma start) | |
423 | */ | |
3854fab2 YC |
424 | val = ctx->vidcon0; |
425 | val |= VIDCON0_ENVID | VIDCON0_ENVID_F; | |
1c248b7d | 426 | |
1d531062 | 427 | if (ctx->driver_data->has_clksel) |
411d9ed4 | 428 | val |= VIDCON0_CLKSEL_LCD; |
411d9ed4 | 429 | |
a968e727 SP |
430 | clkdiv = fimd_calc_clkdiv(ctx, mode); |
431 | if (clkdiv > 1) | |
432 | val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR; | |
1c248b7d | 433 | |
1c248b7d ID |
434 | writel(val, ctx->regs + VIDCON0); |
435 | } | |
436 | ||
93bca243 | 437 | static int fimd_enable_vblank(struct exynos_drm_crtc *crtc) |
1c248b7d | 438 | { |
93bca243 | 439 | struct fimd_context *ctx = crtc->ctx; |
1c248b7d ID |
440 | u32 val; |
441 | ||
cb91f6a0 JS |
442 | if (ctx->suspended) |
443 | return -EPERM; | |
444 | ||
1c248b7d ID |
445 | if (!test_and_set_bit(0, &ctx->irq_flags)) { |
446 | val = readl(ctx->regs + VIDINTCON0); | |
447 | ||
448 | val |= VIDINTCON0_INT_ENABLE; | |
1c248b7d | 449 | |
1c905d95 YC |
450 | if (ctx->i80_if) { |
451 | val |= VIDINTCON0_INT_I80IFDONE; | |
452 | val |= VIDINTCON0_INT_SYSMAINCON; | |
453 | val &= ~VIDINTCON0_INT_SYSSUBCON; | |
454 | } else { | |
455 | val |= VIDINTCON0_INT_FRAME; | |
456 | ||
457 | val &= ~VIDINTCON0_FRAMESEL0_MASK; | |
458 | val |= VIDINTCON0_FRAMESEL0_VSYNC; | |
459 | val &= ~VIDINTCON0_FRAMESEL1_MASK; | |
460 | val |= VIDINTCON0_FRAMESEL1_NONE; | |
461 | } | |
1c248b7d ID |
462 | |
463 | writel(val, ctx->regs + VIDINTCON0); | |
464 | } | |
465 | ||
466 | return 0; | |
467 | } | |
468 | ||
93bca243 | 469 | static void fimd_disable_vblank(struct exynos_drm_crtc *crtc) |
1c248b7d | 470 | { |
93bca243 | 471 | struct fimd_context *ctx = crtc->ctx; |
1c248b7d ID |
472 | u32 val; |
473 | ||
cb91f6a0 JS |
474 | if (ctx->suspended) |
475 | return; | |
476 | ||
1c248b7d ID |
477 | if (test_and_clear_bit(0, &ctx->irq_flags)) { |
478 | val = readl(ctx->regs + VIDINTCON0); | |
479 | ||
1c248b7d ID |
480 | val &= ~VIDINTCON0_INT_ENABLE; |
481 | ||
1c905d95 YC |
482 | if (ctx->i80_if) { |
483 | val &= ~VIDINTCON0_INT_I80IFDONE; | |
484 | val &= ~VIDINTCON0_INT_SYSMAINCON; | |
485 | val &= ~VIDINTCON0_INT_SYSSUBCON; | |
486 | } else | |
487 | val &= ~VIDINTCON0_INT_FRAME; | |
488 | ||
1c248b7d ID |
489 | writel(val, ctx->regs + VIDINTCON0); |
490 | } | |
491 | } | |
492 | ||
bb7704d6 | 493 | static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win) |
1c248b7d | 494 | { |
7ee14cdc | 495 | struct exynos_drm_plane *plane = &ctx->planes[win]; |
1c248b7d ID |
496 | unsigned long val; |
497 | ||
1c248b7d ID |
498 | val = WINCONx_ENWIN; |
499 | ||
5cc4621a ID |
500 | /* |
501 | * In case of s3c64xx, window 0 doesn't support alpha channel. | |
502 | * So the request format is ARGB8888 then change it to XRGB8888. | |
503 | */ | |
504 | if (ctx->driver_data->has_limited_fmt && !win) { | |
7ee14cdc GP |
505 | if (plane->pixel_format == DRM_FORMAT_ARGB8888) |
506 | plane->pixel_format = DRM_FORMAT_XRGB8888; | |
5cc4621a ID |
507 | } |
508 | ||
7ee14cdc | 509 | switch (plane->pixel_format) { |
a4f38a80 | 510 | case DRM_FORMAT_C8: |
1c248b7d ID |
511 | val |= WINCON0_BPPMODE_8BPP_PALETTE; |
512 | val |= WINCONx_BURSTLEN_8WORD; | |
513 | val |= WINCONx_BYTSWP; | |
514 | break; | |
a4f38a80 ID |
515 | case DRM_FORMAT_XRGB1555: |
516 | val |= WINCON0_BPPMODE_16BPP_1555; | |
517 | val |= WINCONx_HAWSWP; | |
518 | val |= WINCONx_BURSTLEN_16WORD; | |
519 | break; | |
520 | case DRM_FORMAT_RGB565: | |
1c248b7d ID |
521 | val |= WINCON0_BPPMODE_16BPP_565; |
522 | val |= WINCONx_HAWSWP; | |
523 | val |= WINCONx_BURSTLEN_16WORD; | |
524 | break; | |
a4f38a80 | 525 | case DRM_FORMAT_XRGB8888: |
1c248b7d ID |
526 | val |= WINCON0_BPPMODE_24BPP_888; |
527 | val |= WINCONx_WSWP; | |
528 | val |= WINCONx_BURSTLEN_16WORD; | |
529 | break; | |
a4f38a80 ID |
530 | case DRM_FORMAT_ARGB8888: |
531 | val |= WINCON1_BPPMODE_25BPP_A1888 | |
1c248b7d ID |
532 | | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL; |
533 | val |= WINCONx_WSWP; | |
534 | val |= WINCONx_BURSTLEN_16WORD; | |
535 | break; | |
536 | default: | |
537 | DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n"); | |
538 | ||
539 | val |= WINCON0_BPPMODE_24BPP_888; | |
540 | val |= WINCONx_WSWP; | |
541 | val |= WINCONx_BURSTLEN_16WORD; | |
542 | break; | |
543 | } | |
544 | ||
7ee14cdc | 545 | DRM_DEBUG_KMS("bpp = %d\n", plane->bpp); |
1c248b7d | 546 | |
66367461 RS |
547 | /* |
548 | * In case of exynos, setting dma-burst to 16Word causes permanent | |
549 | * tearing for very small buffers, e.g. cursor buffer. Burst Mode | |
8837deea GP |
550 | * switching which is based on plane size is not recommended as |
551 | * plane size varies alot towards the end of the screen and rapid | |
66367461 RS |
552 | * movement causes unstable DMA which results into iommu crash/tear. |
553 | */ | |
554 | ||
7ee14cdc | 555 | if (plane->fb_width < MIN_FB_WIDTH_FOR_16WORD_BURST) { |
66367461 RS |
556 | val &= ~WINCONx_BURSTLEN_MASK; |
557 | val |= WINCONx_BURSTLEN_4WORD; | |
558 | } | |
559 | ||
1c248b7d | 560 | writel(val, ctx->regs + WINCON(win)); |
453b44a3 GP |
561 | |
562 | /* hardware window 0 doesn't support alpha channel. */ | |
563 | if (win != 0) { | |
564 | /* OSD alpha */ | |
565 | val = VIDISD14C_ALPHA0_R(0xf) | | |
566 | VIDISD14C_ALPHA0_G(0xf) | | |
567 | VIDISD14C_ALPHA0_B(0xf) | | |
568 | VIDISD14C_ALPHA1_R(0xf) | | |
569 | VIDISD14C_ALPHA1_G(0xf) | | |
570 | VIDISD14C_ALPHA1_B(0xf); | |
571 | ||
572 | writel(val, ctx->regs + VIDOSD_C(win)); | |
573 | ||
574 | val = VIDW_ALPHA_R(0xf) | VIDW_ALPHA_G(0xf) | | |
575 | VIDW_ALPHA_G(0xf); | |
576 | writel(val, ctx->regs + VIDWnALPHA0(win)); | |
577 | writel(val, ctx->regs + VIDWnALPHA1(win)); | |
578 | } | |
1c248b7d ID |
579 | } |
580 | ||
bb7704d6 | 581 | static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win) |
1c248b7d | 582 | { |
1c248b7d ID |
583 | unsigned int keycon0 = 0, keycon1 = 0; |
584 | ||
1c248b7d ID |
585 | keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F | |
586 | WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); | |
587 | ||
588 | keycon1 = WxKEYCON1_COLVAL(0xffffffff); | |
589 | ||
590 | writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); | |
591 | writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); | |
592 | } | |
593 | ||
de7af100 TF |
594 | /** |
595 | * shadow_protect_win() - disable updating values from shadow registers at vsync | |
596 | * | |
597 | * @win: window to protect registers for | |
598 | * @protect: 1 to protect (disable updates) | |
599 | */ | |
600 | static void fimd_shadow_protect_win(struct fimd_context *ctx, | |
6e2a3b66 | 601 | unsigned int win, bool protect) |
de7af100 TF |
602 | { |
603 | u32 reg, bits, val; | |
604 | ||
605 | if (ctx->driver_data->has_shadowcon) { | |
606 | reg = SHADOWCON; | |
607 | bits = SHADOWCON_WINx_PROTECT(win); | |
608 | } else { | |
609 | reg = PRTCON; | |
610 | bits = PRTCON_PROTECT; | |
611 | } | |
612 | ||
613 | val = readl(ctx->regs + reg); | |
614 | if (protect) | |
615 | val |= bits; | |
616 | else | |
617 | val &= ~bits; | |
618 | writel(val, ctx->regs + reg); | |
619 | } | |
620 | ||
6e2a3b66 | 621 | static void fimd_win_commit(struct exynos_drm_crtc *crtc, unsigned int win) |
1c248b7d | 622 | { |
93bca243 | 623 | struct fimd_context *ctx = crtc->ctx; |
7ee14cdc | 624 | struct exynos_drm_plane *plane; |
7ee14cdc GP |
625 | dma_addr_t dma_addr; |
626 | unsigned long val, size, offset; | |
627 | unsigned int last_x, last_y, buf_offsize, line_size; | |
1c248b7d | 628 | |
e30d4bcf ID |
629 | if (ctx->suspended) |
630 | return; | |
631 | ||
37b006e8 | 632 | if (win < 0 || win >= WINDOWS_NR) |
1c248b7d ID |
633 | return; |
634 | ||
7ee14cdc | 635 | plane = &ctx->planes[win]; |
1c248b7d | 636 | |
a43b933b SP |
637 | /* If suspended, enable this on resume */ |
638 | if (ctx->suspended) { | |
7ee14cdc | 639 | plane->resume = true; |
a43b933b SP |
640 | return; |
641 | } | |
642 | ||
1c248b7d | 643 | /* |
de7af100 | 644 | * SHADOWCON/PRTCON register is used for enabling timing. |
1c248b7d ID |
645 | * |
646 | * for example, once only width value of a register is set, | |
647 | * if the dma is started then fimd hardware could malfunction so | |
648 | * with protect window setting, the register fields with prefix '_F' | |
649 | * wouldn't be updated at vsync also but updated once unprotect window | |
650 | * is set. | |
651 | */ | |
652 | ||
653 | /* protect windows */ | |
de7af100 | 654 | fimd_shadow_protect_win(ctx, win, true); |
1c248b7d | 655 | |
7ee14cdc | 656 | |
cb8a3db2 JS |
657 | offset = plane->src_x * (plane->bpp >> 3); |
658 | offset += plane->src_y * plane->pitch; | |
7ee14cdc | 659 | |
1c248b7d | 660 | /* buffer start address */ |
7ee14cdc GP |
661 | dma_addr = plane->dma_addr[0] + offset; |
662 | val = (unsigned long)dma_addr; | |
1c248b7d ID |
663 | writel(val, ctx->regs + VIDWx_BUF_START(win, 0)); |
664 | ||
665 | /* buffer end address */ | |
68a29134 | 666 | size = plane->pitch * plane->crtc_height; |
7ee14cdc | 667 | val = (unsigned long)(dma_addr + size); |
1c248b7d ID |
668 | writel(val, ctx->regs + VIDWx_BUF_END(win, 0)); |
669 | ||
670 | DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n", | |
7ee14cdc | 671 | (unsigned long)dma_addr, val, size); |
19c8b834 | 672 | DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", |
7ee14cdc | 673 | plane->crtc_width, plane->crtc_height); |
1c248b7d ID |
674 | |
675 | /* buffer size */ | |
68a29134 | 676 | buf_offsize = plane->pitch - (plane->crtc_width * (plane->bpp >> 3)); |
7ee14cdc GP |
677 | line_size = plane->crtc_width * (plane->bpp >> 3); |
678 | val = VIDW_BUF_SIZE_OFFSET(buf_offsize) | | |
679 | VIDW_BUF_SIZE_PAGEWIDTH(line_size) | | |
680 | VIDW_BUF_SIZE_OFFSET_E(buf_offsize) | | |
681 | VIDW_BUF_SIZE_PAGEWIDTH_E(line_size); | |
1c248b7d ID |
682 | writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0)); |
683 | ||
684 | /* OSD position */ | |
7ee14cdc GP |
685 | val = VIDOSDxA_TOPLEFT_X(plane->crtc_x) | |
686 | VIDOSDxA_TOPLEFT_Y(plane->crtc_y) | | |
687 | VIDOSDxA_TOPLEFT_X_E(plane->crtc_x) | | |
688 | VIDOSDxA_TOPLEFT_Y_E(plane->crtc_y); | |
1c248b7d ID |
689 | writel(val, ctx->regs + VIDOSD_A(win)); |
690 | ||
7ee14cdc | 691 | last_x = plane->crtc_x + plane->crtc_width; |
f56aad3a JS |
692 | if (last_x) |
693 | last_x--; | |
7ee14cdc | 694 | last_y = plane->crtc_y + plane->crtc_height; |
f56aad3a JS |
695 | if (last_y) |
696 | last_y--; | |
697 | ||
ca555e5a JS |
698 | val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) | |
699 | VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y); | |
700 | ||
1c248b7d ID |
701 | writel(val, ctx->regs + VIDOSD_B(win)); |
702 | ||
19c8b834 | 703 | DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", |
7ee14cdc | 704 | plane->crtc_x, plane->crtc_y, last_x, last_y); |
1c248b7d | 705 | |
1c248b7d ID |
706 | /* OSD size */ |
707 | if (win != 3 && win != 4) { | |
708 | u32 offset = VIDOSD_D(win); | |
709 | if (win == 0) | |
0f10cf14 | 710 | offset = VIDOSD_C(win); |
7ee14cdc | 711 | val = plane->crtc_width * plane->crtc_height; |
1c248b7d ID |
712 | writel(val, ctx->regs + offset); |
713 | ||
714 | DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val); | |
715 | } | |
716 | ||
bb7704d6 | 717 | fimd_win_set_pixfmt(ctx, win); |
1c248b7d ID |
718 | |
719 | /* hardware window 0 doesn't support color key. */ | |
720 | if (win != 0) | |
bb7704d6 | 721 | fimd_win_set_colkey(ctx, win); |
1c248b7d | 722 | |
f181a543 | 723 | fimd_enable_video_output(ctx, win, true); |
ec05da95 | 724 | |
999d8b31 YC |
725 | if (ctx->driver_data->has_shadowcon) |
726 | fimd_enable_shadow_channel_path(ctx, win, true); | |
ec05da95 | 727 | |
74944a58 YC |
728 | /* Enable DMA channel and unprotect windows */ |
729 | fimd_shadow_protect_win(ctx, win, false); | |
730 | ||
7ee14cdc | 731 | plane->enabled = true; |
3854fab2 YC |
732 | |
733 | if (ctx->i80_if) | |
734 | atomic_set(&ctx->win_updated, 1); | |
1c248b7d ID |
735 | } |
736 | ||
6e2a3b66 | 737 | static void fimd_win_disable(struct exynos_drm_crtc *crtc, unsigned int win) |
1c248b7d | 738 | { |
93bca243 | 739 | struct fimd_context *ctx = crtc->ctx; |
7ee14cdc | 740 | struct exynos_drm_plane *plane; |
864ee9e6 | 741 | |
37b006e8 | 742 | if (win < 0 || win >= WINDOWS_NR) |
1c248b7d ID |
743 | return; |
744 | ||
7ee14cdc | 745 | plane = &ctx->planes[win]; |
ec05da95 | 746 | |
db7e55ae P |
747 | if (ctx->suspended) { |
748 | /* do not resume this window*/ | |
7ee14cdc | 749 | plane->resume = false; |
db7e55ae P |
750 | return; |
751 | } | |
752 | ||
1c248b7d | 753 | /* protect windows */ |
de7af100 | 754 | fimd_shadow_protect_win(ctx, win, true); |
1c248b7d | 755 | |
f181a543 | 756 | fimd_enable_video_output(ctx, win, false); |
1c248b7d | 757 | |
999d8b31 YC |
758 | if (ctx->driver_data->has_shadowcon) |
759 | fimd_enable_shadow_channel_path(ctx, win, false); | |
de7af100 | 760 | |
999d8b31 | 761 | /* unprotect windows */ |
de7af100 | 762 | fimd_shadow_protect_win(ctx, win, false); |
ec05da95 | 763 | |
7ee14cdc | 764 | plane->enabled = false; |
1c248b7d ID |
765 | } |
766 | ||
92dc7a04 | 767 | static void fimd_window_suspend(struct fimd_context *ctx) |
a43b933b | 768 | { |
7ee14cdc | 769 | struct exynos_drm_plane *plane; |
a43b933b SP |
770 | int i; |
771 | ||
772 | for (i = 0; i < WINDOWS_NR; i++) { | |
7ee14cdc GP |
773 | plane = &ctx->planes[i]; |
774 | plane->resume = plane->enabled; | |
775 | if (plane->enabled) | |
92dc7a04 | 776 | fimd_win_disable(ctx->crtc, i); |
a43b933b | 777 | } |
a43b933b SP |
778 | } |
779 | ||
92dc7a04 | 780 | static void fimd_window_resume(struct fimd_context *ctx) |
a43b933b | 781 | { |
7ee14cdc | 782 | struct exynos_drm_plane *plane; |
a43b933b SP |
783 | int i; |
784 | ||
785 | for (i = 0; i < WINDOWS_NR; i++) { | |
7ee14cdc GP |
786 | plane = &ctx->planes[i]; |
787 | plane->enabled = plane->resume; | |
788 | plane->resume = false; | |
a43b933b SP |
789 | } |
790 | } | |
791 | ||
92dc7a04 | 792 | static void fimd_apply(struct fimd_context *ctx) |
a43b933b | 793 | { |
7ee14cdc | 794 | struct exynos_drm_plane *plane; |
a43b933b SP |
795 | int i; |
796 | ||
797 | for (i = 0; i < WINDOWS_NR; i++) { | |
7ee14cdc GP |
798 | plane = &ctx->planes[i]; |
799 | if (plane->enabled) | |
92dc7a04 | 800 | fimd_win_commit(ctx->crtc, i); |
d9b68d89 | 801 | else |
92dc7a04 | 802 | fimd_win_disable(ctx->crtc, i); |
a43b933b SP |
803 | } |
804 | ||
92dc7a04 | 805 | fimd_commit(ctx->crtc); |
a43b933b SP |
806 | } |
807 | ||
92dc7a04 | 808 | static int fimd_poweron(struct fimd_context *ctx) |
a43b933b | 809 | { |
a43b933b SP |
810 | int ret; |
811 | ||
812 | if (!ctx->suspended) | |
813 | return 0; | |
814 | ||
815 | ctx->suspended = false; | |
816 | ||
af65c804 SP |
817 | pm_runtime_get_sync(ctx->dev); |
818 | ||
a43b933b SP |
819 | ret = clk_prepare_enable(ctx->bus_clk); |
820 | if (ret < 0) { | |
821 | DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret); | |
822 | goto bus_clk_err; | |
823 | } | |
824 | ||
825 | ret = clk_prepare_enable(ctx->lcd_clk); | |
826 | if (ret < 0) { | |
827 | DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret); | |
828 | goto lcd_clk_err; | |
829 | } | |
830 | ||
831 | /* if vblank was enabled status, enable it again. */ | |
832 | if (test_and_clear_bit(0, &ctx->irq_flags)) { | |
92dc7a04 | 833 | ret = fimd_enable_vblank(ctx->crtc); |
a43b933b SP |
834 | if (ret) { |
835 | DRM_ERROR("Failed to re-enable vblank [%d]\n", ret); | |
836 | goto enable_vblank_err; | |
837 | } | |
838 | } | |
839 | ||
92dc7a04 | 840 | fimd_window_resume(ctx); |
a43b933b | 841 | |
92dc7a04 | 842 | fimd_apply(ctx); |
a43b933b SP |
843 | |
844 | return 0; | |
845 | ||
846 | enable_vblank_err: | |
847 | clk_disable_unprepare(ctx->lcd_clk); | |
848 | lcd_clk_err: | |
849 | clk_disable_unprepare(ctx->bus_clk); | |
850 | bus_clk_err: | |
851 | ctx->suspended = true; | |
852 | return ret; | |
853 | } | |
854 | ||
92dc7a04 | 855 | static int fimd_poweroff(struct fimd_context *ctx) |
a43b933b | 856 | { |
a43b933b SP |
857 | if (ctx->suspended) |
858 | return 0; | |
859 | ||
860 | /* | |
861 | * We need to make sure that all windows are disabled before we | |
862 | * suspend that connector. Otherwise we might try to scan from | |
863 | * a destroyed buffer later. | |
864 | */ | |
92dc7a04 | 865 | fimd_window_suspend(ctx); |
a43b933b SP |
866 | |
867 | clk_disable_unprepare(ctx->lcd_clk); | |
868 | clk_disable_unprepare(ctx->bus_clk); | |
869 | ||
af65c804 SP |
870 | pm_runtime_put_sync(ctx->dev); |
871 | ||
a43b933b SP |
872 | ctx->suspended = true; |
873 | return 0; | |
874 | } | |
875 | ||
93bca243 | 876 | static void fimd_dpms(struct exynos_drm_crtc *crtc, int mode) |
080be03d | 877 | { |
af65c804 | 878 | DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode); |
080be03d | 879 | |
080be03d SP |
880 | switch (mode) { |
881 | case DRM_MODE_DPMS_ON: | |
92dc7a04 | 882 | fimd_poweron(crtc->ctx); |
080be03d SP |
883 | break; |
884 | case DRM_MODE_DPMS_STANDBY: | |
885 | case DRM_MODE_DPMS_SUSPEND: | |
886 | case DRM_MODE_DPMS_OFF: | |
92dc7a04 | 887 | fimd_poweroff(crtc->ctx); |
080be03d SP |
888 | break; |
889 | default: | |
890 | DRM_DEBUG_KMS("unspecified mode %d\n", mode); | |
891 | break; | |
892 | } | |
080be03d SP |
893 | } |
894 | ||
3854fab2 YC |
895 | static void fimd_trigger(struct device *dev) |
896 | { | |
e152dbd7 | 897 | struct fimd_context *ctx = dev_get_drvdata(dev); |
3854fab2 YC |
898 | struct fimd_driver_data *driver_data = ctx->driver_data; |
899 | void *timing_base = ctx->regs + driver_data->timing_base; | |
900 | u32 reg; | |
901 | ||
9b67eb73 | 902 | /* |
1c905d95 YC |
903 | * Skips triggering if in triggering state, because multiple triggering |
904 | * requests can cause panel reset. | |
905 | */ | |
9b67eb73 JS |
906 | if (atomic_read(&ctx->triggering)) |
907 | return; | |
908 | ||
1c905d95 | 909 | /* Enters triggering mode */ |
3854fab2 YC |
910 | atomic_set(&ctx->triggering, 1); |
911 | ||
3854fab2 YC |
912 | reg = readl(timing_base + TRIGCON); |
913 | reg |= (TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE); | |
914 | writel(reg, timing_base + TRIGCON); | |
87ab85b3 YC |
915 | |
916 | /* | |
917 | * Exits triggering mode if vblank is not enabled yet, because when the | |
918 | * VIDINTCON0 register is not set, it can not exit from triggering mode. | |
919 | */ | |
920 | if (!test_bit(0, &ctx->irq_flags)) | |
921 | atomic_set(&ctx->triggering, 0); | |
3854fab2 YC |
922 | } |
923 | ||
93bca243 | 924 | static void fimd_te_handler(struct exynos_drm_crtc *crtc) |
3854fab2 | 925 | { |
93bca243 | 926 | struct fimd_context *ctx = crtc->ctx; |
3854fab2 YC |
927 | |
928 | /* Checks the crtc is detached already from encoder */ | |
929 | if (ctx->pipe < 0 || !ctx->drm_dev) | |
930 | return; | |
931 | ||
3854fab2 YC |
932 | /* |
933 | * If there is a page flip request, triggers and handles the page flip | |
934 | * event so that current fb can be updated into panel GRAM. | |
935 | */ | |
936 | if (atomic_add_unless(&ctx->win_updated, -1, 0)) | |
937 | fimd_trigger(ctx->dev); | |
938 | ||
939 | /* Wakes up vsync event queue */ | |
940 | if (atomic_read(&ctx->wait_vsync_event)) { | |
941 | atomic_set(&ctx->wait_vsync_event, 0); | |
942 | wake_up(&ctx->wait_vsync_queue); | |
3854fab2 | 943 | } |
b301ae24 | 944 | |
adf67abf | 945 | if (test_bit(0, &ctx->irq_flags)) |
b301ae24 | 946 | drm_handle_vblank(ctx->drm_dev, ctx->pipe); |
3854fab2 YC |
947 | } |
948 | ||
93bca243 | 949 | static struct exynos_drm_crtc_ops fimd_crtc_ops = { |
1c6244c3 | 950 | .dpms = fimd_dpms, |
a968e727 | 951 | .mode_fixup = fimd_mode_fixup, |
1c6244c3 SP |
952 | .commit = fimd_commit, |
953 | .enable_vblank = fimd_enable_vblank, | |
954 | .disable_vblank = fimd_disable_vblank, | |
955 | .wait_for_vblank = fimd_wait_for_vblank, | |
1c6244c3 SP |
956 | .win_commit = fimd_win_commit, |
957 | .win_disable = fimd_win_disable, | |
3854fab2 | 958 | .te_handler = fimd_te_handler, |
1c248b7d ID |
959 | }; |
960 | ||
1c248b7d ID |
961 | static irqreturn_t fimd_irq_handler(int irq, void *dev_id) |
962 | { | |
963 | struct fimd_context *ctx = (struct fimd_context *)dev_id; | |
3854fab2 | 964 | u32 val, clear_bit; |
1c248b7d ID |
965 | |
966 | val = readl(ctx->regs + VIDINTCON1); | |
967 | ||
3854fab2 YC |
968 | clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME; |
969 | if (val & clear_bit) | |
970 | writel(clear_bit, ctx->regs + VIDINTCON1); | |
1c248b7d | 971 | |
ec05da95 | 972 | /* check the crtc is detached already from encoder */ |
080be03d | 973 | if (ctx->pipe < 0 || !ctx->drm_dev) |
ec05da95 | 974 | goto out; |
483b88f8 | 975 | |
1c905d95 | 976 | if (ctx->i80_if) { |
adf67abf JS |
977 | exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe); |
978 | ||
1c905d95 | 979 | /* Exits triggering mode */ |
3854fab2 | 980 | atomic_set(&ctx->triggering, 0); |
3854fab2 | 981 | } else { |
adf67abf JS |
982 | drm_handle_vblank(ctx->drm_dev, ctx->pipe); |
983 | exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe); | |
984 | ||
3854fab2 YC |
985 | /* set wait vsync event to zero and wake up queue. */ |
986 | if (atomic_read(&ctx->wait_vsync_event)) { | |
987 | atomic_set(&ctx->wait_vsync_event, 0); | |
988 | wake_up(&ctx->wait_vsync_queue); | |
989 | } | |
01ce113c | 990 | } |
3854fab2 | 991 | |
ec05da95 | 992 | out: |
1c248b7d ID |
993 | return IRQ_HANDLED; |
994 | } | |
995 | ||
f37cd5e8 | 996 | static int fimd_bind(struct device *dev, struct device *master, void *data) |
562ad9f4 | 997 | { |
e152dbd7 | 998 | struct fimd_context *ctx = dev_get_drvdata(dev); |
f37cd5e8 | 999 | struct drm_device *drm_dev = data; |
cdbfca89 | 1000 | struct exynos_drm_private *priv = drm_dev->dev_private; |
7ee14cdc GP |
1001 | struct exynos_drm_plane *exynos_plane; |
1002 | enum drm_plane_type type; | |
6e2a3b66 GP |
1003 | unsigned int zpos; |
1004 | int ret; | |
000cc920 | 1005 | |
cdbfca89 HH |
1006 | ctx->drm_dev = drm_dev; |
1007 | ctx->pipe = priv->pipe++; | |
efa75bcd | 1008 | |
7ee14cdc GP |
1009 | for (zpos = 0; zpos < WINDOWS_NR; zpos++) { |
1010 | type = (zpos == ctx->default_win) ? DRM_PLANE_TYPE_PRIMARY : | |
1011 | DRM_PLANE_TYPE_OVERLAY; | |
1012 | ret = exynos_plane_init(drm_dev, &ctx->planes[zpos], | |
6e2a3b66 | 1013 | 1 << ctx->pipe, type, zpos); |
7ee14cdc GP |
1014 | if (ret) |
1015 | return ret; | |
1016 | } | |
1017 | ||
1018 | exynos_plane = &ctx->planes[ctx->default_win]; | |
1019 | ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, | |
1020 | ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD, | |
0f04cf8d | 1021 | &fimd_crtc_ops, ctx); |
d1222842 HH |
1022 | if (IS_ERR(ctx->crtc)) |
1023 | return PTR_ERR(ctx->crtc); | |
93bca243 | 1024 | |
000cc920 AH |
1025 | if (ctx->display) |
1026 | exynos_drm_create_enc_conn(drm_dev, ctx->display); | |
1027 | ||
cdbfca89 HH |
1028 | ret = fimd_iommu_attach_devices(ctx, drm_dev); |
1029 | if (ret) | |
1030 | return ret; | |
1031 | ||
000cc920 AH |
1032 | return 0; |
1033 | ||
1034 | } | |
1035 | ||
1036 | static void fimd_unbind(struct device *dev, struct device *master, | |
1037 | void *data) | |
1038 | { | |
e152dbd7 | 1039 | struct fimd_context *ctx = dev_get_drvdata(dev); |
000cc920 | 1040 | |
93bca243 | 1041 | fimd_dpms(ctx->crtc, DRM_MODE_DPMS_OFF); |
000cc920 | 1042 | |
cdbfca89 HH |
1043 | fimd_iommu_detach_devices(ctx); |
1044 | ||
000cc920 | 1045 | if (ctx->display) |
4cfde1f2 | 1046 | exynos_dpi_remove(ctx->display); |
000cc920 AH |
1047 | } |
1048 | ||
1049 | static const struct component_ops fimd_component_ops = { | |
1050 | .bind = fimd_bind, | |
1051 | .unbind = fimd_unbind, | |
1052 | }; | |
1053 | ||
1054 | static int fimd_probe(struct platform_device *pdev) | |
1055 | { | |
1056 | struct device *dev = &pdev->dev; | |
562ad9f4 | 1057 | struct fimd_context *ctx; |
3854fab2 | 1058 | struct device_node *i80_if_timings; |
562ad9f4 | 1059 | struct resource *res; |
fe42cfb4 | 1060 | int ret; |
1c248b7d | 1061 | |
e152dbd7 AH |
1062 | if (!dev->of_node) |
1063 | return -ENODEV; | |
2d3f173c | 1064 | |
d873ab99 | 1065 | ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); |
e152dbd7 AH |
1066 | if (!ctx) |
1067 | return -ENOMEM; | |
1068 | ||
e152dbd7 | 1069 | ret = exynos_drm_component_add(dev, EXYNOS_DEVICE_TYPE_CRTC, |
5d1741ad | 1070 | EXYNOS_DISPLAY_TYPE_LCD); |
e152dbd7 AH |
1071 | if (ret) |
1072 | return ret; | |
1c248b7d | 1073 | |
bb7704d6 | 1074 | ctx->dev = dev; |
a43b933b | 1075 | ctx->suspended = true; |
3854fab2 | 1076 | ctx->driver_data = drm_fimd_get_driver_data(pdev); |
bb7704d6 | 1077 | |
1417f109 SP |
1078 | if (of_property_read_bool(dev->of_node, "samsung,invert-vden")) |
1079 | ctx->vidcon1 |= VIDCON1_INV_VDEN; | |
1080 | if (of_property_read_bool(dev->of_node, "samsung,invert-vclk")) | |
1081 | ctx->vidcon1 |= VIDCON1_INV_VCLK; | |
562ad9f4 | 1082 | |
3854fab2 YC |
1083 | i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings"); |
1084 | if (i80_if_timings) { | |
1085 | u32 val; | |
1086 | ||
1087 | ctx->i80_if = true; | |
1088 | ||
1089 | if (ctx->driver_data->has_vidoutcon) | |
1090 | ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0; | |
1091 | else | |
1092 | ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0; | |
1093 | /* | |
1094 | * The user manual describes that this "DSI_EN" bit is required | |
1095 | * to enable I80 24-bit data interface. | |
1096 | */ | |
1097 | ctx->vidcon0 |= VIDCON0_DSI_EN; | |
1098 | ||
1099 | if (of_property_read_u32(i80_if_timings, "cs-setup", &val)) | |
1100 | val = 0; | |
1101 | ctx->i80ifcon = LCD_CS_SETUP(val); | |
1102 | if (of_property_read_u32(i80_if_timings, "wr-setup", &val)) | |
1103 | val = 0; | |
1104 | ctx->i80ifcon |= LCD_WR_SETUP(val); | |
1105 | if (of_property_read_u32(i80_if_timings, "wr-active", &val)) | |
1106 | val = 1; | |
1107 | ctx->i80ifcon |= LCD_WR_ACTIVE(val); | |
1108 | if (of_property_read_u32(i80_if_timings, "wr-hold", &val)) | |
1109 | val = 0; | |
1110 | ctx->i80ifcon |= LCD_WR_HOLD(val); | |
1111 | } | |
1112 | of_node_put(i80_if_timings); | |
1113 | ||
1114 | ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node, | |
1115 | "samsung,sysreg"); | |
1116 | if (IS_ERR(ctx->sysreg)) { | |
1117 | dev_warn(dev, "failed to get system register.\n"); | |
1118 | ctx->sysreg = NULL; | |
1119 | } | |
1120 | ||
a968e727 SP |
1121 | ctx->bus_clk = devm_clk_get(dev, "fimd"); |
1122 | if (IS_ERR(ctx->bus_clk)) { | |
1123 | dev_err(dev, "failed to get bus clock\n"); | |
df5225bc ID |
1124 | ret = PTR_ERR(ctx->bus_clk); |
1125 | goto err_del_component; | |
a968e727 SP |
1126 | } |
1127 | ||
1128 | ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd"); | |
1129 | if (IS_ERR(ctx->lcd_clk)) { | |
1130 | dev_err(dev, "failed to get lcd clock\n"); | |
df5225bc ID |
1131 | ret = PTR_ERR(ctx->lcd_clk); |
1132 | goto err_del_component; | |
a968e727 | 1133 | } |
1c248b7d | 1134 | |
1c248b7d | 1135 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1c248b7d | 1136 | |
d873ab99 | 1137 | ctx->regs = devm_ioremap_resource(dev, res); |
df5225bc ID |
1138 | if (IS_ERR(ctx->regs)) { |
1139 | ret = PTR_ERR(ctx->regs); | |
1140 | goto err_del_component; | |
1141 | } | |
1c248b7d | 1142 | |
3854fab2 YC |
1143 | res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, |
1144 | ctx->i80_if ? "lcd_sys" : "vsync"); | |
1c248b7d ID |
1145 | if (!res) { |
1146 | dev_err(dev, "irq request failed.\n"); | |
df5225bc ID |
1147 | ret = -ENXIO; |
1148 | goto err_del_component; | |
1c248b7d ID |
1149 | } |
1150 | ||
055e0c06 | 1151 | ret = devm_request_irq(dev, res->start, fimd_irq_handler, |
edc57266 SK |
1152 | 0, "drm_fimd", ctx); |
1153 | if (ret) { | |
1c248b7d | 1154 | dev_err(dev, "irq request failed.\n"); |
df5225bc | 1155 | goto err_del_component; |
1c248b7d ID |
1156 | } |
1157 | ||
57ed0f7b | 1158 | init_waitqueue_head(&ctx->wait_vsync_queue); |
01ce113c | 1159 | atomic_set(&ctx->wait_vsync_event, 0); |
1c248b7d | 1160 | |
e152dbd7 | 1161 | platform_set_drvdata(pdev, ctx); |
14b6873a | 1162 | |
000cc920 | 1163 | ctx->display = exynos_dpi_probe(dev); |
5baf5d44 GP |
1164 | if (IS_ERR(ctx->display)) { |
1165 | ret = PTR_ERR(ctx->display); | |
1166 | goto err_del_component; | |
1167 | } | |
f37cd5e8 | 1168 | |
e152dbd7 | 1169 | pm_runtime_enable(dev); |
f37cd5e8 | 1170 | |
e152dbd7 | 1171 | ret = component_add(dev, &fimd_component_ops); |
df5225bc ID |
1172 | if (ret) |
1173 | goto err_disable_pm_runtime; | |
1174 | ||
1175 | return ret; | |
1176 | ||
1177 | err_disable_pm_runtime: | |
e152dbd7 | 1178 | pm_runtime_disable(dev); |
df5225bc ID |
1179 | |
1180 | err_del_component: | |
e152dbd7 | 1181 | exynos_drm_component_del(dev, EXYNOS_DEVICE_TYPE_CRTC); |
df5225bc | 1182 | return ret; |
f37cd5e8 | 1183 | } |
cb91f6a0 | 1184 | |
f37cd5e8 ID |
1185 | static int fimd_remove(struct platform_device *pdev) |
1186 | { | |
af65c804 | 1187 | pm_runtime_disable(&pdev->dev); |
5d55393a | 1188 | |
df5225bc ID |
1189 | component_del(&pdev->dev, &fimd_component_ops); |
1190 | exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC); | |
1191 | ||
5d55393a | 1192 | return 0; |
e30d4bcf ID |
1193 | } |
1194 | ||
1c363c7c KK |
1195 | void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable) |
1196 | { | |
1197 | struct fimd_context *ctx = crtc->ctx; | |
1198 | u32 val; | |
1199 | ||
1200 | /* | |
1201 | * Only Exynos 5250, 5260, 5410 and 542x requires enabling DP/MIE | |
1202 | * clock. On these SoCs the bootloader may enable it but any | |
1203 | * power domain off/on will reset it to disable state. | |
1204 | */ | |
1205 | if (ctx->driver_data != &exynos5_fimd_driver_data) | |
1206 | return; | |
1207 | ||
1208 | val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE; | |
1209 | writel(DP_MIE_CLK_DP_ENABLE, ctx->regs + DP_MIE_CLKCON); | |
1210 | } | |
1211 | EXPORT_SYMBOL_GPL(fimd_dp_clock_enable); | |
1212 | ||
132a5b91 | 1213 | struct platform_driver fimd_driver = { |
1c248b7d | 1214 | .probe = fimd_probe, |
56550d94 | 1215 | .remove = fimd_remove, |
1c248b7d ID |
1216 | .driver = { |
1217 | .name = "exynos4-fb", | |
1218 | .owner = THIS_MODULE, | |
2d3f173c | 1219 | .of_match_table = fimd_driver_dt_match, |
1c248b7d ID |
1220 | }, |
1221 | }; |