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1c248b7d ID |
1 | /* exynos_drm_fimd.c |
2 | * | |
3 | * Copyright (C) 2011 Samsung Electronics Co.Ltd | |
4 | * Authors: | |
5 | * Joonyoung Shim <jy0922.shim@samsung.com> | |
6 | * Inki Dae <inki.dae@samsung.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | */ | |
760285e7 | 14 | #include <drm/drmP.h> |
1c248b7d ID |
15 | |
16 | #include <linux/kernel.h> | |
1c248b7d ID |
17 | #include <linux/platform_device.h> |
18 | #include <linux/clk.h> | |
3f1c781d | 19 | #include <linux/of.h> |
d636ead8 | 20 | #include <linux/of_device.h> |
cb91f6a0 | 21 | #include <linux/pm_runtime.h> |
f37cd5e8 | 22 | #include <linux/component.h> |
3854fab2 YC |
23 | #include <linux/mfd/syscon.h> |
24 | #include <linux/regmap.h> | |
1c248b7d | 25 | |
7f4596f4 | 26 | #include <video/of_display_timing.h> |
111e6055 | 27 | #include <video/of_videomode.h> |
5a213a55 | 28 | #include <video/samsung_fimd.h> |
1c248b7d | 29 | #include <drm/exynos_drm.h> |
1c248b7d ID |
30 | |
31 | #include "exynos_drm_drv.h" | |
0488f50e | 32 | #include "exynos_drm_fb.h" |
1c248b7d | 33 | #include "exynos_drm_crtc.h" |
7ee14cdc | 34 | #include "exynos_drm_plane.h" |
bcc5cd1c | 35 | #include "exynos_drm_iommu.h" |
1c248b7d ID |
36 | |
37 | /* | |
b8654b37 | 38 | * FIMD stands for Fully Interactive Mobile Display and |
1c248b7d ID |
39 | * as a display controller, it transfers contents drawn on memory |
40 | * to a LCD Panel through Display Interfaces such as RGB or | |
41 | * CPU Interface. | |
42 | */ | |
43 | ||
66367461 | 44 | #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 |
111e6055 | 45 | |
1c248b7d ID |
46 | /* position control register for hardware window 0, 2 ~ 4.*/ |
47 | #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16) | |
48 | #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16) | |
0f10cf14 LKA |
49 | /* |
50 | * size control register for hardware windows 0 and alpha control register | |
51 | * for hardware windows 1 ~ 4 | |
52 | */ | |
53 | #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16) | |
54 | /* size control register for hardware windows 1 ~ 2. */ | |
1c248b7d ID |
55 | #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16) |
56 | ||
453b44a3 GP |
57 | #define VIDWnALPHA0(win) (VIDW_ALPHA + 0x00 + (win) * 8) |
58 | #define VIDWnALPHA1(win) (VIDW_ALPHA + 0x04 + (win) * 8) | |
59 | ||
1c248b7d | 60 | #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8) |
cb11b3f1 | 61 | #define VIDWx_BUF_START_S(win, buf) (VIDW_BUF_START_S(buf) + (win) * 8) |
1c248b7d ID |
62 | #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8) |
63 | #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4) | |
64 | ||
65 | /* color key control register for hardware window 1 ~ 4. */ | |
0f10cf14 | 66 | #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8)) |
1c248b7d | 67 | /* color key value register for hardware window 1 ~ 4. */ |
0f10cf14 | 68 | #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8)) |
1c248b7d | 69 | |
b5bf0f1e | 70 | /* I80 trigger control register */ |
3854fab2 | 71 | #define TRIGCON 0x1A4 |
b5bf0f1e ID |
72 | #define TRGMODE_ENABLE (1 << 0) |
73 | #define SWTRGCMD_ENABLE (1 << 1) | |
a6f75aa1 | 74 | /* Exynos3250, 3472, 4415, 5260 5410, 5420 and 5422 only supported. */ |
b5bf0f1e ID |
75 | #define HWTRGEN_ENABLE (1 << 3) |
76 | #define HWTRGMASK_ENABLE (1 << 4) | |
a6f75aa1 | 77 | /* Exynos3250, 3472, 4415, 5260, 5420 and 5422 only supported. */ |
b5bf0f1e | 78 | #define HWTRIGEN_PER_ENABLE (1 << 31) |
3854fab2 YC |
79 | |
80 | /* display mode change control register except exynos4 */ | |
81 | #define VIDOUT_CON 0x000 | |
82 | #define VIDOUT_CON_F_I80_LDI0 (0x2 << 8) | |
83 | ||
84 | /* I80 interface control for main LDI register */ | |
85 | #define I80IFCONFAx(x) (0x1B0 + (x) * 4) | |
86 | #define I80IFCONFBx(x) (0x1B8 + (x) * 4) | |
87 | #define LCD_CS_SETUP(x) ((x) << 16) | |
88 | #define LCD_WR_SETUP(x) ((x) << 12) | |
89 | #define LCD_WR_ACTIVE(x) ((x) << 8) | |
90 | #define LCD_WR_HOLD(x) ((x) << 4) | |
91 | #define I80IFEN_ENABLE (1 << 0) | |
92 | ||
1c248b7d ID |
93 | /* FIMD has totally five hardware windows. */ |
94 | #define WINDOWS_NR 5 | |
95 | ||
a6f75aa1 ID |
96 | /* HW trigger flag on i80 panel. */ |
97 | #define I80_HW_TRG (1 << 1) | |
98 | ||
e2e13389 LKA |
99 | struct fimd_driver_data { |
100 | unsigned int timing_base; | |
3854fab2 YC |
101 | unsigned int lcdblk_offset; |
102 | unsigned int lcdblk_vt_shift; | |
103 | unsigned int lcdblk_bypass_shift; | |
1feafd3a | 104 | unsigned int lcdblk_mic_bypass_shift; |
a6f75aa1 | 105 | unsigned int trg_type; |
de7af100 TF |
106 | |
107 | unsigned int has_shadowcon:1; | |
411d9ed4 | 108 | unsigned int has_clksel:1; |
5cc4621a | 109 | unsigned int has_limited_fmt:1; |
3854fab2 | 110 | unsigned int has_vidoutcon:1; |
3c3c9c1d | 111 | unsigned int has_vtsel:1; |
1feafd3a | 112 | unsigned int has_mic_bypass:1; |
196e059a | 113 | unsigned int has_dp_clk:1; |
a6f75aa1 ID |
114 | unsigned int has_hw_trigger:1; |
115 | unsigned int has_trigger_per_te:1; | |
e2e13389 LKA |
116 | }; |
117 | ||
725ddead TF |
118 | static struct fimd_driver_data s3c64xx_fimd_driver_data = { |
119 | .timing_base = 0x0, | |
120 | .has_clksel = 1, | |
5cc4621a | 121 | .has_limited_fmt = 1, |
725ddead TF |
122 | }; |
123 | ||
d6ce7b58 ID |
124 | static struct fimd_driver_data exynos3_fimd_driver_data = { |
125 | .timing_base = 0x20000, | |
126 | .lcdblk_offset = 0x210, | |
127 | .lcdblk_bypass_shift = 1, | |
a6f75aa1 | 128 | .trg_type = I80_HW_TRG, |
d6ce7b58 ID |
129 | .has_shadowcon = 1, |
130 | .has_vidoutcon = 1, | |
a6f75aa1 | 131 | .has_trigger_per_te = 1, |
d6ce7b58 ID |
132 | }; |
133 | ||
6ecf18f9 | 134 | static struct fimd_driver_data exynos4_fimd_driver_data = { |
e2e13389 | 135 | .timing_base = 0x0, |
3854fab2 YC |
136 | .lcdblk_offset = 0x210, |
137 | .lcdblk_vt_shift = 10, | |
138 | .lcdblk_bypass_shift = 1, | |
de7af100 | 139 | .has_shadowcon = 1, |
3c3c9c1d | 140 | .has_vtsel = 1, |
e2e13389 LKA |
141 | }; |
142 | ||
dcb622aa YC |
143 | static struct fimd_driver_data exynos4415_fimd_driver_data = { |
144 | .timing_base = 0x20000, | |
145 | .lcdblk_offset = 0x210, | |
146 | .lcdblk_vt_shift = 10, | |
147 | .lcdblk_bypass_shift = 1, | |
a6f75aa1 | 148 | .trg_type = I80_HW_TRG, |
dcb622aa YC |
149 | .has_shadowcon = 1, |
150 | .has_vidoutcon = 1, | |
3c3c9c1d | 151 | .has_vtsel = 1, |
a6f75aa1 | 152 | .has_trigger_per_te = 1, |
dcb622aa YC |
153 | }; |
154 | ||
6ecf18f9 | 155 | static struct fimd_driver_data exynos5_fimd_driver_data = { |
e2e13389 | 156 | .timing_base = 0x20000, |
3854fab2 YC |
157 | .lcdblk_offset = 0x214, |
158 | .lcdblk_vt_shift = 24, | |
159 | .lcdblk_bypass_shift = 15, | |
de7af100 | 160 | .has_shadowcon = 1, |
3854fab2 | 161 | .has_vidoutcon = 1, |
3c3c9c1d | 162 | .has_vtsel = 1, |
196e059a | 163 | .has_dp_clk = 1, |
e2e13389 LKA |
164 | }; |
165 | ||
1feafd3a CP |
166 | static struct fimd_driver_data exynos5420_fimd_driver_data = { |
167 | .timing_base = 0x20000, | |
168 | .lcdblk_offset = 0x214, | |
169 | .lcdblk_vt_shift = 24, | |
170 | .lcdblk_bypass_shift = 15, | |
171 | .lcdblk_mic_bypass_shift = 11, | |
172 | .has_shadowcon = 1, | |
173 | .has_vidoutcon = 1, | |
174 | .has_vtsel = 1, | |
175 | .has_mic_bypass = 1, | |
196e059a | 176 | .has_dp_clk = 1, |
1feafd3a CP |
177 | }; |
178 | ||
1c248b7d | 179 | struct fimd_context { |
bb7704d6 | 180 | struct device *dev; |
40c8ab4b | 181 | struct drm_device *drm_dev; |
93bca243 | 182 | struct exynos_drm_crtc *crtc; |
7ee14cdc | 183 | struct exynos_drm_plane planes[WINDOWS_NR]; |
fd2d2fc2 | 184 | struct exynos_drm_plane_config configs[WINDOWS_NR]; |
1c248b7d ID |
185 | struct clk *bus_clk; |
186 | struct clk *lcd_clk; | |
1c248b7d | 187 | void __iomem *regs; |
3854fab2 | 188 | struct regmap *sysreg; |
1c248b7d | 189 | unsigned long irq_flags; |
3854fab2 | 190 | u32 vidcon0; |
1c248b7d | 191 | u32 vidcon1; |
3854fab2 YC |
192 | u32 vidout_con; |
193 | u32 i80ifcon; | |
194 | bool i80_if; | |
cb91f6a0 | 195 | bool suspended; |
080be03d | 196 | int pipe; |
01ce113c P |
197 | wait_queue_head_t wait_vsync_queue; |
198 | atomic_t wait_vsync_event; | |
3854fab2 YC |
199 | atomic_t win_updated; |
200 | atomic_t triggering; | |
1c248b7d | 201 | |
e1a7b9b4 | 202 | const struct fimd_driver_data *driver_data; |
2b8376c8 | 203 | struct drm_encoder *encoder; |
196e059a | 204 | struct exynos_drm_clk dp_clk; |
1c248b7d ID |
205 | }; |
206 | ||
d636ead8 | 207 | static const struct of_device_id fimd_driver_dt_match[] = { |
725ddead TF |
208 | { .compatible = "samsung,s3c6400-fimd", |
209 | .data = &s3c64xx_fimd_driver_data }, | |
d6ce7b58 ID |
210 | { .compatible = "samsung,exynos3250-fimd", |
211 | .data = &exynos3_fimd_driver_data }, | |
5830daf8 | 212 | { .compatible = "samsung,exynos4210-fimd", |
d636ead8 | 213 | .data = &exynos4_fimd_driver_data }, |
dcb622aa YC |
214 | { .compatible = "samsung,exynos4415-fimd", |
215 | .data = &exynos4415_fimd_driver_data }, | |
5830daf8 | 216 | { .compatible = "samsung,exynos5250-fimd", |
d636ead8 | 217 | .data = &exynos5_fimd_driver_data }, |
1feafd3a CP |
218 | { .compatible = "samsung,exynos5420-fimd", |
219 | .data = &exynos5420_fimd_driver_data }, | |
d636ead8 JS |
220 | {}, |
221 | }; | |
0262ceeb | 222 | MODULE_DEVICE_TABLE(of, fimd_driver_dt_match); |
d636ead8 | 223 | |
fd2d2fc2 MS |
224 | static const enum drm_plane_type fimd_win_types[WINDOWS_NR] = { |
225 | DRM_PLANE_TYPE_PRIMARY, | |
226 | DRM_PLANE_TYPE_OVERLAY, | |
227 | DRM_PLANE_TYPE_OVERLAY, | |
228 | DRM_PLANE_TYPE_OVERLAY, | |
229 | DRM_PLANE_TYPE_CURSOR, | |
230 | }; | |
231 | ||
fbbb1e1a MS |
232 | static const uint32_t fimd_formats[] = { |
233 | DRM_FORMAT_C8, | |
234 | DRM_FORMAT_XRGB1555, | |
235 | DRM_FORMAT_RGB565, | |
236 | DRM_FORMAT_XRGB8888, | |
237 | DRM_FORMAT_ARGB8888, | |
238 | }; | |
239 | ||
fb88e214 MS |
240 | static int fimd_enable_vblank(struct exynos_drm_crtc *crtc) |
241 | { | |
242 | struct fimd_context *ctx = crtc->ctx; | |
243 | u32 val; | |
244 | ||
245 | if (ctx->suspended) | |
246 | return -EPERM; | |
247 | ||
248 | if (!test_and_set_bit(0, &ctx->irq_flags)) { | |
249 | val = readl(ctx->regs + VIDINTCON0); | |
250 | ||
251 | val |= VIDINTCON0_INT_ENABLE; | |
252 | ||
253 | if (ctx->i80_if) { | |
254 | val |= VIDINTCON0_INT_I80IFDONE; | |
255 | val |= VIDINTCON0_INT_SYSMAINCON; | |
256 | val &= ~VIDINTCON0_INT_SYSSUBCON; | |
257 | } else { | |
258 | val |= VIDINTCON0_INT_FRAME; | |
259 | ||
260 | val &= ~VIDINTCON0_FRAMESEL0_MASK; | |
261 | val |= VIDINTCON0_FRAMESEL0_VSYNC; | |
262 | val &= ~VIDINTCON0_FRAMESEL1_MASK; | |
263 | val |= VIDINTCON0_FRAMESEL1_NONE; | |
264 | } | |
265 | ||
266 | writel(val, ctx->regs + VIDINTCON0); | |
267 | } | |
268 | ||
269 | return 0; | |
270 | } | |
271 | ||
272 | static void fimd_disable_vblank(struct exynos_drm_crtc *crtc) | |
273 | { | |
274 | struct fimd_context *ctx = crtc->ctx; | |
275 | u32 val; | |
276 | ||
277 | if (ctx->suspended) | |
278 | return; | |
279 | ||
280 | if (test_and_clear_bit(0, &ctx->irq_flags)) { | |
281 | val = readl(ctx->regs + VIDINTCON0); | |
282 | ||
283 | val &= ~VIDINTCON0_INT_ENABLE; | |
284 | ||
285 | if (ctx->i80_if) { | |
286 | val &= ~VIDINTCON0_INT_I80IFDONE; | |
287 | val &= ~VIDINTCON0_INT_SYSMAINCON; | |
288 | val &= ~VIDINTCON0_INT_SYSSUBCON; | |
289 | } else | |
290 | val &= ~VIDINTCON0_INT_FRAME; | |
291 | ||
292 | writel(val, ctx->regs + VIDINTCON0); | |
293 | } | |
294 | } | |
295 | ||
93bca243 | 296 | static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc) |
f13bdbd1 | 297 | { |
93bca243 | 298 | struct fimd_context *ctx = crtc->ctx; |
f13bdbd1 AA |
299 | |
300 | if (ctx->suspended) | |
301 | return; | |
302 | ||
303 | atomic_set(&ctx->wait_vsync_event, 1); | |
304 | ||
305 | /* | |
306 | * wait for FIMD to signal VSYNC interrupt or return after | |
307 | * timeout which is set to 50ms (refresh rate of 20). | |
308 | */ | |
309 | if (!wait_event_timeout(ctx->wait_vsync_queue, | |
310 | !atomic_read(&ctx->wait_vsync_event), | |
311 | HZ/20)) | |
312 | DRM_DEBUG_KMS("vblank wait timed out.\n"); | |
313 | } | |
314 | ||
5b1d5bc6 | 315 | static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win, |
f181a543 YC |
316 | bool enable) |
317 | { | |
318 | u32 val = readl(ctx->regs + WINCON(win)); | |
319 | ||
320 | if (enable) | |
321 | val |= WINCONx_ENWIN; | |
322 | else | |
323 | val &= ~WINCONx_ENWIN; | |
324 | ||
325 | writel(val, ctx->regs + WINCON(win)); | |
326 | } | |
327 | ||
5b1d5bc6 TJ |
328 | static void fimd_enable_shadow_channel_path(struct fimd_context *ctx, |
329 | unsigned int win, | |
999d8b31 YC |
330 | bool enable) |
331 | { | |
332 | u32 val = readl(ctx->regs + SHADOWCON); | |
333 | ||
334 | if (enable) | |
335 | val |= SHADOWCON_CHx_ENABLE(win); | |
336 | else | |
337 | val &= ~SHADOWCON_CHx_ENABLE(win); | |
338 | ||
339 | writel(val, ctx->regs + SHADOWCON); | |
340 | } | |
341 | ||
fc2e013f | 342 | static void fimd_clear_channels(struct exynos_drm_crtc *crtc) |
f13bdbd1 | 343 | { |
fc2e013f | 344 | struct fimd_context *ctx = crtc->ctx; |
5b1d5bc6 | 345 | unsigned int win, ch_enabled = 0; |
f13bdbd1 AA |
346 | |
347 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
348 | ||
fb88e214 MS |
349 | /* Hardware is in unknown state, so ensure it gets enabled properly */ |
350 | pm_runtime_get_sync(ctx->dev); | |
351 | ||
352 | clk_prepare_enable(ctx->bus_clk); | |
353 | clk_prepare_enable(ctx->lcd_clk); | |
354 | ||
f13bdbd1 AA |
355 | /* Check if any channel is enabled. */ |
356 | for (win = 0; win < WINDOWS_NR; win++) { | |
eb8a3bf7 MS |
357 | u32 val = readl(ctx->regs + WINCON(win)); |
358 | ||
359 | if (val & WINCONx_ENWIN) { | |
f181a543 | 360 | fimd_enable_video_output(ctx, win, false); |
eb8a3bf7 | 361 | |
999d8b31 YC |
362 | if (ctx->driver_data->has_shadowcon) |
363 | fimd_enable_shadow_channel_path(ctx, win, | |
364 | false); | |
365 | ||
f13bdbd1 AA |
366 | ch_enabled = 1; |
367 | } | |
368 | } | |
369 | ||
370 | /* Wait for vsync, as disable channel takes effect at next vsync */ | |
eb8a3bf7 | 371 | if (ch_enabled) { |
fb88e214 MS |
372 | int pipe = ctx->pipe; |
373 | ||
374 | /* ensure that vblank interrupt won't be reported to core */ | |
375 | ctx->suspended = false; | |
376 | ctx->pipe = -1; | |
eb8a3bf7 | 377 | |
fb88e214 | 378 | fimd_enable_vblank(ctx->crtc); |
92dc7a04 | 379 | fimd_wait_for_vblank(ctx->crtc); |
fb88e214 MS |
380 | fimd_disable_vblank(ctx->crtc); |
381 | ||
382 | ctx->suspended = true; | |
383 | ctx->pipe = pipe; | |
eb8a3bf7 | 384 | } |
fb88e214 MS |
385 | |
386 | clk_disable_unprepare(ctx->lcd_clk); | |
387 | clk_disable_unprepare(ctx->bus_clk); | |
388 | ||
389 | pm_runtime_put(ctx->dev); | |
f13bdbd1 AA |
390 | } |
391 | ||
a968e727 SP |
392 | static u32 fimd_calc_clkdiv(struct fimd_context *ctx, |
393 | const struct drm_display_mode *mode) | |
394 | { | |
fa9971d6 | 395 | unsigned long ideal_clk; |
a968e727 SP |
396 | u32 clkdiv; |
397 | ||
fa9971d6 TJ |
398 | if (mode->clock == 0) { |
399 | DRM_ERROR("Mode has zero clock value.\n"); | |
400 | return 0xff; | |
401 | } | |
402 | ||
403 | ideal_clk = mode->clock * 1000; | |
404 | ||
3854fab2 YC |
405 | if (ctx->i80_if) { |
406 | /* | |
407 | * The frame done interrupt should be occurred prior to the | |
408 | * next TE signal. | |
409 | */ | |
410 | ideal_clk *= 2; | |
411 | } | |
412 | ||
a968e727 | 413 | /* Find the clock divider value that gets us closest to ideal_clk */ |
217fb00a | 414 | clkdiv = DIV_ROUND_CLOSEST(clk_get_rate(ctx->lcd_clk), ideal_clk); |
a968e727 SP |
415 | |
416 | return (clkdiv < 0x100) ? clkdiv : 0xff; | |
417 | } | |
418 | ||
a6f75aa1 ID |
419 | static void fimd_setup_trigger(struct fimd_context *ctx) |
420 | { | |
421 | void __iomem *timing_base = ctx->regs + ctx->driver_data->timing_base; | |
422 | u32 trg_type = ctx->driver_data->trg_type; | |
423 | u32 val = readl(timing_base + TRIGCON); | |
424 | ||
b5bf0f1e | 425 | val &= ~(TRGMODE_ENABLE); |
a6f75aa1 ID |
426 | |
427 | if (trg_type == I80_HW_TRG) { | |
428 | if (ctx->driver_data->has_hw_trigger) | |
b5bf0f1e | 429 | val |= HWTRGEN_ENABLE | HWTRGMASK_ENABLE; |
a6f75aa1 | 430 | if (ctx->driver_data->has_trigger_per_te) |
b5bf0f1e | 431 | val |= HWTRIGEN_PER_ENABLE; |
a6f75aa1 | 432 | } else { |
b5bf0f1e | 433 | val |= TRGMODE_ENABLE; |
a6f75aa1 ID |
434 | } |
435 | ||
436 | writel(val, timing_base + TRIGCON); | |
437 | } | |
438 | ||
93bca243 | 439 | static void fimd_commit(struct exynos_drm_crtc *crtc) |
1c248b7d | 440 | { |
93bca243 | 441 | struct fimd_context *ctx = crtc->ctx; |
020e79de | 442 | struct drm_display_mode *mode = &crtc->base.state->adjusted_mode; |
e1a7b9b4 | 443 | const struct fimd_driver_data *driver_data = ctx->driver_data; |
3854fab2 YC |
444 | void *timing_base = ctx->regs + driver_data->timing_base; |
445 | u32 val, clkdiv; | |
1c248b7d | 446 | |
e30d4bcf ID |
447 | if (ctx->suspended) |
448 | return; | |
449 | ||
a968e727 SP |
450 | /* nothing to do if we haven't set the mode yet */ |
451 | if (mode->htotal == 0 || mode->vtotal == 0) | |
452 | return; | |
453 | ||
3854fab2 YC |
454 | if (ctx->i80_if) { |
455 | val = ctx->i80ifcon | I80IFEN_ENABLE; | |
456 | writel(val, timing_base + I80IFCONFAx(0)); | |
457 | ||
458 | /* disable auto frame rate */ | |
459 | writel(0, timing_base + I80IFCONFBx(0)); | |
460 | ||
461 | /* set video type selection to I80 interface */ | |
3c3c9c1d JS |
462 | if (driver_data->has_vtsel && ctx->sysreg && |
463 | regmap_update_bits(ctx->sysreg, | |
3854fab2 YC |
464 | driver_data->lcdblk_offset, |
465 | 0x3 << driver_data->lcdblk_vt_shift, | |
466 | 0x1 << driver_data->lcdblk_vt_shift)) { | |
467 | DRM_ERROR("Failed to update sysreg for I80 i/f.\n"); | |
468 | return; | |
469 | } | |
470 | } else { | |
471 | int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd; | |
472 | u32 vidcon1; | |
473 | ||
474 | /* setup polarity values */ | |
475 | vidcon1 = ctx->vidcon1; | |
476 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
477 | vidcon1 |= VIDCON1_INV_VSYNC; | |
478 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
479 | vidcon1 |= VIDCON1_INV_HSYNC; | |
480 | writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1); | |
481 | ||
482 | /* setup vertical timing values. */ | |
483 | vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; | |
484 | vbpd = mode->crtc_vtotal - mode->crtc_vsync_end; | |
485 | vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay; | |
486 | ||
487 | val = VIDTCON0_VBPD(vbpd - 1) | | |
488 | VIDTCON0_VFPD(vfpd - 1) | | |
489 | VIDTCON0_VSPW(vsync_len - 1); | |
490 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON0); | |
491 | ||
492 | /* setup horizontal timing values. */ | |
493 | hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; | |
494 | hbpd = mode->crtc_htotal - mode->crtc_hsync_end; | |
495 | hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay; | |
496 | ||
497 | val = VIDTCON1_HBPD(hbpd - 1) | | |
498 | VIDTCON1_HFPD(hfpd - 1) | | |
499 | VIDTCON1_HSPW(hsync_len - 1); | |
500 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON1); | |
501 | } | |
502 | ||
503 | if (driver_data->has_vidoutcon) | |
504 | writel(ctx->vidout_con, timing_base + VIDOUT_CON); | |
505 | ||
506 | /* set bypass selection */ | |
507 | if (ctx->sysreg && regmap_update_bits(ctx->sysreg, | |
508 | driver_data->lcdblk_offset, | |
509 | 0x1 << driver_data->lcdblk_bypass_shift, | |
510 | 0x1 << driver_data->lcdblk_bypass_shift)) { | |
511 | DRM_ERROR("Failed to update sysreg for bypass setting.\n"); | |
512 | return; | |
513 | } | |
1c248b7d | 514 | |
1feafd3a CP |
515 | /* TODO: When MIC is enabled for display path, the lcdblk_mic_bypass |
516 | * bit should be cleared. | |
517 | */ | |
518 | if (driver_data->has_mic_bypass && ctx->sysreg && | |
519 | regmap_update_bits(ctx->sysreg, | |
520 | driver_data->lcdblk_offset, | |
521 | 0x1 << driver_data->lcdblk_mic_bypass_shift, | |
522 | 0x1 << driver_data->lcdblk_mic_bypass_shift)) { | |
523 | DRM_ERROR("Failed to update sysreg for bypass mic.\n"); | |
524 | return; | |
525 | } | |
526 | ||
1c248b7d | 527 | /* setup horizontal and vertical display size. */ |
a968e727 SP |
528 | val = VIDTCON2_LINEVAL(mode->vdisplay - 1) | |
529 | VIDTCON2_HOZVAL(mode->hdisplay - 1) | | |
530 | VIDTCON2_LINEVAL_E(mode->vdisplay - 1) | | |
531 | VIDTCON2_HOZVAL_E(mode->hdisplay - 1); | |
e2e13389 | 532 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON2); |
1c248b7d | 533 | |
a6f75aa1 ID |
534 | fimd_setup_trigger(ctx); |
535 | ||
1d531062 AH |
536 | /* |
537 | * fields of register with prefix '_F' would be updated | |
538 | * at vsync(same as dma start) | |
539 | */ | |
3854fab2 YC |
540 | val = ctx->vidcon0; |
541 | val |= VIDCON0_ENVID | VIDCON0_ENVID_F; | |
1c248b7d | 542 | |
1d531062 | 543 | if (ctx->driver_data->has_clksel) |
411d9ed4 | 544 | val |= VIDCON0_CLKSEL_LCD; |
411d9ed4 | 545 | |
a968e727 SP |
546 | clkdiv = fimd_calc_clkdiv(ctx, mode); |
547 | if (clkdiv > 1) | |
548 | val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR; | |
1c248b7d | 549 | |
1c248b7d ID |
550 | writel(val, ctx->regs + VIDCON0); |
551 | } | |
552 | ||
1c248b7d | 553 | |
2eeb2e5e | 554 | static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win, |
8b704d8a | 555 | uint32_t pixel_format, int width) |
1c248b7d | 556 | { |
1c248b7d ID |
557 | unsigned long val; |
558 | ||
1c248b7d ID |
559 | val = WINCONx_ENWIN; |
560 | ||
5cc4621a ID |
561 | /* |
562 | * In case of s3c64xx, window 0 doesn't support alpha channel. | |
563 | * So the request format is ARGB8888 then change it to XRGB8888. | |
564 | */ | |
565 | if (ctx->driver_data->has_limited_fmt && !win) { | |
8b704d8a MS |
566 | if (pixel_format == DRM_FORMAT_ARGB8888) |
567 | pixel_format = DRM_FORMAT_XRGB8888; | |
5cc4621a ID |
568 | } |
569 | ||
8b704d8a | 570 | switch (pixel_format) { |
a4f38a80 | 571 | case DRM_FORMAT_C8: |
1c248b7d ID |
572 | val |= WINCON0_BPPMODE_8BPP_PALETTE; |
573 | val |= WINCONx_BURSTLEN_8WORD; | |
574 | val |= WINCONx_BYTSWP; | |
575 | break; | |
a4f38a80 ID |
576 | case DRM_FORMAT_XRGB1555: |
577 | val |= WINCON0_BPPMODE_16BPP_1555; | |
578 | val |= WINCONx_HAWSWP; | |
579 | val |= WINCONx_BURSTLEN_16WORD; | |
580 | break; | |
581 | case DRM_FORMAT_RGB565: | |
1c248b7d ID |
582 | val |= WINCON0_BPPMODE_16BPP_565; |
583 | val |= WINCONx_HAWSWP; | |
584 | val |= WINCONx_BURSTLEN_16WORD; | |
585 | break; | |
a4f38a80 | 586 | case DRM_FORMAT_XRGB8888: |
1c248b7d ID |
587 | val |= WINCON0_BPPMODE_24BPP_888; |
588 | val |= WINCONx_WSWP; | |
589 | val |= WINCONx_BURSTLEN_16WORD; | |
590 | break; | |
a4f38a80 ID |
591 | case DRM_FORMAT_ARGB8888: |
592 | val |= WINCON1_BPPMODE_25BPP_A1888 | |
1c248b7d ID |
593 | | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL; |
594 | val |= WINCONx_WSWP; | |
595 | val |= WINCONx_BURSTLEN_16WORD; | |
596 | break; | |
597 | default: | |
598 | DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n"); | |
599 | ||
600 | val |= WINCON0_BPPMODE_24BPP_888; | |
601 | val |= WINCONx_WSWP; | |
602 | val |= WINCONx_BURSTLEN_16WORD; | |
603 | break; | |
604 | } | |
605 | ||
66367461 | 606 | /* |
8b704d8a MS |
607 | * Setting dma-burst to 16Word causes permanent tearing for very small |
608 | * buffers, e.g. cursor buffer. Burst Mode switching which based on | |
609 | * plane size is not recommended as plane size varies alot towards the | |
610 | * end of the screen and rapid movement causes unstable DMA, but it is | |
611 | * still better to change dma-burst than displaying garbage. | |
66367461 RS |
612 | */ |
613 | ||
8b704d8a | 614 | if (width < MIN_FB_WIDTH_FOR_16WORD_BURST) { |
66367461 RS |
615 | val &= ~WINCONx_BURSTLEN_MASK; |
616 | val |= WINCONx_BURSTLEN_4WORD; | |
617 | } | |
618 | ||
1c248b7d | 619 | writel(val, ctx->regs + WINCON(win)); |
453b44a3 GP |
620 | |
621 | /* hardware window 0 doesn't support alpha channel. */ | |
622 | if (win != 0) { | |
623 | /* OSD alpha */ | |
624 | val = VIDISD14C_ALPHA0_R(0xf) | | |
625 | VIDISD14C_ALPHA0_G(0xf) | | |
626 | VIDISD14C_ALPHA0_B(0xf) | | |
627 | VIDISD14C_ALPHA1_R(0xf) | | |
628 | VIDISD14C_ALPHA1_G(0xf) | | |
629 | VIDISD14C_ALPHA1_B(0xf); | |
630 | ||
631 | writel(val, ctx->regs + VIDOSD_C(win)); | |
632 | ||
633 | val = VIDW_ALPHA_R(0xf) | VIDW_ALPHA_G(0xf) | | |
634 | VIDW_ALPHA_G(0xf); | |
635 | writel(val, ctx->regs + VIDWnALPHA0(win)); | |
636 | writel(val, ctx->regs + VIDWnALPHA1(win)); | |
637 | } | |
1c248b7d ID |
638 | } |
639 | ||
bb7704d6 | 640 | static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win) |
1c248b7d | 641 | { |
1c248b7d ID |
642 | unsigned int keycon0 = 0, keycon1 = 0; |
643 | ||
1c248b7d ID |
644 | keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F | |
645 | WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); | |
646 | ||
647 | keycon1 = WxKEYCON1_COLVAL(0xffffffff); | |
648 | ||
649 | writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); | |
650 | writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); | |
651 | } | |
652 | ||
de7af100 TF |
653 | /** |
654 | * shadow_protect_win() - disable updating values from shadow registers at vsync | |
655 | * | |
656 | * @win: window to protect registers for | |
657 | * @protect: 1 to protect (disable updates) | |
658 | */ | |
659 | static void fimd_shadow_protect_win(struct fimd_context *ctx, | |
6e2a3b66 | 660 | unsigned int win, bool protect) |
de7af100 TF |
661 | { |
662 | u32 reg, bits, val; | |
663 | ||
ce3ff36b GP |
664 | /* |
665 | * SHADOWCON/PRTCON register is used for enabling timing. | |
666 | * | |
667 | * for example, once only width value of a register is set, | |
668 | * if the dma is started then fimd hardware could malfunction so | |
669 | * with protect window setting, the register fields with prefix '_F' | |
670 | * wouldn't be updated at vsync also but updated once unprotect window | |
671 | * is set. | |
672 | */ | |
673 | ||
de7af100 TF |
674 | if (ctx->driver_data->has_shadowcon) { |
675 | reg = SHADOWCON; | |
676 | bits = SHADOWCON_WINx_PROTECT(win); | |
677 | } else { | |
678 | reg = PRTCON; | |
679 | bits = PRTCON_PROTECT; | |
680 | } | |
681 | ||
682 | val = readl(ctx->regs + reg); | |
683 | if (protect) | |
684 | val |= bits; | |
685 | else | |
686 | val &= ~bits; | |
687 | writel(val, ctx->regs + reg); | |
688 | } | |
689 | ||
d29c2c14 | 690 | static void fimd_atomic_begin(struct exynos_drm_crtc *crtc) |
ce3ff36b GP |
691 | { |
692 | struct fimd_context *ctx = crtc->ctx; | |
d29c2c14 | 693 | int i; |
ce3ff36b GP |
694 | |
695 | if (ctx->suspended) | |
696 | return; | |
697 | ||
d29c2c14 MS |
698 | for (i = 0; i < WINDOWS_NR; i++) |
699 | fimd_shadow_protect_win(ctx, i, true); | |
ce3ff36b GP |
700 | } |
701 | ||
d29c2c14 | 702 | static void fimd_atomic_flush(struct exynos_drm_crtc *crtc) |
ce3ff36b GP |
703 | { |
704 | struct fimd_context *ctx = crtc->ctx; | |
d29c2c14 | 705 | int i; |
ce3ff36b GP |
706 | |
707 | if (ctx->suspended) | |
708 | return; | |
709 | ||
d29c2c14 MS |
710 | for (i = 0; i < WINDOWS_NR; i++) |
711 | fimd_shadow_protect_win(ctx, i, false); | |
ce3ff36b GP |
712 | } |
713 | ||
1e1d1393 GP |
714 | static void fimd_update_plane(struct exynos_drm_crtc *crtc, |
715 | struct exynos_drm_plane *plane) | |
1c248b7d | 716 | { |
0114f404 MS |
717 | struct exynos_drm_plane_state *state = |
718 | to_exynos_plane_state(plane->base.state); | |
93bca243 | 719 | struct fimd_context *ctx = crtc->ctx; |
0114f404 | 720 | struct drm_framebuffer *fb = state->base.fb; |
7ee14cdc GP |
721 | dma_addr_t dma_addr; |
722 | unsigned long val, size, offset; | |
723 | unsigned int last_x, last_y, buf_offsize, line_size; | |
40bdfb0a | 724 | unsigned int win = plane->index; |
0488f50e MS |
725 | unsigned int bpp = fb->bits_per_pixel >> 3; |
726 | unsigned int pitch = fb->pitches[0]; | |
1c248b7d | 727 | |
e30d4bcf ID |
728 | if (ctx->suspended) |
729 | return; | |
730 | ||
0114f404 MS |
731 | offset = state->src.x * bpp; |
732 | offset += state->src.y * pitch; | |
7ee14cdc | 733 | |
1c248b7d | 734 | /* buffer start address */ |
0488f50e | 735 | dma_addr = exynos_drm_fb_dma_addr(fb, 0) + offset; |
7ee14cdc | 736 | val = (unsigned long)dma_addr; |
1c248b7d ID |
737 | writel(val, ctx->regs + VIDWx_BUF_START(win, 0)); |
738 | ||
739 | /* buffer end address */ | |
0114f404 | 740 | size = pitch * state->crtc.h; |
7ee14cdc | 741 | val = (unsigned long)(dma_addr + size); |
1c248b7d ID |
742 | writel(val, ctx->regs + VIDWx_BUF_END(win, 0)); |
743 | ||
744 | DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n", | |
7ee14cdc | 745 | (unsigned long)dma_addr, val, size); |
19c8b834 | 746 | DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", |
0114f404 | 747 | state->crtc.w, state->crtc.h); |
1c248b7d ID |
748 | |
749 | /* buffer size */ | |
0114f404 MS |
750 | buf_offsize = pitch - (state->crtc.w * bpp); |
751 | line_size = state->crtc.w * bpp; | |
7ee14cdc GP |
752 | val = VIDW_BUF_SIZE_OFFSET(buf_offsize) | |
753 | VIDW_BUF_SIZE_PAGEWIDTH(line_size) | | |
754 | VIDW_BUF_SIZE_OFFSET_E(buf_offsize) | | |
755 | VIDW_BUF_SIZE_PAGEWIDTH_E(line_size); | |
1c248b7d ID |
756 | writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0)); |
757 | ||
758 | /* OSD position */ | |
0114f404 MS |
759 | val = VIDOSDxA_TOPLEFT_X(state->crtc.x) | |
760 | VIDOSDxA_TOPLEFT_Y(state->crtc.y) | | |
761 | VIDOSDxA_TOPLEFT_X_E(state->crtc.x) | | |
762 | VIDOSDxA_TOPLEFT_Y_E(state->crtc.y); | |
1c248b7d ID |
763 | writel(val, ctx->regs + VIDOSD_A(win)); |
764 | ||
0114f404 | 765 | last_x = state->crtc.x + state->crtc.w; |
f56aad3a JS |
766 | if (last_x) |
767 | last_x--; | |
0114f404 | 768 | last_y = state->crtc.y + state->crtc.h; |
f56aad3a JS |
769 | if (last_y) |
770 | last_y--; | |
771 | ||
ca555e5a JS |
772 | val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) | |
773 | VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y); | |
774 | ||
1c248b7d ID |
775 | writel(val, ctx->regs + VIDOSD_B(win)); |
776 | ||
19c8b834 | 777 | DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", |
0114f404 | 778 | state->crtc.x, state->crtc.y, last_x, last_y); |
1c248b7d | 779 | |
1c248b7d ID |
780 | /* OSD size */ |
781 | if (win != 3 && win != 4) { | |
782 | u32 offset = VIDOSD_D(win); | |
783 | if (win == 0) | |
0f10cf14 | 784 | offset = VIDOSD_C(win); |
0114f404 | 785 | val = state->crtc.w * state->crtc.h; |
1c248b7d ID |
786 | writel(val, ctx->regs + offset); |
787 | ||
788 | DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val); | |
789 | } | |
790 | ||
8b704d8a | 791 | fimd_win_set_pixfmt(ctx, win, fb->pixel_format, state->src.w); |
1c248b7d ID |
792 | |
793 | /* hardware window 0 doesn't support color key. */ | |
794 | if (win != 0) | |
bb7704d6 | 795 | fimd_win_set_colkey(ctx, win); |
1c248b7d | 796 | |
f181a543 | 797 | fimd_enable_video_output(ctx, win, true); |
ec05da95 | 798 | |
999d8b31 YC |
799 | if (ctx->driver_data->has_shadowcon) |
800 | fimd_enable_shadow_channel_path(ctx, win, true); | |
ec05da95 | 801 | |
3854fab2 YC |
802 | if (ctx->i80_if) |
803 | atomic_set(&ctx->win_updated, 1); | |
1c248b7d ID |
804 | } |
805 | ||
1e1d1393 GP |
806 | static void fimd_disable_plane(struct exynos_drm_crtc *crtc, |
807 | struct exynos_drm_plane *plane) | |
1c248b7d | 808 | { |
93bca243 | 809 | struct fimd_context *ctx = crtc->ctx; |
40bdfb0a | 810 | unsigned int win = plane->index; |
ec05da95 | 811 | |
c329f667 | 812 | if (ctx->suspended) |
db7e55ae | 813 | return; |
db7e55ae | 814 | |
f181a543 | 815 | fimd_enable_video_output(ctx, win, false); |
1c248b7d | 816 | |
999d8b31 YC |
817 | if (ctx->driver_data->has_shadowcon) |
818 | fimd_enable_shadow_channel_path(ctx, win, false); | |
a43b933b SP |
819 | } |
820 | ||
3cecda03 | 821 | static void fimd_enable(struct exynos_drm_crtc *crtc) |
a43b933b | 822 | { |
3cecda03 | 823 | struct fimd_context *ctx = crtc->ctx; |
a43b933b SP |
824 | |
825 | if (!ctx->suspended) | |
3cecda03 | 826 | return; |
a43b933b SP |
827 | |
828 | ctx->suspended = false; | |
829 | ||
af65c804 SP |
830 | pm_runtime_get_sync(ctx->dev); |
831 | ||
a43b933b | 832 | /* if vblank was enabled status, enable it again. */ |
3cecda03 GP |
833 | if (test_and_clear_bit(0, &ctx->irq_flags)) |
834 | fimd_enable_vblank(ctx->crtc); | |
a43b933b | 835 | |
c329f667 | 836 | fimd_commit(ctx->crtc); |
a43b933b SP |
837 | } |
838 | ||
3cecda03 | 839 | static void fimd_disable(struct exynos_drm_crtc *crtc) |
a43b933b | 840 | { |
3cecda03 | 841 | struct fimd_context *ctx = crtc->ctx; |
c329f667 | 842 | int i; |
3cecda03 | 843 | |
a43b933b | 844 | if (ctx->suspended) |
3cecda03 | 845 | return; |
a43b933b SP |
846 | |
847 | /* | |
848 | * We need to make sure that all windows are disabled before we | |
849 | * suspend that connector. Otherwise we might try to scan from | |
850 | * a destroyed buffer later. | |
851 | */ | |
c329f667 | 852 | for (i = 0; i < WINDOWS_NR; i++) |
1e1d1393 | 853 | fimd_disable_plane(crtc, &ctx->planes[i]); |
a43b933b | 854 | |
94ab95a9 ID |
855 | fimd_enable_vblank(crtc); |
856 | fimd_wait_for_vblank(crtc); | |
857 | fimd_disable_vblank(crtc); | |
858 | ||
b74f14fd JS |
859 | writel(0, ctx->regs + VIDCON0); |
860 | ||
af65c804 | 861 | pm_runtime_put_sync(ctx->dev); |
a43b933b | 862 | ctx->suspended = true; |
080be03d SP |
863 | } |
864 | ||
3854fab2 YC |
865 | static void fimd_trigger(struct device *dev) |
866 | { | |
e152dbd7 | 867 | struct fimd_context *ctx = dev_get_drvdata(dev); |
e1a7b9b4 | 868 | const struct fimd_driver_data *driver_data = ctx->driver_data; |
3854fab2 YC |
869 | void *timing_base = ctx->regs + driver_data->timing_base; |
870 | u32 reg; | |
871 | ||
9b67eb73 | 872 | /* |
1c905d95 YC |
873 | * Skips triggering if in triggering state, because multiple triggering |
874 | * requests can cause panel reset. | |
875 | */ | |
9b67eb73 JS |
876 | if (atomic_read(&ctx->triggering)) |
877 | return; | |
878 | ||
1c905d95 | 879 | /* Enters triggering mode */ |
3854fab2 YC |
880 | atomic_set(&ctx->triggering, 1); |
881 | ||
3854fab2 | 882 | reg = readl(timing_base + TRIGCON); |
b5bf0f1e | 883 | reg |= (TRGMODE_ENABLE | SWTRGCMD_ENABLE); |
3854fab2 | 884 | writel(reg, timing_base + TRIGCON); |
87ab85b3 YC |
885 | |
886 | /* | |
887 | * Exits triggering mode if vblank is not enabled yet, because when the | |
888 | * VIDINTCON0 register is not set, it can not exit from triggering mode. | |
889 | */ | |
890 | if (!test_bit(0, &ctx->irq_flags)) | |
891 | atomic_set(&ctx->triggering, 0); | |
3854fab2 YC |
892 | } |
893 | ||
93bca243 | 894 | static void fimd_te_handler(struct exynos_drm_crtc *crtc) |
3854fab2 | 895 | { |
93bca243 | 896 | struct fimd_context *ctx = crtc->ctx; |
a6f75aa1 | 897 | u32 trg_type = ctx->driver_data->trg_type; |
3854fab2 YC |
898 | |
899 | /* Checks the crtc is detached already from encoder */ | |
900 | if (ctx->pipe < 0 || !ctx->drm_dev) | |
901 | return; | |
902 | ||
a6f75aa1 ID |
903 | if (trg_type == I80_HW_TRG) |
904 | goto out; | |
905 | ||
3854fab2 YC |
906 | /* |
907 | * If there is a page flip request, triggers and handles the page flip | |
908 | * event so that current fb can be updated into panel GRAM. | |
909 | */ | |
910 | if (atomic_add_unless(&ctx->win_updated, -1, 0)) | |
911 | fimd_trigger(ctx->dev); | |
912 | ||
a6f75aa1 | 913 | out: |
3854fab2 YC |
914 | /* Wakes up vsync event queue */ |
915 | if (atomic_read(&ctx->wait_vsync_event)) { | |
916 | atomic_set(&ctx->wait_vsync_event, 0); | |
917 | wake_up(&ctx->wait_vsync_queue); | |
3854fab2 | 918 | } |
b301ae24 | 919 | |
adf67abf | 920 | if (test_bit(0, &ctx->irq_flags)) |
eafd540a | 921 | drm_crtc_handle_vblank(&ctx->crtc->base); |
3854fab2 YC |
922 | } |
923 | ||
196e059a | 924 | static void fimd_dp_clock_enable(struct exynos_drm_clk *clk, bool enable) |
48107d7b | 925 | { |
196e059a AH |
926 | struct fimd_context *ctx = container_of(clk, struct fimd_context, |
927 | dp_clk); | |
928 | u32 val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE; | |
3c79fb8c | 929 | writel(val, ctx->regs + DP_MIE_CLKCON); |
48107d7b KK |
930 | } |
931 | ||
f3aaf762 | 932 | static const struct exynos_drm_crtc_ops fimd_crtc_ops = { |
3cecda03 GP |
933 | .enable = fimd_enable, |
934 | .disable = fimd_disable, | |
1c6244c3 SP |
935 | .commit = fimd_commit, |
936 | .enable_vblank = fimd_enable_vblank, | |
937 | .disable_vblank = fimd_disable_vblank, | |
ce3ff36b | 938 | .atomic_begin = fimd_atomic_begin, |
9cc7610a GP |
939 | .update_plane = fimd_update_plane, |
940 | .disable_plane = fimd_disable_plane, | |
ce3ff36b | 941 | .atomic_flush = fimd_atomic_flush, |
3854fab2 | 942 | .te_handler = fimd_te_handler, |
1c248b7d ID |
943 | }; |
944 | ||
1c248b7d ID |
945 | static irqreturn_t fimd_irq_handler(int irq, void *dev_id) |
946 | { | |
947 | struct fimd_context *ctx = (struct fimd_context *)dev_id; | |
cb11b3f1 | 948 | u32 val, clear_bit, start, start_s; |
822f6dfd | 949 | int win; |
1c248b7d ID |
950 | |
951 | val = readl(ctx->regs + VIDINTCON1); | |
952 | ||
3854fab2 YC |
953 | clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME; |
954 | if (val & clear_bit) | |
955 | writel(clear_bit, ctx->regs + VIDINTCON1); | |
1c248b7d | 956 | |
ec05da95 | 957 | /* check the crtc is detached already from encoder */ |
080be03d | 958 | if (ctx->pipe < 0 || !ctx->drm_dev) |
ec05da95 | 959 | goto out; |
483b88f8 | 960 | |
fc75f710 GP |
961 | if (!ctx->i80_if) |
962 | drm_crtc_handle_vblank(&ctx->crtc->base); | |
963 | ||
822f6dfd GP |
964 | for (win = 0 ; win < WINDOWS_NR ; win++) { |
965 | struct exynos_drm_plane *plane = &ctx->planes[win]; | |
966 | ||
967 | if (!plane->pending_fb) | |
968 | continue; | |
969 | ||
cb11b3f1 GP |
970 | start = readl(ctx->regs + VIDWx_BUF_START(win, 0)); |
971 | start_s = readl(ctx->regs + VIDWx_BUF_START_S(win, 0)); | |
972 | if (start == start_s) | |
973 | exynos_drm_crtc_finish_update(ctx->crtc, plane); | |
822f6dfd | 974 | } |
adf67abf | 975 | |
fc75f710 | 976 | if (ctx->i80_if) { |
1c905d95 | 977 | /* Exits triggering mode */ |
3854fab2 | 978 | atomic_set(&ctx->triggering, 0); |
3854fab2 | 979 | } else { |
3854fab2 YC |
980 | /* set wait vsync event to zero and wake up queue. */ |
981 | if (atomic_read(&ctx->wait_vsync_event)) { | |
982 | atomic_set(&ctx->wait_vsync_event, 0); | |
983 | wake_up(&ctx->wait_vsync_queue); | |
984 | } | |
01ce113c | 985 | } |
3854fab2 | 986 | |
ec05da95 | 987 | out: |
1c248b7d ID |
988 | return IRQ_HANDLED; |
989 | } | |
990 | ||
f37cd5e8 | 991 | static int fimd_bind(struct device *dev, struct device *master, void *data) |
562ad9f4 | 992 | { |
e152dbd7 | 993 | struct fimd_context *ctx = dev_get_drvdata(dev); |
f37cd5e8 | 994 | struct drm_device *drm_dev = data; |
cdbfca89 | 995 | struct exynos_drm_private *priv = drm_dev->dev_private; |
7ee14cdc | 996 | struct exynos_drm_plane *exynos_plane; |
fd2d2fc2 | 997 | unsigned int i; |
6e2a3b66 | 998 | int ret; |
000cc920 | 999 | |
cdbfca89 HH |
1000 | ctx->drm_dev = drm_dev; |
1001 | ctx->pipe = priv->pipe++; | |
efa75bcd | 1002 | |
fd2d2fc2 MS |
1003 | for (i = 0; i < WINDOWS_NR; i++) { |
1004 | ctx->configs[i].pixel_formats = fimd_formats; | |
1005 | ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats); | |
1006 | ctx->configs[i].zpos = i; | |
1007 | ctx->configs[i].type = fimd_win_types[i]; | |
40bdfb0a | 1008 | ret = exynos_plane_init(drm_dev, &ctx->planes[i], i, |
fd2d2fc2 | 1009 | 1 << ctx->pipe, &ctx->configs[i]); |
7ee14cdc GP |
1010 | if (ret) |
1011 | return ret; | |
1012 | } | |
1013 | ||
5d3d0995 | 1014 | exynos_plane = &ctx->planes[DEFAULT_WIN]; |
7ee14cdc GP |
1015 | ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, |
1016 | ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD, | |
0f04cf8d | 1017 | &fimd_crtc_ops, ctx); |
d1222842 HH |
1018 | if (IS_ERR(ctx->crtc)) |
1019 | return PTR_ERR(ctx->crtc); | |
93bca243 | 1020 | |
196e059a AH |
1021 | if (ctx->driver_data->has_dp_clk) { |
1022 | ctx->dp_clk.enable = fimd_dp_clock_enable; | |
1023 | ctx->crtc->pipe_clk = &ctx->dp_clk; | |
1024 | } | |
1025 | ||
cf67cc9a | 1026 | if (ctx->encoder) |
a2986e80 | 1027 | exynos_dpi_bind(drm_dev, ctx->encoder); |
000cc920 | 1028 | |
43a3b866 JS |
1029 | if (is_drm_iommu_supported(drm_dev)) |
1030 | fimd_clear_channels(ctx->crtc); | |
eb7a3fc7 JS |
1031 | |
1032 | ret = drm_iommu_attach_device(drm_dev, dev); | |
fc2e013f HH |
1033 | if (ret) |
1034 | priv->pipe--; | |
1035 | ||
1036 | return ret; | |
000cc920 AH |
1037 | } |
1038 | ||
1039 | static void fimd_unbind(struct device *dev, struct device *master, | |
1040 | void *data) | |
1041 | { | |
e152dbd7 | 1042 | struct fimd_context *ctx = dev_get_drvdata(dev); |
000cc920 | 1043 | |
3cecda03 | 1044 | fimd_disable(ctx->crtc); |
000cc920 | 1045 | |
bf56608a | 1046 | drm_iommu_detach_device(ctx->drm_dev, ctx->dev); |
cdbfca89 | 1047 | |
cf67cc9a GP |
1048 | if (ctx->encoder) |
1049 | exynos_dpi_remove(ctx->encoder); | |
000cc920 AH |
1050 | } |
1051 | ||
1052 | static const struct component_ops fimd_component_ops = { | |
1053 | .bind = fimd_bind, | |
1054 | .unbind = fimd_unbind, | |
1055 | }; | |
1056 | ||
1057 | static int fimd_probe(struct platform_device *pdev) | |
1058 | { | |
1059 | struct device *dev = &pdev->dev; | |
562ad9f4 | 1060 | struct fimd_context *ctx; |
3854fab2 | 1061 | struct device_node *i80_if_timings; |
562ad9f4 | 1062 | struct resource *res; |
fe42cfb4 | 1063 | int ret; |
1c248b7d | 1064 | |
e152dbd7 AH |
1065 | if (!dev->of_node) |
1066 | return -ENODEV; | |
2d3f173c | 1067 | |
d873ab99 | 1068 | ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); |
e152dbd7 AH |
1069 | if (!ctx) |
1070 | return -ENOMEM; | |
1071 | ||
bb7704d6 | 1072 | ctx->dev = dev; |
a43b933b | 1073 | ctx->suspended = true; |
e1a7b9b4 | 1074 | ctx->driver_data = of_device_get_match_data(dev); |
bb7704d6 | 1075 | |
1417f109 SP |
1076 | if (of_property_read_bool(dev->of_node, "samsung,invert-vden")) |
1077 | ctx->vidcon1 |= VIDCON1_INV_VDEN; | |
1078 | if (of_property_read_bool(dev->of_node, "samsung,invert-vclk")) | |
1079 | ctx->vidcon1 |= VIDCON1_INV_VCLK; | |
562ad9f4 | 1080 | |
3854fab2 YC |
1081 | i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings"); |
1082 | if (i80_if_timings) { | |
1083 | u32 val; | |
1084 | ||
1085 | ctx->i80_if = true; | |
1086 | ||
1087 | if (ctx->driver_data->has_vidoutcon) | |
1088 | ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0; | |
1089 | else | |
1090 | ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0; | |
1091 | /* | |
1092 | * The user manual describes that this "DSI_EN" bit is required | |
1093 | * to enable I80 24-bit data interface. | |
1094 | */ | |
1095 | ctx->vidcon0 |= VIDCON0_DSI_EN; | |
1096 | ||
1097 | if (of_property_read_u32(i80_if_timings, "cs-setup", &val)) | |
1098 | val = 0; | |
1099 | ctx->i80ifcon = LCD_CS_SETUP(val); | |
1100 | if (of_property_read_u32(i80_if_timings, "wr-setup", &val)) | |
1101 | val = 0; | |
1102 | ctx->i80ifcon |= LCD_WR_SETUP(val); | |
1103 | if (of_property_read_u32(i80_if_timings, "wr-active", &val)) | |
1104 | val = 1; | |
1105 | ctx->i80ifcon |= LCD_WR_ACTIVE(val); | |
1106 | if (of_property_read_u32(i80_if_timings, "wr-hold", &val)) | |
1107 | val = 0; | |
1108 | ctx->i80ifcon |= LCD_WR_HOLD(val); | |
1109 | } | |
1110 | of_node_put(i80_if_timings); | |
1111 | ||
1112 | ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node, | |
1113 | "samsung,sysreg"); | |
1114 | if (IS_ERR(ctx->sysreg)) { | |
1115 | dev_warn(dev, "failed to get system register.\n"); | |
1116 | ctx->sysreg = NULL; | |
1117 | } | |
1118 | ||
a968e727 SP |
1119 | ctx->bus_clk = devm_clk_get(dev, "fimd"); |
1120 | if (IS_ERR(ctx->bus_clk)) { | |
1121 | dev_err(dev, "failed to get bus clock\n"); | |
86650408 | 1122 | return PTR_ERR(ctx->bus_clk); |
a968e727 SP |
1123 | } |
1124 | ||
1125 | ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd"); | |
1126 | if (IS_ERR(ctx->lcd_clk)) { | |
1127 | dev_err(dev, "failed to get lcd clock\n"); | |
86650408 | 1128 | return PTR_ERR(ctx->lcd_clk); |
a968e727 | 1129 | } |
1c248b7d | 1130 | |
1c248b7d | 1131 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1c248b7d | 1132 | |
d873ab99 | 1133 | ctx->regs = devm_ioremap_resource(dev, res); |
86650408 AH |
1134 | if (IS_ERR(ctx->regs)) |
1135 | return PTR_ERR(ctx->regs); | |
1c248b7d | 1136 | |
3854fab2 YC |
1137 | res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, |
1138 | ctx->i80_if ? "lcd_sys" : "vsync"); | |
1c248b7d ID |
1139 | if (!res) { |
1140 | dev_err(dev, "irq request failed.\n"); | |
86650408 | 1141 | return -ENXIO; |
1c248b7d ID |
1142 | } |
1143 | ||
055e0c06 | 1144 | ret = devm_request_irq(dev, res->start, fimd_irq_handler, |
edc57266 SK |
1145 | 0, "drm_fimd", ctx); |
1146 | if (ret) { | |
1c248b7d | 1147 | dev_err(dev, "irq request failed.\n"); |
86650408 | 1148 | return ret; |
1c248b7d ID |
1149 | } |
1150 | ||
57ed0f7b | 1151 | init_waitqueue_head(&ctx->wait_vsync_queue); |
01ce113c | 1152 | atomic_set(&ctx->wait_vsync_event, 0); |
1c248b7d | 1153 | |
e152dbd7 | 1154 | platform_set_drvdata(pdev, ctx); |
14b6873a | 1155 | |
cf67cc9a GP |
1156 | ctx->encoder = exynos_dpi_probe(dev); |
1157 | if (IS_ERR(ctx->encoder)) | |
1158 | return PTR_ERR(ctx->encoder); | |
f37cd5e8 | 1159 | |
e152dbd7 | 1160 | pm_runtime_enable(dev); |
f37cd5e8 | 1161 | |
e152dbd7 | 1162 | ret = component_add(dev, &fimd_component_ops); |
df5225bc ID |
1163 | if (ret) |
1164 | goto err_disable_pm_runtime; | |
1165 | ||
1166 | return ret; | |
1167 | ||
1168 | err_disable_pm_runtime: | |
e152dbd7 | 1169 | pm_runtime_disable(dev); |
df5225bc | 1170 | |
df5225bc | 1171 | return ret; |
f37cd5e8 | 1172 | } |
cb91f6a0 | 1173 | |
f37cd5e8 ID |
1174 | static int fimd_remove(struct platform_device *pdev) |
1175 | { | |
af65c804 | 1176 | pm_runtime_disable(&pdev->dev); |
5d55393a | 1177 | |
df5225bc | 1178 | component_del(&pdev->dev, &fimd_component_ops); |
df5225bc | 1179 | |
5d55393a | 1180 | return 0; |
e30d4bcf ID |
1181 | } |
1182 | ||
41571976 GP |
1183 | #ifdef CONFIG_PM |
1184 | static int exynos_fimd_suspend(struct device *dev) | |
1185 | { | |
1186 | struct fimd_context *ctx = dev_get_drvdata(dev); | |
1187 | ||
1188 | clk_disable_unprepare(ctx->lcd_clk); | |
1189 | clk_disable_unprepare(ctx->bus_clk); | |
1190 | ||
1191 | return 0; | |
1192 | } | |
1193 | ||
1194 | static int exynos_fimd_resume(struct device *dev) | |
1195 | { | |
1196 | struct fimd_context *ctx = dev_get_drvdata(dev); | |
1197 | int ret; | |
1198 | ||
1199 | ret = clk_prepare_enable(ctx->bus_clk); | |
1200 | if (ret < 0) { | |
1201 | DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret); | |
1202 | return ret; | |
1203 | } | |
1204 | ||
1205 | ret = clk_prepare_enable(ctx->lcd_clk); | |
1206 | if (ret < 0) { | |
1207 | DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret); | |
1208 | return ret; | |
1209 | } | |
1210 | ||
1211 | return 0; | |
1212 | } | |
1213 | #endif | |
1214 | ||
1215 | static const struct dev_pm_ops exynos_fimd_pm_ops = { | |
1216 | SET_RUNTIME_PM_OPS(exynos_fimd_suspend, exynos_fimd_resume, NULL) | |
1217 | }; | |
1218 | ||
132a5b91 | 1219 | struct platform_driver fimd_driver = { |
1c248b7d | 1220 | .probe = fimd_probe, |
56550d94 | 1221 | .remove = fimd_remove, |
1c248b7d ID |
1222 | .driver = { |
1223 | .name = "exynos4-fb", | |
1224 | .owner = THIS_MODULE, | |
41571976 | 1225 | .pm = &exynos_fimd_pm_ops, |
2d3f173c | 1226 | .of_match_table = fimd_driver_dt_match, |
1c248b7d ID |
1227 | }, |
1228 | }; |