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1c248b7d ID |
1 | /* exynos_drm_fimd.c |
2 | * | |
3 | * Copyright (C) 2011 Samsung Electronics Co.Ltd | |
4 | * Authors: | |
5 | * Joonyoung Shim <jy0922.shim@samsung.com> | |
6 | * Inki Dae <inki.dae@samsung.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | */ | |
760285e7 | 14 | #include <drm/drmP.h> |
1c248b7d ID |
15 | |
16 | #include <linux/kernel.h> | |
1c248b7d ID |
17 | #include <linux/platform_device.h> |
18 | #include <linux/clk.h> | |
3f1c781d | 19 | #include <linux/of.h> |
d636ead8 | 20 | #include <linux/of_device.h> |
cb91f6a0 | 21 | #include <linux/pm_runtime.h> |
f37cd5e8 | 22 | #include <linux/component.h> |
3854fab2 YC |
23 | #include <linux/mfd/syscon.h> |
24 | #include <linux/regmap.h> | |
1c248b7d | 25 | |
7f4596f4 | 26 | #include <video/of_display_timing.h> |
111e6055 | 27 | #include <video/of_videomode.h> |
5a213a55 | 28 | #include <video/samsung_fimd.h> |
1c248b7d | 29 | #include <drm/exynos_drm.h> |
1c248b7d ID |
30 | |
31 | #include "exynos_drm_drv.h" | |
32 | #include "exynos_drm_fbdev.h" | |
33 | #include "exynos_drm_crtc.h" | |
7ee14cdc | 34 | #include "exynos_drm_plane.h" |
bcc5cd1c | 35 | #include "exynos_drm_iommu.h" |
1c248b7d ID |
36 | |
37 | /* | |
b8654b37 | 38 | * FIMD stands for Fully Interactive Mobile Display and |
1c248b7d ID |
39 | * as a display controller, it transfers contents drawn on memory |
40 | * to a LCD Panel through Display Interfaces such as RGB or | |
41 | * CPU Interface. | |
42 | */ | |
43 | ||
111e6055 | 44 | #define FIMD_DEFAULT_FRAMERATE 60 |
66367461 | 45 | #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 |
111e6055 | 46 | |
1c248b7d ID |
47 | /* position control register for hardware window 0, 2 ~ 4.*/ |
48 | #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16) | |
49 | #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16) | |
0f10cf14 LKA |
50 | /* |
51 | * size control register for hardware windows 0 and alpha control register | |
52 | * for hardware windows 1 ~ 4 | |
53 | */ | |
54 | #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16) | |
55 | /* size control register for hardware windows 1 ~ 2. */ | |
1c248b7d ID |
56 | #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16) |
57 | ||
453b44a3 GP |
58 | #define VIDWnALPHA0(win) (VIDW_ALPHA + 0x00 + (win) * 8) |
59 | #define VIDWnALPHA1(win) (VIDW_ALPHA + 0x04 + (win) * 8) | |
60 | ||
1c248b7d ID |
61 | #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8) |
62 | #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8) | |
63 | #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4) | |
64 | ||
65 | /* color key control register for hardware window 1 ~ 4. */ | |
0f10cf14 | 66 | #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8)) |
1c248b7d | 67 | /* color key value register for hardware window 1 ~ 4. */ |
0f10cf14 | 68 | #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8)) |
1c248b7d | 69 | |
3854fab2 YC |
70 | /* I80 / RGB trigger control register */ |
71 | #define TRIGCON 0x1A4 | |
72 | #define TRGMODE_I80_RGB_ENABLE_I80 (1 << 0) | |
73 | #define SWTRGCMD_I80_RGB_ENABLE (1 << 1) | |
74 | ||
75 | /* display mode change control register except exynos4 */ | |
76 | #define VIDOUT_CON 0x000 | |
77 | #define VIDOUT_CON_F_I80_LDI0 (0x2 << 8) | |
78 | ||
79 | /* I80 interface control for main LDI register */ | |
80 | #define I80IFCONFAx(x) (0x1B0 + (x) * 4) | |
81 | #define I80IFCONFBx(x) (0x1B8 + (x) * 4) | |
82 | #define LCD_CS_SETUP(x) ((x) << 16) | |
83 | #define LCD_WR_SETUP(x) ((x) << 12) | |
84 | #define LCD_WR_ACTIVE(x) ((x) << 8) | |
85 | #define LCD_WR_HOLD(x) ((x) << 4) | |
86 | #define I80IFEN_ENABLE (1 << 0) | |
87 | ||
1c248b7d ID |
88 | /* FIMD has totally five hardware windows. */ |
89 | #define WINDOWS_NR 5 | |
90 | ||
e2e13389 LKA |
91 | struct fimd_driver_data { |
92 | unsigned int timing_base; | |
3854fab2 YC |
93 | unsigned int lcdblk_offset; |
94 | unsigned int lcdblk_vt_shift; | |
95 | unsigned int lcdblk_bypass_shift; | |
de7af100 TF |
96 | |
97 | unsigned int has_shadowcon:1; | |
411d9ed4 | 98 | unsigned int has_clksel:1; |
5cc4621a | 99 | unsigned int has_limited_fmt:1; |
3854fab2 | 100 | unsigned int has_vidoutcon:1; |
3c3c9c1d | 101 | unsigned int has_vtsel:1; |
e2e13389 LKA |
102 | }; |
103 | ||
725ddead TF |
104 | static struct fimd_driver_data s3c64xx_fimd_driver_data = { |
105 | .timing_base = 0x0, | |
106 | .has_clksel = 1, | |
5cc4621a | 107 | .has_limited_fmt = 1, |
725ddead TF |
108 | }; |
109 | ||
d6ce7b58 ID |
110 | static struct fimd_driver_data exynos3_fimd_driver_data = { |
111 | .timing_base = 0x20000, | |
112 | .lcdblk_offset = 0x210, | |
113 | .lcdblk_bypass_shift = 1, | |
114 | .has_shadowcon = 1, | |
115 | .has_vidoutcon = 1, | |
116 | }; | |
117 | ||
6ecf18f9 | 118 | static struct fimd_driver_data exynos4_fimd_driver_data = { |
e2e13389 | 119 | .timing_base = 0x0, |
3854fab2 YC |
120 | .lcdblk_offset = 0x210, |
121 | .lcdblk_vt_shift = 10, | |
122 | .lcdblk_bypass_shift = 1, | |
de7af100 | 123 | .has_shadowcon = 1, |
3c3c9c1d | 124 | .has_vtsel = 1, |
e2e13389 LKA |
125 | }; |
126 | ||
dcb622aa YC |
127 | static struct fimd_driver_data exynos4415_fimd_driver_data = { |
128 | .timing_base = 0x20000, | |
129 | .lcdblk_offset = 0x210, | |
130 | .lcdblk_vt_shift = 10, | |
131 | .lcdblk_bypass_shift = 1, | |
132 | .has_shadowcon = 1, | |
133 | .has_vidoutcon = 1, | |
3c3c9c1d | 134 | .has_vtsel = 1, |
dcb622aa YC |
135 | }; |
136 | ||
6ecf18f9 | 137 | static struct fimd_driver_data exynos5_fimd_driver_data = { |
e2e13389 | 138 | .timing_base = 0x20000, |
3854fab2 YC |
139 | .lcdblk_offset = 0x214, |
140 | .lcdblk_vt_shift = 24, | |
141 | .lcdblk_bypass_shift = 15, | |
de7af100 | 142 | .has_shadowcon = 1, |
3854fab2 | 143 | .has_vidoutcon = 1, |
3c3c9c1d | 144 | .has_vtsel = 1, |
e2e13389 LKA |
145 | }; |
146 | ||
1c248b7d | 147 | struct fimd_context { |
bb7704d6 | 148 | struct device *dev; |
40c8ab4b | 149 | struct drm_device *drm_dev; |
93bca243 | 150 | struct exynos_drm_crtc *crtc; |
7ee14cdc | 151 | struct exynos_drm_plane planes[WINDOWS_NR]; |
1c248b7d ID |
152 | struct clk *bus_clk; |
153 | struct clk *lcd_clk; | |
1c248b7d | 154 | void __iomem *regs; |
3854fab2 | 155 | struct regmap *sysreg; |
1c248b7d ID |
156 | unsigned int default_win; |
157 | unsigned long irq_flags; | |
3854fab2 | 158 | u32 vidcon0; |
1c248b7d | 159 | u32 vidcon1; |
3854fab2 YC |
160 | u32 vidout_con; |
161 | u32 i80ifcon; | |
162 | bool i80_if; | |
cb91f6a0 | 163 | bool suspended; |
080be03d | 164 | int pipe; |
01ce113c P |
165 | wait_queue_head_t wait_vsync_queue; |
166 | atomic_t wait_vsync_event; | |
3854fab2 YC |
167 | atomic_t win_updated; |
168 | atomic_t triggering; | |
1c248b7d | 169 | |
562ad9f4 | 170 | struct exynos_drm_panel_info panel; |
18873465 | 171 | struct fimd_driver_data *driver_data; |
000cc920 | 172 | struct exynos_drm_display *display; |
1c248b7d ID |
173 | }; |
174 | ||
d636ead8 | 175 | static const struct of_device_id fimd_driver_dt_match[] = { |
725ddead TF |
176 | { .compatible = "samsung,s3c6400-fimd", |
177 | .data = &s3c64xx_fimd_driver_data }, | |
d6ce7b58 ID |
178 | { .compatible = "samsung,exynos3250-fimd", |
179 | .data = &exynos3_fimd_driver_data }, | |
5830daf8 | 180 | { .compatible = "samsung,exynos4210-fimd", |
d636ead8 | 181 | .data = &exynos4_fimd_driver_data }, |
dcb622aa YC |
182 | { .compatible = "samsung,exynos4415-fimd", |
183 | .data = &exynos4415_fimd_driver_data }, | |
5830daf8 | 184 | { .compatible = "samsung,exynos5250-fimd", |
d636ead8 JS |
185 | .data = &exynos5_fimd_driver_data }, |
186 | {}, | |
187 | }; | |
0262ceeb | 188 | MODULE_DEVICE_TABLE(of, fimd_driver_dt_match); |
d636ead8 | 189 | |
e2e13389 LKA |
190 | static inline struct fimd_driver_data *drm_fimd_get_driver_data( |
191 | struct platform_device *pdev) | |
192 | { | |
d636ead8 JS |
193 | const struct of_device_id *of_id = |
194 | of_match_device(fimd_driver_dt_match, &pdev->dev); | |
195 | ||
2d3f173c | 196 | return (struct fimd_driver_data *)of_id->data; |
e2e13389 LKA |
197 | } |
198 | ||
93bca243 | 199 | static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc) |
f13bdbd1 | 200 | { |
93bca243 | 201 | struct fimd_context *ctx = crtc->ctx; |
f13bdbd1 AA |
202 | |
203 | if (ctx->suspended) | |
204 | return; | |
205 | ||
206 | atomic_set(&ctx->wait_vsync_event, 1); | |
207 | ||
208 | /* | |
209 | * wait for FIMD to signal VSYNC interrupt or return after | |
210 | * timeout which is set to 50ms (refresh rate of 20). | |
211 | */ | |
212 | if (!wait_event_timeout(ctx->wait_vsync_queue, | |
213 | !atomic_read(&ctx->wait_vsync_event), | |
214 | HZ/20)) | |
215 | DRM_DEBUG_KMS("vblank wait timed out.\n"); | |
216 | } | |
217 | ||
f181a543 YC |
218 | static void fimd_enable_video_output(struct fimd_context *ctx, int win, |
219 | bool enable) | |
220 | { | |
221 | u32 val = readl(ctx->regs + WINCON(win)); | |
222 | ||
223 | if (enable) | |
224 | val |= WINCONx_ENWIN; | |
225 | else | |
226 | val &= ~WINCONx_ENWIN; | |
227 | ||
228 | writel(val, ctx->regs + WINCON(win)); | |
229 | } | |
230 | ||
999d8b31 YC |
231 | static void fimd_enable_shadow_channel_path(struct fimd_context *ctx, int win, |
232 | bool enable) | |
233 | { | |
234 | u32 val = readl(ctx->regs + SHADOWCON); | |
235 | ||
236 | if (enable) | |
237 | val |= SHADOWCON_CHx_ENABLE(win); | |
238 | else | |
239 | val &= ~SHADOWCON_CHx_ENABLE(win); | |
240 | ||
241 | writel(val, ctx->regs + SHADOWCON); | |
242 | } | |
243 | ||
92dc7a04 | 244 | static void fimd_clear_channel(struct fimd_context *ctx) |
f13bdbd1 | 245 | { |
f13bdbd1 AA |
246 | int win, ch_enabled = 0; |
247 | ||
248 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
249 | ||
250 | /* Check if any channel is enabled. */ | |
251 | for (win = 0; win < WINDOWS_NR; win++) { | |
eb8a3bf7 MS |
252 | u32 val = readl(ctx->regs + WINCON(win)); |
253 | ||
254 | if (val & WINCONx_ENWIN) { | |
f181a543 | 255 | fimd_enable_video_output(ctx, win, false); |
eb8a3bf7 | 256 | |
999d8b31 YC |
257 | if (ctx->driver_data->has_shadowcon) |
258 | fimd_enable_shadow_channel_path(ctx, win, | |
259 | false); | |
260 | ||
f13bdbd1 AA |
261 | ch_enabled = 1; |
262 | } | |
263 | } | |
264 | ||
265 | /* Wait for vsync, as disable channel takes effect at next vsync */ | |
eb8a3bf7 MS |
266 | if (ch_enabled) { |
267 | unsigned int state = ctx->suspended; | |
268 | ||
269 | ctx->suspended = 0; | |
92dc7a04 | 270 | fimd_wait_for_vblank(ctx->crtc); |
eb8a3bf7 MS |
271 | ctx->suspended = state; |
272 | } | |
f13bdbd1 AA |
273 | } |
274 | ||
cdbfca89 | 275 | static int fimd_iommu_attach_devices(struct fimd_context *ctx, |
f37cd5e8 | 276 | struct drm_device *drm_dev) |
40c8ab4b | 277 | { |
40c8ab4b | 278 | |
080be03d | 279 | /* attach this sub driver to iommu mapping if supported. */ |
f13bdbd1 | 280 | if (is_drm_iommu_supported(ctx->drm_dev)) { |
efa75bcd AK |
281 | int ret; |
282 | ||
f13bdbd1 AA |
283 | /* |
284 | * If any channel is already active, iommu will throw | |
285 | * a PAGE FAULT when enabled. So clear any channel if enabled. | |
286 | */ | |
92dc7a04 | 287 | fimd_clear_channel(ctx); |
efa75bcd AK |
288 | ret = drm_iommu_attach_device(ctx->drm_dev, ctx->dev); |
289 | if (ret) { | |
290 | DRM_ERROR("drm_iommu_attach failed.\n"); | |
291 | return ret; | |
292 | } | |
293 | ||
f13bdbd1 | 294 | } |
c32b06ef | 295 | |
080be03d | 296 | return 0; |
ec05da95 ID |
297 | } |
298 | ||
cdbfca89 | 299 | static void fimd_iommu_detach_devices(struct fimd_context *ctx) |
ec05da95 | 300 | { |
080be03d SP |
301 | /* detach this sub driver from iommu mapping if supported. */ |
302 | if (is_drm_iommu_supported(ctx->drm_dev)) | |
303 | drm_iommu_detach_device(ctx->drm_dev, ctx->dev); | |
ec05da95 ID |
304 | } |
305 | ||
a968e727 SP |
306 | static u32 fimd_calc_clkdiv(struct fimd_context *ctx, |
307 | const struct drm_display_mode *mode) | |
308 | { | |
309 | unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh; | |
310 | u32 clkdiv; | |
311 | ||
3854fab2 YC |
312 | if (ctx->i80_if) { |
313 | /* | |
314 | * The frame done interrupt should be occurred prior to the | |
315 | * next TE signal. | |
316 | */ | |
317 | ideal_clk *= 2; | |
318 | } | |
319 | ||
a968e727 SP |
320 | /* Find the clock divider value that gets us closest to ideal_clk */ |
321 | clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk); | |
322 | ||
323 | return (clkdiv < 0x100) ? clkdiv : 0xff; | |
324 | } | |
325 | ||
93bca243 | 326 | static bool fimd_mode_fixup(struct exynos_drm_crtc *crtc, |
a968e727 SP |
327 | const struct drm_display_mode *mode, |
328 | struct drm_display_mode *adjusted_mode) | |
329 | { | |
330 | if (adjusted_mode->vrefresh == 0) | |
331 | adjusted_mode->vrefresh = FIMD_DEFAULT_FRAMERATE; | |
332 | ||
333 | return true; | |
334 | } | |
335 | ||
93bca243 | 336 | static void fimd_commit(struct exynos_drm_crtc *crtc) |
1c248b7d | 337 | { |
93bca243 | 338 | struct fimd_context *ctx = crtc->ctx; |
a8dc5ed6 | 339 | struct drm_display_mode *mode = &crtc->base.mode; |
3854fab2 YC |
340 | struct fimd_driver_data *driver_data = ctx->driver_data; |
341 | void *timing_base = ctx->regs + driver_data->timing_base; | |
342 | u32 val, clkdiv; | |
1c248b7d | 343 | |
e30d4bcf ID |
344 | if (ctx->suspended) |
345 | return; | |
346 | ||
a968e727 SP |
347 | /* nothing to do if we haven't set the mode yet */ |
348 | if (mode->htotal == 0 || mode->vtotal == 0) | |
349 | return; | |
350 | ||
3854fab2 YC |
351 | if (ctx->i80_if) { |
352 | val = ctx->i80ifcon | I80IFEN_ENABLE; | |
353 | writel(val, timing_base + I80IFCONFAx(0)); | |
354 | ||
355 | /* disable auto frame rate */ | |
356 | writel(0, timing_base + I80IFCONFBx(0)); | |
357 | ||
358 | /* set video type selection to I80 interface */ | |
3c3c9c1d JS |
359 | if (driver_data->has_vtsel && ctx->sysreg && |
360 | regmap_update_bits(ctx->sysreg, | |
3854fab2 YC |
361 | driver_data->lcdblk_offset, |
362 | 0x3 << driver_data->lcdblk_vt_shift, | |
363 | 0x1 << driver_data->lcdblk_vt_shift)) { | |
364 | DRM_ERROR("Failed to update sysreg for I80 i/f.\n"); | |
365 | return; | |
366 | } | |
367 | } else { | |
368 | int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd; | |
369 | u32 vidcon1; | |
370 | ||
371 | /* setup polarity values */ | |
372 | vidcon1 = ctx->vidcon1; | |
373 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
374 | vidcon1 |= VIDCON1_INV_VSYNC; | |
375 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
376 | vidcon1 |= VIDCON1_INV_HSYNC; | |
377 | writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1); | |
378 | ||
379 | /* setup vertical timing values. */ | |
380 | vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; | |
381 | vbpd = mode->crtc_vtotal - mode->crtc_vsync_end; | |
382 | vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay; | |
383 | ||
384 | val = VIDTCON0_VBPD(vbpd - 1) | | |
385 | VIDTCON0_VFPD(vfpd - 1) | | |
386 | VIDTCON0_VSPW(vsync_len - 1); | |
387 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON0); | |
388 | ||
389 | /* setup horizontal timing values. */ | |
390 | hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; | |
391 | hbpd = mode->crtc_htotal - mode->crtc_hsync_end; | |
392 | hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay; | |
393 | ||
394 | val = VIDTCON1_HBPD(hbpd - 1) | | |
395 | VIDTCON1_HFPD(hfpd - 1) | | |
396 | VIDTCON1_HSPW(hsync_len - 1); | |
397 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON1); | |
398 | } | |
399 | ||
400 | if (driver_data->has_vidoutcon) | |
401 | writel(ctx->vidout_con, timing_base + VIDOUT_CON); | |
402 | ||
403 | /* set bypass selection */ | |
404 | if (ctx->sysreg && regmap_update_bits(ctx->sysreg, | |
405 | driver_data->lcdblk_offset, | |
406 | 0x1 << driver_data->lcdblk_bypass_shift, | |
407 | 0x1 << driver_data->lcdblk_bypass_shift)) { | |
408 | DRM_ERROR("Failed to update sysreg for bypass setting.\n"); | |
409 | return; | |
410 | } | |
1c248b7d ID |
411 | |
412 | /* setup horizontal and vertical display size. */ | |
a968e727 SP |
413 | val = VIDTCON2_LINEVAL(mode->vdisplay - 1) | |
414 | VIDTCON2_HOZVAL(mode->hdisplay - 1) | | |
415 | VIDTCON2_LINEVAL_E(mode->vdisplay - 1) | | |
416 | VIDTCON2_HOZVAL_E(mode->hdisplay - 1); | |
e2e13389 | 417 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON2); |
1c248b7d | 418 | |
1d531062 AH |
419 | /* |
420 | * fields of register with prefix '_F' would be updated | |
421 | * at vsync(same as dma start) | |
422 | */ | |
3854fab2 YC |
423 | val = ctx->vidcon0; |
424 | val |= VIDCON0_ENVID | VIDCON0_ENVID_F; | |
1c248b7d | 425 | |
1d531062 | 426 | if (ctx->driver_data->has_clksel) |
411d9ed4 | 427 | val |= VIDCON0_CLKSEL_LCD; |
411d9ed4 | 428 | |
a968e727 SP |
429 | clkdiv = fimd_calc_clkdiv(ctx, mode); |
430 | if (clkdiv > 1) | |
431 | val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR; | |
1c248b7d | 432 | |
1c248b7d ID |
433 | writel(val, ctx->regs + VIDCON0); |
434 | } | |
435 | ||
93bca243 | 436 | static int fimd_enable_vblank(struct exynos_drm_crtc *crtc) |
1c248b7d | 437 | { |
93bca243 | 438 | struct fimd_context *ctx = crtc->ctx; |
1c248b7d ID |
439 | u32 val; |
440 | ||
cb91f6a0 JS |
441 | if (ctx->suspended) |
442 | return -EPERM; | |
443 | ||
1c248b7d ID |
444 | if (!test_and_set_bit(0, &ctx->irq_flags)) { |
445 | val = readl(ctx->regs + VIDINTCON0); | |
446 | ||
447 | val |= VIDINTCON0_INT_ENABLE; | |
1c248b7d | 448 | |
1c905d95 YC |
449 | if (ctx->i80_if) { |
450 | val |= VIDINTCON0_INT_I80IFDONE; | |
451 | val |= VIDINTCON0_INT_SYSMAINCON; | |
452 | val &= ~VIDINTCON0_INT_SYSSUBCON; | |
453 | } else { | |
454 | val |= VIDINTCON0_INT_FRAME; | |
455 | ||
456 | val &= ~VIDINTCON0_FRAMESEL0_MASK; | |
457 | val |= VIDINTCON0_FRAMESEL0_VSYNC; | |
458 | val &= ~VIDINTCON0_FRAMESEL1_MASK; | |
459 | val |= VIDINTCON0_FRAMESEL1_NONE; | |
460 | } | |
1c248b7d ID |
461 | |
462 | writel(val, ctx->regs + VIDINTCON0); | |
463 | } | |
464 | ||
465 | return 0; | |
466 | } | |
467 | ||
93bca243 | 468 | static void fimd_disable_vblank(struct exynos_drm_crtc *crtc) |
1c248b7d | 469 | { |
93bca243 | 470 | struct fimd_context *ctx = crtc->ctx; |
1c248b7d ID |
471 | u32 val; |
472 | ||
cb91f6a0 JS |
473 | if (ctx->suspended) |
474 | return; | |
475 | ||
1c248b7d ID |
476 | if (test_and_clear_bit(0, &ctx->irq_flags)) { |
477 | val = readl(ctx->regs + VIDINTCON0); | |
478 | ||
1c248b7d ID |
479 | val &= ~VIDINTCON0_INT_ENABLE; |
480 | ||
1c905d95 YC |
481 | if (ctx->i80_if) { |
482 | val &= ~VIDINTCON0_INT_I80IFDONE; | |
483 | val &= ~VIDINTCON0_INT_SYSMAINCON; | |
484 | val &= ~VIDINTCON0_INT_SYSSUBCON; | |
485 | } else | |
486 | val &= ~VIDINTCON0_INT_FRAME; | |
487 | ||
1c248b7d ID |
488 | writel(val, ctx->regs + VIDINTCON0); |
489 | } | |
490 | } | |
491 | ||
bb7704d6 | 492 | static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win) |
1c248b7d | 493 | { |
7ee14cdc | 494 | struct exynos_drm_plane *plane = &ctx->planes[win]; |
1c248b7d ID |
495 | unsigned long val; |
496 | ||
1c248b7d ID |
497 | val = WINCONx_ENWIN; |
498 | ||
5cc4621a ID |
499 | /* |
500 | * In case of s3c64xx, window 0 doesn't support alpha channel. | |
501 | * So the request format is ARGB8888 then change it to XRGB8888. | |
502 | */ | |
503 | if (ctx->driver_data->has_limited_fmt && !win) { | |
7ee14cdc GP |
504 | if (plane->pixel_format == DRM_FORMAT_ARGB8888) |
505 | plane->pixel_format = DRM_FORMAT_XRGB8888; | |
5cc4621a ID |
506 | } |
507 | ||
7ee14cdc | 508 | switch (plane->pixel_format) { |
a4f38a80 | 509 | case DRM_FORMAT_C8: |
1c248b7d ID |
510 | val |= WINCON0_BPPMODE_8BPP_PALETTE; |
511 | val |= WINCONx_BURSTLEN_8WORD; | |
512 | val |= WINCONx_BYTSWP; | |
513 | break; | |
a4f38a80 ID |
514 | case DRM_FORMAT_XRGB1555: |
515 | val |= WINCON0_BPPMODE_16BPP_1555; | |
516 | val |= WINCONx_HAWSWP; | |
517 | val |= WINCONx_BURSTLEN_16WORD; | |
518 | break; | |
519 | case DRM_FORMAT_RGB565: | |
1c248b7d ID |
520 | val |= WINCON0_BPPMODE_16BPP_565; |
521 | val |= WINCONx_HAWSWP; | |
522 | val |= WINCONx_BURSTLEN_16WORD; | |
523 | break; | |
a4f38a80 | 524 | case DRM_FORMAT_XRGB8888: |
1c248b7d ID |
525 | val |= WINCON0_BPPMODE_24BPP_888; |
526 | val |= WINCONx_WSWP; | |
527 | val |= WINCONx_BURSTLEN_16WORD; | |
528 | break; | |
a4f38a80 ID |
529 | case DRM_FORMAT_ARGB8888: |
530 | val |= WINCON1_BPPMODE_25BPP_A1888 | |
1c248b7d ID |
531 | | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL; |
532 | val |= WINCONx_WSWP; | |
533 | val |= WINCONx_BURSTLEN_16WORD; | |
534 | break; | |
535 | default: | |
536 | DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n"); | |
537 | ||
538 | val |= WINCON0_BPPMODE_24BPP_888; | |
539 | val |= WINCONx_WSWP; | |
540 | val |= WINCONx_BURSTLEN_16WORD; | |
541 | break; | |
542 | } | |
543 | ||
7ee14cdc | 544 | DRM_DEBUG_KMS("bpp = %d\n", plane->bpp); |
1c248b7d | 545 | |
66367461 RS |
546 | /* |
547 | * In case of exynos, setting dma-burst to 16Word causes permanent | |
548 | * tearing for very small buffers, e.g. cursor buffer. Burst Mode | |
8837deea GP |
549 | * switching which is based on plane size is not recommended as |
550 | * plane size varies alot towards the end of the screen and rapid | |
66367461 RS |
551 | * movement causes unstable DMA which results into iommu crash/tear. |
552 | */ | |
553 | ||
7ee14cdc | 554 | if (plane->fb_width < MIN_FB_WIDTH_FOR_16WORD_BURST) { |
66367461 RS |
555 | val &= ~WINCONx_BURSTLEN_MASK; |
556 | val |= WINCONx_BURSTLEN_4WORD; | |
557 | } | |
558 | ||
1c248b7d | 559 | writel(val, ctx->regs + WINCON(win)); |
453b44a3 GP |
560 | |
561 | /* hardware window 0 doesn't support alpha channel. */ | |
562 | if (win != 0) { | |
563 | /* OSD alpha */ | |
564 | val = VIDISD14C_ALPHA0_R(0xf) | | |
565 | VIDISD14C_ALPHA0_G(0xf) | | |
566 | VIDISD14C_ALPHA0_B(0xf) | | |
567 | VIDISD14C_ALPHA1_R(0xf) | | |
568 | VIDISD14C_ALPHA1_G(0xf) | | |
569 | VIDISD14C_ALPHA1_B(0xf); | |
570 | ||
571 | writel(val, ctx->regs + VIDOSD_C(win)); | |
572 | ||
573 | val = VIDW_ALPHA_R(0xf) | VIDW_ALPHA_G(0xf) | | |
574 | VIDW_ALPHA_G(0xf); | |
575 | writel(val, ctx->regs + VIDWnALPHA0(win)); | |
576 | writel(val, ctx->regs + VIDWnALPHA1(win)); | |
577 | } | |
1c248b7d ID |
578 | } |
579 | ||
bb7704d6 | 580 | static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win) |
1c248b7d | 581 | { |
1c248b7d ID |
582 | unsigned int keycon0 = 0, keycon1 = 0; |
583 | ||
1c248b7d ID |
584 | keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F | |
585 | WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); | |
586 | ||
587 | keycon1 = WxKEYCON1_COLVAL(0xffffffff); | |
588 | ||
589 | writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); | |
590 | writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); | |
591 | } | |
592 | ||
de7af100 TF |
593 | /** |
594 | * shadow_protect_win() - disable updating values from shadow registers at vsync | |
595 | * | |
596 | * @win: window to protect registers for | |
597 | * @protect: 1 to protect (disable updates) | |
598 | */ | |
599 | static void fimd_shadow_protect_win(struct fimd_context *ctx, | |
6e2a3b66 | 600 | unsigned int win, bool protect) |
de7af100 TF |
601 | { |
602 | u32 reg, bits, val; | |
603 | ||
604 | if (ctx->driver_data->has_shadowcon) { | |
605 | reg = SHADOWCON; | |
606 | bits = SHADOWCON_WINx_PROTECT(win); | |
607 | } else { | |
608 | reg = PRTCON; | |
609 | bits = PRTCON_PROTECT; | |
610 | } | |
611 | ||
612 | val = readl(ctx->regs + reg); | |
613 | if (protect) | |
614 | val |= bits; | |
615 | else | |
616 | val &= ~bits; | |
617 | writel(val, ctx->regs + reg); | |
618 | } | |
619 | ||
6e2a3b66 | 620 | static void fimd_win_commit(struct exynos_drm_crtc *crtc, unsigned int win) |
1c248b7d | 621 | { |
93bca243 | 622 | struct fimd_context *ctx = crtc->ctx; |
7ee14cdc | 623 | struct exynos_drm_plane *plane; |
7ee14cdc GP |
624 | dma_addr_t dma_addr; |
625 | unsigned long val, size, offset; | |
626 | unsigned int last_x, last_y, buf_offsize, line_size; | |
1c248b7d | 627 | |
e30d4bcf ID |
628 | if (ctx->suspended) |
629 | return; | |
630 | ||
37b006e8 | 631 | if (win < 0 || win >= WINDOWS_NR) |
1c248b7d ID |
632 | return; |
633 | ||
7ee14cdc | 634 | plane = &ctx->planes[win]; |
1c248b7d | 635 | |
a43b933b SP |
636 | /* If suspended, enable this on resume */ |
637 | if (ctx->suspended) { | |
7ee14cdc | 638 | plane->resume = true; |
a43b933b SP |
639 | return; |
640 | } | |
641 | ||
1c248b7d | 642 | /* |
de7af100 | 643 | * SHADOWCON/PRTCON register is used for enabling timing. |
1c248b7d ID |
644 | * |
645 | * for example, once only width value of a register is set, | |
646 | * if the dma is started then fimd hardware could malfunction so | |
647 | * with protect window setting, the register fields with prefix '_F' | |
648 | * wouldn't be updated at vsync also but updated once unprotect window | |
649 | * is set. | |
650 | */ | |
651 | ||
652 | /* protect windows */ | |
de7af100 | 653 | fimd_shadow_protect_win(ctx, win, true); |
1c248b7d | 654 | |
7ee14cdc | 655 | |
cb8a3db2 JS |
656 | offset = plane->src_x * (plane->bpp >> 3); |
657 | offset += plane->src_y * plane->pitch; | |
7ee14cdc | 658 | |
1c248b7d | 659 | /* buffer start address */ |
7ee14cdc GP |
660 | dma_addr = plane->dma_addr[0] + offset; |
661 | val = (unsigned long)dma_addr; | |
1c248b7d ID |
662 | writel(val, ctx->regs + VIDWx_BUF_START(win, 0)); |
663 | ||
664 | /* buffer end address */ | |
68a29134 | 665 | size = plane->pitch * plane->crtc_height; |
7ee14cdc | 666 | val = (unsigned long)(dma_addr + size); |
1c248b7d ID |
667 | writel(val, ctx->regs + VIDWx_BUF_END(win, 0)); |
668 | ||
669 | DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n", | |
7ee14cdc | 670 | (unsigned long)dma_addr, val, size); |
19c8b834 | 671 | DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", |
7ee14cdc | 672 | plane->crtc_width, plane->crtc_height); |
1c248b7d ID |
673 | |
674 | /* buffer size */ | |
68a29134 | 675 | buf_offsize = plane->pitch - (plane->crtc_width * (plane->bpp >> 3)); |
7ee14cdc GP |
676 | line_size = plane->crtc_width * (plane->bpp >> 3); |
677 | val = VIDW_BUF_SIZE_OFFSET(buf_offsize) | | |
678 | VIDW_BUF_SIZE_PAGEWIDTH(line_size) | | |
679 | VIDW_BUF_SIZE_OFFSET_E(buf_offsize) | | |
680 | VIDW_BUF_SIZE_PAGEWIDTH_E(line_size); | |
1c248b7d ID |
681 | writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0)); |
682 | ||
683 | /* OSD position */ | |
7ee14cdc GP |
684 | val = VIDOSDxA_TOPLEFT_X(plane->crtc_x) | |
685 | VIDOSDxA_TOPLEFT_Y(plane->crtc_y) | | |
686 | VIDOSDxA_TOPLEFT_X_E(plane->crtc_x) | | |
687 | VIDOSDxA_TOPLEFT_Y_E(plane->crtc_y); | |
1c248b7d ID |
688 | writel(val, ctx->regs + VIDOSD_A(win)); |
689 | ||
7ee14cdc | 690 | last_x = plane->crtc_x + plane->crtc_width; |
f56aad3a JS |
691 | if (last_x) |
692 | last_x--; | |
7ee14cdc | 693 | last_y = plane->crtc_y + plane->crtc_height; |
f56aad3a JS |
694 | if (last_y) |
695 | last_y--; | |
696 | ||
ca555e5a JS |
697 | val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) | |
698 | VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y); | |
699 | ||
1c248b7d ID |
700 | writel(val, ctx->regs + VIDOSD_B(win)); |
701 | ||
19c8b834 | 702 | DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", |
7ee14cdc | 703 | plane->crtc_x, plane->crtc_y, last_x, last_y); |
1c248b7d | 704 | |
1c248b7d ID |
705 | /* OSD size */ |
706 | if (win != 3 && win != 4) { | |
707 | u32 offset = VIDOSD_D(win); | |
708 | if (win == 0) | |
0f10cf14 | 709 | offset = VIDOSD_C(win); |
7ee14cdc | 710 | val = plane->crtc_width * plane->crtc_height; |
1c248b7d ID |
711 | writel(val, ctx->regs + offset); |
712 | ||
713 | DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val); | |
714 | } | |
715 | ||
bb7704d6 | 716 | fimd_win_set_pixfmt(ctx, win); |
1c248b7d ID |
717 | |
718 | /* hardware window 0 doesn't support color key. */ | |
719 | if (win != 0) | |
bb7704d6 | 720 | fimd_win_set_colkey(ctx, win); |
1c248b7d | 721 | |
f181a543 | 722 | fimd_enable_video_output(ctx, win, true); |
ec05da95 | 723 | |
999d8b31 YC |
724 | if (ctx->driver_data->has_shadowcon) |
725 | fimd_enable_shadow_channel_path(ctx, win, true); | |
ec05da95 | 726 | |
74944a58 YC |
727 | /* Enable DMA channel and unprotect windows */ |
728 | fimd_shadow_protect_win(ctx, win, false); | |
729 | ||
7ee14cdc | 730 | plane->enabled = true; |
3854fab2 YC |
731 | |
732 | if (ctx->i80_if) | |
733 | atomic_set(&ctx->win_updated, 1); | |
1c248b7d ID |
734 | } |
735 | ||
6e2a3b66 | 736 | static void fimd_win_disable(struct exynos_drm_crtc *crtc, unsigned int win) |
1c248b7d | 737 | { |
93bca243 | 738 | struct fimd_context *ctx = crtc->ctx; |
7ee14cdc | 739 | struct exynos_drm_plane *plane; |
864ee9e6 | 740 | |
37b006e8 | 741 | if (win < 0 || win >= WINDOWS_NR) |
1c248b7d ID |
742 | return; |
743 | ||
7ee14cdc | 744 | plane = &ctx->planes[win]; |
ec05da95 | 745 | |
db7e55ae P |
746 | if (ctx->suspended) { |
747 | /* do not resume this window*/ | |
7ee14cdc | 748 | plane->resume = false; |
db7e55ae P |
749 | return; |
750 | } | |
751 | ||
1c248b7d | 752 | /* protect windows */ |
de7af100 | 753 | fimd_shadow_protect_win(ctx, win, true); |
1c248b7d | 754 | |
f181a543 | 755 | fimd_enable_video_output(ctx, win, false); |
1c248b7d | 756 | |
999d8b31 YC |
757 | if (ctx->driver_data->has_shadowcon) |
758 | fimd_enable_shadow_channel_path(ctx, win, false); | |
de7af100 | 759 | |
999d8b31 | 760 | /* unprotect windows */ |
de7af100 | 761 | fimd_shadow_protect_win(ctx, win, false); |
ec05da95 | 762 | |
7ee14cdc | 763 | plane->enabled = false; |
1c248b7d ID |
764 | } |
765 | ||
92dc7a04 | 766 | static void fimd_window_suspend(struct fimd_context *ctx) |
a43b933b | 767 | { |
7ee14cdc | 768 | struct exynos_drm_plane *plane; |
a43b933b SP |
769 | int i; |
770 | ||
771 | for (i = 0; i < WINDOWS_NR; i++) { | |
7ee14cdc GP |
772 | plane = &ctx->planes[i]; |
773 | plane->resume = plane->enabled; | |
774 | if (plane->enabled) | |
92dc7a04 | 775 | fimd_win_disable(ctx->crtc, i); |
a43b933b | 776 | } |
a43b933b SP |
777 | } |
778 | ||
92dc7a04 | 779 | static void fimd_window_resume(struct fimd_context *ctx) |
a43b933b | 780 | { |
7ee14cdc | 781 | struct exynos_drm_plane *plane; |
a43b933b SP |
782 | int i; |
783 | ||
784 | for (i = 0; i < WINDOWS_NR; i++) { | |
7ee14cdc GP |
785 | plane = &ctx->planes[i]; |
786 | plane->enabled = plane->resume; | |
787 | plane->resume = false; | |
a43b933b SP |
788 | } |
789 | } | |
790 | ||
92dc7a04 | 791 | static void fimd_apply(struct fimd_context *ctx) |
a43b933b | 792 | { |
7ee14cdc | 793 | struct exynos_drm_plane *plane; |
a43b933b SP |
794 | int i; |
795 | ||
796 | for (i = 0; i < WINDOWS_NR; i++) { | |
7ee14cdc GP |
797 | plane = &ctx->planes[i]; |
798 | if (plane->enabled) | |
92dc7a04 | 799 | fimd_win_commit(ctx->crtc, i); |
d9b68d89 | 800 | else |
92dc7a04 | 801 | fimd_win_disable(ctx->crtc, i); |
a43b933b SP |
802 | } |
803 | ||
92dc7a04 | 804 | fimd_commit(ctx->crtc); |
a43b933b SP |
805 | } |
806 | ||
92dc7a04 | 807 | static int fimd_poweron(struct fimd_context *ctx) |
a43b933b | 808 | { |
a43b933b SP |
809 | int ret; |
810 | ||
811 | if (!ctx->suspended) | |
812 | return 0; | |
813 | ||
814 | ctx->suspended = false; | |
815 | ||
af65c804 SP |
816 | pm_runtime_get_sync(ctx->dev); |
817 | ||
a43b933b SP |
818 | ret = clk_prepare_enable(ctx->bus_clk); |
819 | if (ret < 0) { | |
820 | DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret); | |
821 | goto bus_clk_err; | |
822 | } | |
823 | ||
824 | ret = clk_prepare_enable(ctx->lcd_clk); | |
825 | if (ret < 0) { | |
826 | DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret); | |
827 | goto lcd_clk_err; | |
828 | } | |
829 | ||
830 | /* if vblank was enabled status, enable it again. */ | |
831 | if (test_and_clear_bit(0, &ctx->irq_flags)) { | |
92dc7a04 | 832 | ret = fimd_enable_vblank(ctx->crtc); |
a43b933b SP |
833 | if (ret) { |
834 | DRM_ERROR("Failed to re-enable vblank [%d]\n", ret); | |
835 | goto enable_vblank_err; | |
836 | } | |
837 | } | |
838 | ||
92dc7a04 | 839 | fimd_window_resume(ctx); |
a43b933b | 840 | |
92dc7a04 | 841 | fimd_apply(ctx); |
a43b933b SP |
842 | |
843 | return 0; | |
844 | ||
845 | enable_vblank_err: | |
846 | clk_disable_unprepare(ctx->lcd_clk); | |
847 | lcd_clk_err: | |
848 | clk_disable_unprepare(ctx->bus_clk); | |
849 | bus_clk_err: | |
850 | ctx->suspended = true; | |
851 | return ret; | |
852 | } | |
853 | ||
92dc7a04 | 854 | static int fimd_poweroff(struct fimd_context *ctx) |
a43b933b | 855 | { |
a43b933b SP |
856 | if (ctx->suspended) |
857 | return 0; | |
858 | ||
859 | /* | |
860 | * We need to make sure that all windows are disabled before we | |
861 | * suspend that connector. Otherwise we might try to scan from | |
862 | * a destroyed buffer later. | |
863 | */ | |
92dc7a04 | 864 | fimd_window_suspend(ctx); |
a43b933b SP |
865 | |
866 | clk_disable_unprepare(ctx->lcd_clk); | |
867 | clk_disable_unprepare(ctx->bus_clk); | |
868 | ||
af65c804 SP |
869 | pm_runtime_put_sync(ctx->dev); |
870 | ||
a43b933b SP |
871 | ctx->suspended = true; |
872 | return 0; | |
873 | } | |
874 | ||
93bca243 | 875 | static void fimd_dpms(struct exynos_drm_crtc *crtc, int mode) |
080be03d | 876 | { |
af65c804 | 877 | DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode); |
080be03d | 878 | |
080be03d SP |
879 | switch (mode) { |
880 | case DRM_MODE_DPMS_ON: | |
92dc7a04 | 881 | fimd_poweron(crtc->ctx); |
080be03d SP |
882 | break; |
883 | case DRM_MODE_DPMS_STANDBY: | |
884 | case DRM_MODE_DPMS_SUSPEND: | |
885 | case DRM_MODE_DPMS_OFF: | |
92dc7a04 | 886 | fimd_poweroff(crtc->ctx); |
080be03d SP |
887 | break; |
888 | default: | |
889 | DRM_DEBUG_KMS("unspecified mode %d\n", mode); | |
890 | break; | |
891 | } | |
080be03d SP |
892 | } |
893 | ||
3854fab2 YC |
894 | static void fimd_trigger(struct device *dev) |
895 | { | |
e152dbd7 | 896 | struct fimd_context *ctx = dev_get_drvdata(dev); |
3854fab2 YC |
897 | struct fimd_driver_data *driver_data = ctx->driver_data; |
898 | void *timing_base = ctx->regs + driver_data->timing_base; | |
899 | u32 reg; | |
900 | ||
9b67eb73 | 901 | /* |
1c905d95 YC |
902 | * Skips triggering if in triggering state, because multiple triggering |
903 | * requests can cause panel reset. | |
904 | */ | |
9b67eb73 JS |
905 | if (atomic_read(&ctx->triggering)) |
906 | return; | |
907 | ||
1c905d95 | 908 | /* Enters triggering mode */ |
3854fab2 YC |
909 | atomic_set(&ctx->triggering, 1); |
910 | ||
3854fab2 YC |
911 | reg = readl(timing_base + TRIGCON); |
912 | reg |= (TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE); | |
913 | writel(reg, timing_base + TRIGCON); | |
87ab85b3 YC |
914 | |
915 | /* | |
916 | * Exits triggering mode if vblank is not enabled yet, because when the | |
917 | * VIDINTCON0 register is not set, it can not exit from triggering mode. | |
918 | */ | |
919 | if (!test_bit(0, &ctx->irq_flags)) | |
920 | atomic_set(&ctx->triggering, 0); | |
3854fab2 YC |
921 | } |
922 | ||
93bca243 | 923 | static void fimd_te_handler(struct exynos_drm_crtc *crtc) |
3854fab2 | 924 | { |
93bca243 | 925 | struct fimd_context *ctx = crtc->ctx; |
3854fab2 YC |
926 | |
927 | /* Checks the crtc is detached already from encoder */ | |
928 | if (ctx->pipe < 0 || !ctx->drm_dev) | |
929 | return; | |
930 | ||
3854fab2 YC |
931 | /* |
932 | * If there is a page flip request, triggers and handles the page flip | |
933 | * event so that current fb can be updated into panel GRAM. | |
934 | */ | |
935 | if (atomic_add_unless(&ctx->win_updated, -1, 0)) | |
936 | fimd_trigger(ctx->dev); | |
937 | ||
938 | /* Wakes up vsync event queue */ | |
939 | if (atomic_read(&ctx->wait_vsync_event)) { | |
940 | atomic_set(&ctx->wait_vsync_event, 0); | |
941 | wake_up(&ctx->wait_vsync_queue); | |
3854fab2 | 942 | } |
b301ae24 | 943 | |
adf67abf | 944 | if (test_bit(0, &ctx->irq_flags)) |
b301ae24 | 945 | drm_handle_vblank(ctx->drm_dev, ctx->pipe); |
3854fab2 YC |
946 | } |
947 | ||
48107d7b KK |
948 | static void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable) |
949 | { | |
950 | struct fimd_context *ctx = crtc->ctx; | |
951 | u32 val; | |
952 | ||
953 | /* | |
954 | * Only Exynos 5250, 5260, 5410 and 542x requires enabling DP/MIE | |
955 | * clock. On these SoCs the bootloader may enable it but any | |
956 | * power domain off/on will reset it to disable state. | |
957 | */ | |
958 | if (ctx->driver_data != &exynos5_fimd_driver_data) | |
959 | return; | |
960 | ||
961 | val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE; | |
962 | writel(DP_MIE_CLK_DP_ENABLE, ctx->regs + DP_MIE_CLKCON); | |
963 | } | |
964 | ||
f3aaf762 | 965 | static const struct exynos_drm_crtc_ops fimd_crtc_ops = { |
1c6244c3 | 966 | .dpms = fimd_dpms, |
a968e727 | 967 | .mode_fixup = fimd_mode_fixup, |
1c6244c3 SP |
968 | .commit = fimd_commit, |
969 | .enable_vblank = fimd_enable_vblank, | |
970 | .disable_vblank = fimd_disable_vblank, | |
971 | .wait_for_vblank = fimd_wait_for_vblank, | |
1c6244c3 SP |
972 | .win_commit = fimd_win_commit, |
973 | .win_disable = fimd_win_disable, | |
3854fab2 | 974 | .te_handler = fimd_te_handler, |
48107d7b | 975 | .clock_enable = fimd_dp_clock_enable, |
1c248b7d ID |
976 | }; |
977 | ||
1c248b7d ID |
978 | static irqreturn_t fimd_irq_handler(int irq, void *dev_id) |
979 | { | |
980 | struct fimd_context *ctx = (struct fimd_context *)dev_id; | |
3854fab2 | 981 | u32 val, clear_bit; |
1c248b7d ID |
982 | |
983 | val = readl(ctx->regs + VIDINTCON1); | |
984 | ||
3854fab2 YC |
985 | clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME; |
986 | if (val & clear_bit) | |
987 | writel(clear_bit, ctx->regs + VIDINTCON1); | |
1c248b7d | 988 | |
ec05da95 | 989 | /* check the crtc is detached already from encoder */ |
080be03d | 990 | if (ctx->pipe < 0 || !ctx->drm_dev) |
ec05da95 | 991 | goto out; |
483b88f8 | 992 | |
1c905d95 | 993 | if (ctx->i80_if) { |
adf67abf JS |
994 | exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe); |
995 | ||
1c905d95 | 996 | /* Exits triggering mode */ |
3854fab2 | 997 | atomic_set(&ctx->triggering, 0); |
3854fab2 | 998 | } else { |
adf67abf JS |
999 | drm_handle_vblank(ctx->drm_dev, ctx->pipe); |
1000 | exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe); | |
1001 | ||
3854fab2 YC |
1002 | /* set wait vsync event to zero and wake up queue. */ |
1003 | if (atomic_read(&ctx->wait_vsync_event)) { | |
1004 | atomic_set(&ctx->wait_vsync_event, 0); | |
1005 | wake_up(&ctx->wait_vsync_queue); | |
1006 | } | |
01ce113c | 1007 | } |
3854fab2 | 1008 | |
ec05da95 | 1009 | out: |
1c248b7d ID |
1010 | return IRQ_HANDLED; |
1011 | } | |
1012 | ||
f37cd5e8 | 1013 | static int fimd_bind(struct device *dev, struct device *master, void *data) |
562ad9f4 | 1014 | { |
e152dbd7 | 1015 | struct fimd_context *ctx = dev_get_drvdata(dev); |
f37cd5e8 | 1016 | struct drm_device *drm_dev = data; |
cdbfca89 | 1017 | struct exynos_drm_private *priv = drm_dev->dev_private; |
7ee14cdc GP |
1018 | struct exynos_drm_plane *exynos_plane; |
1019 | enum drm_plane_type type; | |
6e2a3b66 GP |
1020 | unsigned int zpos; |
1021 | int ret; | |
000cc920 | 1022 | |
cdbfca89 HH |
1023 | ctx->drm_dev = drm_dev; |
1024 | ctx->pipe = priv->pipe++; | |
efa75bcd | 1025 | |
7ee14cdc GP |
1026 | for (zpos = 0; zpos < WINDOWS_NR; zpos++) { |
1027 | type = (zpos == ctx->default_win) ? DRM_PLANE_TYPE_PRIMARY : | |
1028 | DRM_PLANE_TYPE_OVERLAY; | |
1029 | ret = exynos_plane_init(drm_dev, &ctx->planes[zpos], | |
6e2a3b66 | 1030 | 1 << ctx->pipe, type, zpos); |
7ee14cdc GP |
1031 | if (ret) |
1032 | return ret; | |
1033 | } | |
1034 | ||
1035 | exynos_plane = &ctx->planes[ctx->default_win]; | |
1036 | ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, | |
1037 | ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD, | |
0f04cf8d | 1038 | &fimd_crtc_ops, ctx); |
d1222842 HH |
1039 | if (IS_ERR(ctx->crtc)) |
1040 | return PTR_ERR(ctx->crtc); | |
93bca243 | 1041 | |
000cc920 AH |
1042 | if (ctx->display) |
1043 | exynos_drm_create_enc_conn(drm_dev, ctx->display); | |
1044 | ||
cdbfca89 HH |
1045 | ret = fimd_iommu_attach_devices(ctx, drm_dev); |
1046 | if (ret) | |
1047 | return ret; | |
1048 | ||
000cc920 AH |
1049 | return 0; |
1050 | ||
1051 | } | |
1052 | ||
1053 | static void fimd_unbind(struct device *dev, struct device *master, | |
1054 | void *data) | |
1055 | { | |
e152dbd7 | 1056 | struct fimd_context *ctx = dev_get_drvdata(dev); |
000cc920 | 1057 | |
93bca243 | 1058 | fimd_dpms(ctx->crtc, DRM_MODE_DPMS_OFF); |
000cc920 | 1059 | |
cdbfca89 HH |
1060 | fimd_iommu_detach_devices(ctx); |
1061 | ||
000cc920 | 1062 | if (ctx->display) |
4cfde1f2 | 1063 | exynos_dpi_remove(ctx->display); |
000cc920 AH |
1064 | } |
1065 | ||
1066 | static const struct component_ops fimd_component_ops = { | |
1067 | .bind = fimd_bind, | |
1068 | .unbind = fimd_unbind, | |
1069 | }; | |
1070 | ||
1071 | static int fimd_probe(struct platform_device *pdev) | |
1072 | { | |
1073 | struct device *dev = &pdev->dev; | |
562ad9f4 | 1074 | struct fimd_context *ctx; |
3854fab2 | 1075 | struct device_node *i80_if_timings; |
562ad9f4 | 1076 | struct resource *res; |
fe42cfb4 | 1077 | int ret; |
1c248b7d | 1078 | |
e152dbd7 AH |
1079 | if (!dev->of_node) |
1080 | return -ENODEV; | |
2d3f173c | 1081 | |
d873ab99 | 1082 | ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); |
e152dbd7 AH |
1083 | if (!ctx) |
1084 | return -ENOMEM; | |
1085 | ||
e152dbd7 | 1086 | ret = exynos_drm_component_add(dev, EXYNOS_DEVICE_TYPE_CRTC, |
5d1741ad | 1087 | EXYNOS_DISPLAY_TYPE_LCD); |
e152dbd7 AH |
1088 | if (ret) |
1089 | return ret; | |
1c248b7d | 1090 | |
bb7704d6 | 1091 | ctx->dev = dev; |
a43b933b | 1092 | ctx->suspended = true; |
3854fab2 | 1093 | ctx->driver_data = drm_fimd_get_driver_data(pdev); |
bb7704d6 | 1094 | |
1417f109 SP |
1095 | if (of_property_read_bool(dev->of_node, "samsung,invert-vden")) |
1096 | ctx->vidcon1 |= VIDCON1_INV_VDEN; | |
1097 | if (of_property_read_bool(dev->of_node, "samsung,invert-vclk")) | |
1098 | ctx->vidcon1 |= VIDCON1_INV_VCLK; | |
562ad9f4 | 1099 | |
3854fab2 YC |
1100 | i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings"); |
1101 | if (i80_if_timings) { | |
1102 | u32 val; | |
1103 | ||
1104 | ctx->i80_if = true; | |
1105 | ||
1106 | if (ctx->driver_data->has_vidoutcon) | |
1107 | ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0; | |
1108 | else | |
1109 | ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0; | |
1110 | /* | |
1111 | * The user manual describes that this "DSI_EN" bit is required | |
1112 | * to enable I80 24-bit data interface. | |
1113 | */ | |
1114 | ctx->vidcon0 |= VIDCON0_DSI_EN; | |
1115 | ||
1116 | if (of_property_read_u32(i80_if_timings, "cs-setup", &val)) | |
1117 | val = 0; | |
1118 | ctx->i80ifcon = LCD_CS_SETUP(val); | |
1119 | if (of_property_read_u32(i80_if_timings, "wr-setup", &val)) | |
1120 | val = 0; | |
1121 | ctx->i80ifcon |= LCD_WR_SETUP(val); | |
1122 | if (of_property_read_u32(i80_if_timings, "wr-active", &val)) | |
1123 | val = 1; | |
1124 | ctx->i80ifcon |= LCD_WR_ACTIVE(val); | |
1125 | if (of_property_read_u32(i80_if_timings, "wr-hold", &val)) | |
1126 | val = 0; | |
1127 | ctx->i80ifcon |= LCD_WR_HOLD(val); | |
1128 | } | |
1129 | of_node_put(i80_if_timings); | |
1130 | ||
1131 | ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node, | |
1132 | "samsung,sysreg"); | |
1133 | if (IS_ERR(ctx->sysreg)) { | |
1134 | dev_warn(dev, "failed to get system register.\n"); | |
1135 | ctx->sysreg = NULL; | |
1136 | } | |
1137 | ||
a968e727 SP |
1138 | ctx->bus_clk = devm_clk_get(dev, "fimd"); |
1139 | if (IS_ERR(ctx->bus_clk)) { | |
1140 | dev_err(dev, "failed to get bus clock\n"); | |
df5225bc ID |
1141 | ret = PTR_ERR(ctx->bus_clk); |
1142 | goto err_del_component; | |
a968e727 SP |
1143 | } |
1144 | ||
1145 | ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd"); | |
1146 | if (IS_ERR(ctx->lcd_clk)) { | |
1147 | dev_err(dev, "failed to get lcd clock\n"); | |
df5225bc ID |
1148 | ret = PTR_ERR(ctx->lcd_clk); |
1149 | goto err_del_component; | |
a968e727 | 1150 | } |
1c248b7d | 1151 | |
1c248b7d | 1152 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1c248b7d | 1153 | |
d873ab99 | 1154 | ctx->regs = devm_ioremap_resource(dev, res); |
df5225bc ID |
1155 | if (IS_ERR(ctx->regs)) { |
1156 | ret = PTR_ERR(ctx->regs); | |
1157 | goto err_del_component; | |
1158 | } | |
1c248b7d | 1159 | |
3854fab2 YC |
1160 | res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, |
1161 | ctx->i80_if ? "lcd_sys" : "vsync"); | |
1c248b7d ID |
1162 | if (!res) { |
1163 | dev_err(dev, "irq request failed.\n"); | |
df5225bc ID |
1164 | ret = -ENXIO; |
1165 | goto err_del_component; | |
1c248b7d ID |
1166 | } |
1167 | ||
055e0c06 | 1168 | ret = devm_request_irq(dev, res->start, fimd_irq_handler, |
edc57266 SK |
1169 | 0, "drm_fimd", ctx); |
1170 | if (ret) { | |
1c248b7d | 1171 | dev_err(dev, "irq request failed.\n"); |
df5225bc | 1172 | goto err_del_component; |
1c248b7d ID |
1173 | } |
1174 | ||
57ed0f7b | 1175 | init_waitqueue_head(&ctx->wait_vsync_queue); |
01ce113c | 1176 | atomic_set(&ctx->wait_vsync_event, 0); |
1c248b7d | 1177 | |
e152dbd7 | 1178 | platform_set_drvdata(pdev, ctx); |
14b6873a | 1179 | |
000cc920 | 1180 | ctx->display = exynos_dpi_probe(dev); |
5baf5d44 GP |
1181 | if (IS_ERR(ctx->display)) { |
1182 | ret = PTR_ERR(ctx->display); | |
1183 | goto err_del_component; | |
1184 | } | |
f37cd5e8 | 1185 | |
e152dbd7 | 1186 | pm_runtime_enable(dev); |
f37cd5e8 | 1187 | |
e152dbd7 | 1188 | ret = component_add(dev, &fimd_component_ops); |
df5225bc ID |
1189 | if (ret) |
1190 | goto err_disable_pm_runtime; | |
1191 | ||
1192 | return ret; | |
1193 | ||
1194 | err_disable_pm_runtime: | |
e152dbd7 | 1195 | pm_runtime_disable(dev); |
df5225bc ID |
1196 | |
1197 | err_del_component: | |
e152dbd7 | 1198 | exynos_drm_component_del(dev, EXYNOS_DEVICE_TYPE_CRTC); |
df5225bc | 1199 | return ret; |
f37cd5e8 | 1200 | } |
cb91f6a0 | 1201 | |
f37cd5e8 ID |
1202 | static int fimd_remove(struct platform_device *pdev) |
1203 | { | |
af65c804 | 1204 | pm_runtime_disable(&pdev->dev); |
5d55393a | 1205 | |
df5225bc ID |
1206 | component_del(&pdev->dev, &fimd_component_ops); |
1207 | exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC); | |
1208 | ||
5d55393a | 1209 | return 0; |
e30d4bcf ID |
1210 | } |
1211 | ||
132a5b91 | 1212 | struct platform_driver fimd_driver = { |
1c248b7d | 1213 | .probe = fimd_probe, |
56550d94 | 1214 | .remove = fimd_remove, |
1c248b7d ID |
1215 | .driver = { |
1216 | .name = "exynos4-fb", | |
1217 | .owner = THIS_MODULE, | |
2d3f173c | 1218 | .of_match_table = fimd_driver_dt_match, |
1c248b7d ID |
1219 | }, |
1220 | }; |